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Generate the Verilog code corresponding to the following Chisel files. File fNFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ object fNFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2 val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in) val isSubnormal = rawIn.sExp < minNormExp.S val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0) val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0) val expOut = Mux(isSubnormal, 0.U, rawIn.sExp(expWidth - 1, 0) - ((BigInt(1)<<(expWidth - 1)) + 1).U ) | Fill(expWidth, rawIn.isNaN || rawIn.isInf) val fractOut = Mux(isSubnormal, denormFract, Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0)) ) Cat(rawIn.sign, expOut, fractOut) } } File execution-unit.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Execution Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // The issue window schedules micro-ops onto a specific execution pipeline // A given execution pipeline may contain multiple functional units; one or more // read ports, and one or more writeports. package boom.v3.exu import scala.collection.mutable.{ArrayBuffer} import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.rocket.{BP} import freechips.rocketchip.tile import FUConstants._ import boom.v3.common._ import boom.v3.ifu.{GetPCFromFtqIO} import boom.v3.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringPrefix} /** * Response from Execution Unit. Bundles a MicroOp with data * * @param dataWidth width of the data coming from the execution unit */ class ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val data = Bits(dataWidth.W) val predicated = Bool() // Was this predicated off? val fflags = new ValidIO(new FFlagsResp) // write fflags to ROB // TODO: Do this better } /** * Floating Point flag response */ class FFlagsResp(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp() val flags = Bits(tile.FPConstants.FLAGS_SZ.W) } /** * Abstract Top level Execution Unit that wraps lower level functional units to make a * multi function execution unit. * * @param readsIrf does this exe unit need a integer regfile port * @param writesIrf does this exe unit need a integer regfile port * @param readsFrf does this exe unit need a integer regfile port * @param writesFrf does this exe unit need a integer regfile port * @param writesLlIrf does this exe unit need a integer regfile port * @param writesLlFrf does this exe unit need a integer regfile port * @param numBypassStages number of bypass ports for the exe unit * @param dataWidth width of the data coming out of the exe unit * @param bypassable is the exe unit able to be bypassed * @param hasMem does the exe unit have a MemAddrCalcUnit * @param hasCSR does the exe unit write to the CSRFile * @param hasBrUnit does the exe unit have a branch unit * @param hasAlu does the exe unit have a alu * @param hasFpu does the exe unit have a fpu * @param hasMul does the exe unit have a multiplier * @param hasDiv does the exe unit have a divider * @param hasFdiv does the exe unit have a FP divider * @param hasIfpu does the exe unit have a int to FP unit * @param hasFpiu does the exe unit have a FP to int unit */ abstract class ExecutionUnit( val readsIrf : Boolean = false, val writesIrf : Boolean = false, val readsFrf : Boolean = false, val writesFrf : Boolean = false, val writesLlIrf : Boolean = false, val writesLlFrf : Boolean = false, val numBypassStages : Int, val dataWidth : Int, val bypassable : Boolean = false, // TODO make override def for code clarity val alwaysBypassable : Boolean = false, val hasMem : Boolean = false, val hasCSR : Boolean = false, val hasJmpUnit : Boolean = false, val hasAlu : Boolean = false, val hasFpu : Boolean = false, val hasMul : Boolean = false, val hasDiv : Boolean = false, val hasFdiv : Boolean = false, val hasIfpu : Boolean = false, val hasFpiu : Boolean = false, val hasRocc : Boolean = false )(implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val fu_types = Output(Bits(FUC_SZ.W)) val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val iresp = if (writesIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null val fresp = if (writesFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null val ll_iresp = if (writesLlIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null val ll_fresp = if (writesLlFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth)))) val brupdate = Input(new BrUpdateInfo()) // only used by the rocc unit val rocc = if (hasRocc) new RoCCShimCoreIO else null // only used by the branch unit val brinfo = if (hasAlu) Output(new BrResolutionInfo()) else null val get_ftq_pc = if (hasJmpUnit) Flipped(new GetPCFromFtqIO()) else null val status = Input(new freechips.rocketchip.rocket.MStatus()) // only used by the fpu unit val fcsr_rm = if (hasFcsr) Input(Bits(tile.FPConstants.RM_SZ.W)) else null // only used by the mem unit val lsu_io = if (hasMem) Flipped(new boom.v3.lsu.LSUExeIO) else null val bp = if (hasMem) Input(Vec(nBreakpoints, new BP)) else null val mcontext = if (hasMem) Input(UInt(coreParams.mcontextWidth.W)) else null val scontext = if (hasMem) Input(UInt(coreParams.scontextWidth.W)) else null // TODO move this out of ExecutionUnit val com_exception = if (hasMem || hasRocc) Input(Bool()) else null }) io.req.ready := false.B if (writesIrf) { io.iresp.valid := false.B io.iresp.bits := DontCare io.iresp.bits.fflags.valid := false.B io.iresp.bits.predicated := false.B assert(io.iresp.ready) } if (writesLlIrf) { io.ll_iresp.valid := false.B io.ll_iresp.bits := DontCare io.ll_iresp.bits.fflags.valid := false.B io.ll_iresp.bits.predicated := false.B } if (writesFrf) { io.fresp.valid := false.B io.fresp.bits := DontCare io.fresp.bits.fflags.valid := false.B io.fresp.bits.predicated := false.B assert(io.fresp.ready) } if (writesLlFrf) { io.ll_fresp.valid := false.B io.ll_fresp.bits := DontCare io.ll_fresp.bits.fflags.valid := false.B io.ll_fresp.bits.predicated := false.B } // TODO add "number of fflag ports", so we can properly account for FPU+Mem combinations def hasFFlags : Boolean = hasFpu || hasFdiv require ((hasFpu || hasFdiv) ^ (hasAlu || hasMul || hasMem || hasIfpu), "[execute] we no longer support mixing FP and Integer functional units in the same exe unit.") def hasFcsr = hasIfpu || hasFpu || hasFdiv require (bypassable || !alwaysBypassable, "[execute] an execution unit must be bypassable if it is always bypassable") def supportedFuncUnits = { new SupportedFuncUnits( alu = hasAlu, jmp = hasJmpUnit, mem = hasMem, muld = hasMul || hasDiv, fpu = hasFpu, csr = hasCSR, fdiv = hasFdiv, ifpu = hasIfpu) } } /** * ALU execution unit that can have a branch, alu, mul, div, int to FP, * and memory unit. * * @param hasBrUnit does the exe unit have a branch unit * @param hasCSR does the exe unit write to the CSRFile * @param hasAlu does the exe unit have a alu * @param hasMul does the exe unit have a multiplier * @param hasDiv does the exe unit have a divider * @param hasIfpu does the exe unit have a int to FP unit * @param hasMem does the exe unit have a MemAddrCalcUnit */ class ALUExeUnit( hasJmpUnit : Boolean = false, hasCSR : Boolean = false, hasAlu : Boolean = true, hasMul : Boolean = false, hasDiv : Boolean = false, hasIfpu : Boolean = false, hasMem : Boolean = false, hasRocc : Boolean = false) (implicit p: Parameters) extends ExecutionUnit( readsIrf = true, writesIrf = hasAlu || hasMul || hasDiv, writesLlIrf = hasMem || hasRocc, writesLlFrf = (hasIfpu || hasMem) && p(tile.TileKey).core.fpu != None, numBypassStages = if (hasAlu && hasMul) 3 //TODO XXX p(tile.TileKey).core.imulLatency else if (hasAlu) 1 else 0, dataWidth = 64 + 1, bypassable = hasAlu, alwaysBypassable = hasAlu && !(hasMem || hasJmpUnit || hasMul || hasDiv || hasCSR || hasIfpu || hasRocc), hasCSR = hasCSR, hasJmpUnit = hasJmpUnit, hasAlu = hasAlu, hasMul = hasMul, hasDiv = hasDiv, hasIfpu = hasIfpu, hasMem = hasMem, hasRocc = hasRocc) with freechips.rocketchip.rocket.constants.MemoryOpConstants { require(!(hasRocc && !hasCSR), "RoCC needs to be shared with CSR unit") require(!(hasMem && hasRocc), "We do not support execution unit with both Mem and Rocc writebacks") require(!(hasMem && hasIfpu), "TODO. Currently do not support AluMemExeUnit with FP") val out_str = BoomCoreStringPrefix("==ExeUnit==") + (if (hasAlu) BoomCoreStringPrefix(" - ALU") else "") + (if (hasMul) BoomCoreStringPrefix(" - Mul") else "") + (if (hasDiv) BoomCoreStringPrefix(" - Div") else "") + (if (hasIfpu) BoomCoreStringPrefix(" - IFPU") else "") + (if (hasMem) BoomCoreStringPrefix(" - Mem") else "") + (if (hasRocc) BoomCoreStringPrefix(" - RoCC") else "") override def toString: String = out_str.toString val div_busy = WireInit(false.B) val ifpu_busy = WireInit(false.B) // The Functional Units -------------------- // Specifically the functional units with fast writeback to IRF val iresp_fu_units = ArrayBuffer[FunctionalUnit]() io.fu_types := Mux(hasAlu.B, FU_ALU, 0.U) | Mux(hasMul.B, FU_MUL, 0.U) | Mux(!div_busy && hasDiv.B, FU_DIV, 0.U) | Mux(hasCSR.B, FU_CSR, 0.U) | Mux(hasJmpUnit.B, FU_JMP, 0.U) | Mux(!ifpu_busy && hasIfpu.B, FU_I2F, 0.U) | Mux(hasMem.B, FU_MEM, 0.U) // ALU Unit ------------------------------- var alu: ALUUnit = null if (hasAlu) { alu = Module(new ALUUnit(isJmpUnit = hasJmpUnit, numStages = numBypassStages, dataWidth = xLen)) alu.io.req.valid := ( io.req.valid && (io.req.bits.uop.fu_code === FU_ALU || io.req.bits.uop.fu_code === FU_JMP || (io.req.bits.uop.fu_code === FU_CSR && io.req.bits.uop.uopc =/= uopROCC))) //ROCC Rocc Commands are taken by the RoCC unit alu.io.req.bits.uop := io.req.bits.uop alu.io.req.bits.kill := io.req.bits.kill alu.io.req.bits.rs1_data := io.req.bits.rs1_data alu.io.req.bits.rs2_data := io.req.bits.rs2_data alu.io.req.bits.rs3_data := DontCare alu.io.req.bits.pred_data := io.req.bits.pred_data alu.io.resp.ready := DontCare alu.io.brupdate := io.brupdate iresp_fu_units += alu // Bypassing only applies to ALU io.bypass := alu.io.bypass // branch unit is embedded inside the ALU io.brinfo := alu.io.brinfo if (hasJmpUnit) { alu.io.get_ftq_pc <> io.get_ftq_pc } } var rocc: RoCCShim = null if (hasRocc) { rocc = Module(new RoCCShim) rocc.io.req.valid := io.req.valid && io.req.bits.uop.uopc === uopROCC rocc.io.req.bits := DontCare rocc.io.req.bits.uop := io.req.bits.uop rocc.io.req.bits.kill := io.req.bits.kill rocc.io.req.bits.rs1_data := io.req.bits.rs1_data rocc.io.req.bits.rs2_data := io.req.bits.rs2_data rocc.io.brupdate := io.brupdate // We should assert on this somewhere rocc.io.status := io.status rocc.io.exception := io.com_exception io.rocc <> rocc.io.core rocc.io.resp.ready := io.ll_iresp.ready io.ll_iresp.valid := rocc.io.resp.valid io.ll_iresp.bits.uop := rocc.io.resp.bits.uop io.ll_iresp.bits.data := rocc.io.resp.bits.data } // Pipelined, IMul Unit ------------------ var imul: PipelinedMulUnit = null if (hasMul) { imul = Module(new PipelinedMulUnit(imulLatency, xLen)) imul.io <> DontCare imul.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MUL) imul.io.req.bits.uop := io.req.bits.uop imul.io.req.bits.rs1_data := io.req.bits.rs1_data imul.io.req.bits.rs2_data := io.req.bits.rs2_data imul.io.req.bits.kill := io.req.bits.kill imul.io.brupdate := io.brupdate iresp_fu_units += imul } var ifpu: IntToFPUnit = null if (hasIfpu) { ifpu = Module(new IntToFPUnit(latency=intToFpLatency)) ifpu.io.req <> io.req ifpu.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_I2F) ifpu.io.fcsr_rm := io.fcsr_rm ifpu.io.brupdate <> io.brupdate ifpu.io.resp.ready := DontCare // buffer up results since we share write-port on integer regfile. val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth), entries = intToFpLatency + 3)) // TODO being overly conservative queue.io.enq.valid := ifpu.io.resp.valid queue.io.enq.bits.uop := ifpu.io.resp.bits.uop queue.io.enq.bits.data := ifpu.io.resp.bits.data queue.io.enq.bits.predicated := ifpu.io.resp.bits.predicated queue.io.enq.bits.fflags := ifpu.io.resp.bits.fflags queue.io.brupdate := io.brupdate queue.io.flush := io.req.bits.kill io.ll_fresp <> queue.io.deq ifpu_busy := !(queue.io.empty) assert (queue.io.enq.ready) } // Div/Rem Unit ----------------------- var div: DivUnit = null val div_resp_val = WireInit(false.B) if (hasDiv) { div = Module(new DivUnit(xLen)) div.io <> DontCare div.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV) && hasDiv.B div.io.req.bits.uop := io.req.bits.uop div.io.req.bits.rs1_data := io.req.bits.rs1_data div.io.req.bits.rs2_data := io.req.bits.rs2_data div.io.brupdate := io.brupdate div.io.req.bits.kill := io.req.bits.kill // share write port with the pipelined units div.io.resp.ready := !(iresp_fu_units.map(_.io.resp.valid).reduce(_|_)) div_resp_val := div.io.resp.valid div_busy := !div.io.req.ready || (io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV)) iresp_fu_units += div } // Mem Unit -------------------------- if (hasMem) { require(!hasAlu) val maddrcalc = Module(new MemAddrCalcUnit) maddrcalc.io.req <> io.req maddrcalc.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MEM) maddrcalc.io.brupdate <> io.brupdate maddrcalc.io.status := io.status maddrcalc.io.bp := io.bp maddrcalc.io.mcontext := io.mcontext maddrcalc.io.scontext := io.scontext maddrcalc.io.resp.ready := DontCare require(numBypassStages == 0) io.lsu_io.req := maddrcalc.io.resp io.ll_iresp <> io.lsu_io.iresp if (usingFPU) { io.ll_fresp <> io.lsu_io.fresp } } // Outputs (Write Port #0) --------------- if (writesIrf) { io.iresp.valid := iresp_fu_units.map(_.io.resp.valid).reduce(_|_) io.iresp.bits.uop := PriorityMux(iresp_fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.uop)).toSeq) io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq) io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.predicated)).toSeq) // pulled out for critical path reasons // TODO: Does this make sense as part of the iresp bundle? if (hasAlu) { io.iresp.bits.uop.csr_addr := ImmGen(alu.io.resp.bits.uop.imm_packed, IS_I).asUInt io.iresp.bits.uop.ctrl.csr_cmd := alu.io.resp.bits.uop.ctrl.csr_cmd } } assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) || (PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 2.U && (div_resp_val)), "Multiple functional units are fighting over the write port.") } /** * FPU-only unit, with optional second write-port for ToInt micro-ops. * * @param hasFpu does the exe unit have a fpu * @param hasFdiv does the exe unit have a FP divider * @param hasFpiu does the exe unit have a FP to int unit */ class FPUExeUnit( hasFpu : Boolean = true, hasFdiv : Boolean = false, hasFpiu : Boolean = false ) (implicit p: Parameters) extends ExecutionUnit( readsFrf = true, writesFrf = true, writesLlIrf = hasFpiu, writesIrf = false, numBypassStages = 0, dataWidth = p(tile.TileKey).core.fpu.get.fLen + 1, bypassable = false, hasFpu = hasFpu, hasFdiv = hasFdiv, hasFpiu = hasFpiu) with tile.HasFPUParameters { val out_str = BoomCoreStringPrefix("==ExeUnit==") (if (hasFpu) BoomCoreStringPrefix("- FPU (Latency: " + dfmaLatency + ")") else "") + (if (hasFdiv) BoomCoreStringPrefix("- FDiv/FSqrt") else "") + (if (hasFpiu) BoomCoreStringPrefix("- FPIU (writes to Integer RF)") else "") val fdiv_busy = WireInit(false.B) val fpiu_busy = WireInit(false.B) // The Functional Units -------------------- val fu_units = ArrayBuffer[FunctionalUnit]() io.fu_types := Mux(hasFpu.B, FU_FPU, 0.U) | Mux(!fdiv_busy && hasFdiv.B, FU_FDV, 0.U) | Mux(!fpiu_busy && hasFpiu.B, FU_F2I, 0.U) // FPU Unit ----------------------- var fpu: FPUUnit = null val fpu_resp_val = WireInit(false.B) val fpu_resp_fflags = Wire(new ValidIO(new FFlagsResp())) fpu_resp_fflags.valid := false.B if (hasFpu) { fpu = Module(new FPUUnit()) fpu.io.req.valid := io.req.valid && (io.req.bits.uop.fu_code_is(FU_FPU) || io.req.bits.uop.fu_code_is(FU_F2I)) // TODO move to using a separate unit fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.pred_data := false.B fpu.io.req.bits.kill := io.req.bits.kill fpu.io.fcsr_rm := io.fcsr_rm fpu.io.brupdate := io.brupdate fpu.io.resp.ready := DontCare fpu_resp_val := fpu.io.resp.valid fpu_resp_fflags := fpu.io.resp.bits.fflags fu_units += fpu } // FDiv/FSqrt Unit ----------------------- var fdivsqrt: FDivSqrtUnit = null val fdiv_resp_fflags = Wire(new ValidIO(new FFlagsResp())) fdiv_resp_fflags := DontCare fdiv_resp_fflags.valid := false.B if (hasFdiv) { fdivsqrt = Module(new FDivSqrtUnit()) fdivsqrt.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV) fdivsqrt.io.req.bits.uop := io.req.bits.uop fdivsqrt.io.req.bits.rs1_data := io.req.bits.rs1_data fdivsqrt.io.req.bits.rs2_data := io.req.bits.rs2_data fdivsqrt.io.req.bits.rs3_data := DontCare fdivsqrt.io.req.bits.pred_data := false.B fdivsqrt.io.req.bits.kill := io.req.bits.kill fdivsqrt.io.fcsr_rm := io.fcsr_rm fdivsqrt.io.brupdate := io.brupdate // share write port with the pipelined units fdivsqrt.io.resp.ready := !(fu_units.map(_.io.resp.valid).reduce(_|_)) // TODO PERF will get blocked by fpiu. fdiv_busy := !fdivsqrt.io.req.ready || (io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV)) fdiv_resp_fflags := fdivsqrt.io.resp.bits.fflags fu_units += fdivsqrt } // Outputs (Write Port #0) --------------- io.fresp.valid := fu_units.map(_.io.resp.valid).reduce(_|_) && !(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I)) io.fresp.bits.uop := PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.uop)).toSeq) io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq) io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags) // Outputs (Write Port #1) -- FpToInt Queuing Unit ----------------------- if (hasFpiu) { // TODO instantiate our own fpiu; and remove it from fpu.scala. // buffer up results since we share write-port on integer regfile. val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth), entries = dfmaLatency + 3)) // TODO being overly conservative queue.io.enq.valid := (fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I) && fpu.io.resp.bits.uop.uopc =/= uopSTA) // STA means store data gen for floating point queue.io.enq.bits.uop := fpu.io.resp.bits.uop queue.io.enq.bits.data := fpu.io.resp.bits.data queue.io.enq.bits.predicated := fpu.io.resp.bits.predicated queue.io.enq.bits.fflags := fpu.io.resp.bits.fflags queue.io.brupdate := io.brupdate queue.io.flush := io.req.bits.kill assert (queue.io.enq.ready) // If this backs up, we've miscalculated the size of the queue. val fp_sdq = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth), entries = 3)) // Lets us backpressure floating point store data fp_sdq.io.enq.valid := io.req.valid && io.req.bits.uop.uopc === uopSTA && !IsKilledByBranch(io.brupdate, io.req.bits.uop) fp_sdq.io.enq.bits.uop := io.req.bits.uop fp_sdq.io.enq.bits.data := ieee(io.req.bits.rs2_data) fp_sdq.io.enq.bits.predicated := false.B fp_sdq.io.enq.bits.fflags := DontCare fp_sdq.io.brupdate := io.brupdate fp_sdq.io.flush := io.req.bits.kill assert(!(fp_sdq.io.enq.valid && !fp_sdq.io.enq.ready)) val resp_arb = Module(new Arbiter(new ExeUnitResp(dataWidth), 2)) resp_arb.io.in(0) <> queue.io.deq resp_arb.io.in(1) <> fp_sdq.io.deq io.ll_iresp <> resp_arb.io.out fpiu_busy := !(queue.io.empty && fp_sdq.io.empty) } override def toString: String = out_str.toString } File micro-op.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // MicroOp //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.exu.FUConstants /** * Extension to BoomBundle to add a MicroOp */ abstract trait HasBoomUOP extends BoomBundle { val uop = new MicroOp() } /** * MicroOp passing through the pipeline */ class MicroOp(implicit p: Parameters) extends BoomBundle with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val uopc = UInt(UOPC_SZ.W) // micro-op code val inst = UInt(32.W) val debug_inst = UInt(32.W) val is_rvc = Bool() val debug_pc = UInt(coreMaxAddrBits.W) val iq_type = UInt(IQT_SZ.W) // which issue unit do we use? val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use? val ctrl = new CtrlSignals // What is the next state of this uop in the issue window? useful // for the compacting queue. val iw_state = UInt(2.W) // Has operand 1 or 2 been waken speculatively by a load? // Only integer operands are speculaively woken up, // so we can ignore p3. val iw_p1_poisoned = Bool() val iw_p2_poisoned = Bool() val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst? val is_jalr = Bool() // is this a jump? (jal or jalr) val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit val is_sfb = Bool() // is this a sfb or in the shadow of a sfb val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under? val br_tag = UInt(brTagSz.W) // Index into FTQ to figure out our fetch PC. val ftq_idx = UInt(log2Ceil(ftqSz).W) // This inst straddles two fetch packets val edge_inst = Bool() // Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC. // Aligned to a cache-line size, as that is the greater fetch granularity. // TODO: Shouldn't this be aligned to fetch-width size? val pc_lob = UInt(log2Ceil(icBlockBytes).W) // Was this a branch that was predicted taken? val taken = Bool() val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode... // then translate and sign-extend in execute val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe val rob_idx = UInt(robAddrSz.W) val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) val pdst = UInt(maxPregSz.W) val prs1 = UInt(maxPregSz.W) val prs2 = UInt(maxPregSz.W) val prs3 = UInt(maxPregSz.W) val ppred = UInt(log2Ceil(ftqSz).W) val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() val ppred_busy = Bool() val stale_pdst = UInt(maxPregSz.W) val exception = Bool() val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...) val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes val mem_size = UInt(2.W) val mem_signed = Bool() val is_fence = Bool() val is_fencei = Bool() val is_amo = Bool() val uses_ldq = Bool() val uses_stq = Bool() val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC. val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to // drain, clear fetcha fter it (tell ROB to un-ready until empty) val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them // Preditation def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst, // else copy rs2 to dst // logical specifiers (only used in Decode->Rename), except rollback (ldst) val ldst = UInt(lregSz.W) val lrs1 = UInt(lregSz.W) val lrs2 = UInt(lregSz.W) val lrs3 = UInt(lregSz.W) val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc. val dst_rtype = UInt(2.W) val lrs1_rtype = UInt(2.W) val lrs2_rtype = UInt(2.W) val frs3_en = Bool() // floating point information val fp_val = Bool() // is a floating-point instruction (F- or D-extension)? // If it's non-ld/st it will write back exception bits to the fcsr. val fp_single = Bool() // single-precision floating point instruction (F-extension) // frontend exception information val xcpt_pf_if = Bool() // I-TLB page fault. val xcpt_ae_if = Bool() // I$ access exception. val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr). val bp_debug_if = Bool() // Breakpoint val bp_xcpt_if = Bool() // Breakpoint // What prediction structure provides the prediction FROM this op val debug_fsrc = UInt(BSRC_SZ.W) // What prediction structure provides the prediction TO this op val debug_tsrc = UInt(BSRC_SZ.W) // Do we allocate a branch tag for this? // SFB branches don't get a mask, they get a predicate bit def allocate_brtag = (is_br && !is_sfb) || is_jalr // Does this register write-back def rf_wen = dst_rtype =/= RT_X // Is it possible for this uop to misspeculate, preventing the commit of subsequent uops? def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U } /** * Control signals within a MicroOp * * TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution */ class CtrlSignals extends Bundle() { val br_type = UInt(BR_N.getWidth.W) val op1_sel = UInt(OP1_X.getWidth.W) val op2_sel = UInt(OP2_X.getWidth.W) val imm_sel = UInt(IS_X.getWidth.W) val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W) val fcn_dw = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val is_load = Bool() // will invoke TLB address lookup val is_sta = Bool() // will invoke TLB address lookup val is_std = Bool() } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module FPUExeUnit( // @[execution-unit.scala:437:7] input clock, // @[execution-unit.scala:437:7] input reset, // @[execution-unit.scala:437:7] output [9:0] io_fu_types, // @[execution-unit.scala:104:14] input io_req_valid, // @[execution-unit.scala:104:14] input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14] input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14] input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14] input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14] input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14] input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14] input [7:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14] input io_req_bits_uop_taken, // @[execution-unit.scala:104:14] input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14] input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] input [2:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14] input [3:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] input io_req_bits_uop_exception, // @[execution-unit.scala:104:14] input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14] input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14] input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14] input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14] input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14] input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14] input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14] input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14] input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14] input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14] input [64:0] io_req_bits_rs3_data, // @[execution-unit.scala:104:14] input io_req_bits_kill, // @[execution-unit.scala:104:14] output io_fresp_valid, // @[execution-unit.scala:104:14] output [6:0] io_fresp_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_fresp_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_fresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_fresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_fresp_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_fresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_fresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [7:0] io_fresp_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [3:0] io_fresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_fresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_fresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [4:0] io_fresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_pdst, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_prs1, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_prs2, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_prs3, // @[execution-unit.scala:104:14] output [3:0] io_fresp_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_fresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_fresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_fresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_fresp_bits_data, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_valid, // @[execution-unit.scala:104:14] output [6:0] io_fresp_bits_fflags_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_fresp_bits_fflags_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_fresp_bits_fflags_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_fresp_bits_fflags_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_fflags_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_fresp_bits_fflags_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_fresp_bits_fflags_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_fflags_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_fflags_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_fresp_bits_fflags_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [7:0] io_fresp_bits_fflags_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_fflags_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [3:0] io_fresp_bits_fflags_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_fresp_bits_fflags_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_fresp_bits_fflags_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [4:0] io_fresp_bits_fflags_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_fflags_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [2:0] io_fresp_bits_fflags_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_pdst, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_prs1, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_prs2, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_prs3, // @[execution-unit.scala:104:14] output [3:0] io_fresp_bits_fflags_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_fresp_bits_fflags_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_fresp_bits_fflags_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_fresp_bits_fflags_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_fresp_bits_fflags_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_fresp_bits_fflags_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [4:0] io_fresp_bits_fflags_bits_flags, // @[execution-unit.scala:104:14] input io_ll_iresp_ready, // @[execution-unit.scala:104:14] output io_ll_iresp_valid, // @[execution-unit.scala:104:14] output [6:0] io_ll_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_ll_iresp_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_ll_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_ll_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_ll_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_ll_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_ll_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [7:0] io_ll_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [3:0] io_ll_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_ll_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_ll_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [4:0] io_ll_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14] output [3:0] io_ll_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_ll_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_ll_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [64:0] io_ll_iresp_bits_data, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_predicated, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_valid, // @[execution-unit.scala:104:14] output [6:0] io_ll_iresp_bits_fflags_bits_uop_uopc, // @[execution-unit.scala:104:14] output [31:0] io_ll_iresp_bits_fflags_bits_uop_inst, // @[execution-unit.scala:104:14] output [31:0] io_ll_iresp_bits_fflags_bits_uop_debug_inst, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_rvc, // @[execution-unit.scala:104:14] output [39:0] io_ll_iresp_bits_fflags_bits_uop_debug_pc, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_fflags_bits_uop_iq_type, // @[execution-unit.scala:104:14] output [9:0] io_ll_iresp_bits_fflags_bits_uop_fu_code, // @[execution-unit.scala:104:14] output [3:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] output [4:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_iw_state, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_br, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_jalr, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_jal, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_sfb, // @[execution-unit.scala:104:14] output [7:0] io_ll_iresp_bits_fflags_bits_uop_br_mask, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_fflags_bits_uop_br_tag, // @[execution-unit.scala:104:14] output [3:0] io_ll_iresp_bits_fflags_bits_uop_ftq_idx, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_edge_inst, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_pc_lob, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_taken, // @[execution-unit.scala:104:14] output [19:0] io_ll_iresp_bits_fflags_bits_uop_imm_packed, // @[execution-unit.scala:104:14] output [11:0] io_ll_iresp_bits_fflags_bits_uop_csr_addr, // @[execution-unit.scala:104:14] output [4:0] io_ll_iresp_bits_fflags_bits_uop_rob_idx, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_fflags_bits_uop_ldq_idx, // @[execution-unit.scala:104:14] output [2:0] io_ll_iresp_bits_fflags_bits_uop_stq_idx, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_rxq_idx, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_pdst, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_prs1, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_prs2, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_prs3, // @[execution-unit.scala:104:14] output [3:0] io_ll_iresp_bits_fflags_bits_uop_ppred, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_prs1_busy, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_prs2_busy, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_prs3_busy, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_ppred_busy, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_stale_pdst, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_exception, // @[execution-unit.scala:104:14] output [63:0] io_ll_iresp_bits_fflags_bits_uop_exc_cause, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_bypassable, // @[execution-unit.scala:104:14] output [4:0] io_ll_iresp_bits_fflags_bits_uop_mem_cmd, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_mem_size, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_mem_signed, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_fence, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_fencei, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_amo, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_uses_ldq, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_uses_stq, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_is_unique, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_ldst, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs1, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs2, // @[execution-unit.scala:104:14] output [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs3, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_ldst_val, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_dst_rtype, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_frs3_en, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_fp_val, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_fp_single, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14] output io_ll_iresp_bits_fflags_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14] output [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14] output [4:0] io_ll_iresp_bits_fflags_bits_flags, // @[execution-unit.scala:104:14] input [7:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14] input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14] input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14] input [3:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14] input io_brupdate_b2_valid, // @[execution-unit.scala:104:14] input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14] input io_brupdate_b2_taken, // @[execution-unit.scala:104:14] input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14] input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14] input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14] input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14] input io_status_debug, // @[execution-unit.scala:104:14] input io_status_cease, // @[execution-unit.scala:104:14] input io_status_wfi, // @[execution-unit.scala:104:14] input [1:0] io_status_dprv, // @[execution-unit.scala:104:14] input io_status_dv, // @[execution-unit.scala:104:14] input [1:0] io_status_prv, // @[execution-unit.scala:104:14] input io_status_v, // @[execution-unit.scala:104:14] input io_status_sd, // @[execution-unit.scala:104:14] input io_status_mpv, // @[execution-unit.scala:104:14] input io_status_gva, // @[execution-unit.scala:104:14] input io_status_tsr, // @[execution-unit.scala:104:14] input io_status_tw, // @[execution-unit.scala:104:14] input io_status_tvm, // @[execution-unit.scala:104:14] input io_status_mxr, // @[execution-unit.scala:104:14] input io_status_sum, // @[execution-unit.scala:104:14] input io_status_mprv, // @[execution-unit.scala:104:14] input [1:0] io_status_fs, // @[execution-unit.scala:104:14] input [1:0] io_status_mpp, // @[execution-unit.scala:104:14] input io_status_spp, // @[execution-unit.scala:104:14] input io_status_mpie, // @[execution-unit.scala:104:14] input io_status_spie, // @[execution-unit.scala:104:14] input io_status_mie, // @[execution-unit.scala:104:14] input io_status_sie, // @[execution-unit.scala:104:14] input [2:0] io_fcsr_rm // @[execution-unit.scala:104:14] ); wire _resp_arb_io_in_0_ready; // @[execution-unit.scala:563:26] wire _resp_arb_io_in_1_ready; // @[execution-unit.scala:563:26] wire _fp_sdq_io_enq_ready; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_valid; // @[execution-unit.scala:551:24] wire [6:0] _fp_sdq_io_deq_bits_uop_uopc; // @[execution-unit.scala:551:24] wire [31:0] _fp_sdq_io_deq_bits_uop_inst; // @[execution-unit.scala:551:24] wire [31:0] _fp_sdq_io_deq_bits_uop_debug_inst; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_rvc; // @[execution-unit.scala:551:24] wire [39:0] _fp_sdq_io_deq_bits_uop_debug_pc; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_uop_iq_type; // @[execution-unit.scala:551:24] wire [9:0] _fp_sdq_io_deq_bits_uop_fu_code; // @[execution-unit.scala:551:24] wire [3:0] _fp_sdq_io_deq_bits_uop_ctrl_br_type; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:551:24] wire [4:0] _fp_sdq_io_deq_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_ctrl_is_load; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_ctrl_is_sta; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_ctrl_is_std; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_iw_state; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_br; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_jalr; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_jal; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_sfb; // @[execution-unit.scala:551:24] wire [7:0] _fp_sdq_io_deq_bits_uop_br_mask; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_uop_br_tag; // @[execution-unit.scala:551:24] wire [3:0] _fp_sdq_io_deq_bits_uop_ftq_idx; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_edge_inst; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_pc_lob; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_taken; // @[execution-unit.scala:551:24] wire [19:0] _fp_sdq_io_deq_bits_uop_imm_packed; // @[execution-unit.scala:551:24] wire [11:0] _fp_sdq_io_deq_bits_uop_csr_addr; // @[execution-unit.scala:551:24] wire [4:0] _fp_sdq_io_deq_bits_uop_rob_idx; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_uop_ldq_idx; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_uop_stq_idx; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_rxq_idx; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_pdst; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_prs1; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_prs2; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_prs3; // @[execution-unit.scala:551:24] wire [3:0] _fp_sdq_io_deq_bits_uop_ppred; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_prs1_busy; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_prs2_busy; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_prs3_busy; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_ppred_busy; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_stale_pdst; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_exception; // @[execution-unit.scala:551:24] wire [63:0] _fp_sdq_io_deq_bits_uop_exc_cause; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_bypassable; // @[execution-unit.scala:551:24] wire [4:0] _fp_sdq_io_deq_bits_uop_mem_cmd; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_mem_size; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_mem_signed; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_fence; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_fencei; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_amo; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_uses_ldq; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_uses_stq; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_is_unique; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_flush_on_commit; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_ldst_is_rs1; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_ldst; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_lrs1; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_lrs2; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_uop_lrs3; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_ldst_val; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_dst_rtype; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_lrs1_rtype; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_lrs2_rtype; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_frs3_en; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_fp_val; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_fp_single; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_xcpt_pf_if; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_xcpt_ae_if; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_xcpt_ma_if; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_bp_debug_if; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_uop_bp_xcpt_if; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_debug_fsrc; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_uop_debug_tsrc; // @[execution-unit.scala:551:24] wire [64:0] _fp_sdq_io_deq_bits_data; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_predicated; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_valid; // @[execution-unit.scala:551:24] wire [6:0] _fp_sdq_io_deq_bits_fflags_bits_uop_uopc; // @[execution-unit.scala:551:24] wire [31:0] _fp_sdq_io_deq_bits_fflags_bits_uop_inst; // @[execution-unit.scala:551:24] wire [31:0] _fp_sdq_io_deq_bits_fflags_bits_uop_debug_inst; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_rvc; // @[execution-unit.scala:551:24] wire [39:0] _fp_sdq_io_deq_bits_fflags_bits_uop_debug_pc; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_iq_type; // @[execution-unit.scala:551:24] wire [9:0] _fp_sdq_io_deq_bits_fflags_bits_uop_fu_code; // @[execution-unit.scala:551:24] wire [3:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:551:24] wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_iw_state; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_br; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_jalr; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_jal; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_sfb; // @[execution-unit.scala:551:24] wire [7:0] _fp_sdq_io_deq_bits_fflags_bits_uop_br_mask; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_br_tag; // @[execution-unit.scala:551:24] wire [3:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_edge_inst; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_pc_lob; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_taken; // @[execution-unit.scala:551:24] wire [19:0] _fp_sdq_io_deq_bits_fflags_bits_uop_imm_packed; // @[execution-unit.scala:551:24] wire [11:0] _fp_sdq_io_deq_bits_fflags_bits_uop_csr_addr; // @[execution-unit.scala:551:24] wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_rob_idx; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:551:24] wire [2:0] _fp_sdq_io_deq_bits_fflags_bits_uop_stq_idx; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_pdst; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_prs1; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_prs2; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_prs3; // @[execution-unit.scala:551:24] wire [3:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ppred; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_exception; // @[execution-unit.scala:551:24] wire [63:0] _fp_sdq_io_deq_bits_fflags_bits_uop_exc_cause; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_bypassable; // @[execution-unit.scala:551:24] wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_mem_size; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_mem_signed; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_fence; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_fencei; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_amo; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_uses_stq; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_is_unique; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_ldst; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs1; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs2; // @[execution-unit.scala:551:24] wire [5:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs3; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_ldst_val; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_frs3_en; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_fp_val; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_fp_single; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:551:24] wire _fp_sdq_io_deq_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:551:24] wire [1:0] _fp_sdq_io_deq_bits_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:551:24] wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_flags; // @[execution-unit.scala:551:24] wire _fp_sdq_io_empty; // @[execution-unit.scala:551:24] wire _queue_io_enq_ready; // @[execution-unit.scala:537:23] wire _queue_io_deq_valid; // @[execution-unit.scala:537:23] wire [6:0] _queue_io_deq_bits_uop_uopc; // @[execution-unit.scala:537:23] wire [31:0] _queue_io_deq_bits_uop_inst; // @[execution-unit.scala:537:23] wire [31:0] _queue_io_deq_bits_uop_debug_inst; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_rvc; // @[execution-unit.scala:537:23] wire [39:0] _queue_io_deq_bits_uop_debug_pc; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_uop_iq_type; // @[execution-unit.scala:537:23] wire [9:0] _queue_io_deq_bits_uop_fu_code; // @[execution-unit.scala:537:23] wire [3:0] _queue_io_deq_bits_uop_ctrl_br_type; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:537:23] wire [4:0] _queue_io_deq_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_ctrl_is_load; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_ctrl_is_sta; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_ctrl_is_std; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_iw_state; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_br; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_jalr; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_jal; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_sfb; // @[execution-unit.scala:537:23] wire [7:0] _queue_io_deq_bits_uop_br_mask; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_uop_br_tag; // @[execution-unit.scala:537:23] wire [3:0] _queue_io_deq_bits_uop_ftq_idx; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_edge_inst; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_pc_lob; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_taken; // @[execution-unit.scala:537:23] wire [19:0] _queue_io_deq_bits_uop_imm_packed; // @[execution-unit.scala:537:23] wire [11:0] _queue_io_deq_bits_uop_csr_addr; // @[execution-unit.scala:537:23] wire [4:0] _queue_io_deq_bits_uop_rob_idx; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_uop_ldq_idx; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_uop_stq_idx; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_rxq_idx; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_pdst; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_prs1; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_prs2; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_prs3; // @[execution-unit.scala:537:23] wire [3:0] _queue_io_deq_bits_uop_ppred; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_prs1_busy; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_prs2_busy; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_prs3_busy; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_ppred_busy; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_stale_pdst; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_exception; // @[execution-unit.scala:537:23] wire [63:0] _queue_io_deq_bits_uop_exc_cause; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_bypassable; // @[execution-unit.scala:537:23] wire [4:0] _queue_io_deq_bits_uop_mem_cmd; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_mem_size; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_mem_signed; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_fence; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_fencei; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_amo; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_uses_ldq; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_uses_stq; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_is_unique; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_flush_on_commit; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_ldst_is_rs1; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_ldst; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_lrs1; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_lrs2; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_uop_lrs3; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_ldst_val; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_dst_rtype; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_lrs1_rtype; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_lrs2_rtype; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_frs3_en; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_fp_val; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_fp_single; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_xcpt_pf_if; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_xcpt_ae_if; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_xcpt_ma_if; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_bp_debug_if; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_uop_bp_xcpt_if; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_debug_fsrc; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_uop_debug_tsrc; // @[execution-unit.scala:537:23] wire [64:0] _queue_io_deq_bits_data; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_predicated; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_valid; // @[execution-unit.scala:537:23] wire [6:0] _queue_io_deq_bits_fflags_bits_uop_uopc; // @[execution-unit.scala:537:23] wire [31:0] _queue_io_deq_bits_fflags_bits_uop_inst; // @[execution-unit.scala:537:23] wire [31:0] _queue_io_deq_bits_fflags_bits_uop_debug_inst; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_rvc; // @[execution-unit.scala:537:23] wire [39:0] _queue_io_deq_bits_fflags_bits_uop_debug_pc; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_fflags_bits_uop_iq_type; // @[execution-unit.scala:537:23] wire [9:0] _queue_io_deq_bits_fflags_bits_uop_fu_code; // @[execution-unit.scala:537:23] wire [3:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:537:23] wire [4:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_iw_state; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_br; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_jalr; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_jal; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_sfb; // @[execution-unit.scala:537:23] wire [7:0] _queue_io_deq_bits_fflags_bits_uop_br_mask; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_fflags_bits_uop_br_tag; // @[execution-unit.scala:537:23] wire [3:0] _queue_io_deq_bits_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_edge_inst; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_pc_lob; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_taken; // @[execution-unit.scala:537:23] wire [19:0] _queue_io_deq_bits_fflags_bits_uop_imm_packed; // @[execution-unit.scala:537:23] wire [11:0] _queue_io_deq_bits_fflags_bits_uop_csr_addr; // @[execution-unit.scala:537:23] wire [4:0] _queue_io_deq_bits_fflags_bits_uop_rob_idx; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:537:23] wire [2:0] _queue_io_deq_bits_fflags_bits_uop_stq_idx; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_pdst; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_prs1; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_prs2; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_prs3; // @[execution-unit.scala:537:23] wire [3:0] _queue_io_deq_bits_fflags_bits_uop_ppred; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_exception; // @[execution-unit.scala:537:23] wire [63:0] _queue_io_deq_bits_fflags_bits_uop_exc_cause; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_bypassable; // @[execution-unit.scala:537:23] wire [4:0] _queue_io_deq_bits_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_mem_size; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_mem_signed; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_fence; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_fencei; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_amo; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_uses_stq; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_is_unique; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_ldst; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_lrs1; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_lrs2; // @[execution-unit.scala:537:23] wire [5:0] _queue_io_deq_bits_fflags_bits_uop_lrs3; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_ldst_val; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_frs3_en; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_fp_val; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_fp_single; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:537:23] wire _queue_io_deq_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:537:23] wire [1:0] _queue_io_deq_bits_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:537:23] wire [4:0] _queue_io_deq_bits_fflags_bits_flags; // @[execution-unit.scala:537:23] wire _queue_io_empty; // @[execution-unit.scala:537:23] wire _FDivSqrtUnit_io_req_ready; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_valid; // @[execution-unit.scala:502:22] wire [6:0] _FDivSqrtUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:502:22] wire [31:0] _FDivSqrtUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:502:22] wire [31:0] _FDivSqrtUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:502:22] wire [39:0] _FDivSqrtUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:502:22] wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:502:22] wire [9:0] _FDivSqrtUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:502:22] wire [3:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:502:22] wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:502:22] wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:502:22] wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:502:22] wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:502:22] wire [7:0] _FDivSqrtUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:502:22] wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:502:22] wire [3:0] _FDivSqrtUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:502:22] wire [19:0] _FDivSqrtUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:502:22] wire [11:0] _FDivSqrtUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:502:22] wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:502:22] wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:502:22] wire [2:0] _FDivSqrtUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:502:22] wire [3:0] _FDivSqrtUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:502:22] wire [63:0] _FDivSqrtUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:502:22] wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:502:22] wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:502:22] wire _FDivSqrtUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:502:22] wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:502:22] wire [64:0] _FDivSqrtUnit_io_resp_bits_data; // @[execution-unit.scala:502:22] wire _FPUUnit_io_resp_valid; // @[execution-unit.scala:477:17] wire [6:0] _FPUUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:477:17] wire [31:0] _FPUUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:477:17] wire [31:0] _FPUUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:477:17] wire [39:0] _FPUUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:477:17] wire [9:0] _FPUUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:477:17] wire [3:0] _FPUUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:477:17] wire [4:0] _FPUUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:477:17] wire [7:0] _FPUUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:477:17] wire [3:0] _FPUUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:477:17] wire [19:0] _FPUUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:477:17] wire [11:0] _FPUUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:477:17] wire [4:0] _FPUUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:477:17] wire [3:0] _FPUUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:477:17] wire [63:0] _FPUUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:477:17] wire [4:0] _FPUUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:477:17] wire [64:0] _FPUUnit_io_resp_bits_data; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_valid; // @[execution-unit.scala:477:17] wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_uopc; // @[execution-unit.scala:477:17] wire [31:0] _FPUUnit_io_resp_bits_fflags_bits_uop_inst; // @[execution-unit.scala:477:17] wire [31:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_inst; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_rvc; // @[execution-unit.scala:477:17] wire [39:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_pc; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_iq_type; // @[execution-unit.scala:477:17] wire [9:0] _FPUUnit_io_resp_bits_fflags_bits_uop_fu_code; // @[execution-unit.scala:477:17] wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:477:17] wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_iw_state; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_br; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_jalr; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_jal; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_sfb; // @[execution-unit.scala:477:17] wire [7:0] _FPUUnit_io_resp_bits_fflags_bits_uop_br_mask; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_br_tag; // @[execution-unit.scala:477:17] wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_edge_inst; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_pc_lob; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_taken; // @[execution-unit.scala:477:17] wire [19:0] _FPUUnit_io_resp_bits_fflags_bits_uop_imm_packed; // @[execution-unit.scala:477:17] wire [11:0] _FPUUnit_io_resp_bits_fflags_bits_uop_csr_addr; // @[execution-unit.scala:477:17] wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:477:17] wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_stq_idx; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_pdst; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs1; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs2; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs3; // @[execution-unit.scala:477:17] wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ppred; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_exception; // @[execution-unit.scala:477:17] wire [63:0] _FPUUnit_io_resp_bits_fflags_bits_uop_exc_cause; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_bypassable; // @[execution-unit.scala:477:17] wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_mem_size; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_mem_signed; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_fence; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_fencei; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_amo; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_uses_stq; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_unique; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ldst; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs1; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs2; // @[execution-unit.scala:477:17] wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs3; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_ldst_val; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_frs3_en; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_fp_val; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_fp_single; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:477:17] wire _FPUUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:477:17] wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:477:17] wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_flags; // @[execution-unit.scala:477:17] wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:437:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:437:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:437:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:437:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:437:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:437:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:437:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:437:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:437:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:437:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:437:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:437:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:437:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:437:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:437:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:437:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:437:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:437:7] wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:437:7] wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:437:7] wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:437:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:437:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:437:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:437:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:437:7] wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:437:7] wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:437:7] wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:437:7] wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:437:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:437:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:437:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:437:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:437:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:437:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:437:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:437:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:437:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:437:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:437:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:437:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:437:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:437:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:437:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:437:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:437:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:437:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:437:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:437:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:437:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:437:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:437:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:437:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:437:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:437:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:437:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:437:7] wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[execution-unit.scala:437:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:437:7] wire io_ll_iresp_ready_0 = io_ll_iresp_ready; // @[execution-unit.scala:437:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:437:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:437:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:437:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:437:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:437:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:437:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:437:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:437:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:437:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:437:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:437:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:437:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:437:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:437:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:437:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:437:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:437:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:437:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:437:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:437:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:437:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:437:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:437:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:437:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:437:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:437:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:437:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:437:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:437:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:437:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:437:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:437:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:437:7] wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:437:7] wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:437:7] wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:437:7] wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:437:7] wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:437:7] wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:437:7] wire io_status_v_0 = io_status_v; // @[execution-unit.scala:437:7] wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:437:7] wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:437:7] wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:437:7] wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:437:7] wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:437:7] wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:437:7] wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:437:7] wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:437:7] wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:437:7] wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:437:7] wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:437:7] wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:437:7] wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:437:7] wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:437:7] wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:437:7] wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:437:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[execution-unit.scala:437:7] wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:437:7] wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:437:7] wire io_req_ready = 1'h0; // @[execution-unit.scala:437:7] wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:437:7] wire io_fresp_bits_predicated = 1'h0; // @[execution-unit.scala:437:7] wire io_status_mbe = 1'h0; // @[execution-unit.scala:437:7] wire io_status_sbe = 1'h0; // @[execution-unit.scala:437:7] wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:437:7] wire io_status_ube = 1'h0; // @[execution-unit.scala:437:7] wire io_status_upie = 1'h0; // @[execution-unit.scala:437:7] wire io_status_hie = 1'h0; // @[execution-unit.scala:437:7] wire io_status_uie = 1'h0; // @[execution-unit.scala:437:7] wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:437:7] wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:437:7] wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:437:7] wire io_fresp_ready = 1'h1; // @[execution-unit.scala:437:7] wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:437:7] wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:437:7] wire [9:0] _io_fu_types_T = 10'h40; // @[execution-unit.scala:467:21] wire [9:0] _io_fu_types_T_8; // @[execution-unit.scala:468:60] wire _io_fresp_valid_T_5; // @[execution-unit.scala:525:69] wire [6:0] _io_fresp_bits_uop_T_uopc; // @[Mux.scala:50:70] wire [31:0] _io_fresp_bits_uop_T_inst; // @[Mux.scala:50:70] wire [31:0] _io_fresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70] wire [39:0] _io_fresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70] wire [2:0] _io_fresp_bits_uop_T_iq_type; // @[Mux.scala:50:70] wire [9:0] _io_fresp_bits_uop_T_fu_code; // @[Mux.scala:50:70] wire [3:0] _io_fresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70] wire [2:0] _io_fresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70] wire [2:0] _io_fresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70] wire [4:0] _io_fresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70] wire [2:0] _io_fresp_bits_uop_T_ctrl_csr_cmd; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_iw_state; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_br; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_jal; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70] wire [7:0] _io_fresp_bits_uop_T_br_mask; // @[Mux.scala:50:70] wire [2:0] _io_fresp_bits_uop_T_br_tag; // @[Mux.scala:50:70] wire [3:0] _io_fresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_taken; // @[Mux.scala:50:70] wire [19:0] _io_fresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70] wire [11:0] _io_fresp_bits_uop_T_csr_addr; // @[Mux.scala:50:70] wire [4:0] _io_fresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70] wire [2:0] _io_fresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70] wire [2:0] _io_fresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_pdst; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_prs1; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_prs2; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_prs3; // @[Mux.scala:50:70] wire [3:0] _io_fresp_bits_uop_T_ppred; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_exception; // @[Mux.scala:50:70] wire [63:0] _io_fresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_bypassable; // @[Mux.scala:50:70] wire [4:0] _io_fresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_mem_size; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_fence; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_amo; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_is_unique; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_ldst; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_lrs1; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_lrs2; // @[Mux.scala:50:70] wire [5:0] _io_fresp_bits_uop_T_lrs3; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_fp_val; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_fp_single; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70] wire _io_fresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70] wire [1:0] _io_fresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70] wire [64:0] _io_fresp_bits_data_T; // @[Mux.scala:50:70] wire _io_fresp_bits_fflags_T_valid; // @[execution-unit.scala:530:30] wire [6:0] _io_fresp_bits_fflags_T_bits_uop_uopc; // @[execution-unit.scala:530:30] wire [31:0] _io_fresp_bits_fflags_T_bits_uop_inst; // @[execution-unit.scala:530:30] wire [31:0] _io_fresp_bits_fflags_T_bits_uop_debug_inst; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_rvc; // @[execution-unit.scala:530:30] wire [39:0] _io_fresp_bits_fflags_T_bits_uop_debug_pc; // @[execution-unit.scala:530:30] wire [2:0] _io_fresp_bits_fflags_T_bits_uop_iq_type; // @[execution-unit.scala:530:30] wire [9:0] _io_fresp_bits_fflags_T_bits_uop_fu_code; // @[execution-unit.scala:530:30] wire [3:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_br_type; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:530:30] wire [2:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:530:30] wire [2:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:530:30] wire [4:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:530:30] wire [2:0] _io_fresp_bits_fflags_T_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_ctrl_is_load; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_ctrl_is_sta; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_ctrl_is_std; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_iw_state; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_br; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_jalr; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_jal; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_sfb; // @[execution-unit.scala:530:30] wire [7:0] _io_fresp_bits_fflags_T_bits_uop_br_mask; // @[execution-unit.scala:530:30] wire [2:0] _io_fresp_bits_fflags_T_bits_uop_br_tag; // @[execution-unit.scala:530:30] wire [3:0] _io_fresp_bits_fflags_T_bits_uop_ftq_idx; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_edge_inst; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_pc_lob; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_taken; // @[execution-unit.scala:530:30] wire [19:0] _io_fresp_bits_fflags_T_bits_uop_imm_packed; // @[execution-unit.scala:530:30] wire [11:0] _io_fresp_bits_fflags_T_bits_uop_csr_addr; // @[execution-unit.scala:530:30] wire [4:0] _io_fresp_bits_fflags_T_bits_uop_rob_idx; // @[execution-unit.scala:530:30] wire [2:0] _io_fresp_bits_fflags_T_bits_uop_ldq_idx; // @[execution-unit.scala:530:30] wire [2:0] _io_fresp_bits_fflags_T_bits_uop_stq_idx; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_rxq_idx; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_pdst; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_prs1; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_prs2; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_prs3; // @[execution-unit.scala:530:30] wire [3:0] _io_fresp_bits_fflags_T_bits_uop_ppred; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_prs1_busy; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_prs2_busy; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_prs3_busy; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_ppred_busy; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_stale_pdst; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_exception; // @[execution-unit.scala:530:30] wire [63:0] _io_fresp_bits_fflags_T_bits_uop_exc_cause; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_bypassable; // @[execution-unit.scala:530:30] wire [4:0] _io_fresp_bits_fflags_T_bits_uop_mem_cmd; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_mem_size; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_mem_signed; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_fence; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_fencei; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_amo; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_uses_ldq; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_uses_stq; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_is_unique; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_flush_on_commit; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_ldst_is_rs1; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_ldst; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_lrs1; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_lrs2; // @[execution-unit.scala:530:30] wire [5:0] _io_fresp_bits_fflags_T_bits_uop_lrs3; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_ldst_val; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_dst_rtype; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_lrs1_rtype; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_lrs2_rtype; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_frs3_en; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_fp_val; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_fp_single; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_xcpt_pf_if; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_xcpt_ae_if; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_xcpt_ma_if; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_bp_debug_if; // @[execution-unit.scala:530:30] wire _io_fresp_bits_fflags_T_bits_uop_bp_xcpt_if; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_debug_fsrc; // @[execution-unit.scala:530:30] wire [1:0] _io_fresp_bits_fflags_T_bits_uop_debug_tsrc; // @[execution-unit.scala:530:30] wire [4:0] _io_fresp_bits_fflags_T_bits_flags; // @[execution-unit.scala:530:30] wire [3:0] io_fresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:437:7] wire [4:0] io_fresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:437:7] wire [6:0] io_fresp_bits_uop_uopc_0; // @[execution-unit.scala:437:7] wire [31:0] io_fresp_bits_uop_inst_0; // @[execution-unit.scala:437:7] wire [31:0] io_fresp_bits_uop_debug_inst_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_rvc_0; // @[execution-unit.scala:437:7] wire [39:0] io_fresp_bits_uop_debug_pc_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_uop_iq_type_0; // @[execution-unit.scala:437:7] wire [9:0] io_fresp_bits_uop_fu_code_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_iw_state_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_br_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_jalr_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_jal_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_sfb_0; // @[execution-unit.scala:437:7] wire [7:0] io_fresp_bits_uop_br_mask_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_uop_br_tag_0; // @[execution-unit.scala:437:7] wire [3:0] io_fresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_edge_inst_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_pc_lob_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_taken_0; // @[execution-unit.scala:437:7] wire [19:0] io_fresp_bits_uop_imm_packed_0; // @[execution-unit.scala:437:7] wire [11:0] io_fresp_bits_uop_csr_addr_0; // @[execution-unit.scala:437:7] wire [4:0] io_fresp_bits_uop_rob_idx_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_uop_stq_idx_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_pdst_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_prs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_prs2_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_prs3_0; // @[execution-unit.scala:437:7] wire [3:0] io_fresp_bits_uop_ppred_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_exception_0; // @[execution-unit.scala:437:7] wire [63:0] io_fresp_bits_uop_exc_cause_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_bypassable_0; // @[execution-unit.scala:437:7] wire [4:0] io_fresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_mem_size_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_mem_signed_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_fence_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_fencei_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_amo_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_uses_stq_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_is_unique_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_ldst_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_lrs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_lrs2_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_uop_lrs3_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_ldst_val_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_frs3_en_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_fp_val_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_fp_single_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:437:7] wire [3:0] io_fresp_bits_fflags_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:437:7] wire [4:0] io_fresp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:437:7] wire [6:0] io_fresp_bits_fflags_bits_uop_uopc_0; // @[execution-unit.scala:437:7] wire [31:0] io_fresp_bits_fflags_bits_uop_inst_0; // @[execution-unit.scala:437:7] wire [31:0] io_fresp_bits_fflags_bits_uop_debug_inst_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_rvc_0; // @[execution-unit.scala:437:7] wire [39:0] io_fresp_bits_fflags_bits_uop_debug_pc_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_fflags_bits_uop_iq_type_0; // @[execution-unit.scala:437:7] wire [9:0] io_fresp_bits_fflags_bits_uop_fu_code_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_iw_state_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_br_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_jalr_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_jal_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_sfb_0; // @[execution-unit.scala:437:7] wire [7:0] io_fresp_bits_fflags_bits_uop_br_mask_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_fflags_bits_uop_br_tag_0; // @[execution-unit.scala:437:7] wire [3:0] io_fresp_bits_fflags_bits_uop_ftq_idx_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_edge_inst_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_pc_lob_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_taken_0; // @[execution-unit.scala:437:7] wire [19:0] io_fresp_bits_fflags_bits_uop_imm_packed_0; // @[execution-unit.scala:437:7] wire [11:0] io_fresp_bits_fflags_bits_uop_csr_addr_0; // @[execution-unit.scala:437:7] wire [4:0] io_fresp_bits_fflags_bits_uop_rob_idx_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_fflags_bits_uop_ldq_idx_0; // @[execution-unit.scala:437:7] wire [2:0] io_fresp_bits_fflags_bits_uop_stq_idx_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_rxq_idx_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_pdst_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_prs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_prs2_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_prs3_0; // @[execution-unit.scala:437:7] wire [3:0] io_fresp_bits_fflags_bits_uop_ppred_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_prs1_busy_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_prs2_busy_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_prs3_busy_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_ppred_busy_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_stale_pdst_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_exception_0; // @[execution-unit.scala:437:7] wire [63:0] io_fresp_bits_fflags_bits_uop_exc_cause_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_bypassable_0; // @[execution-unit.scala:437:7] wire [4:0] io_fresp_bits_fflags_bits_uop_mem_cmd_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_mem_size_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_mem_signed_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_fence_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_fencei_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_amo_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_uses_ldq_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_uses_stq_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_is_unique_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_flush_on_commit_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_ldst_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_lrs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_lrs2_0; // @[execution-unit.scala:437:7] wire [5:0] io_fresp_bits_fflags_bits_uop_lrs3_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_ldst_val_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_dst_rtype_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_frs3_en_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_fp_val_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_fp_single_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_bp_debug_if_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_debug_fsrc_0; // @[execution-unit.scala:437:7] wire [1:0] io_fresp_bits_fflags_bits_uop_debug_tsrc_0; // @[execution-unit.scala:437:7] wire [4:0] io_fresp_bits_fflags_bits_flags_0; // @[execution-unit.scala:437:7] wire io_fresp_bits_fflags_valid_0; // @[execution-unit.scala:437:7] wire [64:0] io_fresp_bits_data_0; // @[execution-unit.scala:437:7] wire io_fresp_valid_0; // @[execution-unit.scala:437:7] wire [3:0] io_ll_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:437:7] wire [4:0] io_ll_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:437:7] wire [6:0] io_ll_iresp_bits_uop_uopc_0; // @[execution-unit.scala:437:7] wire [31:0] io_ll_iresp_bits_uop_inst_0; // @[execution-unit.scala:437:7] wire [31:0] io_ll_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:437:7] wire [39:0] io_ll_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:437:7] wire [9:0] io_ll_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_br_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:437:7] wire [7:0] io_ll_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:437:7] wire [3:0] io_ll_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_taken_0; // @[execution-unit.scala:437:7] wire [19:0] io_ll_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:437:7] wire [11:0] io_ll_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:437:7] wire [4:0] io_ll_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_pdst_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_prs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_prs2_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_prs3_0; // @[execution-unit.scala:437:7] wire [3:0] io_ll_iresp_bits_uop_ppred_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_exception_0; // @[execution-unit.scala:437:7] wire [63:0] io_ll_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:437:7] wire [4:0] io_ll_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_ldst_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:437:7] wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:437:7] wire [4:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:437:7] wire [6:0] io_ll_iresp_bits_fflags_bits_uop_uopc_0; // @[execution-unit.scala:437:7] wire [31:0] io_ll_iresp_bits_fflags_bits_uop_inst_0; // @[execution-unit.scala:437:7] wire [31:0] io_ll_iresp_bits_fflags_bits_uop_debug_inst_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_rvc_0; // @[execution-unit.scala:437:7] wire [39:0] io_ll_iresp_bits_fflags_bits_uop_debug_pc_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_fflags_bits_uop_iq_type_0; // @[execution-unit.scala:437:7] wire [9:0] io_ll_iresp_bits_fflags_bits_uop_fu_code_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_iw_state_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_br_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_jalr_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_jal_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_sfb_0; // @[execution-unit.scala:437:7] wire [7:0] io_ll_iresp_bits_fflags_bits_uop_br_mask_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_fflags_bits_uop_br_tag_0; // @[execution-unit.scala:437:7] wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ftq_idx_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_edge_inst_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_pc_lob_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_taken_0; // @[execution-unit.scala:437:7] wire [19:0] io_ll_iresp_bits_fflags_bits_uop_imm_packed_0; // @[execution-unit.scala:437:7] wire [11:0] io_ll_iresp_bits_fflags_bits_uop_csr_addr_0; // @[execution-unit.scala:437:7] wire [4:0] io_ll_iresp_bits_fflags_bits_uop_rob_idx_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ldq_idx_0; // @[execution-unit.scala:437:7] wire [2:0] io_ll_iresp_bits_fflags_bits_uop_stq_idx_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_rxq_idx_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_pdst_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs2_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs3_0; // @[execution-unit.scala:437:7] wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ppred_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_prs1_busy_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_prs2_busy_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_prs3_busy_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_ppred_busy_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_stale_pdst_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_exception_0; // @[execution-unit.scala:437:7] wire [63:0] io_ll_iresp_bits_fflags_bits_uop_exc_cause_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_bypassable_0; // @[execution-unit.scala:437:7] wire [4:0] io_ll_iresp_bits_fflags_bits_uop_mem_cmd_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_mem_size_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_mem_signed_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_fence_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_fencei_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_amo_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_uses_ldq_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_uses_stq_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_is_unique_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_flush_on_commit_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_ldst_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs1_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs2_0; // @[execution-unit.scala:437:7] wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs3_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_ldst_val_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_dst_rtype_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_frs3_en_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_fp_val_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_fp_single_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_bp_debug_if_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_fsrc_0; // @[execution-unit.scala:437:7] wire [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_tsrc_0; // @[execution-unit.scala:437:7] wire [4:0] io_ll_iresp_bits_fflags_bits_flags_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_fflags_valid_0; // @[execution-unit.scala:437:7] wire [64:0] io_ll_iresp_bits_data_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_bits_predicated_0; // @[execution-unit.scala:437:7] wire io_ll_iresp_valid_0; // @[execution-unit.scala:437:7] wire [9:0] io_fu_types_0; // @[execution-unit.scala:437:7] wire _fdiv_busy_T_4; // @[execution-unit.scala:516:41] wire fdiv_busy; // @[execution-unit.scala:461:27] wire _fpiu_busy_T_1; // @[execution-unit.scala:568:18] wire fpiu_busy; // @[execution-unit.scala:462:27] wire _io_fu_types_T_1 = ~fdiv_busy; // @[execution-unit.scala:461:27, :468:22] wire _io_fu_types_T_2 = _io_fu_types_T_1; // @[execution-unit.scala:468:{22,33}] wire [9:0] _io_fu_types_T_3 = {2'h0, _io_fu_types_T_2, 7'h0}; // @[execution-unit.scala:468:{21,33}] wire [9:0] _io_fu_types_T_4 = _io_fu_types_T_3 | 10'h40; // @[execution-unit.scala:467:45, :468:21] wire _io_fu_types_T_5 = ~fpiu_busy; // @[execution-unit.scala:462:27, :469:22] wire _io_fu_types_T_6 = _io_fu_types_T_5; // @[execution-unit.scala:469:{22,33}] wire [9:0] _io_fu_types_T_7 = {_io_fu_types_T_6, 9'h0}; // @[execution-unit.scala:469:{21,33}] assign _io_fu_types_T_8 = _io_fu_types_T_4 | _io_fu_types_T_7; // @[execution-unit.scala:467:45, :468:60, :469:21] assign io_fu_types_0 = _io_fu_types_T_8; // @[execution-unit.scala:437:7, :468:60] wire fpu_resp_val; // @[execution-unit.scala:473:30] wire [3:0] fpu_resp_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:474:29] wire [2:0] fpu_resp_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:474:29] wire [2:0] fpu_resp_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:474:29] wire [4:0] fpu_resp_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:474:29] wire [2:0] fpu_resp_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:474:29] wire [6:0] fpu_resp_fflags_bits_uop_uopc; // @[execution-unit.scala:474:29] wire [31:0] fpu_resp_fflags_bits_uop_inst; // @[execution-unit.scala:474:29] wire [31:0] fpu_resp_fflags_bits_uop_debug_inst; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_rvc; // @[execution-unit.scala:474:29] wire [39:0] fpu_resp_fflags_bits_uop_debug_pc; // @[execution-unit.scala:474:29] wire [2:0] fpu_resp_fflags_bits_uop_iq_type; // @[execution-unit.scala:474:29] wire [9:0] fpu_resp_fflags_bits_uop_fu_code; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_iw_state; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_br; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_jalr; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_jal; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_sfb; // @[execution-unit.scala:474:29] wire [7:0] fpu_resp_fflags_bits_uop_br_mask; // @[execution-unit.scala:474:29] wire [2:0] fpu_resp_fflags_bits_uop_br_tag; // @[execution-unit.scala:474:29] wire [3:0] fpu_resp_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_edge_inst; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_pc_lob; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_taken; // @[execution-unit.scala:474:29] wire [19:0] fpu_resp_fflags_bits_uop_imm_packed; // @[execution-unit.scala:474:29] wire [11:0] fpu_resp_fflags_bits_uop_csr_addr; // @[execution-unit.scala:474:29] wire [4:0] fpu_resp_fflags_bits_uop_rob_idx; // @[execution-unit.scala:474:29] wire [2:0] fpu_resp_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:474:29] wire [2:0] fpu_resp_fflags_bits_uop_stq_idx; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_pdst; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_prs1; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_prs2; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_prs3; // @[execution-unit.scala:474:29] wire [3:0] fpu_resp_fflags_bits_uop_ppred; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_exception; // @[execution-unit.scala:474:29] wire [63:0] fpu_resp_fflags_bits_uop_exc_cause; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_bypassable; // @[execution-unit.scala:474:29] wire [4:0] fpu_resp_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_mem_size; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_mem_signed; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_fence; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_fencei; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_amo; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_uses_stq; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_is_unique; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_ldst; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_lrs1; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_lrs2; // @[execution-unit.scala:474:29] wire [5:0] fpu_resp_fflags_bits_uop_lrs3; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_ldst_val; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_frs3_en; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_fp_val; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_fp_single; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:474:29] wire [1:0] fpu_resp_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:474:29] wire [4:0] fpu_resp_fflags_bits_flags; // @[execution-unit.scala:474:29] wire fpu_resp_fflags_valid; // @[execution-unit.scala:474:29] wire [3:0] fdiv_resp_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:498:30] wire [2:0] fdiv_resp_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:498:30] wire [2:0] fdiv_resp_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:498:30] wire [4:0] fdiv_resp_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:498:30] wire [2:0] fdiv_resp_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:498:30] wire [6:0] fdiv_resp_fflags_bits_uop_uopc; // @[execution-unit.scala:498:30] wire [31:0] fdiv_resp_fflags_bits_uop_inst; // @[execution-unit.scala:498:30] wire [31:0] fdiv_resp_fflags_bits_uop_debug_inst; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_rvc; // @[execution-unit.scala:498:30] wire [39:0] fdiv_resp_fflags_bits_uop_debug_pc; // @[execution-unit.scala:498:30] wire [2:0] fdiv_resp_fflags_bits_uop_iq_type; // @[execution-unit.scala:498:30] wire [9:0] fdiv_resp_fflags_bits_uop_fu_code; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_iw_state; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_br; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_jalr; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_jal; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_sfb; // @[execution-unit.scala:498:30] wire [7:0] fdiv_resp_fflags_bits_uop_br_mask; // @[execution-unit.scala:498:30] wire [2:0] fdiv_resp_fflags_bits_uop_br_tag; // @[execution-unit.scala:498:30] wire [3:0] fdiv_resp_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_edge_inst; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_pc_lob; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_taken; // @[execution-unit.scala:498:30] wire [19:0] fdiv_resp_fflags_bits_uop_imm_packed; // @[execution-unit.scala:498:30] wire [11:0] fdiv_resp_fflags_bits_uop_csr_addr; // @[execution-unit.scala:498:30] wire [4:0] fdiv_resp_fflags_bits_uop_rob_idx; // @[execution-unit.scala:498:30] wire [2:0] fdiv_resp_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:498:30] wire [2:0] fdiv_resp_fflags_bits_uop_stq_idx; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_pdst; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_prs1; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_prs2; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_prs3; // @[execution-unit.scala:498:30] wire [3:0] fdiv_resp_fflags_bits_uop_ppred; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_exception; // @[execution-unit.scala:498:30] wire [63:0] fdiv_resp_fflags_bits_uop_exc_cause; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_bypassable; // @[execution-unit.scala:498:30] wire [4:0] fdiv_resp_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_mem_size; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_mem_signed; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_fence; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_fencei; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_amo; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_uses_stq; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_is_unique; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_ldst; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_lrs1; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_lrs2; // @[execution-unit.scala:498:30] wire [5:0] fdiv_resp_fflags_bits_uop_lrs3; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_ldst_val; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_frs3_en; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_fp_val; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_fp_single; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:498:30] wire [1:0] fdiv_resp_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:498:30] wire [4:0] fdiv_resp_fflags_bits_flags; // @[execution-unit.scala:498:30] wire fdiv_resp_fflags_valid; // @[execution-unit.scala:498:30] wire [9:0] _fdiv_busy_T_1 = io_req_bits_uop_fu_code_0 & 10'h80; // @[execution-unit.scala:437:7] wire _fdiv_busy_T = ~_FDivSqrtUnit_io_req_ready; // @[execution-unit.scala:502:22, :516:18] wire _fdiv_busy_T_2 = |_fdiv_busy_T_1; // @[micro-op.scala:154:{40,47}] wire _fdiv_busy_T_3 = io_req_valid_0 & _fdiv_busy_T_2; // @[execution-unit.scala:437:7, :516:58] assign _fdiv_busy_T_4 = _fdiv_busy_T | _fdiv_busy_T_3; // @[execution-unit.scala:516:{18,41,58}] assign fdiv_busy = _fdiv_busy_T_4; // @[execution-unit.scala:461:27, :516:41] wire _io_fresp_valid_T = _FPUUnit_io_resp_valid | _FDivSqrtUnit_io_resp_valid; // @[execution-unit.scala:477:17, :502:22, :525:65] wire [9:0] _GEN = _FPUUnit_io_resp_bits_uop_fu_code & 10'h200; // @[execution-unit.scala:477:17] wire [9:0] _io_fresp_valid_T_1; // @[micro-op.scala:154:40] assign _io_fresp_valid_T_1 = _GEN; // @[micro-op.scala:154:40] wire [9:0] _queue_io_enq_valid_T; // @[micro-op.scala:154:40] assign _queue_io_enq_valid_T = _GEN; // @[micro-op.scala:154:40] wire _io_fresp_valid_T_2 = |_io_fresp_valid_T_1; // @[micro-op.scala:154:{40,47}] wire _io_fresp_valid_T_3 = _FPUUnit_io_resp_valid & _io_fresp_valid_T_2; // @[execution-unit.scala:477:17, :526:47] wire _io_fresp_valid_T_4 = ~_io_fresp_valid_T_3; // @[execution-unit.scala:526:{27,47}] assign _io_fresp_valid_T_5 = _io_fresp_valid_T & _io_fresp_valid_T_4; // @[execution-unit.scala:525:{65,69}, :526:27] assign io_fresp_valid_0 = _io_fresp_valid_T_5; // @[execution-unit.scala:437:7, :525:69] assign _io_fresp_bits_uop_T_uopc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uopc : _FDivSqrtUnit_io_resp_bits_uop_uopc; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_inst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_inst : _FDivSqrtUnit_io_resp_bits_uop_inst; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_debug_inst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_debug_inst : _FDivSqrtUnit_io_resp_bits_uop_debug_inst; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_rvc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_rvc : _FDivSqrtUnit_io_resp_bits_uop_is_rvc; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_debug_pc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_debug_pc : _FDivSqrtUnit_io_resp_bits_uop_debug_pc; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_iq_type = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_iq_type : _FDivSqrtUnit_io_resp_bits_uop_iq_type; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_fu_code = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_fu_code : _FDivSqrtUnit_io_resp_bits_uop_fu_code; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_br_type = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_br_type : _FDivSqrtUnit_io_resp_bits_uop_ctrl_br_type; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_op1_sel = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_op1_sel : _FDivSqrtUnit_io_resp_bits_uop_ctrl_op1_sel; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_op2_sel = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_op2_sel : _FDivSqrtUnit_io_resp_bits_uop_ctrl_op2_sel; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_imm_sel = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_imm_sel : _FDivSqrtUnit_io_resp_bits_uop_ctrl_imm_sel; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_op_fcn = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_op_fcn : _FDivSqrtUnit_io_resp_bits_uop_ctrl_op_fcn; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_fcn_dw = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_fcn_dw : _FDivSqrtUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_csr_cmd = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_csr_cmd : _FDivSqrtUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_is_load = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_is_load : _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_load; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_is_sta = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_is_sta : _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_sta; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ctrl_is_std = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ctrl_is_std : _FDivSqrtUnit_io_resp_bits_uop_ctrl_is_std; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_iw_state = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_iw_state : _FDivSqrtUnit_io_resp_bits_uop_iw_state; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_iw_p1_poisoned = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_iw_p1_poisoned : _FDivSqrtUnit_io_resp_bits_uop_iw_p1_poisoned; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_iw_p2_poisoned = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_iw_p2_poisoned : _FDivSqrtUnit_io_resp_bits_uop_iw_p2_poisoned; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_br = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_br : _FDivSqrtUnit_io_resp_bits_uop_is_br; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_jalr = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_jalr : _FDivSqrtUnit_io_resp_bits_uop_is_jalr; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_jal = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_jal : _FDivSqrtUnit_io_resp_bits_uop_is_jal; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_sfb = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_sfb : _FDivSqrtUnit_io_resp_bits_uop_is_sfb; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_br_mask = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_br_mask : _FDivSqrtUnit_io_resp_bits_uop_br_mask; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_br_tag = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_br_tag : _FDivSqrtUnit_io_resp_bits_uop_br_tag; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ftq_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ftq_idx : _FDivSqrtUnit_io_resp_bits_uop_ftq_idx; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_edge_inst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_edge_inst : _FDivSqrtUnit_io_resp_bits_uop_edge_inst; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_pc_lob = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_pc_lob : _FDivSqrtUnit_io_resp_bits_uop_pc_lob; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_taken = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_taken : _FDivSqrtUnit_io_resp_bits_uop_taken; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_imm_packed = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_imm_packed : _FDivSqrtUnit_io_resp_bits_uop_imm_packed; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_csr_addr = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_csr_addr : _FDivSqrtUnit_io_resp_bits_uop_csr_addr; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_rob_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_rob_idx : _FDivSqrtUnit_io_resp_bits_uop_rob_idx; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ldq_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ldq_idx : _FDivSqrtUnit_io_resp_bits_uop_ldq_idx; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_stq_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_stq_idx : _FDivSqrtUnit_io_resp_bits_uop_stq_idx; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_rxq_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_rxq_idx : _FDivSqrtUnit_io_resp_bits_uop_rxq_idx; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_pdst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_pdst : _FDivSqrtUnit_io_resp_bits_uop_pdst; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_prs1 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs1 : _FDivSqrtUnit_io_resp_bits_uop_prs1; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_prs2 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs2 : _FDivSqrtUnit_io_resp_bits_uop_prs2; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_prs3 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs3 : _FDivSqrtUnit_io_resp_bits_uop_prs3; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ppred = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ppred : _FDivSqrtUnit_io_resp_bits_uop_ppred; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_prs1_busy = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs1_busy : _FDivSqrtUnit_io_resp_bits_uop_prs1_busy; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_prs2_busy = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs2_busy : _FDivSqrtUnit_io_resp_bits_uop_prs2_busy; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_prs3_busy = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_prs3_busy : _FDivSqrtUnit_io_resp_bits_uop_prs3_busy; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ppred_busy = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ppred_busy : _FDivSqrtUnit_io_resp_bits_uop_ppred_busy; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_stale_pdst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_stale_pdst : _FDivSqrtUnit_io_resp_bits_uop_stale_pdst; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_exception = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_exception : _FDivSqrtUnit_io_resp_bits_uop_exception; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_exc_cause = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_exc_cause : _FDivSqrtUnit_io_resp_bits_uop_exc_cause; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_bypassable = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_bypassable : _FDivSqrtUnit_io_resp_bits_uop_bypassable; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_mem_cmd = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_mem_cmd : _FDivSqrtUnit_io_resp_bits_uop_mem_cmd; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_mem_size = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_mem_size : _FDivSqrtUnit_io_resp_bits_uop_mem_size; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_mem_signed = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_mem_signed : _FDivSqrtUnit_io_resp_bits_uop_mem_signed; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_fence = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_fence : _FDivSqrtUnit_io_resp_bits_uop_is_fence; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_fencei = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_fencei : _FDivSqrtUnit_io_resp_bits_uop_is_fencei; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_amo = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_amo : _FDivSqrtUnit_io_resp_bits_uop_is_amo; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_uses_ldq = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uses_ldq : _FDivSqrtUnit_io_resp_bits_uop_uses_ldq; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_uses_stq = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uses_stq : _FDivSqrtUnit_io_resp_bits_uop_uses_stq; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_sys_pc2epc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_sys_pc2epc : _FDivSqrtUnit_io_resp_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_is_unique = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_unique : _FDivSqrtUnit_io_resp_bits_uop_is_unique; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_flush_on_commit = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_flush_on_commit : _FDivSqrtUnit_io_resp_bits_uop_flush_on_commit; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ldst_is_rs1 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ldst_is_rs1 : _FDivSqrtUnit_io_resp_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ldst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ldst : _FDivSqrtUnit_io_resp_bits_uop_ldst; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_lrs1 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs1 : _FDivSqrtUnit_io_resp_bits_uop_lrs1; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_lrs2 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs2 : _FDivSqrtUnit_io_resp_bits_uop_lrs2; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_lrs3 = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs3 : _FDivSqrtUnit_io_resp_bits_uop_lrs3; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_ldst_val = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_ldst_val : _FDivSqrtUnit_io_resp_bits_uop_ldst_val; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_dst_rtype = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_dst_rtype : _FDivSqrtUnit_io_resp_bits_uop_dst_rtype; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_lrs1_rtype = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs1_rtype : _FDivSqrtUnit_io_resp_bits_uop_lrs1_rtype; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_lrs2_rtype = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_lrs2_rtype : _FDivSqrtUnit_io_resp_bits_uop_lrs2_rtype; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_frs3_en = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_frs3_en : _FDivSqrtUnit_io_resp_bits_uop_frs3_en; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_fp_val = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_fp_val : _FDivSqrtUnit_io_resp_bits_uop_fp_val; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_fp_single = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_fp_single : _FDivSqrtUnit_io_resp_bits_uop_fp_single; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_xcpt_pf_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_xcpt_pf_if : _FDivSqrtUnit_io_resp_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_xcpt_ae_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_xcpt_ae_if : _FDivSqrtUnit_io_resp_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_xcpt_ma_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_xcpt_ma_if : _FDivSqrtUnit_io_resp_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_bp_debug_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_bp_debug_if : _FDivSqrtUnit_io_resp_bits_uop_bp_debug_if; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_bp_xcpt_if = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_bp_xcpt_if : _FDivSqrtUnit_io_resp_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_debug_fsrc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_debug_fsrc : _FDivSqrtUnit_io_resp_bits_uop_debug_fsrc; // @[Mux.scala:50:70] assign _io_fresp_bits_uop_T_debug_tsrc = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_debug_tsrc : _FDivSqrtUnit_io_resp_bits_uop_debug_tsrc; // @[Mux.scala:50:70] assign io_fresp_bits_uop_uopc_0 = _io_fresp_bits_uop_T_uopc; // @[Mux.scala:50:70] assign io_fresp_bits_uop_inst_0 = _io_fresp_bits_uop_T_inst; // @[Mux.scala:50:70] assign io_fresp_bits_uop_debug_inst_0 = _io_fresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_rvc_0 = _io_fresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70] assign io_fresp_bits_uop_debug_pc_0 = _io_fresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70] assign io_fresp_bits_uop_iq_type_0 = _io_fresp_bits_uop_T_iq_type; // @[Mux.scala:50:70] assign io_fresp_bits_uop_fu_code_0 = _io_fresp_bits_uop_T_fu_code; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_br_type_0 = _io_fresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_op1_sel_0 = _io_fresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_op2_sel_0 = _io_fresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_imm_sel_0 = _io_fresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_op_fcn_0 = _io_fresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_fcn_dw_0 = _io_fresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_csr_cmd_0 = _io_fresp_bits_uop_T_ctrl_csr_cmd; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_is_load_0 = _io_fresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_is_sta_0 = _io_fresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ctrl_is_std_0 = _io_fresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70] assign io_fresp_bits_uop_iw_state_0 = _io_fresp_bits_uop_T_iw_state; // @[Mux.scala:50:70] assign io_fresp_bits_uop_iw_p1_poisoned_0 = _io_fresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70] assign io_fresp_bits_uop_iw_p2_poisoned_0 = _io_fresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_br_0 = _io_fresp_bits_uop_T_is_br; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_jalr_0 = _io_fresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_jal_0 = _io_fresp_bits_uop_T_is_jal; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_sfb_0 = _io_fresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70] assign io_fresp_bits_uop_br_mask_0 = _io_fresp_bits_uop_T_br_mask; // @[Mux.scala:50:70] assign io_fresp_bits_uop_br_tag_0 = _io_fresp_bits_uop_T_br_tag; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ftq_idx_0 = _io_fresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70] assign io_fresp_bits_uop_edge_inst_0 = _io_fresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70] assign io_fresp_bits_uop_pc_lob_0 = _io_fresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70] assign io_fresp_bits_uop_taken_0 = _io_fresp_bits_uop_T_taken; // @[Mux.scala:50:70] assign io_fresp_bits_uop_imm_packed_0 = _io_fresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70] assign io_fresp_bits_uop_csr_addr_0 = _io_fresp_bits_uop_T_csr_addr; // @[Mux.scala:50:70] assign io_fresp_bits_uop_rob_idx_0 = _io_fresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ldq_idx_0 = _io_fresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70] assign io_fresp_bits_uop_stq_idx_0 = _io_fresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70] assign io_fresp_bits_uop_rxq_idx_0 = _io_fresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70] assign io_fresp_bits_uop_pdst_0 = _io_fresp_bits_uop_T_pdst; // @[Mux.scala:50:70] assign io_fresp_bits_uop_prs1_0 = _io_fresp_bits_uop_T_prs1; // @[Mux.scala:50:70] assign io_fresp_bits_uop_prs2_0 = _io_fresp_bits_uop_T_prs2; // @[Mux.scala:50:70] assign io_fresp_bits_uop_prs3_0 = _io_fresp_bits_uop_T_prs3; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ppred_0 = _io_fresp_bits_uop_T_ppred; // @[Mux.scala:50:70] assign io_fresp_bits_uop_prs1_busy_0 = _io_fresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70] assign io_fresp_bits_uop_prs2_busy_0 = _io_fresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70] assign io_fresp_bits_uop_prs3_busy_0 = _io_fresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ppred_busy_0 = _io_fresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70] assign io_fresp_bits_uop_stale_pdst_0 = _io_fresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70] assign io_fresp_bits_uop_exception_0 = _io_fresp_bits_uop_T_exception; // @[Mux.scala:50:70] assign io_fresp_bits_uop_exc_cause_0 = _io_fresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70] assign io_fresp_bits_uop_bypassable_0 = _io_fresp_bits_uop_T_bypassable; // @[Mux.scala:50:70] assign io_fresp_bits_uop_mem_cmd_0 = _io_fresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70] assign io_fresp_bits_uop_mem_size_0 = _io_fresp_bits_uop_T_mem_size; // @[Mux.scala:50:70] assign io_fresp_bits_uop_mem_signed_0 = _io_fresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_fence_0 = _io_fresp_bits_uop_T_is_fence; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_fencei_0 = _io_fresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_amo_0 = _io_fresp_bits_uop_T_is_amo; // @[Mux.scala:50:70] assign io_fresp_bits_uop_uses_ldq_0 = _io_fresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70] assign io_fresp_bits_uop_uses_stq_0 = _io_fresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_sys_pc2epc_0 = _io_fresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] assign io_fresp_bits_uop_is_unique_0 = _io_fresp_bits_uop_T_is_unique; // @[Mux.scala:50:70] assign io_fresp_bits_uop_flush_on_commit_0 = _io_fresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ldst_is_rs1_0 = _io_fresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ldst_0 = _io_fresp_bits_uop_T_ldst; // @[Mux.scala:50:70] assign io_fresp_bits_uop_lrs1_0 = _io_fresp_bits_uop_T_lrs1; // @[Mux.scala:50:70] assign io_fresp_bits_uop_lrs2_0 = _io_fresp_bits_uop_T_lrs2; // @[Mux.scala:50:70] assign io_fresp_bits_uop_lrs3_0 = _io_fresp_bits_uop_T_lrs3; // @[Mux.scala:50:70] assign io_fresp_bits_uop_ldst_val_0 = _io_fresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70] assign io_fresp_bits_uop_dst_rtype_0 = _io_fresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70] assign io_fresp_bits_uop_lrs1_rtype_0 = _io_fresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70] assign io_fresp_bits_uop_lrs2_rtype_0 = _io_fresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70] assign io_fresp_bits_uop_frs3_en_0 = _io_fresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70] assign io_fresp_bits_uop_fp_val_0 = _io_fresp_bits_uop_T_fp_val; // @[Mux.scala:50:70] assign io_fresp_bits_uop_fp_single_0 = _io_fresp_bits_uop_T_fp_single; // @[Mux.scala:50:70] assign io_fresp_bits_uop_xcpt_pf_if_0 = _io_fresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] assign io_fresp_bits_uop_xcpt_ae_if_0 = _io_fresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] assign io_fresp_bits_uop_xcpt_ma_if_0 = _io_fresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] assign io_fresp_bits_uop_bp_debug_if_0 = _io_fresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70] assign io_fresp_bits_uop_bp_xcpt_if_0 = _io_fresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] assign io_fresp_bits_uop_debug_fsrc_0 = _io_fresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70] assign io_fresp_bits_uop_debug_tsrc_0 = _io_fresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70] assign _io_fresp_bits_data_T = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_data : _FDivSqrtUnit_io_resp_bits_data; // @[Mux.scala:50:70] assign io_fresp_bits_data_0 = _io_fresp_bits_data_T; // @[Mux.scala:50:70] assign _io_fresp_bits_fflags_T_valid = fpu_resp_val ? fpu_resp_fflags_valid : fdiv_resp_fflags_valid; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_uopc = fpu_resp_val ? fpu_resp_fflags_bits_uop_uopc : fdiv_resp_fflags_bits_uop_uopc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_inst = fpu_resp_val ? fpu_resp_fflags_bits_uop_inst : fdiv_resp_fflags_bits_uop_inst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_debug_inst = fpu_resp_val ? fpu_resp_fflags_bits_uop_debug_inst : fdiv_resp_fflags_bits_uop_debug_inst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_rvc = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_rvc : fdiv_resp_fflags_bits_uop_is_rvc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_debug_pc = fpu_resp_val ? fpu_resp_fflags_bits_uop_debug_pc : fdiv_resp_fflags_bits_uop_debug_pc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_iq_type = fpu_resp_val ? fpu_resp_fflags_bits_uop_iq_type : fdiv_resp_fflags_bits_uop_iq_type; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_fu_code = fpu_resp_val ? fpu_resp_fflags_bits_uop_fu_code : fdiv_resp_fflags_bits_uop_fu_code; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_br_type = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_br_type : fdiv_resp_fflags_bits_uop_ctrl_br_type; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_op1_sel = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_op1_sel : fdiv_resp_fflags_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_op2_sel = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_op2_sel : fdiv_resp_fflags_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_imm_sel = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_imm_sel : fdiv_resp_fflags_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_op_fcn = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_op_fcn : fdiv_resp_fflags_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_fcn_dw = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_fcn_dw : fdiv_resp_fflags_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_csr_cmd = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_csr_cmd : fdiv_resp_fflags_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_is_load = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_is_load : fdiv_resp_fflags_bits_uop_ctrl_is_load; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_is_sta = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_is_sta : fdiv_resp_fflags_bits_uop_ctrl_is_sta; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ctrl_is_std = fpu_resp_val ? fpu_resp_fflags_bits_uop_ctrl_is_std : fdiv_resp_fflags_bits_uop_ctrl_is_std; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_iw_state = fpu_resp_val ? fpu_resp_fflags_bits_uop_iw_state : fdiv_resp_fflags_bits_uop_iw_state; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_iw_p1_poisoned = fpu_resp_val ? fpu_resp_fflags_bits_uop_iw_p1_poisoned : fdiv_resp_fflags_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_iw_p2_poisoned = fpu_resp_val ? fpu_resp_fflags_bits_uop_iw_p2_poisoned : fdiv_resp_fflags_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_br = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_br : fdiv_resp_fflags_bits_uop_is_br; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_jalr = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_jalr : fdiv_resp_fflags_bits_uop_is_jalr; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_jal = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_jal : fdiv_resp_fflags_bits_uop_is_jal; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_sfb = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_sfb : fdiv_resp_fflags_bits_uop_is_sfb; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_br_mask = fpu_resp_val ? fpu_resp_fflags_bits_uop_br_mask : fdiv_resp_fflags_bits_uop_br_mask; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_br_tag = fpu_resp_val ? fpu_resp_fflags_bits_uop_br_tag : fdiv_resp_fflags_bits_uop_br_tag; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ftq_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_ftq_idx : fdiv_resp_fflags_bits_uop_ftq_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_edge_inst = fpu_resp_val ? fpu_resp_fflags_bits_uop_edge_inst : fdiv_resp_fflags_bits_uop_edge_inst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_pc_lob = fpu_resp_val ? fpu_resp_fflags_bits_uop_pc_lob : fdiv_resp_fflags_bits_uop_pc_lob; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_taken = fpu_resp_val ? fpu_resp_fflags_bits_uop_taken : fdiv_resp_fflags_bits_uop_taken; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_imm_packed = fpu_resp_val ? fpu_resp_fflags_bits_uop_imm_packed : fdiv_resp_fflags_bits_uop_imm_packed; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_csr_addr = fpu_resp_val ? fpu_resp_fflags_bits_uop_csr_addr : fdiv_resp_fflags_bits_uop_csr_addr; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_rob_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_rob_idx : fdiv_resp_fflags_bits_uop_rob_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ldq_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_ldq_idx : fdiv_resp_fflags_bits_uop_ldq_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_stq_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_stq_idx : fdiv_resp_fflags_bits_uop_stq_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_rxq_idx = fpu_resp_val ? fpu_resp_fflags_bits_uop_rxq_idx : fdiv_resp_fflags_bits_uop_rxq_idx; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_pdst = fpu_resp_val ? fpu_resp_fflags_bits_uop_pdst : fdiv_resp_fflags_bits_uop_pdst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_prs1 = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs1 : fdiv_resp_fflags_bits_uop_prs1; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_prs2 = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs2 : fdiv_resp_fflags_bits_uop_prs2; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_prs3 = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs3 : fdiv_resp_fflags_bits_uop_prs3; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ppred = fpu_resp_val ? fpu_resp_fflags_bits_uop_ppred : fdiv_resp_fflags_bits_uop_ppred; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_prs1_busy = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs1_busy : fdiv_resp_fflags_bits_uop_prs1_busy; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_prs2_busy = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs2_busy : fdiv_resp_fflags_bits_uop_prs2_busy; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_prs3_busy = fpu_resp_val ? fpu_resp_fflags_bits_uop_prs3_busy : fdiv_resp_fflags_bits_uop_prs3_busy; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ppred_busy = fpu_resp_val ? fpu_resp_fflags_bits_uop_ppred_busy : fdiv_resp_fflags_bits_uop_ppred_busy; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_stale_pdst = fpu_resp_val ? fpu_resp_fflags_bits_uop_stale_pdst : fdiv_resp_fflags_bits_uop_stale_pdst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_exception = fpu_resp_val ? fpu_resp_fflags_bits_uop_exception : fdiv_resp_fflags_bits_uop_exception; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_exc_cause = fpu_resp_val ? fpu_resp_fflags_bits_uop_exc_cause : fdiv_resp_fflags_bits_uop_exc_cause; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_bypassable = fpu_resp_val ? fpu_resp_fflags_bits_uop_bypassable : fdiv_resp_fflags_bits_uop_bypassable; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_mem_cmd = fpu_resp_val ? fpu_resp_fflags_bits_uop_mem_cmd : fdiv_resp_fflags_bits_uop_mem_cmd; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_mem_size = fpu_resp_val ? fpu_resp_fflags_bits_uop_mem_size : fdiv_resp_fflags_bits_uop_mem_size; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_mem_signed = fpu_resp_val ? fpu_resp_fflags_bits_uop_mem_signed : fdiv_resp_fflags_bits_uop_mem_signed; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_fence = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_fence : fdiv_resp_fflags_bits_uop_is_fence; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_fencei = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_fencei : fdiv_resp_fflags_bits_uop_is_fencei; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_amo = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_amo : fdiv_resp_fflags_bits_uop_is_amo; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_uses_ldq = fpu_resp_val ? fpu_resp_fflags_bits_uop_uses_ldq : fdiv_resp_fflags_bits_uop_uses_ldq; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_uses_stq = fpu_resp_val ? fpu_resp_fflags_bits_uop_uses_stq : fdiv_resp_fflags_bits_uop_uses_stq; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_sys_pc2epc = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_sys_pc2epc : fdiv_resp_fflags_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_is_unique = fpu_resp_val ? fpu_resp_fflags_bits_uop_is_unique : fdiv_resp_fflags_bits_uop_is_unique; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_flush_on_commit = fpu_resp_val ? fpu_resp_fflags_bits_uop_flush_on_commit : fdiv_resp_fflags_bits_uop_flush_on_commit; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ldst_is_rs1 = fpu_resp_val ? fpu_resp_fflags_bits_uop_ldst_is_rs1 : fdiv_resp_fflags_bits_uop_ldst_is_rs1; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ldst = fpu_resp_val ? fpu_resp_fflags_bits_uop_ldst : fdiv_resp_fflags_bits_uop_ldst; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_lrs1 = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs1 : fdiv_resp_fflags_bits_uop_lrs1; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_lrs2 = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs2 : fdiv_resp_fflags_bits_uop_lrs2; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_lrs3 = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs3 : fdiv_resp_fflags_bits_uop_lrs3; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_ldst_val = fpu_resp_val ? fpu_resp_fflags_bits_uop_ldst_val : fdiv_resp_fflags_bits_uop_ldst_val; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_dst_rtype = fpu_resp_val ? fpu_resp_fflags_bits_uop_dst_rtype : fdiv_resp_fflags_bits_uop_dst_rtype; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_lrs1_rtype = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs1_rtype : fdiv_resp_fflags_bits_uop_lrs1_rtype; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_lrs2_rtype = fpu_resp_val ? fpu_resp_fflags_bits_uop_lrs2_rtype : fdiv_resp_fflags_bits_uop_lrs2_rtype; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_frs3_en = fpu_resp_val ? fpu_resp_fflags_bits_uop_frs3_en : fdiv_resp_fflags_bits_uop_frs3_en; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_fp_val = fpu_resp_val ? fpu_resp_fflags_bits_uop_fp_val : fdiv_resp_fflags_bits_uop_fp_val; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_fp_single = fpu_resp_val ? fpu_resp_fflags_bits_uop_fp_single : fdiv_resp_fflags_bits_uop_fp_single; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_xcpt_pf_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_xcpt_pf_if : fdiv_resp_fflags_bits_uop_xcpt_pf_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_xcpt_ae_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_xcpt_ae_if : fdiv_resp_fflags_bits_uop_xcpt_ae_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_xcpt_ma_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_xcpt_ma_if : fdiv_resp_fflags_bits_uop_xcpt_ma_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_bp_debug_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_bp_debug_if : fdiv_resp_fflags_bits_uop_bp_debug_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_bp_xcpt_if = fpu_resp_val ? fpu_resp_fflags_bits_uop_bp_xcpt_if : fdiv_resp_fflags_bits_uop_bp_xcpt_if; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_debug_fsrc = fpu_resp_val ? fpu_resp_fflags_bits_uop_debug_fsrc : fdiv_resp_fflags_bits_uop_debug_fsrc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_uop_debug_tsrc = fpu_resp_val ? fpu_resp_fflags_bits_uop_debug_tsrc : fdiv_resp_fflags_bits_uop_debug_tsrc; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign _io_fresp_bits_fflags_T_bits_flags = fpu_resp_val ? fpu_resp_fflags_bits_flags : fdiv_resp_fflags_bits_flags; // @[execution-unit.scala:473:30, :474:29, :498:30, :530:30] assign io_fresp_bits_fflags_valid_0 = _io_fresp_bits_fflags_T_valid; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_uopc_0 = _io_fresp_bits_fflags_T_bits_uop_uopc; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_inst_0 = _io_fresp_bits_fflags_T_bits_uop_inst; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_debug_inst_0 = _io_fresp_bits_fflags_T_bits_uop_debug_inst; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_rvc_0 = _io_fresp_bits_fflags_T_bits_uop_is_rvc; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_debug_pc_0 = _io_fresp_bits_fflags_T_bits_uop_debug_pc; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_iq_type_0 = _io_fresp_bits_fflags_T_bits_uop_iq_type; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_fu_code_0 = _io_fresp_bits_fflags_T_bits_uop_fu_code; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_br_type_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_br_type; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_op1_sel_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_op2_sel_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_imm_sel_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_op_fcn_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_is_load_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_is_load; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_is_sta_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_is_sta; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ctrl_is_std_0 = _io_fresp_bits_fflags_T_bits_uop_ctrl_is_std; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_iw_state_0 = _io_fresp_bits_fflags_T_bits_uop_iw_state; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_iw_p1_poisoned_0 = _io_fresp_bits_fflags_T_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_iw_p2_poisoned_0 = _io_fresp_bits_fflags_T_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_br_0 = _io_fresp_bits_fflags_T_bits_uop_is_br; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_jalr_0 = _io_fresp_bits_fflags_T_bits_uop_is_jalr; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_jal_0 = _io_fresp_bits_fflags_T_bits_uop_is_jal; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_sfb_0 = _io_fresp_bits_fflags_T_bits_uop_is_sfb; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_br_mask_0 = _io_fresp_bits_fflags_T_bits_uop_br_mask; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_br_tag_0 = _io_fresp_bits_fflags_T_bits_uop_br_tag; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ftq_idx_0 = _io_fresp_bits_fflags_T_bits_uop_ftq_idx; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_edge_inst_0 = _io_fresp_bits_fflags_T_bits_uop_edge_inst; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_pc_lob_0 = _io_fresp_bits_fflags_T_bits_uop_pc_lob; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_taken_0 = _io_fresp_bits_fflags_T_bits_uop_taken; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_imm_packed_0 = _io_fresp_bits_fflags_T_bits_uop_imm_packed; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_csr_addr_0 = _io_fresp_bits_fflags_T_bits_uop_csr_addr; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_rob_idx_0 = _io_fresp_bits_fflags_T_bits_uop_rob_idx; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ldq_idx_0 = _io_fresp_bits_fflags_T_bits_uop_ldq_idx; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_stq_idx_0 = _io_fresp_bits_fflags_T_bits_uop_stq_idx; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_rxq_idx_0 = _io_fresp_bits_fflags_T_bits_uop_rxq_idx; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_pdst_0 = _io_fresp_bits_fflags_T_bits_uop_pdst; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_prs1_0 = _io_fresp_bits_fflags_T_bits_uop_prs1; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_prs2_0 = _io_fresp_bits_fflags_T_bits_uop_prs2; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_prs3_0 = _io_fresp_bits_fflags_T_bits_uop_prs3; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ppred_0 = _io_fresp_bits_fflags_T_bits_uop_ppred; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_prs1_busy_0 = _io_fresp_bits_fflags_T_bits_uop_prs1_busy; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_prs2_busy_0 = _io_fresp_bits_fflags_T_bits_uop_prs2_busy; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_prs3_busy_0 = _io_fresp_bits_fflags_T_bits_uop_prs3_busy; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ppred_busy_0 = _io_fresp_bits_fflags_T_bits_uop_ppred_busy; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_stale_pdst_0 = _io_fresp_bits_fflags_T_bits_uop_stale_pdst; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_exception_0 = _io_fresp_bits_fflags_T_bits_uop_exception; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_exc_cause_0 = _io_fresp_bits_fflags_T_bits_uop_exc_cause; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_bypassable_0 = _io_fresp_bits_fflags_T_bits_uop_bypassable; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_mem_cmd_0 = _io_fresp_bits_fflags_T_bits_uop_mem_cmd; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_mem_size_0 = _io_fresp_bits_fflags_T_bits_uop_mem_size; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_mem_signed_0 = _io_fresp_bits_fflags_T_bits_uop_mem_signed; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_fence_0 = _io_fresp_bits_fflags_T_bits_uop_is_fence; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_fencei_0 = _io_fresp_bits_fflags_T_bits_uop_is_fencei; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_amo_0 = _io_fresp_bits_fflags_T_bits_uop_is_amo; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_uses_ldq_0 = _io_fresp_bits_fflags_T_bits_uop_uses_ldq; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_uses_stq_0 = _io_fresp_bits_fflags_T_bits_uop_uses_stq; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_sys_pc2epc_0 = _io_fresp_bits_fflags_T_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_is_unique_0 = _io_fresp_bits_fflags_T_bits_uop_is_unique; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_flush_on_commit_0 = _io_fresp_bits_fflags_T_bits_uop_flush_on_commit; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ldst_is_rs1_0 = _io_fresp_bits_fflags_T_bits_uop_ldst_is_rs1; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ldst_0 = _io_fresp_bits_fflags_T_bits_uop_ldst; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_lrs1_0 = _io_fresp_bits_fflags_T_bits_uop_lrs1; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_lrs2_0 = _io_fresp_bits_fflags_T_bits_uop_lrs2; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_lrs3_0 = _io_fresp_bits_fflags_T_bits_uop_lrs3; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_ldst_val_0 = _io_fresp_bits_fflags_T_bits_uop_ldst_val; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_dst_rtype_0 = _io_fresp_bits_fflags_T_bits_uop_dst_rtype; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_lrs1_rtype_0 = _io_fresp_bits_fflags_T_bits_uop_lrs1_rtype; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_lrs2_rtype_0 = _io_fresp_bits_fflags_T_bits_uop_lrs2_rtype; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_frs3_en_0 = _io_fresp_bits_fflags_T_bits_uop_frs3_en; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_fp_val_0 = _io_fresp_bits_fflags_T_bits_uop_fp_val; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_fp_single_0 = _io_fresp_bits_fflags_T_bits_uop_fp_single; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_xcpt_pf_if_0 = _io_fresp_bits_fflags_T_bits_uop_xcpt_pf_if; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_xcpt_ae_if_0 = _io_fresp_bits_fflags_T_bits_uop_xcpt_ae_if; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_xcpt_ma_if_0 = _io_fresp_bits_fflags_T_bits_uop_xcpt_ma_if; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_bp_debug_if_0 = _io_fresp_bits_fflags_T_bits_uop_bp_debug_if; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_bp_xcpt_if_0 = _io_fresp_bits_fflags_T_bits_uop_bp_xcpt_if; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_debug_fsrc_0 = _io_fresp_bits_fflags_T_bits_uop_debug_fsrc; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_uop_debug_tsrc_0 = _io_fresp_bits_fflags_T_bits_uop_debug_tsrc; // @[execution-unit.scala:437:7, :530:30] assign io_fresp_bits_fflags_bits_flags_0 = _io_fresp_bits_fflags_T_bits_flags; // @[execution-unit.scala:437:7, :530:30] wire _queue_io_enq_valid_T_1 = |_queue_io_enq_valid_T; // @[micro-op.scala:154:{40,47}] wire _queue_io_enq_valid_T_2 = _FPUUnit_io_resp_valid & _queue_io_enq_valid_T_1; // @[execution-unit.scala:477:17, :539:52] wire _queue_io_enq_valid_T_3 = _FPUUnit_io_resp_bits_uop_uopc != 7'h2; // @[execution-unit.scala:477:17, :541:60] wire _queue_io_enq_valid_T_4 = _queue_io_enq_valid_T_2 & _queue_io_enq_valid_T_3; // @[execution-unit.scala:539:52, :540:74, :541:60] wire _fp_sdq_io_enq_valid_T = io_req_bits_uop_uopc_0 == 7'h2; // @[execution-unit.scala:437:7, :553:70] wire _fp_sdq_io_enq_valid_T_1 = io_req_valid_0 & _fp_sdq_io_enq_valid_T; // @[execution-unit.scala:437:7, :553:{46,70}] wire [7:0] _fp_sdq_io_enq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _fp_sdq_io_enq_valid_T_3 = |_fp_sdq_io_enq_valid_T_2; // @[util.scala:118:{51,59}] wire _fp_sdq_io_enq_valid_T_4 = ~_fp_sdq_io_enq_valid_T_3; // @[util.scala:118:59] wire _fp_sdq_io_enq_valid_T_5 = _fp_sdq_io_enq_valid_T_1 & _fp_sdq_io_enq_valid_T_4; // @[execution-unit.scala:553:{46,81,84}] wire [11:0] fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp = io_req_bits_rs2_data_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero_0 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial = &_fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] fp_sdq_io_enq_bits_data_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T_1 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial & _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_isNaN = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_1 = ~_fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_2 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isSpecial & _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sign_T = io_req_bits_rs2_data_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_sign = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sExp_T = {1'h0, fp_sdq_io_enq_bits_data_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T = ~fp_sdq_io_enq_bits_data_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_1 = {1'h0, _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_2 = io_req_bits_rs2_data_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_3 = {_fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_1, _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign fp_sdq_io_enq_bits_data_unrecoded_rawIn_sig = _fp_sdq_io_enq_bits_data_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire fp_sdq_io_enq_bits_data_unrecoded_isSubnormal = $signed(fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist = _fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T_1 = _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T >> fp_sdq_io_enq_bits_data_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] fp_sdq_io_enq_bits_data_unrecoded_denormFract = _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_1 = {1'h0, _fp_sdq_io_enq_bits_data_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_2 = _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_3 = fp_sdq_io_enq_bits_data_unrecoded_isSubnormal ? 11'h0 : _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_4 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isNaN | fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_5 = {11{_fp_sdq_io_enq_bits_data_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] fp_sdq_io_enq_bits_data_unrecoded_expOut = _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_3 | _fp_sdq_io_enq_bits_data_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _fp_sdq_io_enq_bits_data_unrecoded_fractOut_T = fp_sdq_io_enq_bits_data_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _fp_sdq_io_enq_bits_data_unrecoded_fractOut_T_1 = fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf ? 52'h0 : _fp_sdq_io_enq_bits_data_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] fp_sdq_io_enq_bits_data_unrecoded_fractOut = fp_sdq_io_enq_bits_data_unrecoded_isSubnormal ? fp_sdq_io_enq_bits_data_unrecoded_denormFract : _fp_sdq_io_enq_bits_data_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] fp_sdq_io_enq_bits_data_unrecoded_hi = {fp_sdq_io_enq_bits_data_unrecoded_rawIn_sign, fp_sdq_io_enq_bits_data_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] fp_sdq_io_enq_bits_data_unrecoded = {fp_sdq_io_enq_bits_data_unrecoded_hi, fp_sdq_io_enq_bits_data_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _fp_sdq_io_enq_bits_data_prevRecoded_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:442:10] wire _fp_sdq_io_enq_bits_data_prevRecoded_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:443:10] wire [30:0] _fp_sdq_io_enq_bits_data_prevRecoded_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:444:10] wire [1:0] fp_sdq_io_enq_bits_data_prevRecoded_hi = {_fp_sdq_io_enq_bits_data_prevRecoded_T, _fp_sdq_io_enq_bits_data_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] fp_sdq_io_enq_bits_data_prevRecoded = {fp_sdq_io_enq_bits_data_prevRecoded_hi, _fp_sdq_io_enq_bits_data_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp = fp_sdq_io_enq_bits_data_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero_0 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial = &_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial & _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isNaN = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_1 = ~_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_2 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial & _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sign_T = fp_sdq_io_enq_bits_data_prevRecoded[32]; // @[FPU.scala:441:28] assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sign = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sExp_T = {1'h0, fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T = ~fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_2 = fp_sdq_io_enq_bits_data_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_3 = {_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_1, _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sig = _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal = $signed(fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist = _fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T_1 = _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T >> fp_sdq_io_enq_bits_data_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract = _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_1 = {1'h0, _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_2 = _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_3 = fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal ? 8'h0 : _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_4 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isNaN | fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_5 = {8{_fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] fp_sdq_io_enq_bits_data_prevUnrecoded_expOut = _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_3 | _fp_sdq_io_enq_bits_data_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut_T = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut_T_1 = fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf ? 23'h0 : _fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut = fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal ? fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract : _fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] fp_sdq_io_enq_bits_data_prevUnrecoded_hi = {fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_sign, fp_sdq_io_enq_bits_data_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] fp_sdq_io_enq_bits_data_prevUnrecoded = {fp_sdq_io_enq_bits_data_prevUnrecoded_hi, fp_sdq_io_enq_bits_data_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _fp_sdq_io_enq_bits_data_T = fp_sdq_io_enq_bits_data_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _fp_sdq_io_enq_bits_data_T_1 = io_req_bits_rs2_data_0[63:61]; // @[FPU.scala:249:25] wire _fp_sdq_io_enq_bits_data_T_2 = &_fp_sdq_io_enq_bits_data_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _fp_sdq_io_enq_bits_data_T_3 = fp_sdq_io_enq_bits_data_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _fp_sdq_io_enq_bits_data_T_4 = _fp_sdq_io_enq_bits_data_T_2 ? fp_sdq_io_enq_bits_data_prevUnrecoded : _fp_sdq_io_enq_bits_data_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _fp_sdq_io_enq_bits_data_T_5 = {_fp_sdq_io_enq_bits_data_T, _fp_sdq_io_enq_bits_data_T_4}; // @[FPU.scala:446:{10,21,44}]
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File functional-unit.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Functional Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // If regfile bypassing is disabled, then the functional unit must do its own // bypassing in here on the WB stage (i.e., bypassing the io.resp.data) // // TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass? package boom.v3.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ import freechips.rocketchip.tile import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR} import boom.v3.common._ import boom.v3.ifu._ import boom.v3.util._ /**t * Functional unit constants */ object FUConstants { // bit mask, since a given execution pipeline may support multiple functional units val FUC_SZ = 10 val FU_X = BitPat.dontCare(FUC_SZ) val FU_ALU = 1.U(FUC_SZ.W) val FU_JMP = 2.U(FUC_SZ.W) val FU_MEM = 4.U(FUC_SZ.W) val FU_MUL = 8.U(FUC_SZ.W) val FU_DIV = 16.U(FUC_SZ.W) val FU_CSR = 32.U(FUC_SZ.W) val FU_FPU = 64.U(FUC_SZ.W) val FU_FDV = 128.U(FUC_SZ.W) val FU_I2F = 256.U(FUC_SZ.W) val FU_F2I = 512.U(FUC_SZ.W) // FP stores generate data through FP F2I, and generate address through MemAddrCalc val FU_F2IMEM = 516.U(FUC_SZ.W) } import FUConstants._ /** * Class to tell the FUDecoders what units it needs to support * * @param alu support alu unit? * @param bru support br unit? * @param mem support mem unit? * @param muld support multiple div unit? * @param fpu support FP unit? * @param csr support csr writing unit? * @param fdiv support FP div unit? * @param ifpu support int to FP unit? */ class SupportedFuncUnits( val alu: Boolean = false, val jmp: Boolean = false, val mem: Boolean = false, val muld: Boolean = false, val fpu: Boolean = false, val csr: Boolean = false, val fdiv: Boolean = false, val ifpu: Boolean = false) { } /** * Bundle for signals sent to the functional unit * * @param dataWidth width of the data sent to the functional unit */ class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val numOperands = 3 val rs1_data = UInt(dataWidth.W) val rs2_data = UInt(dataWidth.W) val rs3_data = UInt(dataWidth.W) // only used for FMA units val pred_data = Bool() val kill = Bool() // kill everything } /** * Bundle for the signals sent out of the function unit * * @param dataWidth data sent from the functional unit */ class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val predicated = Bool() // Was this response from a predicated-off instruction val data = UInt(dataWidth.W) val fflags = new ValidIO(new FFlagsResp) val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc } /** * Branch resolution information given from the branch unit */ class BrResolutionInfo(implicit p: Parameters) extends BoomBundle { val uop = new MicroOp val valid = Bool() val mispredict = Bool() val taken = Bool() // which direction did the branch go? val cfi_type = UInt(CFI_SZ.W) // Info for recalculating the pc for this branch val pc_sel = UInt(2.W) val jalr_target = UInt(vaddrBitsExtended.W) val target_offset = SInt() } class BrUpdateInfo(implicit p: Parameters) extends BoomBundle { // On the first cycle we get masks to kill registers val b1 = new BrUpdateMasks // On the second cycle we get indices to reset pointers val b2 = new BrResolutionInfo } class BrUpdateMasks(implicit p: Parameters) extends BoomBundle { val resolve_mask = UInt(maxBrCount.W) val mispredict_mask = UInt(maxBrCount.W) } /** * Abstract top level functional unit class that wraps a lower level hand made functional unit * * @param isPipelined is the functional unit pipelined? * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? */ abstract class FunctionalUnit( val isPipelined: Boolean, val numStages: Int, val numBypassStages: Int, val dataWidth: Int, val isJmpUnit: Boolean = false, val isAluUnit: Boolean = false, val isMemAddrCalcUnit: Boolean = false, val needsFcsr: Boolean = false) (implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val resp = (new DecoupledIO(new FuncUnitResp(dataWidth))) val brupdate = Input(new BrUpdateInfo()) val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth)))) // only used by the fpu unit val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null // only used by branch unit val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null // only used by memaddr calc unit val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null }) io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare } io.resp.valid := false.B io.resp.bits := DontCare if (isJmpUnit) { io.get_ftq_pc.ftq_idx := DontCare } } /** * Abstract top level pipelined functional unit * * Note: this helps track which uops get killed while in intermediate stages, * but it is the job of the consumer to check for kills on the same cycle as consumption!!! * * @param numStages how many pipeline stages does the functional unit have * @param numBypassStages how many bypass stages does the function unit have * @param earliestBypassStage first stage that you can start bypassing from * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? */ abstract class PipelinedFunctionalUnit( numStages: Int, numBypassStages: Int, earliestBypassStage: Int, dataWidth: Int, isJmpUnit: Boolean = false, isAluUnit: Boolean = false, isMemAddrCalcUnit: Boolean = false, needsFcsr: Boolean = false )(implicit p: Parameters) extends FunctionalUnit( isPipelined = true, numStages = numStages, numBypassStages = numBypassStages, dataWidth = dataWidth, isJmpUnit = isJmpUnit, isAluUnit = isAluUnit, isMemAddrCalcUnit = isMemAddrCalcUnit, needsFcsr = needsFcsr) { // Pipelined functional unit is always ready. io.req.ready := true.B if (numStages > 0) { val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_uops = Reg(Vec(numStages, new MicroOp())) // handle incoming request r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill r_uops(0) := io.req.bits.uop r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) // handle middle of the pipeline for (i <- 1 until numStages) { r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill r_uops(i) := r_uops(i-1) r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1)) if (numBypassStages > 0) { io.bypass(i-1).bits.uop := r_uops(i-1) } } // handle outgoing (branch could still kill it) // consumer must also check for pipeline flushes (kills) io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1)) io.resp.bits.predicated := false.B io.resp.bits.uop := r_uops(numStages-1) io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1)) // bypassing (TODO allow bypass vector to have a different size from numStages) if (numBypassStages > 0 && earliestBypassStage == 0) { io.bypass(0).bits.uop := io.req.bits.uop for (i <- 1 until numBypassStages) { io.bypass(i).bits.uop := r_uops(i-1) } } } else { require (numStages == 0) // pass req straight through to response // valid doesn't check kill signals, let consumer deal with it. // The LSU already handles it and this hurts critical path. io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) io.resp.bits.predicated := false.B io.resp.bits.uop := io.req.bits.uop io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } } /** * Functional unit that wraps RocketChips ALU * * @param isBranchUnit is this a branch unit? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit */ class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = numStages, isAluUnit = true, earliestBypassStage = 0, dataWidth = dataWidth, isJmpUnit = isJmpUnit) with boom.v3.ifu.HasBoomFrontendParameters { val uop = io.req.bits.uop // immediate generation val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel) // operand 1 select var op1_data: UInt = null if (isJmpUnit) { // Get the uop PC for jumps val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes) val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U) op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen), 0.U)) } else { op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data, 0.U) } // operand 2 select val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen), Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0), Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data, Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U), 0.U)))) val alu = Module(new freechips.rocketchip.rocket.ALU()) alu.io.in1 := op1_data.asUInt alu.io.in2 := op2_data.asUInt alu.io.fn := uop.ctrl.op_fcn alu.io.dw := uop.ctrl.fcn_dw // Did I just get killed by the previous cycle's branch, // or by a flush pipeline? val killed = WireInit(false.B) when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) { killed := true.B } val rs1 = io.req.bits.rs1_data val rs2 = io.req.bits.rs2_data val br_eq = (rs1 === rs2) val br_ltu = (rs1.asUInt < rs2.asUInt) val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu | rs1(xLen-1) & ~rs2(xLen-1)).asBool val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)( Seq( BR_N -> PC_PLUS4, BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4), BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4), BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4), BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4), BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4), BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4), BR_J -> PC_BRJMP, BR_JR -> PC_JALR )) val is_taken = io.req.valid && !killed && (uop.is_br || uop.is_jalr || uop.is_jal) && (pc_sel =/= PC_PLUS4) // "mispredict" means that a branch has been resolved and it must be killed val mispredict = WireInit(false.B) val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb val is_jal = io.req.valid && !killed && uop.is_jal val is_jalr = io.req.valid && !killed && uop.is_jalr when (is_br || is_jalr) { if (!isJmpUnit) { assert (pc_sel =/= PC_JALR) } when (pc_sel === PC_PLUS4) { mispredict := uop.taken } when (pc_sel === PC_BRJMP) { mispredict := !uop.taken } } val brinfo = Wire(new BrResolutionInfo) // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit brinfo.valid := is_br || is_jalr brinfo.mispredict := mispredict brinfo.uop := uop brinfo.cfi_type := Mux(is_jalr, CFI_JALR, Mux(is_br , CFI_BR, CFI_X)) brinfo.taken := is_taken brinfo.pc_sel := pc_sel brinfo.jalr_target := DontCare // Branch/Jump Target Calculation // For jumps we read the FTQ, and can calculate the target // For branches we emit the offset for the core to redirect if necessary val target_offset = imm_xprlen(20,0).asSInt brinfo.jalr_target := DontCare if (isJmpUnit) { def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } val jalr_target_base = io.req.bits.rs1_data.asSInt val jalr_target_xlen = Wire(UInt(xLen.W)) jalr_target_xlen := (jalr_target_base + target_offset).asUInt val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt brinfo.jalr_target := jalr_target val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1) when (pc_sel === PC_JALR) { mispredict := !io.get_ftq_pc.next_val || (io.get_ftq_pc.next_pc =/= jalr_target) || !io.get_ftq_pc.entry.cfi_idx.valid || (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx) } } brinfo.target_offset := target_offset io.brinfo := brinfo // Response // TODO add clock gate on resp bits from functional units // io.resp.bits.data := RegEnable(alu.io.out, io.req.valid) // val reg_data = Reg(outType = Bits(width = xLen)) // reg_data := alu.io.out // io.resp.bits.data := reg_data val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B })) val r_data = Reg(Vec(numStages, UInt(xLen.W))) val r_pred = Reg(Vec(numStages, Bool())) val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data, Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data), Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out)) r_val (0) := io.req.valid r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data for (i <- 1 until numStages) { r_val(i) := r_val(i-1) r_data(i) := r_data(i-1) r_pred(i) := r_pred(i-1) } io.resp.bits.data := r_data(numStages-1) io.resp.bits.predicated := r_pred(numStages-1) // Bypass // for the ALU, we can bypass same cycle as compute require (numStages >= 1) require (numBypassStages >= 1) io.bypass(0).valid := io.req.valid io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) for (i <- 1 until numStages) { io.bypass(i).valid := r_val(i-1) io.bypass(i).bits.data := r_data(i-1) } // Exceptions io.resp.bits.fflags.valid := false.B } /** * Functional unit that passes in base+imm to calculate addresses, and passes store data * to the LSU. * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form */ class MemAddrCalcUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = 0, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, // TODO enable this only if FP is enabled? isMemAddrCalcUnit = true) with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { // perform address calculation val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U, sum(63,vaddrBits) =/= 0.U) val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt val store_data = io.req.bits.rs2_data io.resp.bits.addr := effective_address io.resp.bits.data := store_data if (dataWidth > 63) { assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.") assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val), "FP store-data should now be going through a different unit.") } assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/= uopLD && io.req.bits.uop.uopc =/= uopSTA), "[maddrcalc] assert we never get store data in here.") // Handle misaligned exceptions val size = io.req.bits.uop.mem_size val misaligned = (size === 1.U && (effective_address(0) =/= 0.U)) || (size === 2.U && (effective_address(1,0) =/= 0.U)) || (size === 3.U && (effective_address(2,0) =/= 0.U)) val bkptu = Module(new BreakpointUnit(nBreakpoints)) bkptu.io.status := io.status bkptu.io.bp := io.bp bkptu.io.pc := DontCare bkptu.io.ea := effective_address bkptu.io.mcontext := io.mcontext bkptu.io.scontext := io.scontext val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) || (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st)) val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) || (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st)) def checkExceptions(x: Seq[(Bool, UInt)]) = (x.map(_._1).reduce(_||_), PriorityMux(x)) val (xcpt_val, xcpt_cause) = checkExceptions(List( (ma_ld, (Causes.misaligned_load).U), (ma_st, (Causes.misaligned_store).U), (dbg_bp, (CSR.debugTriggerCause).U), (bp, (Causes.breakpoint).U))) io.resp.bits.mxcpt.valid := xcpt_val io.resp.bits.mxcpt.bits := xcpt_cause assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.") io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0) io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1) io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data } /** * Functional unit to wrap lower level FPU * * Currently, bypassing is unsupported! * All FP instructions are padded out to the max latency unit for easy * write-port scheduling. */ class FPUUnit(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = p(tile.TileKey).core.fpu.get.dfmaLatency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) { val fpu = Module(new FPU()) fpu.io.req.valid := io.req.valid fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.fcsr_rm := io.fcsr_rm io.resp.bits.data := fpu.io.resp.bits.data io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now } /** * Int to FP conversion functional unit * * @param latency the amount of stages to delay by */ class IntToFPUnit(latency: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = latency, numBypassStages = 0, earliestBypassStage = 0, dataWidth = 65, needsFcsr = true) with tile.HasFPUParameters { val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder val io_req = io.req.bits fp_decoder.io.uopc := io_req.uop.uopc val fp_ctrl = fp_decoder.io.sigs val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed)) val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, None) req.in2 := unbox(io_req.rs2_data, tag, None) req.in3 := DontCare req.typ := ImmGenTyp(io_req.uop.imm_packed) req.fmt := DontCare // FIXME: this may not be the right thing to do here req.fmaCmd := DontCare assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool), "[func] IntToFP integer input has 65th high-order bit set!") assert (!(io.req.valid && !fp_ctrl.fromint), "[func] Only support fromInt micro-ops.") val ifpu = Module(new tile.IntToFP(intToFpLatency)) ifpu.io.in.valid := io.req.valid ifpu.io.in.bits := req ifpu.io.in.bits.in1 := io_req.rs1_data val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits //io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single) io.resp.bits.data := box(ifpu.io.out.bits.data, out_double) io.resp.bits.fflags.valid := ifpu.io.out.valid io.resp.bits.fflags.bits.uop := io.resp.bits.uop io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc } /** * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time * assumes at least one register between request and response * * TODO allow up to N micro-ops simultaneously. * * @param dataWidth width of the data to be passed into the functional unit */ abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit( isPipelined = false, numStages = 1, numBypassStages = 0, dataWidth = dataWidth) { val r_uop = Reg(new MicroOp()) val do_kill = Wire(Bool()) do_kill := io.req.bits.kill // irrelevant default when (io.req.fire) { // update incoming uop do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill r_uop := io.req.bits.uop r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop) } .otherwise { do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop) } // assumes at least one pipeline register between request and response io.resp.bits.uop := r_uop } /** * Divide functional unit. * * @param dataWidth data to be passed into the functional unit */ class DivUnit(dataWidth: Int)(implicit p: Parameters) extends IterativeFunctionalUnit(dataWidth) { // We don't use the iterative multiply functionality here. // Instead we use the PipelinedMultiplier val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth)) // request div.io.req.valid := io.req.valid && !this.do_kill div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn div.io.req.bits.in1 := io.req.bits.rs1_data div.io.req.bits.in2 := io.req.bits.rs2_data div.io.req.bits.tag := DontCare io.req.ready := div.io.req.ready // handle pipeline kills and branch misspeculations div.io.kill := this.do_kill // response io.resp.valid := div.io.resp.valid && !this.do_kill div.io.resp.ready := io.resp.ready io.resp.bits.data := div.io.resp.bits.data } /** * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier * * @param numStages number of pipeline stages * @param dataWidth size of the data being passed into the functional unit */ class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters) extends PipelinedFunctionalUnit( numStages = numStages, numBypassStages = 0, earliestBypassStage = 0, dataWidth = dataWidth) { val imul = Module(new PipelinedMultiplier(xLen, numStages)) // request imul.io.req.valid := io.req.valid imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw imul.io.req.bits.in1 := io.req.bits.rs1_data imul.io.req.bits.in2 := io.req.bits.rs2_data imul.io.req.bits.tag := DontCare // response io.resp.bits.data := imul.io.resp.bits.data } File micro-op.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // MicroOp //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.exu.FUConstants /** * Extension to BoomBundle to add a MicroOp */ abstract trait HasBoomUOP extends BoomBundle { val uop = new MicroOp() } /** * MicroOp passing through the pipeline */ class MicroOp(implicit p: Parameters) extends BoomBundle with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val uopc = UInt(UOPC_SZ.W) // micro-op code val inst = UInt(32.W) val debug_inst = UInt(32.W) val is_rvc = Bool() val debug_pc = UInt(coreMaxAddrBits.W) val iq_type = UInt(IQT_SZ.W) // which issue unit do we use? val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use? val ctrl = new CtrlSignals // What is the next state of this uop in the issue window? useful // for the compacting queue. val iw_state = UInt(2.W) // Has operand 1 or 2 been waken speculatively by a load? // Only integer operands are speculaively woken up, // so we can ignore p3. val iw_p1_poisoned = Bool() val iw_p2_poisoned = Bool() val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst? val is_jalr = Bool() // is this a jump? (jal or jalr) val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit val is_sfb = Bool() // is this a sfb or in the shadow of a sfb val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under? val br_tag = UInt(brTagSz.W) // Index into FTQ to figure out our fetch PC. val ftq_idx = UInt(log2Ceil(ftqSz).W) // This inst straddles two fetch packets val edge_inst = Bool() // Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC. // Aligned to a cache-line size, as that is the greater fetch granularity. // TODO: Shouldn't this be aligned to fetch-width size? val pc_lob = UInt(log2Ceil(icBlockBytes).W) // Was this a branch that was predicted taken? val taken = Bool() val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode... // then translate and sign-extend in execute val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe val rob_idx = UInt(robAddrSz.W) val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) val pdst = UInt(maxPregSz.W) val prs1 = UInt(maxPregSz.W) val prs2 = UInt(maxPregSz.W) val prs3 = UInt(maxPregSz.W) val ppred = UInt(log2Ceil(ftqSz).W) val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() val ppred_busy = Bool() val stale_pdst = UInt(maxPregSz.W) val exception = Bool() val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...) val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes val mem_size = UInt(2.W) val mem_signed = Bool() val is_fence = Bool() val is_fencei = Bool() val is_amo = Bool() val uses_ldq = Bool() val uses_stq = Bool() val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC. val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to // drain, clear fetcha fter it (tell ROB to un-ready until empty) val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them // Preditation def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst, // else copy rs2 to dst // logical specifiers (only used in Decode->Rename), except rollback (ldst) val ldst = UInt(lregSz.W) val lrs1 = UInt(lregSz.W) val lrs2 = UInt(lregSz.W) val lrs3 = UInt(lregSz.W) val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc. val dst_rtype = UInt(2.W) val lrs1_rtype = UInt(2.W) val lrs2_rtype = UInt(2.W) val frs3_en = Bool() // floating point information val fp_val = Bool() // is a floating-point instruction (F- or D-extension)? // If it's non-ld/st it will write back exception bits to the fcsr. val fp_single = Bool() // single-precision floating point instruction (F-extension) // frontend exception information val xcpt_pf_if = Bool() // I-TLB page fault. val xcpt_ae_if = Bool() // I$ access exception. val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr). val bp_debug_if = Bool() // Breakpoint val bp_xcpt_if = Bool() // Breakpoint // What prediction structure provides the prediction FROM this op val debug_fsrc = UInt(BSRC_SZ.W) // What prediction structure provides the prediction TO this op val debug_tsrc = UInt(BSRC_SZ.W) // Do we allocate a branch tag for this? // SFB branches don't get a mask, they get a predicate bit def allocate_brtag = (is_br && !is_sfb) || is_jalr // Does this register write-back def rf_wen = dst_rtype =/= RT_X // Is it possible for this uop to misspeculate, preventing the commit of subsequent uops? def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U } /** * Control signals within a MicroOp * * TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution */ class CtrlSignals extends Bundle() { val br_type = UInt(BR_N.getWidth.W) val op1_sel = UInt(OP1_X.getWidth.W) val op2_sel = UInt(OP2_X.getWidth.W) val imm_sel = UInt(IS_X.getWidth.W) val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W) val fcn_dw = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val is_load = Bool() // will invoke TLB address lookup val is_sta = Bool() // will invoke TLB address lookup val is_std = Bool() }
module ALUUnit_2( // @[functional-unit.scala:290:7] input clock, // @[functional-unit.scala:290:7] input reset, // @[functional-unit.scala:290:7] input io_req_valid, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14] input io_req_bits_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_req_bits_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14] input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14] input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14] input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14] input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14] input io_req_bits_kill, // @[functional-unit.scala:168:14] output io_resp_valid, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [63:0] io_resp_bits_data, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14] input io_brupdate_b2_valid, // @[functional-unit.scala:168:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14] input io_brupdate_b2_taken, // @[functional-unit.scala:168:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14] input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14] output io_bypass_0_valid, // @[functional-unit.scala:168:14] output [6:0] io_bypass_0_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_bypass_0_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_bypass_0_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_bypass_0_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_bypass_0_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_bypass_0_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_bypass_0_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_bypass_0_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_bypass_0_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_bypass_0_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_bypass_0_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_bypass_0_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_bypass_0_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_bypass_0_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_bypass_0_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_bypass_0_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_bypass_0_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_bypass_0_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_bypass_0_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_bypass_0_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_bypass_0_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_bypass_0_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_bypass_0_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_bypass_0_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_bypass_0_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_bypass_0_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_bypass_0_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [63:0] io_bypass_0_bits_data, // @[functional-unit.scala:168:14] output io_bypass_1_valid, // @[functional-unit.scala:168:14] output [6:0] io_bypass_1_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_bypass_1_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_bypass_1_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_bypass_1_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_bypass_1_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_bypass_1_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_bypass_1_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_bypass_1_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_bypass_1_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_bypass_1_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_bypass_1_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_bypass_1_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_bypass_1_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_bypass_1_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_bypass_1_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_bypass_1_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_bypass_1_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_bypass_1_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_bypass_1_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_bypass_1_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_bypass_1_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_bypass_1_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_bypass_1_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_bypass_1_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_bypass_1_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_bypass_1_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_bypass_1_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_bypass_1_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_bypass_1_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_bypass_1_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_bypass_1_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_bypass_1_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_bypass_1_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [63:0] io_bypass_1_bits_data, // @[functional-unit.scala:168:14] output io_bypass_2_valid, // @[functional-unit.scala:168:14] output [6:0] io_bypass_2_bits_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_bypass_2_bits_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_bypass_2_bits_uop_debug_inst, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_bypass_2_bits_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_bypass_2_bits_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_bypass_2_bits_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_bypass_2_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_bypass_2_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_bypass_2_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_bypass_2_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_iw_state, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_br, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_jalr, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_jal, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_bypass_2_bits_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_bypass_2_bits_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_bypass_2_bits_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_bypass_2_bits_uop_pc_lob, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_bypass_2_bits_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_bypass_2_bits_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_bypass_2_bits_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_bypass_2_bits_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_bypass_2_bits_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_bypass_2_bits_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_bypass_2_bits_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_bypass_2_bits_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_bypass_2_bits_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_bypass_2_bits_uop_ppred, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_bypass_2_bits_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_bypass_2_bits_uop_exc_cause, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_bypass_2_bits_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_mem_size, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_mem_signed, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_fence, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_fencei, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_amo, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_uses_stq, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_is_unique, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_bypass_2_bits_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_bypass_2_bits_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_bypass_2_bits_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_bypass_2_bits_uop_lrs3, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_frs3_en, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_fp_val, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_fp_single, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_bypass_2_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_bypass_2_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14] output [63:0] io_bypass_2_bits_data, // @[functional-unit.scala:168:14] output [6:0] io_brinfo_uop_uopc, // @[functional-unit.scala:168:14] output [31:0] io_brinfo_uop_inst, // @[functional-unit.scala:168:14] output [31:0] io_brinfo_uop_debug_inst, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_rvc, // @[functional-unit.scala:168:14] output [39:0] io_brinfo_uop_debug_pc, // @[functional-unit.scala:168:14] output [2:0] io_brinfo_uop_iq_type, // @[functional-unit.scala:168:14] output [9:0] io_brinfo_uop_fu_code, // @[functional-unit.scala:168:14] output [3:0] io_brinfo_uop_ctrl_br_type, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14] output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14] output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14] output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14] output io_brinfo_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14] output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14] output io_brinfo_uop_ctrl_is_load, // @[functional-unit.scala:168:14] output io_brinfo_uop_ctrl_is_sta, // @[functional-unit.scala:168:14] output io_brinfo_uop_ctrl_is_std, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_iw_state, // @[functional-unit.scala:168:14] output io_brinfo_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14] output io_brinfo_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_br, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_jalr, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_jal, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_sfb, // @[functional-unit.scala:168:14] output [15:0] io_brinfo_uop_br_mask, // @[functional-unit.scala:168:14] output [3:0] io_brinfo_uop_br_tag, // @[functional-unit.scala:168:14] output [4:0] io_brinfo_uop_ftq_idx, // @[functional-unit.scala:168:14] output io_brinfo_uop_edge_inst, // @[functional-unit.scala:168:14] output [5:0] io_brinfo_uop_pc_lob, // @[functional-unit.scala:168:14] output io_brinfo_uop_taken, // @[functional-unit.scala:168:14] output [19:0] io_brinfo_uop_imm_packed, // @[functional-unit.scala:168:14] output [11:0] io_brinfo_uop_csr_addr, // @[functional-unit.scala:168:14] output [6:0] io_brinfo_uop_rob_idx, // @[functional-unit.scala:168:14] output [4:0] io_brinfo_uop_ldq_idx, // @[functional-unit.scala:168:14] output [4:0] io_brinfo_uop_stq_idx, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_rxq_idx, // @[functional-unit.scala:168:14] output [6:0] io_brinfo_uop_pdst, // @[functional-unit.scala:168:14] output [6:0] io_brinfo_uop_prs1, // @[functional-unit.scala:168:14] output [6:0] io_brinfo_uop_prs2, // @[functional-unit.scala:168:14] output [6:0] io_brinfo_uop_prs3, // @[functional-unit.scala:168:14] output [4:0] io_brinfo_uop_ppred, // @[functional-unit.scala:168:14] output io_brinfo_uop_prs1_busy, // @[functional-unit.scala:168:14] output io_brinfo_uop_prs2_busy, // @[functional-unit.scala:168:14] output io_brinfo_uop_prs3_busy, // @[functional-unit.scala:168:14] output io_brinfo_uop_ppred_busy, // @[functional-unit.scala:168:14] output [6:0] io_brinfo_uop_stale_pdst, // @[functional-unit.scala:168:14] output io_brinfo_uop_exception, // @[functional-unit.scala:168:14] output [63:0] io_brinfo_uop_exc_cause, // @[functional-unit.scala:168:14] output io_brinfo_uop_bypassable, // @[functional-unit.scala:168:14] output [4:0] io_brinfo_uop_mem_cmd, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_mem_size, // @[functional-unit.scala:168:14] output io_brinfo_uop_mem_signed, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_fence, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_fencei, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_amo, // @[functional-unit.scala:168:14] output io_brinfo_uop_uses_ldq, // @[functional-unit.scala:168:14] output io_brinfo_uop_uses_stq, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14] output io_brinfo_uop_is_unique, // @[functional-unit.scala:168:14] output io_brinfo_uop_flush_on_commit, // @[functional-unit.scala:168:14] output io_brinfo_uop_ldst_is_rs1, // @[functional-unit.scala:168:14] output [5:0] io_brinfo_uop_ldst, // @[functional-unit.scala:168:14] output [5:0] io_brinfo_uop_lrs1, // @[functional-unit.scala:168:14] output [5:0] io_brinfo_uop_lrs2, // @[functional-unit.scala:168:14] output [5:0] io_brinfo_uop_lrs3, // @[functional-unit.scala:168:14] output io_brinfo_uop_ldst_val, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_dst_rtype, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_lrs1_rtype, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_lrs2_rtype, // @[functional-unit.scala:168:14] output io_brinfo_uop_frs3_en, // @[functional-unit.scala:168:14] output io_brinfo_uop_fp_val, // @[functional-unit.scala:168:14] output io_brinfo_uop_fp_single, // @[functional-unit.scala:168:14] output io_brinfo_uop_xcpt_pf_if, // @[functional-unit.scala:168:14] output io_brinfo_uop_xcpt_ae_if, // @[functional-unit.scala:168:14] output io_brinfo_uop_xcpt_ma_if, // @[functional-unit.scala:168:14] output io_brinfo_uop_bp_debug_if, // @[functional-unit.scala:168:14] output io_brinfo_uop_bp_xcpt_if, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_debug_fsrc, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_uop_debug_tsrc, // @[functional-unit.scala:168:14] output io_brinfo_valid, // @[functional-unit.scala:168:14] output io_brinfo_mispredict, // @[functional-unit.scala:168:14] output io_brinfo_taken, // @[functional-unit.scala:168:14] output [2:0] io_brinfo_cfi_type, // @[functional-unit.scala:168:14] output [1:0] io_brinfo_pc_sel, // @[functional-unit.scala:168:14] output [20:0] io_brinfo_target_offset // @[functional-unit.scala:168:14] ); wire [63:0] _alu_io_out; // @[functional-unit.scala:327:19] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:290:7] wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:290:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:290:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:290:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:290:7] wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:290:7] wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:290:7] wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:290:7] wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:290:7] wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:290:7] wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:290:7] wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:290:7] wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:290:7] wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:290:7] wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:290:7] wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:290:7] wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:290:7] wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:290:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:290:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:290:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:290:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:290:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:290:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:290:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:290:7] wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:290:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:290:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:290:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:290:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:290:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:290:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:290:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:290:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:290:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:290:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:290:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:290:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:290:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:290:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:290:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:290:7] wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:290:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:290:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:290:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:290:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:290:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:290:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:290:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:290:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:290:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:290:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:290:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:290:7] wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:290:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:290:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:290:7] wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:290:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:290:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:290:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:290:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:290:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:290:7] wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:290:7] wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:290:7] wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:290:7] wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:290:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:290:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:290:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:290:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:290:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:290:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:290:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:290:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:290:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:290:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:290:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:290:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:290:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:290:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:290:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:290:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:290:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:290:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:290:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:290:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:290:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:290:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:290:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:290:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:290:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:290:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:290:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:290:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:290:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:290:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:290:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:290:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:290:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:290:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:290:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:290:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:290:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:290:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:290:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:290:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:290:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:290:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:290:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_ready = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:290:7] wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_predicated = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_predicated = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_predicated = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7] wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35] wire _r_valids_WIRE_2 = 1'h0; // @[functional-unit.scala:236:35] wire _r_val_WIRE_0 = 1'h0; // @[functional-unit.scala:446:31] wire _r_val_WIRE_1 = 1'h0; // @[functional-unit.scala:446:31] wire _r_val_WIRE_2 = 1'h0; // @[functional-unit.scala:446:31] wire _alu_out_T_2 = 1'h0; // @[micro-op.scala:110:43] wire _alu_out_T_3 = 1'h0; // @[functional-unit.scala:449:51] wire _r_data_0_T_1 = 1'h0; // @[micro-op.scala:109:42] wire _r_pred_0_T_2 = 1'h0; // @[micro-op.scala:110:43] wire _r_pred_0_T_3 = 1'h0; // @[functional-unit.scala:454:46] wire _io_bypass_0_bits_data_T_1 = 1'h0; // @[micro-op.scala:109:42] wire io_req_ready = 1'h1; // @[functional-unit.scala:290:7] wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:290:7] wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7] wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7] wire [63:0] io_bypass_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7] wire [63:0] io_bypass_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:290:7] wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7] wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_1_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_2_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7] wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7] wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:290:7] wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7] wire [39:0] io_bypass_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7] wire [39:0] io_bypass_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7] wire [39:0] io_brinfo_jalr_target = 40'h0; // @[functional-unit.scala:290:7] wire [39:0] brinfo_jalr_target = 40'h0; // @[functional-unit.scala:385:20] wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7] wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7] wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7] wire [9:0] io_bypass_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7] wire [9:0] io_bypass_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7] wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7] wire [3:0] io_resp_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7] wire [1:0] _pc_sel_T_10 = 2'h0; // @[functional-unit.scala:349:53] wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7] wire [15:0] io_resp_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:290:7] wire [15:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:290:7] wire [15:0] io_bypass_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:290:7] wire [15:0] io_bypass_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7] wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7] wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7] wire [19:0] io_bypass_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7] wire [19:0] io_bypass_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7] wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7] wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7] wire [11:0] io_bypass_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7] wire [11:0] io_bypass_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7] wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:290:7] wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:290:7] wire io_bypass_0_valid_0 = io_req_valid_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_0_bits_uop_uopc_0 = io_req_bits_uop_uopc_0; // @[functional-unit.scala:290:7] wire [6:0] brinfo_uop_uopc = io_req_bits_uop_uopc_0; // @[functional-unit.scala:290:7, :385:20] wire [31:0] io_bypass_0_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:290:7] wire [31:0] brinfo_uop_inst = io_req_bits_uop_inst_0; // @[functional-unit.scala:290:7, :385:20] wire [31:0] io_bypass_0_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7] wire [31:0] brinfo_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7, :385:20] wire [39:0] io_bypass_0_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7] wire [39:0] brinfo_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7, :385:20] wire [2:0] io_bypass_0_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:290:7] wire [2:0] brinfo_uop_iq_type = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:290:7, :385:20] wire [9:0] io_bypass_0_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:290:7] wire [9:0] brinfo_uop_fu_code = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:290:7, :385:20] wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7] wire [3:0] brinfo_uop_ctrl_br_type = io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_ctrl_op1_sel = io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7, :385:20] wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7] wire [2:0] brinfo_uop_ctrl_op2_sel = io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7, :385:20] wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7] wire [2:0] brinfo_uop_ctrl_imm_sel = io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7, :385:20] wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7] wire [4:0] brinfo_uop_ctrl_op_fcn = io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7] wire brinfo_uop_ctrl_fcn_dw = io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7, :385:20] wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7] wire [2:0] brinfo_uop_ctrl_csr_cmd = io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7] wire brinfo_uop_ctrl_is_load = io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7] wire brinfo_uop_ctrl_is_sta = io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7] wire brinfo_uop_ctrl_is_std = io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_iw_state_0 = io_req_bits_uop_iw_state_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_iw_state = io_req_bits_uop_iw_state_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7] wire brinfo_uop_iw_p1_poisoned = io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7] wire brinfo_uop_iw_p2_poisoned = io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_br_0 = io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_br = io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_jalr = io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_jal_0 = io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_jal = io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7, :385:20] wire [15:0] io_bypass_0_bits_uop_br_mask_0 = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:290:7] wire [15:0] brinfo_uop_br_mask = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:290:7, :385:20] wire [3:0] io_bypass_0_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:290:7] wire [3:0] brinfo_uop_br_tag = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:290:7, :385:20] wire [4:0] io_bypass_0_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7] wire [4:0] brinfo_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7] wire brinfo_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7, :385:20] wire [5:0] io_bypass_0_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7] wire [5:0] brinfo_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:290:7] wire brinfo_uop_taken = io_req_bits_uop_taken_0; // @[functional-unit.scala:290:7, :385:20] wire [19:0] io_bypass_0_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7] wire [19:0] brinfo_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7, :385:20] wire [11:0] io_bypass_0_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7] wire [11:0] brinfo_uop_csr_addr = io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7, :385:20] wire [6:0] io_bypass_0_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7] wire [6:0] brinfo_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7, :385:20] wire [4:0] io_bypass_0_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7] wire [4:0] brinfo_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7, :385:20] wire [4:0] io_bypass_0_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7] wire [4:0] brinfo_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7, :385:20] wire [6:0] io_bypass_0_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:290:7] wire [6:0] brinfo_uop_pdst = io_req_bits_uop_pdst_0; // @[functional-unit.scala:290:7, :385:20] wire [6:0] io_bypass_0_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:290:7] wire [6:0] brinfo_uop_prs1 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:290:7, :385:20] wire [6:0] io_bypass_0_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:290:7] wire [6:0] brinfo_uop_prs2 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:290:7, :385:20] wire [6:0] io_bypass_0_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:290:7] wire [6:0] brinfo_uop_prs3 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:290:7, :385:20] wire [4:0] io_bypass_0_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:290:7] wire [4:0] brinfo_uop_ppred = io_req_bits_uop_ppred_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7] wire brinfo_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7] wire brinfo_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7] wire brinfo_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7] wire brinfo_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7, :385:20] wire [6:0] io_bypass_0_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7] wire [6:0] brinfo_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:290:7] wire brinfo_uop_exception = io_req_bits_uop_exception_0; // @[functional-unit.scala:290:7, :385:20] wire [63:0] io_bypass_0_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7] wire [63:0] brinfo_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_bypassable_0 = io_req_bits_uop_bypassable_0; // @[functional-unit.scala:290:7] wire brinfo_uop_bypassable = io_req_bits_uop_bypassable_0; // @[functional-unit.scala:290:7, :385:20] wire [4:0] io_bypass_0_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7] wire [4:0] brinfo_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_mem_size = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7] wire brinfo_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_fence = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_amo = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7] wire brinfo_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7] wire brinfo_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:290:7] wire brinfo_uop_is_unique = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7] wire brinfo_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7] wire brinfo_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7, :385:20] wire [5:0] io_bypass_0_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:290:7] wire [5:0] brinfo_uop_ldst = io_req_bits_uop_ldst_0; // @[functional-unit.scala:290:7, :385:20] wire [5:0] io_bypass_0_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:290:7] wire [5:0] brinfo_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:290:7, :385:20] wire [5:0] io_bypass_0_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:290:7] wire [5:0] brinfo_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:290:7, :385:20] wire [5:0] io_bypass_0_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:290:7] wire [5:0] brinfo_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7] wire brinfo_uop_ldst_val = io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7] wire brinfo_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:290:7] wire brinfo_uop_fp_val = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_fp_single_0 = io_req_bits_uop_fp_single_0; // @[functional-unit.scala:290:7] wire brinfo_uop_fp_single = io_req_bits_uop_fp_single_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7] wire brinfo_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7] wire brinfo_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7] wire brinfo_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7] wire brinfo_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7, :385:20] wire io_bypass_0_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7] wire brinfo_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7, :385:20] wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7] wire [1:0] brinfo_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7, :385:20] wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47] wire [15:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [63:0] _io_bypass_0_bits_data_T_3; // @[functional-unit.scala:467:32] wire brinfo_valid; // @[functional-unit.scala:385:20] wire brinfo_mispredict; // @[functional-unit.scala:385:20] wire brinfo_taken; // @[functional-unit.scala:385:20] wire [2:0] brinfo_cfi_type; // @[functional-unit.scala:385:20] wire [1:0] brinfo_pc_sel; // @[functional-unit.scala:385:20] wire [20:0] brinfo_target_offset; // @[functional-unit.scala:385:20] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:290:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:290:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:290:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:290:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:290:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:290:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:290:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:290:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7] wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:290:7] wire io_resp_valid_0; // @[functional-unit.scala:290:7] wire [63:0] io_bypass_0_bits_data_0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_1_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_1_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_1_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_uop_uopc_0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_1_bits_uop_inst_0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_1_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7] wire [39:0] io_bypass_1_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_1_bits_uop_iq_type_0; // @[functional-unit.scala:290:7] wire [9:0] io_bypass_1_bits_uop_fu_code_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_iw_state_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_br_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_jal_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7] wire [15:0] io_bypass_1_bits_uop_br_mask_0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_1_bits_uop_br_tag_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_taken_0; // @[functional-unit.scala:290:7] wire [19:0] io_bypass_1_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7] wire [11:0] io_bypass_1_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_uop_pdst_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_uop_prs1_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_uop_prs2_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_uop_prs3_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_uop_ppred_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_1_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_exception_0; // @[functional-unit.scala:290:7] wire [63:0] io_bypass_1_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_bypassable_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_1_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_mem_size_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_fence_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_amo_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_is_unique_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_uop_ldst_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_uop_lrs1_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_uop_lrs2_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_1_bits_uop_lrs3_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_fp_val_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_fp_single_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7] wire io_bypass_1_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_1_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7] wire [63:0] io_bypass_1_bits_data_0; // @[functional-unit.scala:290:7] wire io_bypass_1_valid_0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_2_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_2_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_2_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_uop_uopc_0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_2_bits_uop_inst_0; // @[functional-unit.scala:290:7] wire [31:0] io_bypass_2_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7] wire [39:0] io_bypass_2_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7] wire [2:0] io_bypass_2_bits_uop_iq_type_0; // @[functional-unit.scala:290:7] wire [9:0] io_bypass_2_bits_uop_fu_code_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_iw_state_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_br_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_jal_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7] wire [15:0] io_bypass_2_bits_uop_br_mask_0; // @[functional-unit.scala:290:7] wire [3:0] io_bypass_2_bits_uop_br_tag_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_taken_0; // @[functional-unit.scala:290:7] wire [19:0] io_bypass_2_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7] wire [11:0] io_bypass_2_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_uop_pdst_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_uop_prs1_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_uop_prs2_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_uop_prs3_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_uop_ppred_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7] wire [6:0] io_bypass_2_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_exception_0; // @[functional-unit.scala:290:7] wire [63:0] io_bypass_2_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_bypassable_0; // @[functional-unit.scala:290:7] wire [4:0] io_bypass_2_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_mem_size_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_fence_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_amo_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_is_unique_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_uop_ldst_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_uop_lrs1_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_uop_lrs2_0; // @[functional-unit.scala:290:7] wire [5:0] io_bypass_2_bits_uop_lrs3_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_fp_val_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_fp_single_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7] wire io_bypass_2_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7] wire [1:0] io_bypass_2_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7] wire [63:0] io_bypass_2_bits_data_0; // @[functional-unit.scala:290:7] wire io_bypass_2_valid_0; // @[functional-unit.scala:290:7] wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7] wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7] wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7] wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7] wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7] wire [6:0] io_brinfo_uop_uopc_0; // @[functional-unit.scala:290:7] wire [31:0] io_brinfo_uop_inst_0; // @[functional-unit.scala:290:7] wire [31:0] io_brinfo_uop_debug_inst_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_rvc_0; // @[functional-unit.scala:290:7] wire [39:0] io_brinfo_uop_debug_pc_0; // @[functional-unit.scala:290:7] wire [2:0] io_brinfo_uop_iq_type_0; // @[functional-unit.scala:290:7] wire [9:0] io_brinfo_uop_fu_code_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_iw_state_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_br_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_jalr_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_jal_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_sfb_0; // @[functional-unit.scala:290:7] wire [15:0] io_brinfo_uop_br_mask_0; // @[functional-unit.scala:290:7] wire [3:0] io_brinfo_uop_br_tag_0; // @[functional-unit.scala:290:7] wire [4:0] io_brinfo_uop_ftq_idx_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_edge_inst_0; // @[functional-unit.scala:290:7] wire [5:0] io_brinfo_uop_pc_lob_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_taken_0; // @[functional-unit.scala:290:7] wire [19:0] io_brinfo_uop_imm_packed_0; // @[functional-unit.scala:290:7] wire [11:0] io_brinfo_uop_csr_addr_0; // @[functional-unit.scala:290:7] wire [6:0] io_brinfo_uop_rob_idx_0; // @[functional-unit.scala:290:7] wire [4:0] io_brinfo_uop_ldq_idx_0; // @[functional-unit.scala:290:7] wire [4:0] io_brinfo_uop_stq_idx_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_rxq_idx_0; // @[functional-unit.scala:290:7] wire [6:0] io_brinfo_uop_pdst_0; // @[functional-unit.scala:290:7] wire [6:0] io_brinfo_uop_prs1_0; // @[functional-unit.scala:290:7] wire [6:0] io_brinfo_uop_prs2_0; // @[functional-unit.scala:290:7] wire [6:0] io_brinfo_uop_prs3_0; // @[functional-unit.scala:290:7] wire [4:0] io_brinfo_uop_ppred_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_prs1_busy_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_prs2_busy_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_prs3_busy_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_ppred_busy_0; // @[functional-unit.scala:290:7] wire [6:0] io_brinfo_uop_stale_pdst_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_exception_0; // @[functional-unit.scala:290:7] wire [63:0] io_brinfo_uop_exc_cause_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_bypassable_0; // @[functional-unit.scala:290:7] wire [4:0] io_brinfo_uop_mem_cmd_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_mem_size_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_mem_signed_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_fence_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_fencei_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_amo_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_uses_ldq_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_uses_stq_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_is_unique_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_flush_on_commit_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7] wire [5:0] io_brinfo_uop_ldst_0; // @[functional-unit.scala:290:7] wire [5:0] io_brinfo_uop_lrs1_0; // @[functional-unit.scala:290:7] wire [5:0] io_brinfo_uop_lrs2_0; // @[functional-unit.scala:290:7] wire [5:0] io_brinfo_uop_lrs3_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_ldst_val_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_dst_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_frs3_en_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_fp_val_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_fp_single_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_bp_debug_if_0; // @[functional-unit.scala:290:7] wire io_brinfo_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[functional-unit.scala:290:7] wire io_brinfo_valid_0; // @[functional-unit.scala:290:7] wire io_brinfo_mispredict_0; // @[functional-unit.scala:290:7] wire io_brinfo_taken_0; // @[functional-unit.scala:290:7] wire [2:0] io_brinfo_cfi_type_0; // @[functional-unit.scala:290:7] wire [1:0] io_brinfo_pc_sel_0; // @[functional-unit.scala:290:7] wire [20:0] io_brinfo_target_offset_0; // @[functional-unit.scala:290:7] reg r_valids_0; // @[functional-unit.scala:236:27] reg r_valids_1; // @[functional-unit.scala:236:27] reg r_valids_2; // @[functional-unit.scala:236:27] reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_uopc_0 = r_uops_0_uopc; // @[functional-unit.scala:237:23, :290:7] reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_inst_0 = r_uops_0_inst; // @[functional-unit.scala:237:23, :290:7] reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_debug_inst_0 = r_uops_0_debug_inst; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_rvc_0 = r_uops_0_is_rvc; // @[functional-unit.scala:237:23, :290:7] reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_debug_pc_0 = r_uops_0_debug_pc; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_iq_type_0 = r_uops_0_iq_type; // @[functional-unit.scala:237:23, :290:7] reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_fu_code_0 = r_uops_0_fu_code; // @[functional-unit.scala:237:23, :290:7] reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_br_type_0 = r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_op1_sel_0 = r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_op2_sel_0 = r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_imm_sel_0 = r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_op_fcn_0 = r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_fcn_dw_0 = r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_csr_cmd_0 = r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_is_load_0 = r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_is_sta_0 = r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ctrl_is_std_0 = r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_iw_state_0 = r_uops_0_iw_state; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_iw_p1_poisoned_0 = r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_iw_p2_poisoned_0 = r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_br; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_br_0 = r_uops_0_is_br; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_jalr_0 = r_uops_0_is_jalr; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_jal; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_jal_0 = r_uops_0_is_jal; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_sfb_0 = r_uops_0_is_sfb; // @[functional-unit.scala:237:23, :290:7] reg [15:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_br_mask_0 = r_uops_0_br_mask; // @[functional-unit.scala:237:23, :290:7] reg [3:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_br_tag_0 = r_uops_0_br_tag; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ftq_idx_0 = r_uops_0_ftq_idx; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_edge_inst_0 = r_uops_0_edge_inst; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_pc_lob_0 = r_uops_0_pc_lob; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_taken; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_taken_0 = r_uops_0_taken; // @[functional-unit.scala:237:23, :290:7] reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_imm_packed_0 = r_uops_0_imm_packed; // @[functional-unit.scala:237:23, :290:7] reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_csr_addr_0 = r_uops_0_csr_addr; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_rob_idx_0 = r_uops_0_rob_idx; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ldq_idx_0 = r_uops_0_ldq_idx; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_stq_idx_0 = r_uops_0_stq_idx; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_rxq_idx_0 = r_uops_0_rxq_idx; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_0_pdst; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_pdst_0 = r_uops_0_pdst; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_0_prs1; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_prs1_0 = r_uops_0_prs1; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_0_prs2; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_prs2_0 = r_uops_0_prs2; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_0_prs3; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_prs3_0 = r_uops_0_prs3; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_0_ppred; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ppred_0 = r_uops_0_ppred; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_prs1_busy_0 = r_uops_0_prs1_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_prs2_busy_0 = r_uops_0_prs2_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_prs3_busy_0 = r_uops_0_prs3_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ppred_busy_0 = r_uops_0_ppred_busy; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_stale_pdst_0 = r_uops_0_stale_pdst; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_exception; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_exception_0 = r_uops_0_exception; // @[functional-unit.scala:237:23, :290:7] reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_exc_cause_0 = r_uops_0_exc_cause; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_bypassable; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_bypassable_0 = r_uops_0_bypassable; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_mem_cmd_0 = r_uops_0_mem_cmd; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_mem_size_0 = r_uops_0_mem_size; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_mem_signed_0 = r_uops_0_mem_signed; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_fence; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_fence_0 = r_uops_0_is_fence; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_fencei_0 = r_uops_0_is_fencei; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_amo; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_amo_0 = r_uops_0_is_amo; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_uses_ldq_0 = r_uops_0_uses_ldq; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_uses_stq_0 = r_uops_0_uses_stq; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_sys_pc2epc_0 = r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_is_unique; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_is_unique_0 = r_uops_0_is_unique; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_flush_on_commit_0 = r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ldst_is_rs1_0 = r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ldst_0 = r_uops_0_ldst; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_lrs1_0 = r_uops_0_lrs1; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_lrs2_0 = r_uops_0_lrs2; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_lrs3_0 = r_uops_0_lrs3; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_ldst_val_0 = r_uops_0_ldst_val; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_dst_rtype_0 = r_uops_0_dst_rtype; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_lrs1_rtype_0 = r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_lrs2_rtype_0 = r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_frs3_en_0 = r_uops_0_frs3_en; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_fp_val; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_fp_val_0 = r_uops_0_fp_val; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_fp_single; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_fp_single_0 = r_uops_0_fp_single; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_xcpt_pf_if_0 = r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_xcpt_ae_if_0 = r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_xcpt_ma_if_0 = r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_bp_debug_if_0 = r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_bp_xcpt_if_0 = r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_debug_fsrc_0 = r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23] assign io_bypass_1_bits_uop_debug_tsrc_0 = r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :290:7] reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :290:7] reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :290:7] reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :290:7] reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :290:7] reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_br; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_jal; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :290:7] reg [15:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_br_mask_0 = r_uops_1_br_mask; // @[functional-unit.scala:237:23, :290:7] reg [3:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_taken; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :290:7] reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :290:7] reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_1_pdst; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_1_prs1; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_1_prs2; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_1_prs3; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_1_ppred; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_exception; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :290:7] reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_bypassable; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_fence; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_amo; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_is_unique; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_fp_val; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_fp_single; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23] assign io_bypass_2_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_2_uopc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uopc_0 = r_uops_2_uopc; // @[functional-unit.scala:237:23, :290:7] reg [31:0] r_uops_2_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_inst_0 = r_uops_2_inst; // @[functional-unit.scala:237:23, :290:7] reg [31:0] r_uops_2_debug_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_inst_0 = r_uops_2_debug_inst; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_rvc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_rvc_0 = r_uops_2_is_rvc; // @[functional-unit.scala:237:23, :290:7] reg [39:0] r_uops_2_debug_pc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_pc_0 = r_uops_2_debug_pc; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_2_iq_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iq_type_0 = r_uops_2_iq_type; // @[functional-unit.scala:237:23, :290:7] reg [9:0] r_uops_2_fu_code; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fu_code_0 = r_uops_2_fu_code; // @[functional-unit.scala:237:23, :290:7] reg [3:0] r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7] reg [2:0] r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_iw_state; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_state_0 = r_uops_2_iw_state; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_br; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_br_0 = r_uops_2_is_br; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_jalr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jalr_0 = r_uops_2_is_jalr; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_jal; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_jal_0 = r_uops_2_is_jal; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_sfb; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sfb_0 = r_uops_2_is_sfb; // @[functional-unit.scala:237:23, :290:7] reg [15:0] r_uops_2_br_mask; // @[functional-unit.scala:237:23] reg [3:0] r_uops_2_br_tag; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_br_tag_0 = r_uops_2_br_tag; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_2_ftq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ftq_idx_0 = r_uops_2_ftq_idx; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_edge_inst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_edge_inst_0 = r_uops_2_edge_inst; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_2_pc_lob; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pc_lob_0 = r_uops_2_pc_lob; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_taken; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_taken_0 = r_uops_2_taken; // @[functional-unit.scala:237:23, :290:7] reg [19:0] r_uops_2_imm_packed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_imm_packed_0 = r_uops_2_imm_packed; // @[functional-unit.scala:237:23, :290:7] reg [11:0] r_uops_2_csr_addr; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_csr_addr_0 = r_uops_2_csr_addr; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_2_rob_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rob_idx_0 = r_uops_2_rob_idx; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_2_ldq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldq_idx_0 = r_uops_2_ldq_idx; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_2_stq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stq_idx_0 = r_uops_2_stq_idx; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_rxq_idx; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_rxq_idx_0 = r_uops_2_rxq_idx; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_2_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_pdst_0 = r_uops_2_pdst; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_2_prs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_0 = r_uops_2_prs1; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_2_prs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_0 = r_uops_2_prs2; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_2_prs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_0 = r_uops_2_prs3; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_2_ppred; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_0 = r_uops_2_ppred; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_prs1_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs1_busy_0 = r_uops_2_prs1_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_prs2_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs2_busy_0 = r_uops_2_prs2_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_prs3_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_prs3_busy_0 = r_uops_2_prs3_busy; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_ppred_busy; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ppred_busy_0 = r_uops_2_ppred_busy; // @[functional-unit.scala:237:23, :290:7] reg [6:0] r_uops_2_stale_pdst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_stale_pdst_0 = r_uops_2_stale_pdst; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_exception; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exception_0 = r_uops_2_exception; // @[functional-unit.scala:237:23, :290:7] reg [63:0] r_uops_2_exc_cause; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_exc_cause_0 = r_uops_2_exc_cause; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_bypassable; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bypassable_0 = r_uops_2_bypassable; // @[functional-unit.scala:237:23, :290:7] reg [4:0] r_uops_2_mem_cmd; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_cmd_0 = r_uops_2_mem_cmd; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_mem_size; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_size_0 = r_uops_2_mem_size; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_mem_signed; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_mem_signed_0 = r_uops_2_mem_signed; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_fence; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fence_0 = r_uops_2_is_fence; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_fencei; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_fencei_0 = r_uops_2_is_fencei; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_amo; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_amo_0 = r_uops_2_is_amo; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_uses_ldq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_ldq_0 = r_uops_2_uses_ldq; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_uses_stq; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_uses_stq_0 = r_uops_2_uses_stq; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_is_unique; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_is_unique_0 = r_uops_2_is_unique; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_flush_on_commit_0 = r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_2_ldst; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_0 = r_uops_2_ldst; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_2_lrs1; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_0 = r_uops_2_lrs1; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_2_lrs2; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_0 = r_uops_2_lrs2; // @[functional-unit.scala:237:23, :290:7] reg [5:0] r_uops_2_lrs3; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs3_0 = r_uops_2_lrs3; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_ldst_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_ldst_val_0 = r_uops_2_ldst_val; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_dst_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_dst_rtype_0 = r_uops_2_dst_rtype; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_frs3_en; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_frs3_en_0 = r_uops_2_frs3_en; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_fp_val; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_val_0 = r_uops_2_fp_val; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_fp_single; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_fp_single_0 = r_uops_2_fp_single; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_debug_if_0 = r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23, :290:7] reg r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_fsrc_0 = r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23, :290:7] reg [1:0] r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23] assign io_resp_bits_uop_debug_tsrc_0 = r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23, :290:7] wire [15:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51] wire _r_valids_0_T_1 = |_r_valids_0_T; // @[util.scala:118:{51,59}] wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59] wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :290:7] wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :290:7] wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}] wire [15:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51] wire _r_valids_1_T_1 = |_r_valids_1_T; // @[util.scala:118:{51,59}] wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59] wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :290:7] wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _r_valids_2_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51] wire _r_valids_2_T_1 = |_r_valids_2_T; // @[util.scala:118:{51,59}] wire _r_valids_2_T_2 = ~_r_valids_2_T_1; // @[util.scala:118:59] wire _r_valids_2_T_3 = r_valids_1 & _r_valids_2_T_2; // @[functional-unit.scala:236:27, :246:{36,39}] wire _r_valids_2_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :290:7] wire _r_valids_2_T_5 = _r_valids_2_T_3 & _r_valids_2_T_4; // @[functional-unit.scala:246:{36,83,86}] wire [15:0] _r_uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] wire [15:0] _r_uops_2_br_mask_T_1 = r_uops_1_br_mask & _r_uops_2_br_mask_T; // @[util.scala:85:{25,27}] wire [15:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_2_br_mask; // @[util.scala:118:51] wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59] assign _io_resp_valid_T_3 = r_valids_2 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :290:7] wire [15:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27] assign _io_resp_bits_uop_br_mask_T_1 = r_uops_2_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}] assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire _imm_xprlen_sign_T = io_req_bits_uop_imm_packed_0[19]; // @[util.scala:273:18] wire imm_xprlen_sign = _imm_xprlen_sign_T; // @[util.scala:273:{18,37}] wire imm_xprlen_hi_hi_hi = imm_xprlen_sign; // @[util.scala:273:37, :282:15] wire _GEN = io_req_bits_uop_ctrl_imm_sel_0 == 3'h3; // @[util.scala:274:27] wire _imm_xprlen_i30_20_T; // @[util.scala:274:27] assign _imm_xprlen_i30_20_T = _GEN; // @[util.scala:274:27] wire _imm_xprlen_i19_12_T; // @[util.scala:275:27] assign _imm_xprlen_i19_12_T = _GEN; // @[util.scala:274:27, :275:27] wire _imm_xprlen_i11_T; // @[util.scala:276:27] assign _imm_xprlen_i11_T = _GEN; // @[util.scala:274:27, :276:27] wire _imm_xprlen_i10_5_T; // @[util.scala:278:27] assign _imm_xprlen_i10_5_T = _GEN; // @[util.scala:274:27, :278:27] wire _imm_xprlen_i4_1_T; // @[util.scala:279:27] assign _imm_xprlen_i4_1_T = _GEN; // @[util.scala:274:27, :279:27] wire [10:0] _imm_xprlen_i30_20_T_1 = io_req_bits_uop_imm_packed_0[18:8]; // @[util.scala:274:39] wire [10:0] _imm_xprlen_i30_20_T_2 = _imm_xprlen_i30_20_T_1; // @[util.scala:274:{39,46}] wire [10:0] imm_xprlen_i30_20 = _imm_xprlen_i30_20_T ? _imm_xprlen_i30_20_T_2 : {11{imm_xprlen_sign}}; // @[util.scala:273:37, :274:{21,27,46}] wire [10:0] imm_xprlen_hi_hi_lo = imm_xprlen_i30_20; // @[util.scala:274:21, :282:15] wire _GEN_0 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h4; // @[util.scala:275:44] wire _imm_xprlen_i19_12_T_1; // @[util.scala:275:44] assign _imm_xprlen_i19_12_T_1 = _GEN_0; // @[util.scala:275:44] wire _imm_xprlen_i11_T_1; // @[util.scala:277:27] assign _imm_xprlen_i11_T_1 = _GEN_0; // @[util.scala:275:44, :277:27] wire _imm_xprlen_i19_12_T_2 = _imm_xprlen_i19_12_T | _imm_xprlen_i19_12_T_1; // @[util.scala:275:{27,36,44}] wire [7:0] _imm_xprlen_i19_12_T_3 = io_req_bits_uop_imm_packed_0[7:0]; // @[util.scala:275:56] wire [7:0] _imm_xprlen_i19_12_T_4 = _imm_xprlen_i19_12_T_3; // @[util.scala:275:{56,62}] wire [7:0] imm_xprlen_i19_12 = _imm_xprlen_i19_12_T_2 ? _imm_xprlen_i19_12_T_4 : {8{imm_xprlen_sign}}; // @[util.scala:273:37, :275:{21,36,62}] wire [7:0] imm_xprlen_hi_lo_hi = imm_xprlen_i19_12; // @[util.scala:275:21, :282:15] wire _imm_xprlen_i11_T_2 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h2; // @[util.scala:277:44] wire _imm_xprlen_i11_T_3 = _imm_xprlen_i11_T_1 | _imm_xprlen_i11_T_2; // @[util.scala:277:{27,36,44}] wire _imm_xprlen_i11_T_4 = io_req_bits_uop_imm_packed_0[8]; // @[util.scala:277:56] wire _imm_xprlen_i0_T_3 = io_req_bits_uop_imm_packed_0[8]; // @[util.scala:277:56, :280:56] wire _imm_xprlen_i11_T_5 = _imm_xprlen_i11_T_4; // @[util.scala:277:{56,60}] wire _imm_xprlen_i11_T_6 = _imm_xprlen_i11_T_3 ? _imm_xprlen_i11_T_5 : imm_xprlen_sign; // @[util.scala:273:37, :277:{21,36,60}] wire imm_xprlen_i11 = ~_imm_xprlen_i11_T & _imm_xprlen_i11_T_6; // @[util.scala:276:{21,27}, :277:21] wire imm_xprlen_hi_lo_lo = imm_xprlen_i11; // @[util.scala:276:21, :282:15] wire [4:0] _imm_xprlen_i10_5_T_1 = io_req_bits_uop_imm_packed_0[18:14]; // @[util.scala:278:44] wire [4:0] _imm_xprlen_i10_5_T_2 = _imm_xprlen_i10_5_T_1; // @[util.scala:278:{44,52}] wire [4:0] imm_xprlen_i10_5 = _imm_xprlen_i10_5_T ? 5'h0 : _imm_xprlen_i10_5_T_2; // @[util.scala:278:{21,27,52}] wire [4:0] imm_xprlen_lo_hi_hi = imm_xprlen_i10_5; // @[util.scala:278:21, :282:15] wire [4:0] _imm_xprlen_i4_1_T_1 = io_req_bits_uop_imm_packed_0[13:9]; // @[util.scala:279:44] wire [4:0] _imm_xprlen_i4_1_T_2 = _imm_xprlen_i4_1_T_1; // @[util.scala:279:{44,51}] wire [4:0] imm_xprlen_i4_1 = _imm_xprlen_i4_1_T ? 5'h0 : _imm_xprlen_i4_1_T_2; // @[util.scala:279:{21,27,51}] wire [4:0] imm_xprlen_lo_hi_lo = imm_xprlen_i4_1; // @[util.scala:279:21, :282:15] wire _imm_xprlen_i0_T = io_req_bits_uop_ctrl_imm_sel_0 == 3'h1; // @[util.scala:280:27] wire _imm_xprlen_i0_T_1 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h0; // @[util.scala:280:44] wire _imm_xprlen_i0_T_2 = _imm_xprlen_i0_T | _imm_xprlen_i0_T_1; // @[util.scala:280:{27,36,44}] wire _imm_xprlen_i0_T_4 = _imm_xprlen_i0_T_3; // @[util.scala:280:{56,60}] wire imm_xprlen_i0 = _imm_xprlen_i0_T_2 & _imm_xprlen_i0_T_4; // @[util.scala:280:{21,36,60}] wire imm_xprlen_lo_lo = imm_xprlen_i0; // @[util.scala:280:21, :282:15] wire [9:0] imm_xprlen_lo_hi = {imm_xprlen_lo_hi_hi, imm_xprlen_lo_hi_lo}; // @[util.scala:282:15] wire [10:0] imm_xprlen_lo = {imm_xprlen_lo_hi, imm_xprlen_lo_lo}; // @[util.scala:282:15] wire [8:0] imm_xprlen_hi_lo = {imm_xprlen_hi_lo_hi, imm_xprlen_hi_lo_lo}; // @[util.scala:282:15] wire [11:0] imm_xprlen_hi_hi = {imm_xprlen_hi_hi_hi, imm_xprlen_hi_hi_lo}; // @[util.scala:282:15] wire [20:0] imm_xprlen_hi = {imm_xprlen_hi_hi, imm_xprlen_hi_lo}; // @[util.scala:282:15] wire [31:0] _imm_xprlen_T = {imm_xprlen_hi, imm_xprlen_lo}; // @[util.scala:282:15] wire [31:0] imm_xprlen = _imm_xprlen_T; // @[util.scala:282:{15,60}] wire [31:0] _op2_data_T_1 = imm_xprlen; // @[util.scala:282:60] wire _op2_data_T = io_req_bits_uop_ctrl_op2_sel_0 == 3'h1; // @[functional-unit.scala:290:7, :321:39] wire _op2_data_T_2 = _op2_data_T_1[31]; // @[util.scala:261:46] wire [31:0] _op2_data_T_3 = {32{_op2_data_T_2}}; // @[util.scala:261:{25,46}] wire [63:0] _op2_data_T_4 = {_op2_data_T_3, _op2_data_T_1}; // @[util.scala:261:{20,25}] wire _op2_data_T_5 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h4; // @[functional-unit.scala:290:7, :322:39] wire [4:0] _op2_data_T_6 = io_req_bits_uop_prs1_0[4:0]; // @[functional-unit.scala:290:7, :322:73] wire _op2_data_T_7 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h0; // @[functional-unit.scala:290:7, :323:39] wire _op2_data_T_8 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h3; // @[functional-unit.scala:290:7, :324:39] wire [2:0] _op2_data_T_9 = io_req_bits_uop_is_rvc_0 ? 3'h2 : 3'h4; // @[functional-unit.scala:290:7, :324:56] wire [2:0] _op2_data_T_10 = _op2_data_T_8 ? _op2_data_T_9 : 3'h0; // @[functional-unit.scala:324:{21,39,56}] wire [63:0] _op2_data_T_11 = _op2_data_T_7 ? io_req_bits_rs2_data_0 : {61'h0, _op2_data_T_10}; // @[functional-unit.scala:290:7, :323:{21,39}, :324:21] wire [63:0] _op2_data_T_12 = _op2_data_T_5 ? {59'h0, _op2_data_T_6} : _op2_data_T_11; // @[functional-unit.scala:322:{21,39,73}, :323:21] wire [63:0] op2_data = _op2_data_T ? _op2_data_T_4 : _op2_data_T_12; // @[util.scala:261:20] wire killed; // @[functional-unit.scala:337:24] assign killed = |{io_req_bits_kill_0, _r_valids_0_T}; // @[util.scala:118:{51,59}] wire br_eq = io_req_bits_rs1_data_0 == io_req_bits_rs2_data_0; // @[functional-unit.scala:290:7, :344:21] wire br_ltu = io_req_bits_rs1_data_0 < io_req_bits_rs2_data_0; // @[functional-unit.scala:290:7, :345:28] wire _br_lt_T = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:290:7, :346:22] wire _br_lt_T_5 = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:290:7, :346:22, :347:20] wire _br_lt_T_1 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:290:7, :346:36] wire _br_lt_T_6 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:290:7, :346:36, :347:35] wire _br_lt_T_2 = _br_lt_T ^ _br_lt_T_1; // @[functional-unit.scala:346:{22,31,36}] wire _br_lt_T_3 = ~_br_lt_T_2; // @[functional-unit.scala:346:{17,31}] wire _br_lt_T_4 = _br_lt_T_3 & br_ltu; // @[functional-unit.scala:345:28, :346:{17,46}] wire _br_lt_T_7 = ~_br_lt_T_6; // @[functional-unit.scala:347:{31,35}] wire _br_lt_T_8 = _br_lt_T_5 & _br_lt_T_7; // @[functional-unit.scala:347:{20,29,31}] wire br_lt = _br_lt_T_4 | _br_lt_T_8; // @[functional-unit.scala:346:{46,55}, :347:29] wire _pc_sel_T = ~br_eq; // @[functional-unit.scala:344:21, :351:39] wire [1:0] _pc_sel_T_1 = {1'h0, _pc_sel_T}; // @[functional-unit.scala:351:{38,39}] wire [1:0] _pc_sel_T_2 = {1'h0, br_eq}; // @[functional-unit.scala:344:21, :352:38] wire _pc_sel_T_3 = ~br_lt; // @[functional-unit.scala:346:55, :353:39] wire [1:0] _pc_sel_T_4 = {1'h0, _pc_sel_T_3}; // @[functional-unit.scala:353:{38,39}] wire _pc_sel_T_5 = ~br_ltu; // @[functional-unit.scala:345:28, :354:39] wire [1:0] _pc_sel_T_6 = {1'h0, _pc_sel_T_5}; // @[functional-unit.scala:354:{38,39}] wire [1:0] _pc_sel_T_7 = {1'h0, br_lt}; // @[functional-unit.scala:346:55, :355:38] wire [1:0] _pc_sel_T_8 = {1'h0, br_ltu}; // @[functional-unit.scala:345:28, :356:38] wire _pc_sel_T_9 = io_req_bits_uop_ctrl_br_type_0 == 4'h0; // @[functional-unit.scala:290:7, :349:53] wire _pc_sel_T_11 = io_req_bits_uop_ctrl_br_type_0 == 4'h1; // @[functional-unit.scala:290:7, :349:53] wire [1:0] _pc_sel_T_12 = _pc_sel_T_11 ? _pc_sel_T_1 : 2'h0; // @[functional-unit.scala:349:53, :351:38] wire _pc_sel_T_13 = io_req_bits_uop_ctrl_br_type_0 == 4'h2; // @[functional-unit.scala:290:7, :349:53] wire [1:0] _pc_sel_T_14 = _pc_sel_T_13 ? _pc_sel_T_2 : _pc_sel_T_12; // @[functional-unit.scala:349:53, :352:38] wire _pc_sel_T_15 = io_req_bits_uop_ctrl_br_type_0 == 4'h3; // @[functional-unit.scala:290:7, :349:53] wire [1:0] _pc_sel_T_16 = _pc_sel_T_15 ? _pc_sel_T_4 : _pc_sel_T_14; // @[functional-unit.scala:349:53, :353:38] wire _pc_sel_T_17 = io_req_bits_uop_ctrl_br_type_0 == 4'h4; // @[functional-unit.scala:290:7, :349:53] wire [1:0] _pc_sel_T_18 = _pc_sel_T_17 ? _pc_sel_T_6 : _pc_sel_T_16; // @[functional-unit.scala:349:53, :354:38] wire _pc_sel_T_19 = io_req_bits_uop_ctrl_br_type_0 == 4'h5; // @[functional-unit.scala:290:7, :349:53] wire [1:0] _pc_sel_T_20 = _pc_sel_T_19 ? _pc_sel_T_7 : _pc_sel_T_18; // @[functional-unit.scala:349:53, :355:38] wire _pc_sel_T_21 = io_req_bits_uop_ctrl_br_type_0 == 4'h6; // @[functional-unit.scala:290:7, :349:53] wire [1:0] _pc_sel_T_22 = _pc_sel_T_21 ? _pc_sel_T_8 : _pc_sel_T_20; // @[functional-unit.scala:349:53, :356:38] wire _pc_sel_T_23 = io_req_bits_uop_ctrl_br_type_0 == 4'h7; // @[functional-unit.scala:290:7, :349:53] wire [1:0] _pc_sel_T_24 = _pc_sel_T_23 ? 2'h1 : _pc_sel_T_22; // @[functional-unit.scala:349:53] wire _pc_sel_T_25 = io_req_bits_uop_ctrl_br_type_0 == 4'h8; // @[functional-unit.scala:290:7, :349:53] wire [1:0] pc_sel = _pc_sel_T_25 ? 2'h2 : _pc_sel_T_24; // @[functional-unit.scala:349:53] assign brinfo_pc_sel = pc_sel; // @[functional-unit.scala:349:53, :385:20] wire _is_taken_T = ~killed; // @[functional-unit.scala:337:24, :362:20] wire _is_taken_T_1 = io_req_valid_0 & _is_taken_T; // @[functional-unit.scala:290:7, :361:31, :362:20] wire _is_taken_T_2 = io_req_bits_uop_is_br_0 | io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :363:31] wire _is_taken_T_3 = _is_taken_T_2 | io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :363:{31,46}] wire _is_taken_T_4 = _is_taken_T_1 & _is_taken_T_3; // @[functional-unit.scala:361:31, :362:28, :363:46] wire _is_taken_T_5 = |pc_sel; // @[functional-unit.scala:349:53, :364:28] wire is_taken = _is_taken_T_4 & _is_taken_T_5; // @[functional-unit.scala:362:28, :363:61, :364:28] assign brinfo_taken = is_taken; // @[functional-unit.scala:363:61, :385:20] wire mispredict; // @[functional-unit.scala:367:28] assign brinfo_mispredict = mispredict; // @[functional-unit.scala:367:28, :385:20] wire _is_br_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :369:40] wire _is_br_T_1 = io_req_valid_0 & _is_br_T; // @[functional-unit.scala:290:7, :369:{37,40}] wire _is_br_T_2 = _is_br_T_1 & io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7, :369:{37,48}] wire _is_br_T_3 = ~io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7, :369:64] wire is_br = _is_br_T_2 & _is_br_T_3; // @[functional-unit.scala:369:{48,61,64}] wire _is_jal_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :370:40] wire _is_jal_T_1 = io_req_valid_0 & _is_jal_T; // @[functional-unit.scala:290:7, :370:{37,40}] wire is_jal = _is_jal_T_1 & io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :370:{37,48}] wire _is_jalr_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :371:40] wire _is_jalr_T_1 = io_req_valid_0 & _is_jalr_T; // @[functional-unit.scala:290:7, :371:{37,40}] wire is_jalr = _is_jalr_T_1 & io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :371:{37,48}] wire _brinfo_valid_T = is_br | is_jalr; // @[functional-unit.scala:369:61, :371:48, :373:15, :388:34]
Generate the Verilog code corresponding to the following Chisel files. File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 */ val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2*maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready || drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) || out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied || out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full || !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full || in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module TLInterconnectCoupler_cbus_to_bootrom( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); TLFragmenter_BootROM fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (auto_tl_in_a_ready), .auto_anon_in_a_valid (auto_tl_in_a_valid), .auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .auto_anon_in_a_bits_param (auto_tl_in_a_bits_param), .auto_anon_in_a_bits_size (auto_tl_in_a_bits_size), .auto_anon_in_a_bits_source (auto_tl_in_a_bits_source), .auto_anon_in_a_bits_address (auto_tl_in_a_bits_address), .auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask), .auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .auto_anon_in_d_ready (auto_tl_in_d_ready), .auto_anon_in_d_valid (auto_tl_in_d_valid), .auto_anon_in_d_bits_size (auto_tl_in_d_bits_size), .auto_anon_in_d_bits_source (auto_tl_in_d_bits_source), .auto_anon_in_d_bits_data (auto_tl_in_d_bits_data), .auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready), .auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid), .auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param), .auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size), .auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source), .auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask), .auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready), .auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid), .auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size), .auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source), .auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data) ); // @[Fragmenter.scala:345:34] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_26 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_28 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_30 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_WIRE_5 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_103 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_109 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_115 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_119 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_121 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_125 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_127 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_131 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_133 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_137 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_139 = 1'h1; // @[Parameters.scala:57:20] wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [5:0] io_in_b_bits_source = 6'h10; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_77 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_78 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_79 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_80 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_81 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_82 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_83 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_1 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_2 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_3 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_4 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_5 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _legal_source_uncommonBits_T_6 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _legal_source_T_55 = 6'h10; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_56 = 6'h10; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_57 = 6'h10; // @[Mux.scala:30:73] wire [5:0] _legal_source_WIRE_1 = 6'h10; // @[Mux.scala:30:73] wire [5:0] _uncommonBits_T_84 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_85 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_86 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_87 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_88 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_89 = 6'h10; // @[Parameters.scala:52:29] wire [5:0] _uncommonBits_T_90 = 6'h10; // @[Parameters.scala:52:29] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h6; // @[Misc.scala:202:34] wire [7:0] io_in_b_bits_mask = 8'hFF; // @[Monitor.scala:36:7] wire [7:0] mask_1 = 8'hFF; // @[Misc.scala:222:10] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9] wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_32 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_34 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_36 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_T_38 = 1'h0; // @[Parameters.scala:54:32] wire _legal_source_T_40 = 1'h0; // @[Parameters.scala:54:67] wire _legal_source_T_42 = 1'h0; // @[Parameters.scala:56:48] wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31] wire _legal_source_T_50 = 1'h0; // @[Mux.scala:30:73] wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _legal_source_T_1 = 4'h4; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_7 = 4'h4; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_13 = 4'h4; // @[Parameters.scala:54:10] wire [3:0] _legal_source_T_19 = 4'h4; // @[Parameters.scala:54:10] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _legal_source_T_25 = 3'h2; // @[Parameters.scala:54:10] wire [2:0] _legal_source_T_31 = 3'h2; // @[Parameters.scala:54:10] wire [2:0] _legal_source_T_37 = 3'h2; // @[Parameters.scala:54:10] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] uncommonBits_81 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_82 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_83 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_4 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_5 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] legal_source_uncommonBits_6 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_88 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_89 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] uncommonBits_90 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] b_first_beats1_decode = 3'h7; // @[Edges.scala:220:59] wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76] wire [5:0] _legal_source_T_43 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_44 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_45 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_46 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_47 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_51 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_52 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_53 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _legal_source_T_54 = 6'h0; // @[Mux.scala:30:73] wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71] wire [1:0] uncommonBits_77 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_78 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_79 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_80 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_84 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_85 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_86 = 2'h0; // @[Parameters.scala:52:56] wire [1:0] uncommonBits_87 = 2'h0; // @[Parameters.scala:52:56] wire [3:0] _legal_source_T_49 = 4'h0; // @[Mux.scala:30:73] wire [4:0] _legal_source_T_48 = 5'h10; // @[Mux.scala:30:73] wire [3:0] mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_18 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_19 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_20 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_91 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_92 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_93 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_94 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_95 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_96 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_97 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_98 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_99 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_100 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_101 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_102 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_103 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_104 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_105 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_106 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_107 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_108 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_109 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_110 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_111 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_112 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_113 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_114 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_115 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_116 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_117 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_118 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_119 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_120 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_121 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_122 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_123 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_124 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _uncommonBits_T_125 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [5:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 6'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_37 = io_in_a_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_48 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = io_in_d_bits_source_0 == 6'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_50 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_56 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_62 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_68 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_51 = _source_ok_T_50 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_57 = _source_ok_T_56 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_74 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_80 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_86 = io_in_d_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_75 = _source_ok_T_74 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_81 = _source_ok_T_80 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_97 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31] wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _source_ok_T_98 = io_in_c_bits_source_0 == 6'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_99 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_105 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_111 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_117 = io_in_c_bits_source_0[5:2]; // @[Monitor.scala:36:7] wire _source_ok_T_100 = _source_ok_T_99 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_104 = _source_ok_T_102; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_1 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_106 = _source_ok_T_105 == 4'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_110 = _source_ok_T_108; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_2 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_112 = _source_ok_T_111 == 4'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_116 = _source_ok_T_114; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_3 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_118 = _source_ok_T_117 == 4'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_120 = _source_ok_T_118; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_122 = _source_ok_T_120; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_4 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_18 = _source_ok_uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_123 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_129 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_135 = io_in_c_bits_source_0[5:3]; // @[Monitor.scala:36:7] wire _source_ok_T_124 = _source_ok_T_123 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_126 = _source_ok_T_124; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_128 = _source_ok_T_126; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_5 = _source_ok_T_128; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_19 = _source_ok_uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_130 = _source_ok_T_129 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_132 = _source_ok_T_130; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_134 = _source_ok_T_132; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_6 = _source_ok_T_134; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_20 = _source_ok_uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_136 = _source_ok_T_135 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_138 = _source_ok_T_136; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_140 = _source_ok_T_138; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2_7 = _source_ok_T_140; // @[Parameters.scala:1138:31] wire _source_ok_T_141 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_146 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_94 = _uncommonBits_T_94[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_95 = _uncommonBits_T_95[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_96 = _uncommonBits_T_96[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_97 = _uncommonBits_T_97[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_98 = _uncommonBits_T_98[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_99 = _uncommonBits_T_99[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_100 = _uncommonBits_T_100[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_101 = _uncommonBits_T_101[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_102 = _uncommonBits_T_102[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_103 = _uncommonBits_T_103[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_104 = _uncommonBits_T_104[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_105 = _uncommonBits_T_105[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_106 = _uncommonBits_T_106[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_107 = _uncommonBits_T_107[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_108 = _uncommonBits_T_108[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_109 = _uncommonBits_T_109[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_110 = _uncommonBits_T_110[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_111 = _uncommonBits_T_111[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_112 = _uncommonBits_T_112[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_113 = _uncommonBits_T_113[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_114 = _uncommonBits_T_114[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_115 = _uncommonBits_T_115[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_116 = _uncommonBits_T_116[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_117 = _uncommonBits_T_117[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_118 = _uncommonBits_T_118[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_119 = _uncommonBits_T_119[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_120 = _uncommonBits_T_120[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_121 = _uncommonBits_T_121[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_122 = _uncommonBits_T_122[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_123 = _uncommonBits_T_123[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_124 = _uncommonBits_T_124[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_125 = _uncommonBits_T_125[2:0]; // @[Parameters.scala:52:{29,56}] wire sink_ok_1 = io_in_e_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :367:31] wire _T_2345 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2345; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2345; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2419 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2419; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2419; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2419; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2419; // @[Decoupled.scala:51:35] wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] reg [2:0] b_first_counter; // @[Edges.scala:229:27] wire [3:0] _b_first_counter1_T = {1'h0, b_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] b_first_counter1 = _b_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire [2:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] _b_first_counter_T = b_first ? 3'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2416 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2416; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2416; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [48:0] inflight; // @[Monitor.scala:614:27] reg [195:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [195:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [48:0] a_set; // @[Monitor.scala:626:34] wire [48:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [195:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [195:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [8:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69] wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65] wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101] wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99] wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69] wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67] wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101] wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99] wire [195:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [195:0] _a_opcode_lookup_T_6 = {192'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [195:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[195:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [195:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [195:0] _a_size_lookup_T_6 = {192'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [195:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[195:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [63:0] _GEN_5 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [63:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_2271 = _T_2345 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2271 ? _a_set_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2271 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2271 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [8:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79] wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77] wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2271 ? _a_opcodes_set_T_1[195:0] : 196'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2271 ? _a_sizes_set_T_1[195:0] : 196'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [48:0] d_clr; // @[Monitor.scala:664:34] wire [48:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [195:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [195:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46] wire _T_2317 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [63:0] _GEN_8 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35] wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2317 & ~d_release_ack ? _d_clr_wo_ready_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_2286 = _T_2419 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2286 ? _d_clr_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2286 ? _d_opcodes_clr_T_5[195:0] : 196'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2286 ? _d_sizes_clr_T_5[195:0] : 196'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [48:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [48:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [48:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [195:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [195:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [195:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [195:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [195:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [195:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [48:0] inflight_1; // @[Monitor.scala:726:35] reg [195:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [195:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [48:0] c_set; // @[Monitor.scala:738:34] wire [48:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [195:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [195:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [195:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [195:0] _c_opcode_lookup_T_6 = {192'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [195:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[195:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [195:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [195:0] _c_size_lookup_T_6 = {192'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [195:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[195:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [63:0] _GEN_9 = 64'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [63:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35] wire [63:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_2358 = _T_2416 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2358 ? _c_set_T[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2358 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2358 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [8:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [8:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79] wire [8:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77] wire [514:0] _c_opcodes_set_T_1 = {511'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2358 ? _c_opcodes_set_T_1[195:0] : 196'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [514:0] _c_sizes_set_T_1 = {511'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2358 ? _c_sizes_set_T_1[195:0] : 196'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [48:0] d_clr_1; // @[Monitor.scala:774:34] wire [48:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [195:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [195:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2389 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2389 & d_release_ack_1 ? _d_clr_wo_ready_T_1[48:0] : 49'h0; // @[OneHot.scala:58:35] wire _T_2371 = _T_2419 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2371 ? _d_clr_T_1[48:0] : 49'h0; // @[OneHot.scala:58:35] wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2371 ? _d_opcodes_clr_T_11[195:0] : 196'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2371 ? _d_sizes_clr_T_11[195:0] : 196'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [48:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [48:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [48:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [195:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [195:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [195:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [195:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [195:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [195:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [6:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] d_set; // @[Monitor.scala:833:25] wire _T_2425 = _T_2419 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35] assign d_set = _T_2425 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35] wire [6:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _e_clr_T = 8'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_129( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0) } } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire || !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File mshrs.scala: //****************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v4.common._ import boom.v4.exu.BrUpdateInfo import boom.v4.util._ class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Output(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Output(Valid(new LineBufferWriteReq)) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, fastDeq=true)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en io.meta_write.bits.tag := req_tag io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 io.refill.valid := false.B io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp io.replay.valid := false.B io.replay.bits := rpq.io.deq.bits io.wb_req.valid := false.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B io.resp.valid := false.B io.resp.bits := rpq.io.deq.bits io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en io.mem_finish.valid := false.B io.mem_finish.bits := grantack.bits io.lb_write.valid := false.B io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data io.mem_grant.ready := false.B io.lb_read.offset := rpq.io.deq.bits.addr >> rowOffBits when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { io.mem_grant.ready := true.B when (edge.hasData(io.mem_grant.bits)) { io.lb_write.valid := io.mem_grant.valid } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && drain_load io.lb_read.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && drain_load io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.offset := refill_ctr io.refill.valid := true.B when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid when (io.mem_finish.fire || !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle || !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle || req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := req.is_hella when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp || io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val offset = UInt(log2Ceil(cacheDataBeats).W) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(lsuWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(lsuWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(lsuWidth, Bool())) val block_hit = Output(Vec(lsuWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = WireInit(io.req(req_idx)) val req_is_probe = io.req_is_probe(0) for (w <- 0 until lsuWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Reg(Vec(nLBEntries, Vec(cacheDataBeats, UInt(encRowBits.W)))) def widthMap[T <: Data](f: Int => T) = VecInit((0 until lsuWidth).map(f)) val idx_matches = Wire(Vec(lsuWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(lsuWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(lsuWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_||_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until lsuWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)|| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) || (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill mshr.io.lb_resp := lb(i)(mshr.io.lb_read.offset) when (mshr.io.lb_write.valid) { lb(i)(mshr.io.lb_write.bits.offset) := mshr.io.lb_write.bits.data } commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until lsuWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy || mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until lsuWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid || sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) | PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } }
module BoomMSHRFile( // @[mshrs.scala:498:7] input clock, // @[mshrs.scala:498:7] input reset, // @[mshrs.scala:498:7] output io_req_0_ready, // @[mshrs.scala:501:14] input io_req_0_valid, // @[mshrs.scala:501:14] input [31:0] io_req_0_bits_uop_inst, // @[mshrs.scala:501:14] input [31:0] io_req_0_bits_uop_debug_inst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_rvc, // @[mshrs.scala:501:14] input [39:0] io_req_0_bits_uop_debug_pc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_0, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iq_type_3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_0, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_4, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_5, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_6, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_7, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_8, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fu_code_9, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] input [15:0] io_req_0_bits_uop_br_mask, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_br_tag, // @[mshrs.scala:501:14] input [3:0] io_req_0_bits_uop_br_type, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sfb, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_fence, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_fencei, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sfence, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_amo, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_eret, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_rocc, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_mov, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_ftq_idx, // @[mshrs.scala:501:14] input io_req_0_bits_uop_edge_inst, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_pc_lob, // @[mshrs.scala:501:14] input io_req_0_bits_uop_taken, // @[mshrs.scala:501:14] input io_req_0_bits_uop_imm_rename, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_imm_sel, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_pimm, // @[mshrs.scala:501:14] input [19:0] io_req_0_bits_uop_imm_packed, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_op1_sel, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_op2_sel, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_rob_idx, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_ldq_idx, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_stq_idx, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_rxq_idx, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_pdst, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs1, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs2, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_prs3, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_ppred, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs1_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs2_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_prs3_busy, // @[mshrs.scala:501:14] input io_req_0_bits_uop_ppred_busy, // @[mshrs.scala:501:14] input [6:0] io_req_0_bits_uop_stale_pdst, // @[mshrs.scala:501:14] input io_req_0_bits_uop_exception, // @[mshrs.scala:501:14] input [63:0] io_req_0_bits_uop_exc_cause, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_mem_cmd, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_mem_size, // @[mshrs.scala:501:14] input io_req_0_bits_uop_mem_signed, // @[mshrs.scala:501:14] input io_req_0_bits_uop_uses_ldq, // @[mshrs.scala:501:14] input io_req_0_bits_uop_uses_stq, // @[mshrs.scala:501:14] input io_req_0_bits_uop_is_unique, // @[mshrs.scala:501:14] input io_req_0_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_csr_cmd, // @[mshrs.scala:501:14] input io_req_0_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_ldst, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs1, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs2, // @[mshrs.scala:501:14] input [5:0] io_req_0_bits_uop_lrs3, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_dst_rtype, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] input io_req_0_bits_uop_frs3_en, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fcn_dw, // @[mshrs.scala:501:14] input [4:0] io_req_0_bits_uop_fcn_op, // @[mshrs.scala:501:14] input io_req_0_bits_uop_fp_val, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_fp_rm, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_uop_fp_typ, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] input io_req_0_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] input [2:0] io_req_0_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] input [39:0] io_req_0_bits_addr, // @[mshrs.scala:501:14] input [63:0] io_req_0_bits_data, // @[mshrs.scala:501:14] input io_req_0_bits_is_hella, // @[mshrs.scala:501:14] input io_req_0_bits_tag_match, // @[mshrs.scala:501:14] input [1:0] io_req_0_bits_old_meta_coh_state, // @[mshrs.scala:501:14] input [19:0] io_req_0_bits_old_meta_tag, // @[mshrs.scala:501:14] input [7:0] io_req_0_bits_way_en, // @[mshrs.scala:501:14] input io_req_is_probe_0, // @[mshrs.scala:501:14] input io_resp_ready, // @[mshrs.scala:501:14] output io_resp_valid, // @[mshrs.scala:501:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:501:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:501:14] output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_0, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_1, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_2, // @[mshrs.scala:501:14] output io_resp_bits_uop_iq_type_3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_0, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_1, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_2, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_4, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_5, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_6, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_7, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_8, // @[mshrs.scala:501:14] output io_resp_bits_uop_fu_code_9, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] output [15:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:501:14] output [3:0] io_resp_bits_uop_br_type, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sfence, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_eret, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_rocc, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_mov, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:501:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:501:14] output io_resp_bits_uop_taken, // @[mshrs.scala:501:14] output io_resp_bits_uop_imm_rename, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_imm_sel, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_pimm, // @[mshrs.scala:501:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_op1_sel, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_op2_sel, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_ppred, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:501:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:501:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:501:14] output io_resp_bits_uop_exception, // @[mshrs.scala:501:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:501:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:501:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:501:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:501:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:501:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[mshrs.scala:501:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:501:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:501:14] output io_resp_bits_uop_fcn_dw, // @[mshrs.scala:501:14] output [4:0] io_resp_bits_uop_fcn_op, // @[mshrs.scala:501:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_fp_rm, // @[mshrs.scala:501:14] output [1:0] io_resp_bits_uop_fp_typ, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:501:14] output io_resp_bits_is_hella, // @[mshrs.scala:501:14] output io_secondary_miss_0, // @[mshrs.scala:501:14] output io_block_hit_0, // @[mshrs.scala:501:14] input [15:0] io_brupdate_b1_resolve_mask, // @[mshrs.scala:501:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[mshrs.scala:501:14] input [31:0] io_brupdate_b2_uop_inst, // @[mshrs.scala:501:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_rvc, // @[mshrs.scala:501:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_0, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iq_type_3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_0, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_4, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_5, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_6, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_7, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_8, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fu_code_9, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[mshrs.scala:501:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[mshrs.scala:501:14] input [3:0] io_brupdate_b2_uop_br_type, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sfb, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_fence, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_fencei, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sfence, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_amo, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_eret, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_rocc, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_mov, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_edge_inst, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_taken, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_imm_rename, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_pimm, // @[mshrs.scala:501:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_pdst, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs1, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs2, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_prs3, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_ppred, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs1_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs2_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_prs3_busy, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_ppred_busy, // @[mshrs.scala:501:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_exception, // @[mshrs.scala:501:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_mem_signed, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_uses_ldq, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_uses_stq, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_is_unique, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_flush_on_commit, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_ldst, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[mshrs.scala:501:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_frs3_en, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fcn_dw, // @[mshrs.scala:501:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_fp_val, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_bp_debug_if, // @[mshrs.scala:501:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[mshrs.scala:501:14] input io_brupdate_b2_mispredict, // @[mshrs.scala:501:14] input io_brupdate_b2_taken, // @[mshrs.scala:501:14] input [2:0] io_brupdate_b2_cfi_type, // @[mshrs.scala:501:14] input [1:0] io_brupdate_b2_pc_sel, // @[mshrs.scala:501:14] input [39:0] io_brupdate_b2_jalr_target, // @[mshrs.scala:501:14] input [20:0] io_brupdate_b2_target_offset, // @[mshrs.scala:501:14] input io_exception, // @[mshrs.scala:501:14] input [6:0] io_rob_pnr_idx, // @[mshrs.scala:501:14] input [6:0] io_rob_head_idx, // @[mshrs.scala:501:14] input io_mem_acquire_ready, // @[mshrs.scala:501:14] output io_mem_acquire_valid, // @[mshrs.scala:501:14] output [2:0] io_mem_acquire_bits_opcode, // @[mshrs.scala:501:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:501:14] output [3:0] io_mem_acquire_bits_size, // @[mshrs.scala:501:14] output [2:0] io_mem_acquire_bits_source, // @[mshrs.scala:501:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:501:14] output [15:0] io_mem_acquire_bits_mask, // @[mshrs.scala:501:14] output [127:0] io_mem_acquire_bits_data, // @[mshrs.scala:501:14] output io_mem_grant_ready, // @[mshrs.scala:501:14] input io_mem_grant_valid, // @[mshrs.scala:501:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:501:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:501:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:501:14] input [2:0] io_mem_grant_bits_source, // @[mshrs.scala:501:14] input [3:0] io_mem_grant_bits_sink, // @[mshrs.scala:501:14] input io_mem_grant_bits_denied, // @[mshrs.scala:501:14] input [127:0] io_mem_grant_bits_data, // @[mshrs.scala:501:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:501:14] input io_mem_finish_ready, // @[mshrs.scala:501:14] output io_mem_finish_valid, // @[mshrs.scala:501:14] output [3:0] io_mem_finish_bits_sink, // @[mshrs.scala:501:14] input io_refill_ready, // @[mshrs.scala:501:14] output io_refill_valid, // @[mshrs.scala:501:14] output [7:0] io_refill_bits_way_en, // @[mshrs.scala:501:14] output [11:0] io_refill_bits_addr, // @[mshrs.scala:501:14] output [127:0] io_refill_bits_data, // @[mshrs.scala:501:14] input io_meta_write_ready, // @[mshrs.scala:501:14] output io_meta_write_valid, // @[mshrs.scala:501:14] output [5:0] io_meta_write_bits_idx, // @[mshrs.scala:501:14] output [7:0] io_meta_write_bits_way_en, // @[mshrs.scala:501:14] output [19:0] io_meta_write_bits_tag, // @[mshrs.scala:501:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:501:14] output [19:0] io_meta_write_bits_data_tag, // @[mshrs.scala:501:14] input io_meta_read_ready, // @[mshrs.scala:501:14] output io_meta_read_valid, // @[mshrs.scala:501:14] output [5:0] io_meta_read_bits_idx, // @[mshrs.scala:501:14] output [7:0] io_meta_read_bits_way_en, // @[mshrs.scala:501:14] output [19:0] io_meta_read_bits_tag, // @[mshrs.scala:501:14] input io_meta_resp_valid, // @[mshrs.scala:501:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:501:14] input [19:0] io_meta_resp_bits_tag, // @[mshrs.scala:501:14] input io_replay_ready, // @[mshrs.scala:501:14] output io_replay_valid, // @[mshrs.scala:501:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:501:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:501:14] output [39:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_0, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_1, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_2, // @[mshrs.scala:501:14] output io_replay_bits_uop_iq_type_3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_0, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_1, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_2, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_4, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_5, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_6, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_7, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_8, // @[mshrs.scala:501:14] output io_replay_bits_uop_fu_code_9, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued_partial_agen, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_issued_partial_dgen, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_iw_p1_speculative_child, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_iw_p2_speculative_child, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p1_bypass_hint, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p2_bypass_hint, // @[mshrs.scala:501:14] output io_replay_bits_uop_iw_p3_bypass_hint, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_dis_col_sel, // @[mshrs.scala:501:14] output [15:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:501:14] output [3:0] io_replay_bits_uop_br_type, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sfence, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_eret, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_rocc, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_mov, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:501:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:501:14] output io_replay_bits_uop_taken, // @[mshrs.scala:501:14] output io_replay_bits_uop_imm_rename, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_imm_sel, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_pimm, // @[mshrs.scala:501:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_op1_sel, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_op2_sel, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ldst, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_wen, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren1, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren2, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_ren3, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_swap12, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_swap23, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fromint, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_toint, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fastpipe, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_fma, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_div, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_sqrt, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_wflags, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_ctrl_vec, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_ppred, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:501:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:501:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:501:14] output io_replay_bits_uop_exception, // @[mshrs.scala:501:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:501:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:501:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:501:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:501:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:501:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_csr_cmd, // @[mshrs.scala:501:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:501:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:501:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:501:14] output io_replay_bits_uop_fcn_dw, // @[mshrs.scala:501:14] output [4:0] io_replay_bits_uop_fcn_op, // @[mshrs.scala:501:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_fp_rm, // @[mshrs.scala:501:14] output [1:0] io_replay_bits_uop_fp_typ, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:501:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:501:14] output [2:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:501:14] output [39:0] io_replay_bits_addr, // @[mshrs.scala:501:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:501:14] output io_replay_bits_is_hella, // @[mshrs.scala:501:14] output [7:0] io_replay_bits_way_en, // @[mshrs.scala:501:14] input io_prefetch_ready, // @[mshrs.scala:501:14] input io_wb_req_ready, // @[mshrs.scala:501:14] output io_wb_req_valid, // @[mshrs.scala:501:14] output [19:0] io_wb_req_bits_tag, // @[mshrs.scala:501:14] output [5:0] io_wb_req_bits_idx, // @[mshrs.scala:501:14] output [2:0] io_wb_req_bits_source, // @[mshrs.scala:501:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:501:14] output [7:0] io_wb_req_bits_way_en, // @[mshrs.scala:501:14] input io_prober_state_valid, // @[mshrs.scala:501:14] input [39:0] io_prober_state_bits, // @[mshrs.scala:501:14] input io_clear_all, // @[mshrs.scala:501:14] input io_wb_resp, // @[mshrs.scala:501:14] output io_fence_rdy, // @[mshrs.scala:501:14] output io_probe_rdy // @[mshrs.scala:501:14] ); wire io_req_0_ready_0; // @[mshrs.scala:498:7] wire _respq_io_enq_ready; // @[mshrs.scala:720:21] wire _mmios_0_io_req_ready; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_valid; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_resp_bits_uop_inst; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_resp_bits_uop_debug_inst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_rvc; // @[mshrs.scala:693:22] wire [39:0] _mmios_0_io_resp_bits_uop_debug_pc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:693:22] wire [15:0] _mmios_0_io_resp_bits_uop_br_mask; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_br_tag; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_resp_bits_uop_br_type; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sfb; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_fence; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_fencei; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sfence; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_amo; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_eret; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_rocc; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_mov; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_edge_inst; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_pc_lob; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_taken; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_imm_rename; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_imm_sel; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_pimm; // @[mshrs.scala:693:22] wire [19:0] _mmios_0_io_resp_bits_uop_imm_packed; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_op1_sel; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_op2_sel; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_rob_idx; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_stq_idx; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_pdst; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs1; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs2; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_prs3; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_ppred; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:693:22] wire [6:0] _mmios_0_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_exception; // @[mshrs.scala:693:22] wire [63:0] _mmios_0_io_resp_bits_uop_exc_cause; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_mem_size; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_mem_signed; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_uses_stq; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_is_unique; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_ldst; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs1; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs2; // @[mshrs.scala:693:22] wire [5:0] _mmios_0_io_resp_bits_uop_lrs3; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_frs3_en; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:693:22] wire [4:0] _mmios_0_io_resp_bits_uop_fcn_op; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_fp_val; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_fp_rm; // @[mshrs.scala:693:22] wire [1:0] _mmios_0_io_resp_bits_uop_fp_typ; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:693:22] wire [63:0] _mmios_0_io_resp_bits_data; // @[mshrs.scala:693:22] wire _mmios_0_io_resp_bits_is_hella; // @[mshrs.scala:693:22] wire _mmios_0_io_mem_access_valid; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_mem_access_bits_opcode; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_mem_access_bits_param; // @[mshrs.scala:693:22] wire [3:0] _mmios_0_io_mem_access_bits_size; // @[mshrs.scala:693:22] wire [2:0] _mmios_0_io_mem_access_bits_source; // @[mshrs.scala:693:22] wire [31:0] _mmios_0_io_mem_access_bits_address; // @[mshrs.scala:693:22] wire [15:0] _mmios_0_io_mem_access_bits_mask; // @[mshrs.scala:693:22] wire [127:0] _mmios_0_io_mem_access_bits_data; // @[mshrs.scala:693:22] wire _mmio_alloc_arb_io_in_0_ready; // @[mshrs.scala:686:30] wire _mshrs_3_io_req_pri_rdy; // @[mshrs.scala:602:22] wire _mshrs_3_io_req_sec_rdy; // @[mshrs.scala:602:22] wire _mshrs_3_io_idx_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_idx_bits; // @[mshrs.scala:602:22] wire _mshrs_3_io_way_valid; // @[mshrs.scala:602:22] wire [7:0] _mshrs_3_io_way_bits; // @[mshrs.scala:602:22] wire _mshrs_3_io_tag_valid; // @[mshrs.scala:602:22] wire [27:0] _mshrs_3_io_tag_bits; // @[mshrs.scala:602:22] wire _mshrs_3_io_mem_acquire_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_mem_acquire_bits_param; // @[mshrs.scala:602:22] wire [31:0] _mshrs_3_io_mem_acquire_bits_address; // @[mshrs.scala:602:22] wire _mshrs_3_io_mem_grant_ready; // @[mshrs.scala:602:22] wire _mshrs_3_io_mem_finish_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_3_io_mem_finish_bits_sink; // @[mshrs.scala:602:22] wire _mshrs_3_io_refill_valid; // @[mshrs.scala:602:22] wire [7:0] _mshrs_3_io_refill_bits_way_en; // @[mshrs.scala:602:22] wire [11:0] _mshrs_3_io_refill_bits_addr; // @[mshrs.scala:602:22] wire [127:0] _mshrs_3_io_refill_bits_data; // @[mshrs.scala:602:22] wire _mshrs_3_io_meta_write_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_meta_write_bits_idx; // @[mshrs.scala:602:22] wire [7:0] _mshrs_3_io_meta_write_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_3_io_meta_write_bits_tag; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_meta_write_bits_data_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_3_io_meta_write_bits_data_tag; // @[mshrs.scala:602:22] wire _mshrs_3_io_meta_read_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_meta_read_bits_idx; // @[mshrs.scala:602:22] wire [7:0] _mshrs_3_io_meta_read_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_3_io_meta_read_bits_tag; // @[mshrs.scala:602:22] wire _mshrs_3_io_wb_req_valid; // @[mshrs.scala:602:22] wire [19:0] _mshrs_3_io_wb_req_bits_tag; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_wb_req_bits_idx; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_wb_req_bits_param; // @[mshrs.scala:602:22] wire [7:0] _mshrs_3_io_wb_req_bits_way_en; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_lb_read_offset; // @[mshrs.scala:602:22] wire _mshrs_3_io_lb_write_valid; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_lb_write_bits_offset; // @[mshrs.scala:602:22] wire [127:0] _mshrs_3_io_lb_write_bits_data; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_3_io_replay_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_3_io_replay_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_3_io_replay_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [15:0] _mshrs_3_io_replay_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_3_io_replay_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_3_io_replay_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_replay_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_replay_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_replay_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_3_io_replay_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_replay_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_replay_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_replay_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_replay_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_replay_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_replay_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_replay_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_replay_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_replay_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_3_io_replay_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_replay_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_replay_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_replay_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_replay_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_replay_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_replay_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_replay_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_3_io_replay_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_3_io_replay_bits_data; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_3_io_replay_bits_tag_match; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_replay_bits_old_meta_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_3_io_replay_bits_old_meta_tag; // @[mshrs.scala:602:22] wire [7:0] _mshrs_3_io_replay_bits_way_en; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_replay_bits_sdq_id; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_3_io_resp_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_3_io_resp_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_3_io_resp_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [15:0] _mshrs_3_io_resp_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_3_io_resp_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_3_io_resp_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_resp_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_resp_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_3_io_resp_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_resp_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_resp_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_resp_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_resp_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_resp_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_resp_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_resp_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_3_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_3_io_resp_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_resp_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_resp_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_resp_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_3_io_resp_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_3_io_resp_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_3_io_resp_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_3_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [63:0] _mshrs_3_io_resp_bits_data; // @[mshrs.scala:602:22] wire _mshrs_3_io_resp_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_3_io_probe_rdy; // @[mshrs.scala:602:22] wire _mshrs_2_io_req_pri_rdy; // @[mshrs.scala:602:22] wire _mshrs_2_io_req_sec_rdy; // @[mshrs.scala:602:22] wire _mshrs_2_io_idx_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_idx_bits; // @[mshrs.scala:602:22] wire _mshrs_2_io_way_valid; // @[mshrs.scala:602:22] wire [7:0] _mshrs_2_io_way_bits; // @[mshrs.scala:602:22] wire _mshrs_2_io_tag_valid; // @[mshrs.scala:602:22] wire [27:0] _mshrs_2_io_tag_bits; // @[mshrs.scala:602:22] wire _mshrs_2_io_mem_acquire_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_mem_acquire_bits_param; // @[mshrs.scala:602:22] wire [31:0] _mshrs_2_io_mem_acquire_bits_address; // @[mshrs.scala:602:22] wire _mshrs_2_io_mem_grant_ready; // @[mshrs.scala:602:22] wire _mshrs_2_io_mem_finish_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_2_io_mem_finish_bits_sink; // @[mshrs.scala:602:22] wire _mshrs_2_io_refill_valid; // @[mshrs.scala:602:22] wire [7:0] _mshrs_2_io_refill_bits_way_en; // @[mshrs.scala:602:22] wire [11:0] _mshrs_2_io_refill_bits_addr; // @[mshrs.scala:602:22] wire [127:0] _mshrs_2_io_refill_bits_data; // @[mshrs.scala:602:22] wire _mshrs_2_io_meta_write_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_meta_write_bits_idx; // @[mshrs.scala:602:22] wire [7:0] _mshrs_2_io_meta_write_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_2_io_meta_write_bits_tag; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_meta_write_bits_data_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_2_io_meta_write_bits_data_tag; // @[mshrs.scala:602:22] wire _mshrs_2_io_meta_read_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_meta_read_bits_idx; // @[mshrs.scala:602:22] wire [7:0] _mshrs_2_io_meta_read_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_2_io_meta_read_bits_tag; // @[mshrs.scala:602:22] wire _mshrs_2_io_wb_req_valid; // @[mshrs.scala:602:22] wire [19:0] _mshrs_2_io_wb_req_bits_tag; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_wb_req_bits_idx; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_wb_req_bits_param; // @[mshrs.scala:602:22] wire [7:0] _mshrs_2_io_wb_req_bits_way_en; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_lb_read_offset; // @[mshrs.scala:602:22] wire _mshrs_2_io_lb_write_valid; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_lb_write_bits_offset; // @[mshrs.scala:602:22] wire [127:0] _mshrs_2_io_lb_write_bits_data; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_2_io_replay_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_2_io_replay_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_2_io_replay_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [15:0] _mshrs_2_io_replay_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_2_io_replay_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_2_io_replay_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_replay_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_replay_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_replay_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_2_io_replay_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_replay_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_replay_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_replay_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_replay_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_replay_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_replay_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_replay_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_replay_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_replay_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_2_io_replay_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_replay_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_replay_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_replay_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_replay_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_replay_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_replay_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_replay_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_2_io_replay_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_2_io_replay_bits_data; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_2_io_replay_bits_tag_match; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_replay_bits_old_meta_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_2_io_replay_bits_old_meta_tag; // @[mshrs.scala:602:22] wire [7:0] _mshrs_2_io_replay_bits_way_en; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_replay_bits_sdq_id; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_2_io_resp_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_2_io_resp_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_2_io_resp_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [15:0] _mshrs_2_io_resp_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_2_io_resp_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_2_io_resp_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_resp_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_resp_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_2_io_resp_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_resp_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_resp_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_resp_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_resp_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_resp_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_resp_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_resp_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_2_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_2_io_resp_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_resp_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_resp_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_resp_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_2_io_resp_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_2_io_resp_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_2_io_resp_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_2_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [63:0] _mshrs_2_io_resp_bits_data; // @[mshrs.scala:602:22] wire _mshrs_2_io_resp_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_2_io_probe_rdy; // @[mshrs.scala:602:22] wire _mshrs_1_io_req_pri_rdy; // @[mshrs.scala:602:22] wire _mshrs_1_io_req_sec_rdy; // @[mshrs.scala:602:22] wire _mshrs_1_io_idx_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_idx_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_way_valid; // @[mshrs.scala:602:22] wire [7:0] _mshrs_1_io_way_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_tag_valid; // @[mshrs.scala:602:22] wire [27:0] _mshrs_1_io_tag_bits; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_acquire_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_mem_acquire_bits_param; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_mem_acquire_bits_address; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_grant_ready; // @[mshrs.scala:602:22] wire _mshrs_1_io_mem_finish_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_mem_finish_bits_sink; // @[mshrs.scala:602:22] wire _mshrs_1_io_refill_valid; // @[mshrs.scala:602:22] wire [7:0] _mshrs_1_io_refill_bits_way_en; // @[mshrs.scala:602:22] wire [11:0] _mshrs_1_io_refill_bits_addr; // @[mshrs.scala:602:22] wire [127:0] _mshrs_1_io_refill_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_meta_write_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_meta_write_bits_idx; // @[mshrs.scala:602:22] wire [7:0] _mshrs_1_io_meta_write_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_write_bits_tag; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_meta_write_bits_data_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_write_bits_data_tag; // @[mshrs.scala:602:22] wire _mshrs_1_io_meta_read_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_meta_read_bits_idx; // @[mshrs.scala:602:22] wire [7:0] _mshrs_1_io_meta_read_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_meta_read_bits_tag; // @[mshrs.scala:602:22] wire _mshrs_1_io_wb_req_valid; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_wb_req_bits_tag; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_wb_req_bits_idx; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_wb_req_bits_param; // @[mshrs.scala:602:22] wire [7:0] _mshrs_1_io_wb_req_bits_way_en; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_lb_read_offset; // @[mshrs.scala:602:22] wire _mshrs_1_io_lb_write_valid; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_lb_write_bits_offset; // @[mshrs.scala:602:22] wire [127:0] _mshrs_1_io_lb_write_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_replay_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_replay_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_replay_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [15:0] _mshrs_1_io_replay_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_replay_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_replay_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_replay_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_replay_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_replay_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_replay_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_replay_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_replay_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_1_io_replay_bits_tag_match; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_replay_bits_old_meta_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_replay_bits_old_meta_tag; // @[mshrs.scala:602:22] wire [7:0] _mshrs_1_io_replay_bits_way_en; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_replay_bits_sdq_id; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_resp_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_1_io_resp_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_1_io_resp_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [15:0] _mshrs_1_io_resp_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_1_io_resp_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_1_io_resp_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_1_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_resp_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_1_io_resp_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_1_io_resp_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_1_io_resp_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_1_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [63:0] _mshrs_1_io_resp_bits_data; // @[mshrs.scala:602:22] wire _mshrs_1_io_resp_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_1_io_probe_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_req_pri_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_req_sec_rdy; // @[mshrs.scala:602:22] wire _mshrs_0_io_idx_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_idx_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_way_valid; // @[mshrs.scala:602:22] wire [7:0] _mshrs_0_io_way_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_tag_valid; // @[mshrs.scala:602:22] wire [27:0] _mshrs_0_io_tag_bits; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_acquire_valid; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_mem_acquire_bits_param; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_mem_acquire_bits_address; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_grant_ready; // @[mshrs.scala:602:22] wire _mshrs_0_io_mem_finish_valid; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_mem_finish_bits_sink; // @[mshrs.scala:602:22] wire _mshrs_0_io_refill_valid; // @[mshrs.scala:602:22] wire [7:0] _mshrs_0_io_refill_bits_way_en; // @[mshrs.scala:602:22] wire [11:0] _mshrs_0_io_refill_bits_addr; // @[mshrs.scala:602:22] wire [127:0] _mshrs_0_io_refill_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_meta_write_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_meta_write_bits_idx; // @[mshrs.scala:602:22] wire [7:0] _mshrs_0_io_meta_write_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_write_bits_tag; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_meta_write_bits_data_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_write_bits_data_tag; // @[mshrs.scala:602:22] wire _mshrs_0_io_meta_read_valid; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_meta_read_bits_idx; // @[mshrs.scala:602:22] wire [7:0] _mshrs_0_io_meta_read_bits_way_en; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_meta_read_bits_tag; // @[mshrs.scala:602:22] wire _mshrs_0_io_wb_req_valid; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_wb_req_bits_tag; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_wb_req_bits_idx; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_wb_req_bits_param; // @[mshrs.scala:602:22] wire [7:0] _mshrs_0_io_wb_req_bits_way_en; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_lb_read_offset; // @[mshrs.scala:602:22] wire _mshrs_0_io_lb_write_valid; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_lb_write_bits_offset; // @[mshrs.scala:602:22] wire [127:0] _mshrs_0_io_lb_write_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_replay_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_replay_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_replay_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [15:0] _mshrs_0_io_replay_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_replay_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_replay_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_replay_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_replay_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_replay_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_replay_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_replay_bits_addr; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_replay_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_0_io_replay_bits_tag_match; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_replay_bits_old_meta_coh_state; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_replay_bits_old_meta_tag; // @[mshrs.scala:602:22] wire [7:0] _mshrs_0_io_replay_bits_way_en; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_replay_bits_sdq_id; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_valid; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_resp_bits_uop_inst; // @[mshrs.scala:602:22] wire [31:0] _mshrs_0_io_resp_bits_uop_debug_inst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_rvc; // @[mshrs.scala:602:22] wire [39:0] _mshrs_0_io_resp_bits_uop_debug_pc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iq_type_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_0; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_4; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_5; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_6; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_7; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_8; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fu_code_9; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_dis_col_sel; // @[mshrs.scala:602:22] wire [15:0] _mshrs_0_io_resp_bits_uop_br_mask; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_br_tag; // @[mshrs.scala:602:22] wire [3:0] _mshrs_0_io_resp_bits_uop_br_type; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sfb; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_fence; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_fencei; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sfence; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_amo; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_eret; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_sys_pc2epc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_rocc; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_mov; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_ftq_idx; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_edge_inst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_pc_lob; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_taken; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_imm_rename; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_imm_sel; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_pimm; // @[mshrs.scala:602:22] wire [19:0] _mshrs_0_io_resp_bits_uop_imm_packed; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_op1_sel; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_op2_sel; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_wen; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_toint; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_fma; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_div; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_ctrl_vec; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_rob_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_ldq_idx; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_stq_idx; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_rxq_idx; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_pdst; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs1; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs2; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_prs3; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_ppred; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs1_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs2_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_prs3_busy; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_ppred_busy; // @[mshrs.scala:602:22] wire [6:0] _mshrs_0_io_resp_bits_uop_stale_pdst; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_exception; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_resp_bits_uop_exc_cause; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_mem_cmd; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_mem_size; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_mem_signed; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_uses_ldq; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_uses_stq; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_is_unique; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_flush_on_commit; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_csr_cmd; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_ldst_is_rs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_ldst; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs1; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs2; // @[mshrs.scala:602:22] wire [5:0] _mshrs_0_io_resp_bits_uop_lrs3; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_dst_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_lrs1_rtype; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_lrs2_rtype; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_frs3_en; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fcn_dw; // @[mshrs.scala:602:22] wire [4:0] _mshrs_0_io_resp_bits_uop_fcn_op; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_fp_val; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_fp_rm; // @[mshrs.scala:602:22] wire [1:0] _mshrs_0_io_resp_bits_uop_fp_typ; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_pf_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_ae_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_xcpt_ma_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_bp_debug_if; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_uop_bp_xcpt_if; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_debug_fsrc; // @[mshrs.scala:602:22] wire [2:0] _mshrs_0_io_resp_bits_uop_debug_tsrc; // @[mshrs.scala:602:22] wire [63:0] _mshrs_0_io_resp_bits_data; // @[mshrs.scala:602:22] wire _mshrs_0_io_resp_bits_is_hella; // @[mshrs.scala:602:22] wire _mshrs_0_io_probe_rdy; // @[mshrs.scala:602:22] wire _refill_arb_io_in_0_ready; // @[mshrs.scala:586:30] wire _refill_arb_io_in_1_ready; // @[mshrs.scala:586:30] wire _refill_arb_io_in_2_ready; // @[mshrs.scala:586:30] wire _refill_arb_io_in_3_ready; // @[mshrs.scala:586:30] wire _resp_arb_io_in_0_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_in_1_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_in_2_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_in_3_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_in_4_ready; // @[mshrs.scala:585:30] wire _resp_arb_io_out_valid; // @[mshrs.scala:585:30] wire [31:0] _resp_arb_io_out_bits_uop_inst; // @[mshrs.scala:585:30] wire [31:0] _resp_arb_io_out_bits_uop_debug_inst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_rvc; // @[mshrs.scala:585:30] wire [39:0] _resp_arb_io_out_bits_uop_debug_pc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_0; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iq_type_3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_0; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_4; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_5; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_6; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_7; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_8; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fu_code_9; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_dis_col_sel; // @[mshrs.scala:585:30] wire [15:0] _resp_arb_io_out_bits_uop_br_mask; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_br_tag; // @[mshrs.scala:585:30] wire [3:0] _resp_arb_io_out_bits_uop_br_type; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sfb; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_fence; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_fencei; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sfence; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_amo; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_eret; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_sys_pc2epc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_rocc; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_mov; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_ftq_idx; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_edge_inst; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_pc_lob; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_taken; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_imm_rename; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_imm_sel; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_pimm; // @[mshrs.scala:585:30] wire [19:0] _resp_arb_io_out_bits_uop_imm_packed; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_op1_sel; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_op2_sel; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_wen; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_toint; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_fma; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_div; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_ctrl_vec; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_rob_idx; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_ldq_idx; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_stq_idx; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_rxq_idx; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_pdst; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs1; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs2; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_prs3; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_ppred; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs1_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs2_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_prs3_busy; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_ppred_busy; // @[mshrs.scala:585:30] wire [6:0] _resp_arb_io_out_bits_uop_stale_pdst; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_exception; // @[mshrs.scala:585:30] wire [63:0] _resp_arb_io_out_bits_uop_exc_cause; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_mem_cmd; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_mem_size; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_mem_signed; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_uses_ldq; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_uses_stq; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_is_unique; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_flush_on_commit; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_csr_cmd; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_ldst_is_rs1; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_ldst; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs1; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs2; // @[mshrs.scala:585:30] wire [5:0] _resp_arb_io_out_bits_uop_lrs3; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_dst_rtype; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_lrs1_rtype; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_lrs2_rtype; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_frs3_en; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fcn_dw; // @[mshrs.scala:585:30] wire [4:0] _resp_arb_io_out_bits_uop_fcn_op; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_fp_val; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_fp_rm; // @[mshrs.scala:585:30] wire [1:0] _resp_arb_io_out_bits_uop_fp_typ; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_pf_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_ae_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_xcpt_ma_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_bp_debug_if; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_uop_bp_xcpt_if; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_debug_fsrc; // @[mshrs.scala:585:30] wire [2:0] _resp_arb_io_out_bits_uop_debug_tsrc; // @[mshrs.scala:585:30] wire [63:0] _resp_arb_io_out_bits_data; // @[mshrs.scala:585:30] wire _resp_arb_io_out_bits_is_hella; // @[mshrs.scala:585:30] wire _replay_arb_io_in_0_ready; // @[mshrs.scala:584:30] wire _replay_arb_io_in_1_ready; // @[mshrs.scala:584:30] wire _replay_arb_io_in_2_ready; // @[mshrs.scala:584:30] wire _replay_arb_io_in_3_ready; // @[mshrs.scala:584:30] wire [4:0] _replay_arb_io_out_bits_sdq_id; // @[mshrs.scala:584:30] wire _wb_req_arb_io_in_0_ready; // @[mshrs.scala:583:30] wire _wb_req_arb_io_in_1_ready; // @[mshrs.scala:583:30] wire _wb_req_arb_io_in_2_ready; // @[mshrs.scala:583:30] wire _wb_req_arb_io_in_3_ready; // @[mshrs.scala:583:30] wire _meta_read_arb_io_in_0_ready; // @[mshrs.scala:582:30] wire _meta_read_arb_io_in_1_ready; // @[mshrs.scala:582:30] wire _meta_read_arb_io_in_2_ready; // @[mshrs.scala:582:30] wire _meta_read_arb_io_in_3_ready; // @[mshrs.scala:582:30] wire _meta_write_arb_io_in_0_ready; // @[mshrs.scala:581:30] wire _meta_write_arb_io_in_1_ready; // @[mshrs.scala:581:30] wire _meta_write_arb_io_in_2_ready; // @[mshrs.scala:581:30] wire _meta_write_arb_io_in_3_ready; // @[mshrs.scala:581:30] wire io_req_0_valid_0 = io_req_0_valid; // @[mshrs.scala:498:7] wire [31:0] io_req_0_bits_uop_inst_0 = io_req_0_bits_uop_inst; // @[mshrs.scala:498:7] wire [31:0] io_req_0_bits_uop_debug_inst_0 = io_req_0_bits_uop_debug_inst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_rvc_0 = io_req_0_bits_uop_is_rvc; // @[mshrs.scala:498:7] wire [39:0] io_req_0_bits_uop_debug_pc_0 = io_req_0_bits_uop_debug_pc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_0_0 = io_req_0_bits_uop_iq_type_0; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_1_0 = io_req_0_bits_uop_iq_type_1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_2_0 = io_req_0_bits_uop_iq_type_2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iq_type_3_0 = io_req_0_bits_uop_iq_type_3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_0_0 = io_req_0_bits_uop_fu_code_0; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_1_0 = io_req_0_bits_uop_fu_code_1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_2_0 = io_req_0_bits_uop_fu_code_2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_3_0 = io_req_0_bits_uop_fu_code_3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_4_0 = io_req_0_bits_uop_fu_code_4; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_5_0 = io_req_0_bits_uop_fu_code_5; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_6_0 = io_req_0_bits_uop_fu_code_6; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_7_0 = io_req_0_bits_uop_fu_code_7; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_8_0 = io_req_0_bits_uop_fu_code_8; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fu_code_9_0 = io_req_0_bits_uop_fu_code_9; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_0 = io_req_0_bits_uop_iw_issued; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_partial_agen_0 = io_req_0_bits_uop_iw_issued_partial_agen; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_issued_partial_dgen_0 = io_req_0_bits_uop_iw_issued_partial_dgen; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_iw_p1_speculative_child_0 = io_req_0_bits_uop_iw_p1_speculative_child; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_iw_p2_speculative_child_0 = io_req_0_bits_uop_iw_p2_speculative_child; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p1_bypass_hint_0 = io_req_0_bits_uop_iw_p1_bypass_hint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p2_bypass_hint_0 = io_req_0_bits_uop_iw_p2_bypass_hint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_iw_p3_bypass_hint_0 = io_req_0_bits_uop_iw_p3_bypass_hint; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_dis_col_sel_0 = io_req_0_bits_uop_dis_col_sel; // @[mshrs.scala:498:7] wire [15:0] io_req_0_bits_uop_br_mask_0 = io_req_0_bits_uop_br_mask; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_br_tag_0 = io_req_0_bits_uop_br_tag; // @[mshrs.scala:498:7] wire [3:0] io_req_0_bits_uop_br_type_0 = io_req_0_bits_uop_br_type; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sfb_0 = io_req_0_bits_uop_is_sfb; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_fence_0 = io_req_0_bits_uop_is_fence; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_fencei_0 = io_req_0_bits_uop_is_fencei; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sfence_0 = io_req_0_bits_uop_is_sfence; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_amo_0 = io_req_0_bits_uop_is_amo; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_eret_0 = io_req_0_bits_uop_is_eret; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_sys_pc2epc_0 = io_req_0_bits_uop_is_sys_pc2epc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_rocc_0 = io_req_0_bits_uop_is_rocc; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_mov_0 = io_req_0_bits_uop_is_mov; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_ftq_idx_0 = io_req_0_bits_uop_ftq_idx; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_edge_inst_0 = io_req_0_bits_uop_edge_inst; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_pc_lob_0 = io_req_0_bits_uop_pc_lob; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_taken_0 = io_req_0_bits_uop_taken; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_imm_rename_0 = io_req_0_bits_uop_imm_rename; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_imm_sel_0 = io_req_0_bits_uop_imm_sel; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_pimm_0 = io_req_0_bits_uop_pimm; // @[mshrs.scala:498:7] wire [19:0] io_req_0_bits_uop_imm_packed_0 = io_req_0_bits_uop_imm_packed; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_op1_sel_0 = io_req_0_bits_uop_op1_sel; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_op2_sel_0 = io_req_0_bits_uop_op2_sel; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ldst_0 = io_req_0_bits_uop_fp_ctrl_ldst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_wen_0 = io_req_0_bits_uop_fp_ctrl_wen; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren1_0 = io_req_0_bits_uop_fp_ctrl_ren1; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren2_0 = io_req_0_bits_uop_fp_ctrl_ren2; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_ren3_0 = io_req_0_bits_uop_fp_ctrl_ren3; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_swap12_0 = io_req_0_bits_uop_fp_ctrl_swap12; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_swap23_0 = io_req_0_bits_uop_fp_ctrl_swap23; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_ctrl_typeTagIn_0 = io_req_0_bits_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_ctrl_typeTagOut_0 = io_req_0_bits_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fromint_0 = io_req_0_bits_uop_fp_ctrl_fromint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_toint_0 = io_req_0_bits_uop_fp_ctrl_toint; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fastpipe_0 = io_req_0_bits_uop_fp_ctrl_fastpipe; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_fma_0 = io_req_0_bits_uop_fp_ctrl_fma; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_div_0 = io_req_0_bits_uop_fp_ctrl_div; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_sqrt_0 = io_req_0_bits_uop_fp_ctrl_sqrt; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_wflags_0 = io_req_0_bits_uop_fp_ctrl_wflags; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_ctrl_vec_0 = io_req_0_bits_uop_fp_ctrl_vec; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_rob_idx_0 = io_req_0_bits_uop_rob_idx; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_ldq_idx_0 = io_req_0_bits_uop_ldq_idx; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_stq_idx_0 = io_req_0_bits_uop_stq_idx; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_rxq_idx_0 = io_req_0_bits_uop_rxq_idx; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_pdst_0 = io_req_0_bits_uop_pdst; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs1_0 = io_req_0_bits_uop_prs1; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs2_0 = io_req_0_bits_uop_prs2; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_prs3_0 = io_req_0_bits_uop_prs3; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_ppred_0 = io_req_0_bits_uop_ppred; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs1_busy_0 = io_req_0_bits_uop_prs1_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs2_busy_0 = io_req_0_bits_uop_prs2_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_prs3_busy_0 = io_req_0_bits_uop_prs3_busy; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_ppred_busy_0 = io_req_0_bits_uop_ppred_busy; // @[mshrs.scala:498:7] wire [6:0] io_req_0_bits_uop_stale_pdst_0 = io_req_0_bits_uop_stale_pdst; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_exception_0 = io_req_0_bits_uop_exception; // @[mshrs.scala:498:7] wire [63:0] io_req_0_bits_uop_exc_cause_0 = io_req_0_bits_uop_exc_cause; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_mem_cmd_0 = io_req_0_bits_uop_mem_cmd; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_mem_size_0 = io_req_0_bits_uop_mem_size; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_mem_signed_0 = io_req_0_bits_uop_mem_signed; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_uses_ldq_0 = io_req_0_bits_uop_uses_ldq; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_uses_stq_0 = io_req_0_bits_uop_uses_stq; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_is_unique_0 = io_req_0_bits_uop_is_unique; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_flush_on_commit_0 = io_req_0_bits_uop_flush_on_commit; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_csr_cmd_0 = io_req_0_bits_uop_csr_cmd; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_ldst_is_rs1_0 = io_req_0_bits_uop_ldst_is_rs1; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_ldst_0 = io_req_0_bits_uop_ldst; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs1_0 = io_req_0_bits_uop_lrs1; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs2_0 = io_req_0_bits_uop_lrs2; // @[mshrs.scala:498:7] wire [5:0] io_req_0_bits_uop_lrs3_0 = io_req_0_bits_uop_lrs3; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_dst_rtype_0 = io_req_0_bits_uop_dst_rtype; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_lrs1_rtype_0 = io_req_0_bits_uop_lrs1_rtype; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_lrs2_rtype_0 = io_req_0_bits_uop_lrs2_rtype; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_frs3_en_0 = io_req_0_bits_uop_frs3_en; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fcn_dw_0 = io_req_0_bits_uop_fcn_dw; // @[mshrs.scala:498:7] wire [4:0] io_req_0_bits_uop_fcn_op_0 = io_req_0_bits_uop_fcn_op; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_fp_val_0 = io_req_0_bits_uop_fp_val; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_fp_rm_0 = io_req_0_bits_uop_fp_rm; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_uop_fp_typ_0 = io_req_0_bits_uop_fp_typ; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_pf_if_0 = io_req_0_bits_uop_xcpt_pf_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_ae_if_0 = io_req_0_bits_uop_xcpt_ae_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_xcpt_ma_if_0 = io_req_0_bits_uop_xcpt_ma_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_bp_debug_if_0 = io_req_0_bits_uop_bp_debug_if; // @[mshrs.scala:498:7] wire io_req_0_bits_uop_bp_xcpt_if_0 = io_req_0_bits_uop_bp_xcpt_if; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_debug_fsrc_0 = io_req_0_bits_uop_debug_fsrc; // @[mshrs.scala:498:7] wire [2:0] io_req_0_bits_uop_debug_tsrc_0 = io_req_0_bits_uop_debug_tsrc; // @[mshrs.scala:498:7] wire [39:0] io_req_0_bits_addr_0 = io_req_0_bits_addr; // @[mshrs.scala:498:7] wire [63:0] io_req_0_bits_data_0 = io_req_0_bits_data; // @[mshrs.scala:498:7] wire io_req_0_bits_is_hella_0 = io_req_0_bits_is_hella; // @[mshrs.scala:498:7] wire io_req_0_bits_tag_match_0 = io_req_0_bits_tag_match; // @[mshrs.scala:498:7] wire [1:0] io_req_0_bits_old_meta_coh_state_0 = io_req_0_bits_old_meta_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_req_0_bits_old_meta_tag_0 = io_req_0_bits_old_meta_tag; // @[mshrs.scala:498:7] wire [7:0] io_req_0_bits_way_en_0 = io_req_0_bits_way_en; // @[mshrs.scala:498:7] wire io_req_is_probe_0_0 = io_req_is_probe_0; // @[mshrs.scala:498:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:498:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[mshrs.scala:498:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[mshrs.scala:498:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[mshrs.scala:498:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[mshrs.scala:498:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[mshrs.scala:498:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[mshrs.scala:498:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[mshrs.scala:498:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[mshrs.scala:498:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[mshrs.scala:498:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[mshrs.scala:498:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[mshrs.scala:498:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[mshrs.scala:498:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[mshrs.scala:498:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[mshrs.scala:498:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[mshrs.scala:498:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[mshrs.scala:498:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[mshrs.scala:498:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[mshrs.scala:498:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[mshrs.scala:498:7] wire io_exception_0 = io_exception; // @[mshrs.scala:498:7] wire [6:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:498:7] wire [6:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:498:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:498:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:498:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:498:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:498:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:498:7] wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:498:7] wire [3:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:498:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:498:7] wire [127:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:498:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:498:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:498:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:498:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:498:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:498:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:498:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:498:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:498:7] wire io_prefetch_ready_0 = io_prefetch_ready; // @[mshrs.scala:498:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:498:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:498:7] wire [39:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:498:7] wire io_clear_all_0 = io_clear_all; // @[mshrs.scala:498:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:498:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:498:7] wire _cacheable_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _cacheable_T_20 = 1'h1; // @[Parameters.scala:684:29] wire _mshr_alloc_idx_temp_vec_T_3 = 1'h1; // @[util.scala:352:72] wire _opdata_T = 1'h1; // @[Edges.scala:92:37] wire _opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _opdata_T_2 = 1'h1; // @[Edges.scala:92:37] wire _opdata_T_3 = 1'h1; // @[Edges.scala:92:37] wire _io_req_0_ready_T = 1'h1; // @[mshrs.scala:498:7, :727:34] wire [4:0] io_req_0_bits_sdq_id = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_ftq_idx = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_pimm = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_ldq_idx = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_stq_idx = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_ppred = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_mem_cmd = 5'h0; // @[mshrs.scala:498:7] wire [4:0] io_prefetch_bits_uop_fcn_op = 5'h0; // @[mshrs.scala:498:7] wire [4:0] req_bits_sdq_id = 5'h0; // @[mshrs.scala:536:25] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_valid = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_rvc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_0 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iq_type_3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_0 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_4 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_5 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_6 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_7 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_8 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fu_code_9 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued_partial_agen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_issued_partial_dgen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p1_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p2_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_iw_p3_bypass_hint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sfb = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_fence = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_fencei = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sfence = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_amo = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_eret = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_rocc = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_mov = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_edge_inst = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_taken = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_imm_rename = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ldst = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_wen = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren2 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_ren3 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_swap12 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_swap23 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fromint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_toint = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_fma = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_div = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_sqrt = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_wflags = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_ctrl_vec = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs1_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs2_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_prs3_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_ppred_busy = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_exception = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_mem_signed = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_uses_ldq = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_uses_stq = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_is_unique = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_flush_on_commit = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_frs3_en = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fcn_dw = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_fp_val = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_bp_debug_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:498:7] wire io_prefetch_bits_is_hella = 1'h0; // @[mshrs.scala:498:7] wire _cacheable_T = 1'h0; // @[Parameters.scala:684:29] wire _cacheable_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _cacheable_T_33 = 1'h0; // @[Parameters.scala:686:26] wire opdata = 1'h0; // @[Edges.scala:92:28] wire opdata_1 = 1'h0; // @[Edges.scala:92:28] wire opdata_2 = 1'h0; // @[Edges.scala:92:28] wire opdata_3 = 1'h0; // @[Edges.scala:92:28] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_3 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_4 = 1'h0; // @[Arbiter.scala:88:34] wire _io_mem_acquire_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_3 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_4 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_5 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_6 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_7 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_T_8 = 1'h0; // @[Mux.scala:30:73] wire _io_mem_acquire_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire maskedBeats_0_1 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_1_1 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_2_1 = 1'h0; // @[Arbiter.scala:82:69] wire maskedBeats_3_1 = 1'h0; // @[Arbiter.scala:82:69] wire _initBeats_T_3 = 1'h0; // @[Arbiter.scala:84:44] wire _initBeats_T_4 = 1'h0; // @[Arbiter.scala:84:44] wire initBeats_1 = 1'h0; // @[Arbiter.scala:84:44] wire _state_WIRE_1_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_1 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_2 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1_3 = 1'h0; // @[Arbiter.scala:88:34] wire [1:0] io_refill_bits_wmask = 2'h3; // @[mshrs.scala:498:7] wire [31:0] io_prefetch_bits_uop_inst = 32'h0; // @[mshrs.scala:498:7] wire [31:0] io_prefetch_bits_uop_debug_inst = 32'h0; // @[mshrs.scala:498:7] wire [39:0] io_prefetch_bits_uop_debug_pc = 40'h0; // @[mshrs.scala:498:7] wire [39:0] io_prefetch_bits_addr = 40'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_iw_p1_speculative_child = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_iw_p2_speculative_child = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_dis_col_sel = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_imm_sel = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_op2_sel = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_csr_cmd = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_fp_rm = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_debug_fsrc = 3'h0; // @[mshrs.scala:498:7] wire [2:0] io_prefetch_bits_uop_debug_tsrc = 3'h0; // @[mshrs.scala:498:7] wire [2:0] _io_mem_acquire_bits_T_36 = 3'h0; // @[Mux.scala:30:73] wire [15:0] io_prefetch_bits_uop_br_mask = 16'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_br_tag = 4'h0; // @[mshrs.scala:498:7] wire [3:0] io_prefetch_bits_uop_br_type = 4'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_pc_lob = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_ldst = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs1 = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs2 = 6'h0; // @[mshrs.scala:498:7] wire [5:0] io_prefetch_bits_uop_lrs3 = 6'h0; // @[mshrs.scala:498:7] wire [19:0] io_prefetch_bits_uop_imm_packed = 20'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_op1_sel = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_rxq_idx = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_mem_size = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_dst_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:498:7] wire [1:0] io_prefetch_bits_uop_fp_typ = 2'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_rob_idx = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_pdst = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs1 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs2 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_prs3 = 7'h0; // @[mshrs.scala:498:7] wire [6:0] io_prefetch_bits_uop_stale_pdst = 7'h0; // @[mshrs.scala:498:7] wire [63:0] io_prefetch_bits_uop_exc_cause = 64'h0; // @[mshrs.scala:498:7] wire [63:0] io_prefetch_bits_data = 64'h0; // @[mshrs.scala:498:7] wire [127:0] _io_mem_acquire_bits_T_9 = 128'h0; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_T_10 = 128'h0; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_T_11 = 128'h0; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_T_12 = 128'h0; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_T_14 = 128'h0; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_T_15 = 128'h0; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_T_16 = 128'h0; // @[Mux.scala:30:73] wire [7:0] maskedBeats_0 = 8'h0; // @[Arbiter.scala:82:69] wire [7:0] maskedBeats_1 = 8'h0; // @[Arbiter.scala:82:69] wire [7:0] maskedBeats_2 = 8'h0; // @[Arbiter.scala:82:69] wire [7:0] maskedBeats_3 = 8'h0; // @[Arbiter.scala:82:69] wire [7:0] _initBeats_T = 8'h0; // @[Arbiter.scala:84:44] wire [7:0] _initBeats_T_1 = 8'h0; // @[Arbiter.scala:84:44] wire [7:0] _initBeats_T_2 = 8'h0; // @[Arbiter.scala:84:44] wire [7:0] decode = 8'h3; // @[Edges.scala:220:59] wire [7:0] decode_1 = 8'h3; // @[Edges.scala:220:59] wire [7:0] decode_2 = 8'h3; // @[Edges.scala:220:59] wire [7:0] decode_3 = 8'h3; // @[Edges.scala:220:59] wire [11:0] _decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_8 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_11 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _decode_T_7 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _decode_T_10 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _decode_T_6 = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _decode_T_9 = 27'h3FFC0; // @[package.scala:243:71] wire _io_req_0_ready_T_6; // @[mshrs.scala:727:47] wire req_ready = io_req_0_ready_0; // @[mshrs.scala:498:7, :536:25] wire req_valid = io_req_0_valid_0; // @[mshrs.scala:498:7, :536:25] wire [31:0] req_bits_uop_inst = io_req_0_bits_uop_inst_0; // @[mshrs.scala:498:7, :536:25] wire [31:0] req_bits_uop_debug_inst = io_req_0_bits_uop_debug_inst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_rvc = io_req_0_bits_uop_is_rvc_0; // @[mshrs.scala:498:7, :536:25] wire [39:0] req_bits_uop_debug_pc = io_req_0_bits_uop_debug_pc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_0 = io_req_0_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_1 = io_req_0_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_2 = io_req_0_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iq_type_3 = io_req_0_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_0 = io_req_0_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_1 = io_req_0_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_2 = io_req_0_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_3 = io_req_0_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_4 = io_req_0_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_5 = io_req_0_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_6 = io_req_0_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_7 = io_req_0_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_8 = io_req_0_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fu_code_9 = io_req_0_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued = io_req_0_bits_uop_iw_issued_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued_partial_agen = io_req_0_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_issued_partial_dgen = io_req_0_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_iw_p1_speculative_child = io_req_0_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_iw_p2_speculative_child = io_req_0_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p1_bypass_hint = io_req_0_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p2_bypass_hint = io_req_0_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_iw_p3_bypass_hint = io_req_0_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_dis_col_sel = io_req_0_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7, :536:25] wire [15:0] req_bits_uop_br_mask = io_req_0_bits_uop_br_mask_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_br_tag = io_req_0_bits_uop_br_tag_0; // @[mshrs.scala:498:7, :536:25] wire [3:0] req_bits_uop_br_type = io_req_0_bits_uop_br_type_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sfb = io_req_0_bits_uop_is_sfb_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_fence = io_req_0_bits_uop_is_fence_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_fencei = io_req_0_bits_uop_is_fencei_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sfence = io_req_0_bits_uop_is_sfence_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_amo = io_req_0_bits_uop_is_amo_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_eret = io_req_0_bits_uop_is_eret_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_sys_pc2epc = io_req_0_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_rocc = io_req_0_bits_uop_is_rocc_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_mov = io_req_0_bits_uop_is_mov_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_ftq_idx = io_req_0_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_edge_inst = io_req_0_bits_uop_edge_inst_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_pc_lob = io_req_0_bits_uop_pc_lob_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_taken = io_req_0_bits_uop_taken_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_imm_rename = io_req_0_bits_uop_imm_rename_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_imm_sel = io_req_0_bits_uop_imm_sel_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_pimm = io_req_0_bits_uop_pimm_0; // @[mshrs.scala:498:7, :536:25] wire [19:0] req_bits_uop_imm_packed = io_req_0_bits_uop_imm_packed_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_op1_sel = io_req_0_bits_uop_op1_sel_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_op2_sel = io_req_0_bits_uop_op2_sel_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ldst = io_req_0_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_wen = io_req_0_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren1 = io_req_0_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren2 = io_req_0_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_ren3 = io_req_0_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_swap12 = io_req_0_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_swap23 = io_req_0_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_ctrl_typeTagIn = io_req_0_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_ctrl_typeTagOut = io_req_0_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fromint = io_req_0_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_toint = io_req_0_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fastpipe = io_req_0_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_fma = io_req_0_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_div = io_req_0_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_sqrt = io_req_0_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_wflags = io_req_0_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_ctrl_vec = io_req_0_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_rob_idx = io_req_0_bits_uop_rob_idx_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_ldq_idx = io_req_0_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_stq_idx = io_req_0_bits_uop_stq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_rxq_idx = io_req_0_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_pdst = io_req_0_bits_uop_pdst_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs1 = io_req_0_bits_uop_prs1_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs2 = io_req_0_bits_uop_prs2_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_prs3 = io_req_0_bits_uop_prs3_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_ppred = io_req_0_bits_uop_ppred_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs1_busy = io_req_0_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs2_busy = io_req_0_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_prs3_busy = io_req_0_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_ppred_busy = io_req_0_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7, :536:25] wire [6:0] req_bits_uop_stale_pdst = io_req_0_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_exception = io_req_0_bits_uop_exception_0; // @[mshrs.scala:498:7, :536:25] wire [63:0] req_bits_uop_exc_cause = io_req_0_bits_uop_exc_cause_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_mem_cmd = io_req_0_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_mem_size = io_req_0_bits_uop_mem_size_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_mem_signed = io_req_0_bits_uop_mem_signed_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_uses_ldq = io_req_0_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_uses_stq = io_req_0_bits_uop_uses_stq_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_is_unique = io_req_0_bits_uop_is_unique_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_flush_on_commit = io_req_0_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_csr_cmd = io_req_0_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_ldst_is_rs1 = io_req_0_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_ldst = io_req_0_bits_uop_ldst_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs1 = io_req_0_bits_uop_lrs1_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs2 = io_req_0_bits_uop_lrs2_0; // @[mshrs.scala:498:7, :536:25] wire [5:0] req_bits_uop_lrs3 = io_req_0_bits_uop_lrs3_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_dst_rtype = io_req_0_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_lrs1_rtype = io_req_0_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_lrs2_rtype = io_req_0_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_frs3_en = io_req_0_bits_uop_frs3_en_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fcn_dw = io_req_0_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7, :536:25] wire [4:0] req_bits_uop_fcn_op = io_req_0_bits_uop_fcn_op_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_fp_val = io_req_0_bits_uop_fp_val_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_fp_rm = io_req_0_bits_uop_fp_rm_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_uop_fp_typ = io_req_0_bits_uop_fp_typ_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_pf_if = io_req_0_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_ae_if = io_req_0_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_xcpt_ma_if = io_req_0_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_bp_debug_if = io_req_0_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_uop_bp_xcpt_if = io_req_0_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_debug_fsrc = io_req_0_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7, :536:25] wire [2:0] req_bits_uop_debug_tsrc = io_req_0_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7, :536:25] wire [39:0] req_bits_addr = io_req_0_bits_addr_0; // @[mshrs.scala:498:7, :536:25] wire [63:0] req_bits_data = io_req_0_bits_data_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_is_hella = io_req_0_bits_is_hella_0; // @[mshrs.scala:498:7, :536:25] wire req_bits_tag_match = io_req_0_bits_tag_match_0; // @[mshrs.scala:498:7, :536:25] wire [1:0] req_bits_old_meta_coh_state = io_req_0_bits_old_meta_coh_state_0; // @[mshrs.scala:498:7, :536:25] wire [19:0] req_bits_old_meta_tag = io_req_0_bits_old_meta_tag_0; // @[mshrs.scala:498:7, :536:25] wire [7:0] req_bits_way_en = io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :536:25] wire _io_secondary_miss_0_T_2; // @[mshrs.scala:729:58] wire _io_block_hit_0_T; // @[mshrs.scala:730:42] wire _io_mem_acquire_valid_T_13; // @[Arbiter.scala:96:24] wire [2:0] _io_mem_acquire_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_WIRE_size; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_WIRE_address; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_WIRE_mask; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_WIRE_data; // @[Mux.scala:30:73] wire _io_mem_finish_valid_T_10; // @[Arbiter.scala:96:24] wire [3:0] _io_mem_finish_bits_WIRE_sink; // @[Mux.scala:30:73] wire io_resp_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:498:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:498:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:498:7] wire [3:0] io_resp_bits_uop_br_type_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sfence_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_eret_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_rocc_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_mov_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_imm_rename_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_imm_sel_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_pimm_0; // @[mshrs.scala:498:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_op1_sel_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_op2_sel_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:498:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:498:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7] wire [4:0] io_resp_bits_uop_fcn_op_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_fp_rm_0; // @[mshrs.scala:498:7] wire [1:0] io_resp_bits_uop_fp_typ_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7] wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:498:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:498:7] wire io_resp_valid_0; // @[mshrs.scala:498:7] wire io_secondary_miss_0_0; // @[mshrs.scala:498:7] wire io_block_hit_0_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_acquire_bits_opcode_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:498:7] wire [3:0] io_mem_acquire_bits_size_0; // @[mshrs.scala:498:7] wire [2:0] io_mem_acquire_bits_source_0; // @[mshrs.scala:498:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:498:7] wire [15:0] io_mem_acquire_bits_mask_0; // @[mshrs.scala:498:7] wire [127:0] io_mem_acquire_bits_data_0; // @[mshrs.scala:498:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:498:7] wire io_mem_grant_ready_0; // @[mshrs.scala:498:7] wire [3:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:498:7] wire io_mem_finish_valid_0; // @[mshrs.scala:498:7] wire [7:0] io_refill_bits_way_en_0; // @[mshrs.scala:498:7] wire [11:0] io_refill_bits_addr_0; // @[mshrs.scala:498:7] wire [127:0] io_refill_bits_data_0; // @[mshrs.scala:498:7] wire io_refill_valid_0; // @[mshrs.scala:498:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:498:7] wire [5:0] io_meta_write_bits_idx_0; // @[mshrs.scala:498:7] wire [7:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_write_bits_tag_0; // @[mshrs.scala:498:7] wire io_meta_write_valid_0; // @[mshrs.scala:498:7] wire [5:0] io_meta_read_bits_idx_0; // @[mshrs.scala:498:7] wire [7:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:498:7] wire [19:0] io_meta_read_bits_tag_0; // @[mshrs.scala:498:7] wire io_meta_read_valid_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_0_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iq_type_3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_0_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_4_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_5_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_6_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_7_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_8_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fu_code_9_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ldst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_wen_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren1_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren2_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_ren3_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_swap12_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_swap23_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagIn_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_ctrl_typeTagOut_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fromint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_toint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fastpipe_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_fma_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_div_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_sqrt_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_wflags_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_ctrl_vec_0; // @[mshrs.scala:498:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:498:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:498:7] wire [39:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_partial_agen_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_issued_partial_dgen_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_iw_p1_speculative_child_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_iw_p2_speculative_child_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p1_bypass_hint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p2_bypass_hint_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_iw_p3_bypass_hint_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_dis_col_sel_0; // @[mshrs.scala:498:7] wire [15:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:498:7] wire [3:0] io_replay_bits_uop_br_type_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sfence_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_eret_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_rocc_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_mov_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_imm_rename_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_imm_sel_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_pimm_0; // @[mshrs.scala:498:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_op1_sel_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_op2_sel_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:498:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:498:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_csr_cmd_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:498:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fcn_dw_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_uop_fcn_op_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_fp_rm_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_uop_fp_typ_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:498:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:498:7] wire [2:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:498:7] wire [1:0] io_replay_bits_old_meta_coh_state; // @[mshrs.scala:498:7] wire [19:0] io_replay_bits_old_meta_tag; // @[mshrs.scala:498:7] wire [39:0] io_replay_bits_addr_0; // @[mshrs.scala:498:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:498:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:498:7] wire io_replay_bits_tag_match; // @[mshrs.scala:498:7] wire [7:0] io_replay_bits_way_en_0; // @[mshrs.scala:498:7] wire [4:0] io_replay_bits_sdq_id; // @[mshrs.scala:498:7] wire io_replay_valid_0; // @[mshrs.scala:498:7] wire [19:0] io_wb_req_bits_tag_0; // @[mshrs.scala:498:7] wire [5:0] io_wb_req_bits_idx_0; // @[mshrs.scala:498:7] wire [2:0] io_wb_req_bits_source_0; // @[mshrs.scala:498:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:498:7] wire [7:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:498:7] wire io_wb_req_valid_0; // @[mshrs.scala:498:7] wire io_fence_rdy_0; // @[mshrs.scala:498:7] wire io_probe_rdy_0; // @[mshrs.scala:498:7] wire [39:0] _cacheable_T_1 = req_bits_addr; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_2 = {1'h0, _cacheable_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_3 = _cacheable_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_4 = _cacheable_T_3; // @[Parameters.scala:137:46] wire _cacheable_T_5 = _cacheable_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_6 = {req_bits_addr[39:17], req_bits_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_7 = {1'h0, _cacheable_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_8 = _cacheable_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_9 = _cacheable_T_8; // @[Parameters.scala:137:46] wire _cacheable_T_10 = _cacheable_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_11 = {req_bits_addr[39:28], req_bits_addr[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_12 = {1'h0, _cacheable_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_13 = _cacheable_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_14 = _cacheable_T_13; // @[Parameters.scala:137:46] wire _cacheable_T_15 = _cacheable_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_16 = _cacheable_T_5 | _cacheable_T_10; // @[Parameters.scala:685:42] wire _cacheable_T_17 = _cacheable_T_16 | _cacheable_T_15; // @[Parameters.scala:685:42] wire [39:0] _cacheable_T_21 = {req_bits_addr[39:28], req_bits_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_22 = {1'h0, _cacheable_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_23 = _cacheable_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_24 = _cacheable_T_23; // @[Parameters.scala:137:46] wire _cacheable_T_25 = _cacheable_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _cacheable_T_26 = {req_bits_addr[39:32], req_bits_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31] wire [40:0] _cacheable_T_27 = {1'h0, _cacheable_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _cacheable_T_28 = _cacheable_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _cacheable_T_29 = _cacheable_T_28; // @[Parameters.scala:137:46] wire _cacheable_T_30 = _cacheable_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _cacheable_T_31 = _cacheable_T_25 | _cacheable_T_30; // @[Parameters.scala:685:42] wire _cacheable_T_32 = _cacheable_T_31; // @[Parameters.scala:684:54, :685:42] wire cacheable = _cacheable_T_32; // @[Parameters.scala:684:54, :686:26] reg [16:0] sdq_val; // @[mshrs.scala:552:29] wire [16:0] _sdq_alloc_id_T = sdq_val; // @[mshrs.scala:552:29, :553:46] wire [16:0] _sdq_val_T_5 = sdq_val; // @[mshrs.scala:552:29, :741:33] wire [16:0] _sdq_alloc_id_T_1 = ~_sdq_alloc_id_T; // @[mshrs.scala:553:{38,46}] wire _sdq_alloc_id_T_2 = _sdq_alloc_id_T_1[0]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_3 = _sdq_alloc_id_T_1[1]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_4 = _sdq_alloc_id_T_1[2]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_5 = _sdq_alloc_id_T_1[3]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_6 = _sdq_alloc_id_T_1[4]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_7 = _sdq_alloc_id_T_1[5]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_8 = _sdq_alloc_id_T_1[6]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_9 = _sdq_alloc_id_T_1[7]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_10 = _sdq_alloc_id_T_1[8]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_11 = _sdq_alloc_id_T_1[9]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_12 = _sdq_alloc_id_T_1[10]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_13 = _sdq_alloc_id_T_1[11]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_14 = _sdq_alloc_id_T_1[12]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_15 = _sdq_alloc_id_T_1[13]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_16 = _sdq_alloc_id_T_1[14]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_17 = _sdq_alloc_id_T_1[15]; // @[OneHot.scala:48:45] wire _sdq_alloc_id_T_18 = _sdq_alloc_id_T_1[16]; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_19 = _sdq_alloc_id_T_17 ? 5'hF : 5'h10; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_20 = _sdq_alloc_id_T_16 ? 5'hE : _sdq_alloc_id_T_19; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_21 = _sdq_alloc_id_T_15 ? 5'hD : _sdq_alloc_id_T_20; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_22 = _sdq_alloc_id_T_14 ? 5'hC : _sdq_alloc_id_T_21; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_23 = _sdq_alloc_id_T_13 ? 5'hB : _sdq_alloc_id_T_22; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_24 = _sdq_alloc_id_T_12 ? 5'hA : _sdq_alloc_id_T_23; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_25 = _sdq_alloc_id_T_11 ? 5'h9 : _sdq_alloc_id_T_24; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_26 = _sdq_alloc_id_T_10 ? 5'h8 : _sdq_alloc_id_T_25; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_27 = _sdq_alloc_id_T_9 ? 5'h7 : _sdq_alloc_id_T_26; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_28 = _sdq_alloc_id_T_8 ? 5'h6 : _sdq_alloc_id_T_27; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_29 = _sdq_alloc_id_T_7 ? 5'h5 : _sdq_alloc_id_T_28; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_30 = _sdq_alloc_id_T_6 ? 5'h4 : _sdq_alloc_id_T_29; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_31 = _sdq_alloc_id_T_5 ? 5'h3 : _sdq_alloc_id_T_30; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_32 = _sdq_alloc_id_T_4 ? 5'h2 : _sdq_alloc_id_T_31; // @[OneHot.scala:48:45] wire [4:0] _sdq_alloc_id_T_33 = _sdq_alloc_id_T_3 ? 5'h1 : _sdq_alloc_id_T_32; // @[OneHot.scala:48:45] wire [4:0] sdq_alloc_id = _sdq_alloc_id_T_2 ? 5'h0 : _sdq_alloc_id_T_33; // @[OneHot.scala:48:45] wire _sdq_rdy_T = &sdq_val; // @[mshrs.scala:552:29, :554:31] wire sdq_rdy = ~_sdq_rdy_T; // @[mshrs.scala:554:{22,31}] wire _sdq_enq_T = req_ready & req_valid; // @[Decoupled.scala:51:35] wire _sdq_enq_T_1 = _sdq_enq_T & cacheable; // @[Decoupled.scala:51:35] wire _sdq_enq_T_2 = req_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _sdq_enq_T_3 = req_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _sdq_enq_T_4 = _sdq_enq_T_2 | _sdq_enq_T_3; // @[Consts.scala:90:{32,42,49}] wire _sdq_enq_T_5 = req_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _sdq_enq_T_6 = _sdq_enq_T_4 | _sdq_enq_T_5; // @[Consts.scala:90:{42,59,66}] wire _sdq_enq_T_7 = req_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _sdq_enq_T_8 = req_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _sdq_enq_T_9 = req_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _sdq_enq_T_10 = req_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _sdq_enq_T_11 = _sdq_enq_T_7 | _sdq_enq_T_8; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_12 = _sdq_enq_T_11 | _sdq_enq_T_9; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_13 = _sdq_enq_T_12 | _sdq_enq_T_10; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_14 = req_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _sdq_enq_T_15 = req_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _sdq_enq_T_16 = req_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _sdq_enq_T_17 = req_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _sdq_enq_T_18 = req_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _sdq_enq_T_19 = _sdq_enq_T_14 | _sdq_enq_T_15; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_20 = _sdq_enq_T_19 | _sdq_enq_T_16; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_21 = _sdq_enq_T_20 | _sdq_enq_T_17; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_22 = _sdq_enq_T_21 | _sdq_enq_T_18; // @[package.scala:16:47, :81:59] wire _sdq_enq_T_23 = _sdq_enq_T_13 | _sdq_enq_T_22; // @[package.scala:81:59] wire _sdq_enq_T_24 = _sdq_enq_T_6 | _sdq_enq_T_23; // @[Consts.scala:87:44, :90:{59,76}] wire sdq_enq = _sdq_enq_T_1 & _sdq_enq_T_24; // @[Consts.scala:90:76] reg [127:0] lb_0_0; // @[mshrs.scala:565:15] reg [127:0] lb_0_1; // @[mshrs.scala:565:15] reg [127:0] lb_0_2; // @[mshrs.scala:565:15] reg [127:0] lb_0_3; // @[mshrs.scala:565:15] reg [127:0] lb_1_0; // @[mshrs.scala:565:15] reg [127:0] lb_1_1; // @[mshrs.scala:565:15] reg [127:0] lb_1_2; // @[mshrs.scala:565:15] reg [127:0] lb_1_3; // @[mshrs.scala:565:15] reg [127:0] lb_2_0; // @[mshrs.scala:565:15] reg [127:0] lb_2_1; // @[mshrs.scala:565:15] reg [127:0] lb_2_2; // @[mshrs.scala:565:15] reg [127:0] lb_2_3; // @[mshrs.scala:565:15] reg [127:0] lb_3_0; // @[mshrs.scala:565:15] reg [127:0] lb_3_1; // @[mshrs.scala:565:15] reg [127:0] lb_3_2; // @[mshrs.scala:565:15] reg [127:0] lb_3_3; // @[mshrs.scala:565:15] wire _idx_matches_0_0_T_2; // @[mshrs.scala:606:46] wire _idx_matches_0_1_T_2; // @[mshrs.scala:606:46] wire _idx_matches_0_2_T_2; // @[mshrs.scala:606:46] wire _idx_matches_0_3_T_2; // @[mshrs.scala:606:46] wire idx_matches_0_0; // @[mshrs.scala:571:25] wire idx_matches_0_1; // @[mshrs.scala:571:25] wire idx_matches_0_2; // @[mshrs.scala:571:25] wire idx_matches_0_3; // @[mshrs.scala:571:25] wire _tag_matches_0_0_T_2; // @[mshrs.scala:607:46] wire _tag_matches_0_1_T_2; // @[mshrs.scala:607:46] wire _tag_matches_0_2_T_2; // @[mshrs.scala:607:46] wire _tag_matches_0_3_T_2; // @[mshrs.scala:607:46] wire tag_matches_0_0; // @[mshrs.scala:572:25] wire tag_matches_0_1; // @[mshrs.scala:572:25] wire tag_matches_0_2; // @[mshrs.scala:572:25] wire tag_matches_0_3; // @[mshrs.scala:572:25] wire _way_matches_0_0_T_1; // @[mshrs.scala:608:46] wire _way_matches_0_1_T_1; // @[mshrs.scala:608:46] wire _way_matches_0_2_T_1; // @[mshrs.scala:608:46] wire _way_matches_0_3_T_1; // @[mshrs.scala:608:46] wire way_matches_0_0; // @[mshrs.scala:573:25] wire way_matches_0_1; // @[mshrs.scala:573:25] wire way_matches_0_2; // @[mshrs.scala:573:25] wire way_matches_0_3; // @[mshrs.scala:573:25] wire _tag_match_T = idx_matches_0_0 & tag_matches_0_0; // @[Mux.scala:30:73] wire _tag_match_T_1 = idx_matches_0_1 & tag_matches_0_1; // @[Mux.scala:30:73] wire _tag_match_T_2 = idx_matches_0_2 & tag_matches_0_2; // @[Mux.scala:30:73] wire _tag_match_T_3 = idx_matches_0_3 & tag_matches_0_3; // @[Mux.scala:30:73] wire _tag_match_T_4 = _tag_match_T | _tag_match_T_1; // @[Mux.scala:30:73] wire _tag_match_T_5 = _tag_match_T_4 | _tag_match_T_2; // @[Mux.scala:30:73] wire _tag_match_T_6 = _tag_match_T_5 | _tag_match_T_3; // @[Mux.scala:30:73] wire _tag_match_WIRE = _tag_match_T_6; // @[Mux.scala:30:73] wire tag_match_0 = _tag_match_WIRE; // @[Mux.scala:30:73] wire _idx_match_T = idx_matches_0_0 | idx_matches_0_1; // @[mshrs.scala:571:25, :576:58] wire _idx_match_T_1 = _idx_match_T | idx_matches_0_2; // @[mshrs.scala:571:25, :576:58] wire _idx_match_T_2 = _idx_match_T_1 | idx_matches_0_3; // @[mshrs.scala:571:25, :576:58] wire idx_match_0 = _idx_match_T_2; // @[mshrs.scala:566:49, :576:58] wire _way_match_T = idx_matches_0_0 & way_matches_0_0; // @[Mux.scala:30:73] wire _way_match_T_1 = idx_matches_0_1 & way_matches_0_1; // @[Mux.scala:30:73] wire _way_match_T_2 = idx_matches_0_2 & way_matches_0_2; // @[Mux.scala:30:73] wire _way_match_T_3 = idx_matches_0_3 & way_matches_0_3; // @[Mux.scala:30:73] wire _way_match_T_4 = _way_match_T | _way_match_T_1; // @[Mux.scala:30:73] wire _way_match_T_5 = _way_match_T_4 | _way_match_T_2; // @[Mux.scala:30:73] wire _way_match_T_6 = _way_match_T_5 | _way_match_T_3; // @[Mux.scala:30:73] wire _way_match_WIRE = _way_match_T_6; // @[Mux.scala:30:73] wire way_match_0 = _way_match_WIRE; // @[Mux.scala:30:73] wire [19:0] wb_tag_list_0; // @[mshrs.scala:579:25] wire [19:0] wb_tag_list_1; // @[mshrs.scala:579:25] wire [19:0] wb_tag_list_2; // @[mshrs.scala:579:25] wire [19:0] wb_tag_list_3; // @[mshrs.scala:579:25] wire commit_vals_0; // @[mshrs.scala:588:28] wire commit_vals_1; // @[mshrs.scala:588:28] wire commit_vals_2; // @[mshrs.scala:588:28] wire commit_vals_3; // @[mshrs.scala:588:28] wire [39:0] commit_addrs_0; // @[mshrs.scala:589:28] wire [39:0] commit_addrs_1; // @[mshrs.scala:589:28] wire [39:0] commit_addrs_2; // @[mshrs.scala:589:28] wire [39:0] commit_addrs_3; // @[mshrs.scala:589:28] wire [1:0] commit_cohs_0_state; // @[mshrs.scala:590:28] wire [1:0] commit_cohs_1_state; // @[mshrs.scala:590:28] wire [1:0] commit_cohs_2_state; // @[mshrs.scala:590:28] wire [1:0] commit_cohs_3_state; // @[mshrs.scala:590:28] wire [1:0] mshr_alloc_idx; // @[mshrs.scala:598:28] wire pri_rdy; // @[mshrs.scala:599:25] wire _GEN = req_valid & sdq_rdy; // @[mshrs.scala:536:25, :554:22, :600:27] wire _pri_val_T; // @[mshrs.scala:600:27] assign _pri_val_T = _GEN; // @[mshrs.scala:600:27] wire _mshr_io_req_sec_val_T; // @[mshrs.scala:619:39] assign _mshr_io_req_sec_val_T = _GEN; // @[mshrs.scala:600:27, :619:39] wire _mshr_io_req_sec_val_T_4; // @[mshrs.scala:619:39] assign _mshr_io_req_sec_val_T_4 = _GEN; // @[mshrs.scala:600:27, :619:39] wire _mshr_io_req_sec_val_T_8; // @[mshrs.scala:619:39] assign _mshr_io_req_sec_val_T_8 = _GEN; // @[mshrs.scala:600:27, :619:39] wire _mshr_io_req_sec_val_T_12; // @[mshrs.scala:619:39] assign _mshr_io_req_sec_val_T_12 = _GEN; // @[mshrs.scala:600:27, :619:39] wire _pri_val_T_1 = _pri_val_T & cacheable; // @[Parameters.scala:686:26] wire _pri_val_T_2 = ~idx_match_0; // @[mshrs.scala:566:49, :600:54] wire pri_val = _pri_val_T_1 & _pri_val_T_2; // @[mshrs.scala:600:{38,51,54}] wire [5:0] _idx_matches_0_0_T = io_req_0_bits_addr_0[11:6]; // @[mshrs.scala:498:7, :606:89] wire [5:0] _idx_matches_0_1_T = io_req_0_bits_addr_0[11:6]; // @[mshrs.scala:498:7, :606:89] wire [5:0] _idx_matches_0_2_T = io_req_0_bits_addr_0[11:6]; // @[mshrs.scala:498:7, :606:89] wire [5:0] _idx_matches_0_3_T = io_req_0_bits_addr_0[11:6]; // @[mshrs.scala:498:7, :606:89] wire _idx_matches_0_0_T_1 = _mshrs_0_io_idx_bits == _idx_matches_0_0_T; // @[mshrs.scala:602:22, :606:{66,89}] assign _idx_matches_0_0_T_2 = _mshrs_0_io_idx_valid & _idx_matches_0_0_T_1; // @[mshrs.scala:602:22, :606:{46,66}] assign idx_matches_0_0 = _idx_matches_0_0_T_2; // @[mshrs.scala:571:25, :606:46] wire [27:0] _tag_matches_0_0_T = io_req_0_bits_addr_0[39:12]; // @[mshrs.scala:498:7, :607:90] wire [27:0] _tag_matches_0_1_T = io_req_0_bits_addr_0[39:12]; // @[mshrs.scala:498:7, :607:90] wire [27:0] _tag_matches_0_2_T = io_req_0_bits_addr_0[39:12]; // @[mshrs.scala:498:7, :607:90] wire [27:0] _tag_matches_0_3_T = io_req_0_bits_addr_0[39:12]; // @[mshrs.scala:498:7, :607:90] wire _tag_matches_0_0_T_1 = _mshrs_0_io_tag_bits == _tag_matches_0_0_T; // @[mshrs.scala:602:22, :607:{66,90}] assign _tag_matches_0_0_T_2 = _mshrs_0_io_tag_valid & _tag_matches_0_0_T_1; // @[mshrs.scala:602:22, :607:{46,66}] assign tag_matches_0_0 = _tag_matches_0_0_T_2; // @[mshrs.scala:572:25, :607:46] wire _way_matches_0_0_T = _mshrs_0_io_way_bits == io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :602:22, :608:66] assign _way_matches_0_0_T_1 = _mshrs_0_io_way_valid & _way_matches_0_0_T; // @[mshrs.scala:602:22, :608:{46,66}] assign way_matches_0_0 = _way_matches_0_0_T_1; // @[mshrs.scala:573:25, :608:46] wire _mshr_io_req_pri_val_T = mshr_alloc_idx == 2'h0; // @[mshrs.scala:598:28, :614:34] wire _mshr_io_req_pri_val_T_1 = _mshr_io_req_pri_val_T & pri_val; // @[mshrs.scala:600:51, :614:{34,54}] wire _mshr_io_req_sec_val_T_1 = _mshr_io_req_sec_val_T & tag_match_0; // @[mshrs.scala:566:49, :619:{39,50}] wire _mshr_io_req_sec_val_T_2 = _mshr_io_req_sec_val_T_1 & idx_matches_0_0; // @[mshrs.scala:571:25, :619:{50,72}] wire _mshr_io_req_sec_val_T_3 = _mshr_io_req_sec_val_T_2 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T = ~req_valid; // @[mshrs.scala:536:25, :626:49] wire _mshr_io_clear_prefetch_T_1 = io_clear_all_0 & _mshr_io_clear_prefetch_T; // @[mshrs.scala:498:7, :626:{46,49}] wire _mshr_io_clear_prefetch_T_2 = req_valid & idx_matches_0_0; // @[mshrs.scala:536:25, :571:25, :627:18] wire _mshr_io_clear_prefetch_T_3 = _mshr_io_clear_prefetch_T_2 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_4 = ~tag_match_0; // @[mshrs.scala:566:49, :627:61] wire _mshr_io_clear_prefetch_T_5 = _mshr_io_clear_prefetch_T_3 & _mshr_io_clear_prefetch_T_4; // @[mshrs.scala:627:{45,58,61}] wire _mshr_io_clear_prefetch_T_6 = _mshr_io_clear_prefetch_T_1 | _mshr_io_clear_prefetch_T_5; // @[mshrs.scala:626:{46,60}, :627:58] wire _mshr_io_clear_prefetch_T_7 = io_req_is_probe_0_0 & idx_matches_0_0; // @[mshrs.scala:498:7, :571:25, :628:21] wire _mshr_io_clear_prefetch_T_8 = _mshr_io_clear_prefetch_T_6 | _mshr_io_clear_prefetch_T_7; // @[mshrs.scala:626:60, :627:82, :628:21] wire [3:0][127:0] _GEN_0 = {{lb_0_3}, {lb_0_2}, {lb_0_1}, {lb_0_0}}; // @[mshrs.scala:565:15, :645:32] wire _T_1 = io_mem_grant_bits_source_0 == 3'h0; // @[mshrs.scala:498:7, :656:36] wire _idx_matches_0_1_T_1 = _mshrs_1_io_idx_bits == _idx_matches_0_1_T; // @[mshrs.scala:602:22, :606:{66,89}] assign _idx_matches_0_1_T_2 = _mshrs_1_io_idx_valid & _idx_matches_0_1_T_1; // @[mshrs.scala:602:22, :606:{46,66}] assign idx_matches_0_1 = _idx_matches_0_1_T_2; // @[mshrs.scala:571:25, :606:46] wire _tag_matches_0_1_T_1 = _mshrs_1_io_tag_bits == _tag_matches_0_1_T; // @[mshrs.scala:602:22, :607:{66,90}] assign _tag_matches_0_1_T_2 = _mshrs_1_io_tag_valid & _tag_matches_0_1_T_1; // @[mshrs.scala:602:22, :607:{46,66}] assign tag_matches_0_1 = _tag_matches_0_1_T_2; // @[mshrs.scala:572:25, :607:46] wire _way_matches_0_1_T = _mshrs_1_io_way_bits == io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :602:22, :608:66] assign _way_matches_0_1_T_1 = _mshrs_1_io_way_valid & _way_matches_0_1_T; // @[mshrs.scala:602:22, :608:{46,66}] assign way_matches_0_1 = _way_matches_0_1_T_1; // @[mshrs.scala:573:25, :608:46] wire _mshr_io_req_pri_val_T_2 = mshr_alloc_idx == 2'h1; // @[mshrs.scala:598:28, :614:34] wire _mshr_io_req_pri_val_T_3 = _mshr_io_req_pri_val_T_2 & pri_val; // @[mshrs.scala:600:51, :614:{34,54}] wire _mshr_io_req_sec_val_T_5 = _mshr_io_req_sec_val_T_4 & tag_match_0; // @[mshrs.scala:566:49, :619:{39,50}] wire _mshr_io_req_sec_val_T_6 = _mshr_io_req_sec_val_T_5 & idx_matches_0_1; // @[mshrs.scala:571:25, :619:{50,72}] wire _mshr_io_req_sec_val_T_7 = _mshr_io_req_sec_val_T_6 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_9 = ~req_valid; // @[mshrs.scala:536:25, :626:49] wire _mshr_io_clear_prefetch_T_10 = io_clear_all_0 & _mshr_io_clear_prefetch_T_9; // @[mshrs.scala:498:7, :626:{46,49}] wire _mshr_io_clear_prefetch_T_11 = req_valid & idx_matches_0_1; // @[mshrs.scala:536:25, :571:25, :627:18] wire _mshr_io_clear_prefetch_T_12 = _mshr_io_clear_prefetch_T_11 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_13 = ~tag_match_0; // @[mshrs.scala:566:49, :627:61] wire _mshr_io_clear_prefetch_T_14 = _mshr_io_clear_prefetch_T_12 & _mshr_io_clear_prefetch_T_13; // @[mshrs.scala:627:{45,58,61}] wire _mshr_io_clear_prefetch_T_15 = _mshr_io_clear_prefetch_T_10 | _mshr_io_clear_prefetch_T_14; // @[mshrs.scala:626:{46,60}, :627:58] wire _mshr_io_clear_prefetch_T_16 = io_req_is_probe_0_0 & idx_matches_0_1; // @[mshrs.scala:498:7, :571:25, :628:21] wire _mshr_io_clear_prefetch_T_17 = _mshr_io_clear_prefetch_T_15 | _mshr_io_clear_prefetch_T_16; // @[mshrs.scala:626:60, :627:82, :628:21] wire [3:0][127:0] _GEN_1 = {{lb_1_3}, {lb_1_2}, {lb_1_1}, {lb_1_0}}; // @[mshrs.scala:565:15, :645:32] wire _T_9 = io_mem_grant_bits_source_0 == 3'h1; // @[mshrs.scala:498:7, :656:36] wire _idx_matches_0_2_T_1 = _mshrs_2_io_idx_bits == _idx_matches_0_2_T; // @[mshrs.scala:602:22, :606:{66,89}] assign _idx_matches_0_2_T_2 = _mshrs_2_io_idx_valid & _idx_matches_0_2_T_1; // @[mshrs.scala:602:22, :606:{46,66}] assign idx_matches_0_2 = _idx_matches_0_2_T_2; // @[mshrs.scala:571:25, :606:46] wire _tag_matches_0_2_T_1 = _mshrs_2_io_tag_bits == _tag_matches_0_2_T; // @[mshrs.scala:602:22, :607:{66,90}] assign _tag_matches_0_2_T_2 = _mshrs_2_io_tag_valid & _tag_matches_0_2_T_1; // @[mshrs.scala:602:22, :607:{46,66}] assign tag_matches_0_2 = _tag_matches_0_2_T_2; // @[mshrs.scala:572:25, :607:46] wire _way_matches_0_2_T = _mshrs_2_io_way_bits == io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :602:22, :608:66] assign _way_matches_0_2_T_1 = _mshrs_2_io_way_valid & _way_matches_0_2_T; // @[mshrs.scala:602:22, :608:{46,66}] assign way_matches_0_2 = _way_matches_0_2_T_1; // @[mshrs.scala:573:25, :608:46] wire _mshr_io_req_pri_val_T_4 = mshr_alloc_idx == 2'h2; // @[mshrs.scala:598:28, :614:34] wire _mshr_io_req_pri_val_T_5 = _mshr_io_req_pri_val_T_4 & pri_val; // @[mshrs.scala:600:51, :614:{34,54}] wire _mshr_io_req_sec_val_T_9 = _mshr_io_req_sec_val_T_8 & tag_match_0; // @[mshrs.scala:566:49, :619:{39,50}] wire _mshr_io_req_sec_val_T_10 = _mshr_io_req_sec_val_T_9 & idx_matches_0_2; // @[mshrs.scala:571:25, :619:{50,72}] wire _mshr_io_req_sec_val_T_11 = _mshr_io_req_sec_val_T_10 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_18 = ~req_valid; // @[mshrs.scala:536:25, :626:49] wire _mshr_io_clear_prefetch_T_19 = io_clear_all_0 & _mshr_io_clear_prefetch_T_18; // @[mshrs.scala:498:7, :626:{46,49}] wire _mshr_io_clear_prefetch_T_20 = req_valid & idx_matches_0_2; // @[mshrs.scala:536:25, :571:25, :627:18] wire _mshr_io_clear_prefetch_T_21 = _mshr_io_clear_prefetch_T_20 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_22 = ~tag_match_0; // @[mshrs.scala:566:49, :627:61] wire _mshr_io_clear_prefetch_T_23 = _mshr_io_clear_prefetch_T_21 & _mshr_io_clear_prefetch_T_22; // @[mshrs.scala:627:{45,58,61}] wire _mshr_io_clear_prefetch_T_24 = _mshr_io_clear_prefetch_T_19 | _mshr_io_clear_prefetch_T_23; // @[mshrs.scala:626:{46,60}, :627:58] wire _mshr_io_clear_prefetch_T_25 = io_req_is_probe_0_0 & idx_matches_0_2; // @[mshrs.scala:498:7, :571:25, :628:21] wire _mshr_io_clear_prefetch_T_26 = _mshr_io_clear_prefetch_T_24 | _mshr_io_clear_prefetch_T_25; // @[mshrs.scala:626:60, :627:82, :628:21] wire [3:0][127:0] _GEN_2 = {{lb_2_3}, {lb_2_2}, {lb_2_1}, {lb_2_0}}; // @[mshrs.scala:565:15, :645:32] wire _T_17 = io_mem_grant_bits_source_0 == 3'h2; // @[mshrs.scala:498:7, :656:36] wire _idx_matches_0_3_T_1 = _mshrs_3_io_idx_bits == _idx_matches_0_3_T; // @[mshrs.scala:602:22, :606:{66,89}] assign _idx_matches_0_3_T_2 = _mshrs_3_io_idx_valid & _idx_matches_0_3_T_1; // @[mshrs.scala:602:22, :606:{46,66}] assign idx_matches_0_3 = _idx_matches_0_3_T_2; // @[mshrs.scala:571:25, :606:46] wire _tag_matches_0_3_T_1 = _mshrs_3_io_tag_bits == _tag_matches_0_3_T; // @[mshrs.scala:602:22, :607:{66,90}] assign _tag_matches_0_3_T_2 = _mshrs_3_io_tag_valid & _tag_matches_0_3_T_1; // @[mshrs.scala:602:22, :607:{46,66}] assign tag_matches_0_3 = _tag_matches_0_3_T_2; // @[mshrs.scala:572:25, :607:46] wire _way_matches_0_3_T = _mshrs_3_io_way_bits == io_req_0_bits_way_en_0; // @[mshrs.scala:498:7, :602:22, :608:66] assign _way_matches_0_3_T_1 = _mshrs_3_io_way_valid & _way_matches_0_3_T; // @[mshrs.scala:602:22, :608:{46,66}] assign way_matches_0_3 = _way_matches_0_3_T_1; // @[mshrs.scala:573:25, :608:46] wire _mshr_io_req_pri_val_T_6 = &mshr_alloc_idx; // @[mshrs.scala:598:28, :614:34] wire _mshr_io_req_pri_val_T_7 = _mshr_io_req_pri_val_T_6 & pri_val; // @[mshrs.scala:600:51, :614:{34,54}] wire [3:0] _GEN_3 = {{_mshrs_3_io_req_pri_rdy}, {_mshrs_2_io_req_pri_rdy}, {_mshrs_1_io_req_pri_rdy}, {_mshr_io_req_pri_val_T & _mshrs_0_io_req_pri_rdy}}; // @[mshrs.scala:599:25, :602:22, :614:34, :615:35, :616:15] assign pri_rdy = _GEN_3[mshr_alloc_idx]; // @[mshrs.scala:598:28, :599:25, :614:34, :615:35, :616:15] wire _mshr_io_req_sec_val_T_13 = _mshr_io_req_sec_val_T_12 & tag_match_0; // @[mshrs.scala:566:49, :619:{39,50}] wire _mshr_io_req_sec_val_T_14 = _mshr_io_req_sec_val_T_13 & idx_matches_0_3; // @[mshrs.scala:571:25, :619:{50,72}] wire _mshr_io_req_sec_val_T_15 = _mshr_io_req_sec_val_T_14 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_27 = ~req_valid; // @[mshrs.scala:536:25, :626:49] wire _mshr_io_clear_prefetch_T_28 = io_clear_all_0 & _mshr_io_clear_prefetch_T_27; // @[mshrs.scala:498:7, :626:{46,49}] wire _mshr_io_clear_prefetch_T_29 = req_valid & idx_matches_0_3; // @[mshrs.scala:536:25, :571:25, :627:18] wire _mshr_io_clear_prefetch_T_30 = _mshr_io_clear_prefetch_T_29 & cacheable; // @[Parameters.scala:686:26] wire _mshr_io_clear_prefetch_T_31 = ~tag_match_0; // @[mshrs.scala:566:49, :627:61] wire _mshr_io_clear_prefetch_T_32 = _mshr_io_clear_prefetch_T_30 & _mshr_io_clear_prefetch_T_31; // @[mshrs.scala:627:{45,58,61}] wire _mshr_io_clear_prefetch_T_33 = _mshr_io_clear_prefetch_T_28 | _mshr_io_clear_prefetch_T_32; // @[mshrs.scala:626:{46,60}, :627:58] wire _mshr_io_clear_prefetch_T_34 = io_req_is_probe_0_0 & idx_matches_0_3; // @[mshrs.scala:498:7, :571:25, :628:21] wire _mshr_io_clear_prefetch_T_35 = _mshr_io_clear_prefetch_T_33 | _mshr_io_clear_prefetch_T_34; // @[mshrs.scala:626:60, :627:82, :628:21] wire [3:0][127:0] _GEN_4 = {{lb_3_3}, {lb_3_2}, {lb_3_1}, {lb_3_0}}; // @[mshrs.scala:565:15, :645:32] wire _T_25 = io_mem_grant_bits_source_0 == 3'h3; // @[mshrs.scala:498:7, :656:36] assign io_probe_rdy_0 = ~(~_mshrs_3_io_probe_rdy & idx_matches_0_3 & io_req_is_probe_0_0 | ~_mshrs_2_io_probe_rdy & idx_matches_0_2 & io_req_is_probe_0_0 | ~_mshrs_1_io_probe_rdy & idx_matches_0_1 & io_req_is_probe_0_0 | ~_mshrs_0_io_probe_rdy & idx_matches_0_0 & io_req_is_probe_0_0); // @[mshrs.scala:498:7, :571:25, :595:16, :602:22, :667:{13,32,53,76}, :668:22] reg [1:0] mshr_head; // @[mshrs.scala:676:31] wire _mshr_alloc_idx_temp_vec_T = mshr_head == 2'h0; // @[util.scala:352:72] wire mshr_alloc_idx_temp_vec_0 = _mshrs_0_io_req_pri_rdy & _mshr_alloc_idx_temp_vec_T; // @[util.scala:352:{65,72}] wire _mshr_alloc_idx_temp_vec_T_1 = ~(mshr_head[1]); // @[util.scala:352:72] wire mshr_alloc_idx_temp_vec_1 = _mshrs_1_io_req_pri_rdy & _mshr_alloc_idx_temp_vec_T_1; // @[util.scala:352:{65,72}] wire _mshr_alloc_idx_temp_vec_T_2 = mshr_head != 2'h3; // @[util.scala:352:72] wire mshr_alloc_idx_temp_vec_2 = _mshrs_2_io_req_pri_rdy & _mshr_alloc_idx_temp_vec_T_2; // @[util.scala:352:{65,72}] wire mshr_alloc_idx_temp_vec_3; // @[util.scala:352:65] wire [2:0] _mshr_alloc_idx_idx_T = {2'h3, ~_mshrs_2_io_req_pri_rdy}; // @[Mux.scala:50:70] wire [2:0] _mshr_alloc_idx_idx_T_1 = _mshrs_1_io_req_pri_rdy ? 3'h5 : _mshr_alloc_idx_idx_T; // @[Mux.scala:50:70] wire [2:0] _mshr_alloc_idx_idx_T_2 = _mshrs_0_io_req_pri_rdy ? 3'h4 : _mshr_alloc_idx_idx_T_1; // @[Mux.scala:50:70] wire [2:0] _mshr_alloc_idx_idx_T_3 = mshr_alloc_idx_temp_vec_3 ? 3'h3 : _mshr_alloc_idx_idx_T_2; // @[Mux.scala:50:70] wire [2:0] _mshr_alloc_idx_idx_T_4 = mshr_alloc_idx_temp_vec_2 ? 3'h2 : _mshr_alloc_idx_idx_T_3; // @[Mux.scala:50:70] wire [2:0] _mshr_alloc_idx_idx_T_5 = mshr_alloc_idx_temp_vec_1 ? 3'h1 : _mshr_alloc_idx_idx_T_4; // @[Mux.scala:50:70] wire [2:0] mshr_alloc_idx_idx = mshr_alloc_idx_temp_vec_0 ? 3'h0 : _mshr_alloc_idx_idx_T_5; // @[Mux.scala:50:70] wire [1:0] _mshr_alloc_idx_T = mshr_alloc_idx_idx[1:0]; // @[Mux.scala:50:70] reg [1:0] mshr_alloc_idx_REG; // @[mshrs.scala:677:31] assign mshr_alloc_idx = mshr_alloc_idx_REG; // @[mshrs.scala:598:28, :677:31] wire [2:0] _mshr_head_T = {1'h0, mshr_head} + 3'h1; // @[util.scala:211:14] wire [1:0] _mshr_head_T_1 = _mshr_head_T[1:0]; // @[util.scala:211:14] wire [1:0] _mshr_head_T_2 = _mshr_head_T_1; // @[util.scala:211:{14,20}] wire _mshr_io_mem_ack_valid_T = io_mem_grant_bits_source_0 == 3'h5; // @[mshrs.scala:498:7, :703:77] wire _mshr_io_mem_ack_valid_T_1 = io_mem_grant_valid_0 & _mshr_io_mem_ack_valid_T; // @[mshrs.scala:498:7, :703:{49,77}] assign io_mem_grant_ready_0 = _mshr_io_mem_ack_valid_T | (_T_25 ? _mshrs_3_io_mem_grant_ready : _T_17 ? _mshrs_2_io_mem_grant_ready : _T_9 ? _mshrs_1_io_mem_grant_ready : _T_1 & _mshrs_0_io_mem_grant_ready); // @[mshrs.scala:498:7, :596:22, :602:22, :656:{36,45}, :657:25, :703:77, :704:46, :705:26] assign io_fence_rdy_0 = ~(~_mmios_0_io_req_ready | ~_mshrs_3_io_req_pri_rdy | ~_mshrs_2_io_req_pri_rdy | ~_mshrs_1_io_req_pri_rdy | ~_mshrs_0_io_req_pri_rdy); // @[mshrs.scala:498:7, :594:16, :602:22, :663:{11,33}, :664:20, :693:22, :709:{11,31}, :710:20] wire _mmio_alloc_arb_io_out_ready_T = ~cacheable; // @[Parameters.scala:686:26] wire _mmio_alloc_arb_io_out_ready_T_1 = req_valid & _mmio_alloc_arb_io_out_ready_T; // @[mshrs.scala:536:25, :715:{44,47}] wire [26:0] _decode_T_12 = 27'hFFF << _mmios_0_io_mem_access_bits_size; // @[package.scala:243:71] wire [11:0] _decode_T_13 = _decode_T_12[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _decode_T_14 = ~_decode_T_13; // @[package.scala:243:{46,76}] wire [7:0] decode_4 = _decode_T_14[11:4]; // @[package.scala:243:46] wire _opdata_T_4 = _mmios_0_io_mem_access_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata_4 = ~_opdata_T_4; // @[Edges.scala:92:{28,37}] reg [7:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & io_mem_acquire_ready_0; // @[Arbiter.scala:61:28, :62:24] wire [1:0] readys_lo = {_mshrs_1_io_mem_acquire_valid, _mshrs_0_io_mem_acquire_valid}; // @[Arbiter.scala:68:51] wire [1:0] readys_hi_hi = {_mmios_0_io_mem_access_valid, _mshrs_3_io_mem_acquire_valid}; // @[Arbiter.scala:68:51] wire [2:0] readys_hi = {readys_hi_hi, _mshrs_2_io_mem_acquire_valid}; // @[Arbiter.scala:68:51] wire [4:0] _readys_T = {readys_hi, readys_lo}; // @[Arbiter.scala:68:51] wire [5:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [4:0] _readys_T_2 = _readys_T_1[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}] wire [6:0] _readys_T_4 = {_readys_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_T_5 = _readys_T_4[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_T_6 = _readys_T_3 | _readys_T_5; // @[package.scala:253:{43,53}] wire [8:0] _readys_T_7 = {_readys_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [4:0] _readys_T_8 = _readys_T_7[4:0]; // @[package.scala:253:{48,53}] wire [4:0] _readys_T_9 = _readys_T_6 | _readys_T_8; // @[package.scala:253:{43,53}] wire [4:0] _readys_T_10 = _readys_T_9; // @[package.scala:253:43, :254:17] wire [5:0] _readys_T_11 = {_readys_T_10, 1'h0}; // @[package.scala:254:17] wire [4:0] _readys_T_12 = _readys_T_11[4:0]; // @[Arbiter.scala:16:{78,83}] wire [4:0] _readys_T_13 = ~_readys_T_12; // @[Arbiter.scala:16:{61,83}] wire _readys_T_14 = _readys_T_13[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_14; // @[Arbiter.scala:68:{27,76}] wire _readys_T_15 = _readys_T_13[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_15; // @[Arbiter.scala:68:{27,76}] wire _readys_T_16 = _readys_T_13[2]; // @[Arbiter.scala:16:61, :68:76] wire readys_2 = _readys_T_16; // @[Arbiter.scala:68:{27,76}] wire _readys_T_17 = _readys_T_13[3]; // @[Arbiter.scala:16:61, :68:76] wire readys_3 = _readys_T_17; // @[Arbiter.scala:68:{27,76}] wire _readys_T_18 = _readys_T_13[4]; // @[Arbiter.scala:16:61, :68:76] wire readys_4 = _readys_T_18; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & _mshrs_0_io_mem_acquire_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & _mshrs_1_io_mem_acquire_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire _winner_T_2 = readys_2 & _mshrs_2_io_mem_acquire_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}] wire _winner_T_3 = readys_3 & _mshrs_3_io_mem_acquire_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_3 = _winner_T_3; // @[Arbiter.scala:71:{27,69}] wire _winner_T_4 = readys_4 & _mmios_0_io_mem_access_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_4 = _winner_T_4; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3 = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_4 = prefixOR_3 | winner_3; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_4 | winner_4; // @[Arbiter.scala:71:27, :76:48] wire _io_mem_acquire_valid_T = _mshrs_0_io_mem_acquire_valid | _mshrs_1_io_mem_acquire_valid; // @[Arbiter.scala:79:31, :96:46] wire [7:0] maskedBeats_4 = winner_4 & opdata_4 ? decode_4 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [7:0] initBeats = maskedBeats_4; // @[Arbiter.scala:82:69, :84:44] wire _beatsLeft_T = io_mem_acquire_ready_0 & io_mem_acquire_valid_0; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {8'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_2 = _beatsLeft_T_1[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] reg state_2; // @[Arbiter.scala:88:26] reg state_3; // @[Arbiter.scala:88:26] reg state_4; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_3 = idle ? winner_3 : state_3; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_4 = idle ? winner_4 : state_4; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_4 = idle ? readys_4 : state_4; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire _mshrs_0_io_mem_acquire_ready_T = io_mem_acquire_ready_0 & allowed_0; // @[Arbiter.scala:92:24, :94:31] wire _mshrs_1_io_mem_acquire_ready_T = io_mem_acquire_ready_0 & allowed_1; // @[Arbiter.scala:92:24, :94:31] wire _mshrs_2_io_mem_acquire_ready_T = io_mem_acquire_ready_0 & allowed_2; // @[Arbiter.scala:92:24, :94:31] wire _mshrs_3_io_mem_acquire_ready_T = io_mem_acquire_ready_0 & allowed_3; // @[Arbiter.scala:92:24, :94:31] wire _mmios_0_io_mem_access_ready_T = io_mem_acquire_ready_0 & allowed_4; // @[Arbiter.scala:92:24, :94:31] wire _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T | _mshrs_2_io_mem_acquire_valid; // @[Arbiter.scala:96:46] wire _io_mem_acquire_valid_T_2 = _io_mem_acquire_valid_T_1 | _mshrs_3_io_mem_acquire_valid; // @[Arbiter.scala:96:46] wire _io_mem_acquire_valid_T_3 = _io_mem_acquire_valid_T_2 | _mmios_0_io_mem_access_valid; // @[Arbiter.scala:96:46] wire _io_mem_acquire_valid_T_4 = state_0 & _mshrs_0_io_mem_acquire_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_5 = state_1 & _mshrs_1_io_mem_acquire_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_6 = state_2 & _mshrs_2_io_mem_acquire_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_7 = state_3 & _mshrs_3_io_mem_acquire_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_8 = state_4 & _mmios_0_io_mem_access_valid; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_9 = _io_mem_acquire_valid_T_4 | _io_mem_acquire_valid_T_5; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_10 = _io_mem_acquire_valid_T_9 | _io_mem_acquire_valid_T_6; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_11 = _io_mem_acquire_valid_T_10 | _io_mem_acquire_valid_T_7; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_T_12 = _io_mem_acquire_valid_T_11 | _io_mem_acquire_valid_T_8; // @[Mux.scala:30:73] wire _io_mem_acquire_valid_WIRE = _io_mem_acquire_valid_T_12; // @[Mux.scala:30:73] assign _io_mem_acquire_valid_T_13 = idle ? _io_mem_acquire_valid_T_3 : _io_mem_acquire_valid_WIRE; // @[Mux.scala:30:73] assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_13; // @[Arbiter.scala:96:24] wire [2:0] _io_mem_acquire_bits_WIRE_10; // @[Mux.scala:30:73] assign io_mem_acquire_bits_opcode_0 = _io_mem_acquire_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_WIRE_9; // @[Mux.scala:30:73] assign io_mem_acquire_bits_param_0 = _io_mem_acquire_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_WIRE_8; // @[Mux.scala:30:73] assign io_mem_acquire_bits_size_0 = _io_mem_acquire_bits_WIRE_size; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_WIRE_7; // @[Mux.scala:30:73] assign io_mem_acquire_bits_source_0 = _io_mem_acquire_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_WIRE_6; // @[Mux.scala:30:73] assign io_mem_acquire_bits_address_0 = _io_mem_acquire_bits_WIRE_address; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_WIRE_3; // @[Mux.scala:30:73] assign io_mem_acquire_bits_mask_0 = _io_mem_acquire_bits_WIRE_mask; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_WIRE_2; // @[Mux.scala:30:73] assign io_mem_acquire_bits_data_0 = _io_mem_acquire_bits_WIRE_data; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_T_13 = muxState_4 ? _mmios_0_io_mem_access_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _io_mem_acquire_bits_T_17 = _io_mem_acquire_bits_T_13; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_2 = _io_mem_acquire_bits_T_17; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_data = _io_mem_acquire_bits_WIRE_2; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_18 = {16{muxState_0}}; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_19 = {16{muxState_1}}; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_20 = {16{muxState_2}}; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_21 = {16{muxState_3}}; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_22 = muxState_4 ? _mmios_0_io_mem_access_bits_mask : 16'h0; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_23 = _io_mem_acquire_bits_T_18 | _io_mem_acquire_bits_T_19; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_24 = _io_mem_acquire_bits_T_23 | _io_mem_acquire_bits_T_20; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_25 = _io_mem_acquire_bits_T_24 | _io_mem_acquire_bits_T_21; // @[Mux.scala:30:73] wire [15:0] _io_mem_acquire_bits_T_26 = _io_mem_acquire_bits_T_25 | _io_mem_acquire_bits_T_22; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_3 = _io_mem_acquire_bits_T_26; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_mask = _io_mem_acquire_bits_WIRE_3; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_27 = muxState_0 ? _mshrs_0_io_mem_acquire_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_28 = muxState_1 ? _mshrs_1_io_mem_acquire_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_29 = muxState_2 ? _mshrs_2_io_mem_acquire_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_30 = muxState_3 ? _mshrs_3_io_mem_acquire_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_31 = muxState_4 ? _mmios_0_io_mem_access_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_32 = _io_mem_acquire_bits_T_27 | _io_mem_acquire_bits_T_28; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_33 = _io_mem_acquire_bits_T_32 | _io_mem_acquire_bits_T_29; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_34 = _io_mem_acquire_bits_T_33 | _io_mem_acquire_bits_T_30; // @[Mux.scala:30:73] wire [31:0] _io_mem_acquire_bits_T_35 = _io_mem_acquire_bits_T_34 | _io_mem_acquire_bits_T_31; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_6 = _io_mem_acquire_bits_T_35; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_address = _io_mem_acquire_bits_WIRE_6; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_37 = {2'h0, muxState_1}; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_41 = _io_mem_acquire_bits_T_37; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_38 = {1'h0, muxState_2, 1'h0}; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_39 = muxState_3 ? 3'h3 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_40 = muxState_4 ? _mmios_0_io_mem_access_bits_source : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_42 = _io_mem_acquire_bits_T_41 | _io_mem_acquire_bits_T_38; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_43 = _io_mem_acquire_bits_T_42 | _io_mem_acquire_bits_T_39; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_44 = _io_mem_acquire_bits_T_43 | _io_mem_acquire_bits_T_40; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_7 = _io_mem_acquire_bits_T_44; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_source = _io_mem_acquire_bits_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_45 = muxState_0 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_46 = muxState_1 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_47 = muxState_2 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_48 = muxState_3 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_49 = muxState_4 ? _mmios_0_io_mem_access_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_50 = _io_mem_acquire_bits_T_45 | _io_mem_acquire_bits_T_46; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_51 = _io_mem_acquire_bits_T_50 | _io_mem_acquire_bits_T_47; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_52 = _io_mem_acquire_bits_T_51 | _io_mem_acquire_bits_T_48; // @[Mux.scala:30:73] wire [3:0] _io_mem_acquire_bits_T_53 = _io_mem_acquire_bits_T_52 | _io_mem_acquire_bits_T_49; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_8 = _io_mem_acquire_bits_T_53; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_size = _io_mem_acquire_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_54 = muxState_0 ? _mshrs_0_io_mem_acquire_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_55 = muxState_1 ? _mshrs_1_io_mem_acquire_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_56 = muxState_2 ? _mshrs_2_io_mem_acquire_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_57 = muxState_3 ? _mshrs_3_io_mem_acquire_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_58 = muxState_4 ? _mmios_0_io_mem_access_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_59 = _io_mem_acquire_bits_T_54 | _io_mem_acquire_bits_T_55; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_60 = _io_mem_acquire_bits_T_59 | _io_mem_acquire_bits_T_56; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_61 = _io_mem_acquire_bits_T_60 | _io_mem_acquire_bits_T_57; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_62 = _io_mem_acquire_bits_T_61 | _io_mem_acquire_bits_T_58; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_9 = _io_mem_acquire_bits_T_62; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_param = _io_mem_acquire_bits_WIRE_9; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_63 = muxState_0 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_64 = muxState_1 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_65 = muxState_2 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_66 = muxState_3 ? 3'h6 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_67 = muxState_4 ? _mmios_0_io_mem_access_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_68 = _io_mem_acquire_bits_T_63 | _io_mem_acquire_bits_T_64; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_69 = _io_mem_acquire_bits_T_68 | _io_mem_acquire_bits_T_65; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_70 = _io_mem_acquire_bits_T_69 | _io_mem_acquire_bits_T_66; // @[Mux.scala:30:73] wire [2:0] _io_mem_acquire_bits_T_71 = _io_mem_acquire_bits_T_70 | _io_mem_acquire_bits_T_67; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_10 = _io_mem_acquire_bits_T_71; // @[Mux.scala:30:73] assign _io_mem_acquire_bits_WIRE_opcode = _io_mem_acquire_bits_WIRE_10; // @[Mux.scala:30:73] reg beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = ~beatsLeft_1; // @[Arbiter.scala:60:30, :61:28] wire latch_1 = idle_1 & io_mem_finish_ready_0; // @[Arbiter.scala:61:28, :62:24] wire [1:0] readys_lo_1 = {_mshrs_1_io_mem_finish_valid, _mshrs_0_io_mem_finish_valid}; // @[Arbiter.scala:68:51] wire [1:0] readys_hi_1 = {_mshrs_3_io_mem_finish_valid, _mshrs_2_io_mem_finish_valid}; // @[Arbiter.scala:68:51] wire [3:0] _readys_T_19 = {readys_hi_1, readys_lo_1}; // @[Arbiter.scala:68:51] wire [4:0] _readys_T_20 = {_readys_T_19, 1'h0}; // @[package.scala:253:48] wire [3:0] _readys_T_21 = _readys_T_20[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_T_22 = _readys_T_19 | _readys_T_21; // @[package.scala:253:{43,53}] wire [5:0] _readys_T_23 = {_readys_T_22, 2'h0}; // @[package.scala:253:{43,48}] wire [3:0] _readys_T_24 = _readys_T_23[3:0]; // @[package.scala:253:{48,53}] wire [3:0] _readys_T_25 = _readys_T_22 | _readys_T_24; // @[package.scala:253:{43,53}] wire [3:0] _readys_T_26 = _readys_T_25; // @[package.scala:253:43, :254:17] wire [4:0] _readys_T_27 = {_readys_T_26, 1'h0}; // @[package.scala:254:17] wire [3:0] _readys_T_28 = _readys_T_27[3:0]; // @[Arbiter.scala:16:{78,83}] wire [3:0] _readys_T_29 = ~_readys_T_28; // @[Arbiter.scala:16:{61,83}] wire _readys_T_30 = _readys_T_29[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_0 = _readys_T_30; // @[Arbiter.scala:68:{27,76}] wire _readys_T_31 = _readys_T_29[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_1 = _readys_T_31; // @[Arbiter.scala:68:{27,76}] wire _readys_T_32 = _readys_T_29[2]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_2 = _readys_T_32; // @[Arbiter.scala:68:{27,76}] wire _readys_T_33 = _readys_T_29[3]; // @[Arbiter.scala:16:61, :68:76] wire readys_1_3 = _readys_T_33; // @[Arbiter.scala:68:{27,76}] wire _winner_T_5 = readys_1_0 & _mshrs_0_io_mem_finish_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1_0 = _winner_T_5; // @[Arbiter.scala:71:{27,69}] wire _winner_T_6 = readys_1_1 & _mshrs_1_io_mem_finish_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1_1 = _winner_T_6; // @[Arbiter.scala:71:{27,69}] wire _winner_T_7 = readys_1_2 & _mshrs_2_io_mem_finish_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1_2 = _winner_T_7; // @[Arbiter.scala:71:{27,69}] wire _winner_T_8 = readys_1_3 & _mshrs_3_io_mem_finish_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1_3 = _winner_T_8; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1_1 = winner_1_0; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_2_1 = prefixOR_1_1 | winner_1_1; // @[Arbiter.scala:71:27, :76:48] wire prefixOR_3_1 = prefixOR_2_1 | winner_1_2; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T_1 = prefixOR_3_1 | winner_1_3; // @[Arbiter.scala:71:27, :76:48] wire _io_mem_finish_valid_T = _mshrs_0_io_mem_finish_valid | _mshrs_1_io_mem_finish_valid; // @[Arbiter.scala:79:31, :96:46]
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid || io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }
module PriorityQueueStage_96( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel | (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens | chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_||_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }
module SwitchArbiter_137( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [2:0] unassigned = {io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [2:0] mask; // @[SwitchAllocator.scala:27:21] wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_valids = {io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [2:0] chosen = (|(in_valids & lock_0)) ? lock_0 : sel[2:0] | sel[5:3]; // @[Mux.scala:50:70] wire [2:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [1:0] _GEN = chosen[1:0] | chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38] mask <= 3'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (|_io_out_0_valid_T) ? {chosen[2], _GEN[1], _GEN[0] | chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_12( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [7:0] _roundMask_T_5 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_4 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_10 = 8'hF0; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_13 = 6'hF; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_14 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_15 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_20 = 8'hCC; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_23 = 7'h33; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_24 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_25 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_30 = 8'hAA; // @[primitives.scala:77:20] wire [5:0] _expOut_T_4 = 6'h37; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [13:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49] wire [16:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[13]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [5:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [5:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [9:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [9:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [5:0] _roundMask_T = io_in_sExp_0[5:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [5:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1); // @[primitives.scala:52:21, :76:56] wire [11:0] _roundMask_T_2 = roundMask_shift[18:7]; // @[primitives.scala:76:56, :78:22] wire [7:0] _roundMask_T_3 = _roundMask_T_2[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_6 = _roundMask_T_3[7:4]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_7 = {4'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_8 = _roundMask_T_3[3:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_9 = {_roundMask_T_8, 4'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_11 = _roundMask_T_9 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_16 = _roundMask_T_12[7:2]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_17 = {2'h0, _roundMask_T_16 & 6'h33}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_18 = _roundMask_T_12[5:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_19 = {_roundMask_T_18, 2'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_21 = _roundMask_T_19 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_26 = _roundMask_T_22[7:1]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_27 = {1'h0, _roundMask_T_26 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _roundMask_T_28 = _roundMask_T_22[6:0]; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_29 = {_roundMask_T_28, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_31 = _roundMask_T_29 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_33 = _roundMask_T_2[11:8]; // @[primitives.scala:77:20, :78:22] wire [1:0] _roundMask_T_34 = _roundMask_T_33[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_35 = _roundMask_T_34[0]; // @[primitives.scala:77:20] wire _roundMask_T_36 = _roundMask_T_34[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_37 = {_roundMask_T_35, _roundMask_T_36}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_38 = _roundMask_T_33[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_39 = _roundMask_T_38[0]; // @[primitives.scala:77:20] wire _roundMask_T_40 = _roundMask_T_38[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_41 = {_roundMask_T_39, _roundMask_T_40}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_42 = {_roundMask_T_37, _roundMask_T_41}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_43 = {_roundMask_T_32, _roundMask_T_42}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_44 = {_roundMask_T_43[11:1], _roundMask_T_43[0] | doShiftSigDown1}; // @[primitives.scala:77:20] wire [13:0] roundMask = {_roundMask_T_44, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [14:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [13:0] shiftedRoundMask = _shiftedRoundMask_T[14:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [13:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [13:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [13:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [13:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [13:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [11:0] _roundedSig_T_1 = _roundedSig_T[13:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [12:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 13'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [12:0] _roundedSig_T_6 = roundMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [12:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [12:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [12:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [13:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [13:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [11:0] _roundedSig_T_12 = _roundedSig_T_11[13:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [12:0] _roundedSig_T_14 = roundPosMask[13:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [12:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 13'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [12:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [12:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[12:11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [7:0] sRoundedExp = {io_in_sExp_0[6], io_in_sExp_0} + {{5{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [9:0] _common_fractOut_T = roundedSig[10:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [9:0] _common_fractOut_T_1 = roundedSig[9:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[7:4]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 8'sh8; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[12]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[6:5]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [5:0] _expOut_T_1 = _expOut_T ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [5:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [5:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [5:0] _expOut_T_5 = pegMinNonzeroMagOut ? 6'h37 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [5:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [5:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [5:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 4'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [5:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [5:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [5:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [5:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [5:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [5:0] _expOut_T_14 = {2'h0, pegMinNonzeroMagOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [5:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [5:0] _expOut_T_16 = pegMaxFiniteMagOut ? 6'h2F : 6'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [5:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [5:0] _expOut_T_18 = notNaN_isInfOut ? 6'h30 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [5:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [5:0] _expOut_T_20 = isNaNOut ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [5:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [9:0] _fractOut_T_2 = {isNaNOut, 9'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [9:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [9:0] _fractOut_T_4 = {10{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [9:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [6:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_38( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_49 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_28( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_284 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /** =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} */ class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /** request address from CPU. */ val vaddr = UInt(vaddrBitsExtended.W) /** don't lookup TLB, bypass vaddr as paddr */ val passthrough = Bool() /** granularity */ val size = UInt(log2Ceil(lgMaxSize + 1).W) /** memory command. */ val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /** virtualization mode */ val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /** physical address */ val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /** page fault exception */ val pf = new TLBExceptions /** guest page fault exception */ val gf = new TLBExceptions /** access exception */ val ae = new TLBExceptions /** misaligned access exception */ val ma = new TLBExceptions /** if this address is cacheable */ val cacheable = Bool() /** if caches must allocate this address */ val must_alloc = Bool() /** if this address is prefetchable for caches*/ val prefetchable = Bool() /** size/cmd of request that generated this response*/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /** pte.u user */ val u = Bool() /** pte.g global */ val g = Bool() /** access exception. * D$ -> PTW -> TLB AE * Alignment failed. */ val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** supervisor write */ val sw = Bool() /** supervisor execute */ val sx = Bool() /** supervisor read */ val sr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor excute */ val hx = Bool() /** hypervisor read */ val hr = Bool() /** prot_w */ val pw = Bool() /** prot_x */ val px = Bool() /** prot_r */ val pr = Bool() /** PutPartial */ val ppp = Bool() /** AMO logical */ val pal = Bool() /** AMO arithmetic */ val paa = Bool() /** get/put effects */ val eff = Bool() /** cacheable */ val c = Bool() /** fragmented_superpage support */ val fragmented_superpage = Bool() } /** basic cell for TLB data */ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 || !superpage) require(!superpageOnly || superpage) val level = UInt(log2Ceil(pgLevels).W) /** use vpn as tag */ val tag_vpn = UInt(vpnBits.W) /** tag in vitualization mode */ val tag_v = Bool() /** entry data */ val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /** valid bit */ val valid = Vec(nSectors, Bool()) /** returns all entry data in this entry */ def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /** returns the index of sector */ private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /** returns the entry data matched with this vpn*/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /** returns whether a sector hits */ def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /** returns whether tag matches vpn */ def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /** returns hit signal */ def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) * pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore || (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData */ def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels * pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits*(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U || (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) | data.ppn)(supervisorVPNBits - j*pgLevelBits - 1, supervisorVPNBits - (j + 1)*pgLevelBits)) } res } else { data.ppn } } /** does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data */ def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits * (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries */ case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /** =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * |vaddr | * |ppn/vpn | pgIndex | * | | | * | |nSets |nSector | |}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB*2+ITLB}}} * @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. */ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /** request from Core */ val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /** response to Core */ val resp = Output(new TLBResp(lgMaxSize)) /** SFence Input */ val sfence = Flipped(Valid(new SFenceReq)) /** IO to PTW */ val ptw = new TLBPTWIO /** suppress a TLB refill, one cycle after a miss */ val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /** index for sectored_Entry */ val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /** TLB Entry */ val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /** Superpage Entry */ val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /** Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. */ val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /** privilege mode */ val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /** VS-stage translation enable */ val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /** G-stage translation enable */ val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /** Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) */ val vm_enabled = (stage1_en || stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /** refill signal */ val do_refill = usingVM.B && io.ptw.resp.valid /** sfence invalidate refill */ val invalidate_refill = state.isOneOf(s_request /* don't care */, s_wait_invalidate) || io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction || !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en || r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s || sum, entries.map(_.u).asUInt, 0.U) | Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) | entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr | Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt | Mux(mxr, entries.map(_.sx).asUInt, 0.U))) | stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) | stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) | stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt | Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) | stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt | stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt | stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array | final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array | final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array | c_array val paa_array_if_cached = paa_array | (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array | (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels * pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U || signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM || (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write || io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad || usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) | Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) | Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) | Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) | Mux(cmd_amo_logical, ~pal_array, 0.U) | Mux(cmd_amo_arithmetic, ~paa_array, 0.U) | Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) | ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array | ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array | gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) | Fill(all_entries.size, !vstage1_en) hit_mask | ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) || (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) || (pf_st_array & hits).orR io.resp.pf.inst := bad_va || (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) || (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) || (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa || (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint).B io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv || hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits || reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement */ def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r || w || x || c || a || l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet || m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull || m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet || m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial || m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB || m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT || m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ || _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ || _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ || _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /** PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss */ class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /** PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info */ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /** ptw access exception */ val ae_ptw = Bool() /** final access exception */ val ae_final = Bool() /** page fault */ val pf = Bool() /** guest page fault */ val gf = Bool() /** hypervisor read */ val hr = Bool() /** hypervisor write */ val hw = Bool() /** hypervisor execute */ val hx = Bool() /** PTE to refill L1TLB * * source: L2TLB */ val pte = new PTE /** pte pglevel */ val level = UInt(log2Ceil(pgLevels).W) /** fragmented_superpage support */ val fragmented_superpage = Bool() /** homogeneous for both pma and pmp */ val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /** IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) */ class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /** PTW performance statistics */ class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /** Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core */ class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /** enable clock generated by ptw */ val clock_enabled = Output(Bool()) } /** PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format */ class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** global mapping */ val g = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() /** valid bit */ val v = Bool() /** return true if find a pointer to next level page table */ def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /** return true if find a leaf PTE */ def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a /** user read */ def ur(dummy: Int = 0) = sr() && u /** user write*/ def uw(dummy: Int = 0) = sw() && u /** user execute */ def ux(dummy: Int = 0) = sx() && u /** supervisor read */ def sr(dummy: Int = 0) = leaf() && r /** supervisor write */ def sw(dummy: Int = 0) = leaf() && w && d /** supervisor execute */ def sx(dummy: Int = 0) = leaf() && x /** full permission: writable and executable in user mode */ def isFullPerm(dummy: Int = 0) = uw() && ux() } /** L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format */ class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /** dirty bit */ val d = Bool() /** access bit */ val a = Bool() /** user mode accessible */ val u = Bool() /** whether the page is executable */ val x = Bool() /** whether the page is writable */ val w = Bool() /** whether the page is readable */ val r = Bool() } /** PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation */ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /** to n TLB */ val requestor = Flipped(Vec(n, new TLBPTWIO)) /** to HellaCache */ val mem = new HellaCacheIO /** to Core * * contains CSRs info and performance statistics */ val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /** Arbiter to arbite request from n TLB */ val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready || l2_refill_wire || arb.io.out.valid || io.dpath.sfence.valid || io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM || !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /** current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} */ val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /** tlb request */ val r_req = Reg(new PTWReq) /** current selected way in arbitor */ val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /** pte for 2-stage translation */ val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /** 2-stage translation both enable */ val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r || tmp.w || tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /** address send to mem for enquerry */ val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) * pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) | vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr */ val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) * pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i))) } /** PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation */ def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid | UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 || usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /** the valid vec for the selected set(including n ways) */ val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) | mask g(way) := Mux(r_pte.g, g(way) | mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) || s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid || (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req || state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit || (state =/= s_wait1) || resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor || pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous || pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)*pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), aux_pte.ppn((pgLevels-i-1)*pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req || state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) || (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 || do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages || aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf || (pf && stage2) resp_hr := !stage2 || (!pf && !gf && pte.ur()) resp_hw := !stage2 || (!pf && !gf && pte.uw()) resp_hx := !stage2 || (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)*pgLevelBits), r_req.addr(((pgLevels-i-1)*pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)*pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn */ private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /** use hgatp and vpn to construct a new ppn */ private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range */ private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)*pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW */ trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } }
module ITLB( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_prv, // @[TLB.scala:320:14] input io_req_bits_v, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] output [39:0] io_resp_gpa, // @[TLB.scala:320:14] output io_resp_pf_ld, // @[TLB.scala:320:14] output io_resp_pf_inst, // @[TLB.scala:320:14] output io_resp_ae_ld, // @[TLB.scala:320:14] output io_resp_ae_inst, // @[TLB.scala:320:14] output io_resp_ma_ld, // @[TLB.scala:320:14] output io_resp_cacheable, // @[TLB.scala:320:14] output io_resp_prefetchable, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_sfence_bits_rs1, // @[TLB.scala:320:14] input io_sfence_bits_rs2, // @[TLB.scala:320:14] input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14] input io_sfence_bits_asid, // @[TLB.scala:320:14] input io_sfence_bits_hv, // @[TLB.scala:320:14] input io_sfence_bits_hg, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_8_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_7_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_6_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_5_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7] wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7] wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7] wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7] wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7] wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33] wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59] wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40] wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59] wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59] wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43] wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41] wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47] wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59] wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44] wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32] wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49] wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42] wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66] wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59] wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47] wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59] wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44] wire cmd_write = 1'h0; // @[Consts.scala:90:76] wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59] wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72] wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41] wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31] wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire ignore_6 = 1'h0; // @[TLB.scala:182:34] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire ignore_9 = 1'h0; // @[TLB.scala:182:34] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire ignore_12 = 1'h0; // @[TLB.scala:182:34] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [2:0] io_req_bits_size = 3'h4; // @[TLB.scala:318:7] wire [2:0] io_resp_size = 3'h4; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _cmd_read_T = 1'h1; // @[package.scala:16:47] wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59] wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59] wire cmd_read = 1'h1; // @[Consts.scala:89:68] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire ignore_5 = 1'h1; // @[TLB.scala:182:34] wire ignore_8 = 1'h1; // @[TLB.scala:182:34] wire ignore_11 = 1'h1; // @[TLB.scala:182:34] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8] wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8] wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8] wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53] wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8] wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53] wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8] wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53] wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8] wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8] wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43] wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8] wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43] wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8] wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46] wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24] wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64] wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33] wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43] wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [7:0] _misaligned_T_2 = 8'hF; // @[TLB.scala:550:69] wire [8:0] _misaligned_T_1 = 9'hF; // @[TLB.scala:550:69] wire [7:0] _misaligned_T = 8'h10; // @[OneHot.scala:58:35] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready; // @[TLB.scala:318:7] wire io_resp_pf_ld_0; // @[TLB.scala:318:7] wire io_resp_pf_inst_0; // @[TLB.scala:318:7] wire io_resp_ae_ld_0; // @[TLB.scala:318:7] wire io_resp_ae_inst_0; // @[TLB.scala:318:7] wire io_resp_ma_ld_0; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7] wire io_resp_cacheable_0; // @[TLB.scala:318:7] wire io_resp_prefetchable_0; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29] reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_1_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_1_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_2_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_2_valid_0; // @[TLB.scala:341:30] reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_3_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_3_valid_0; // @[TLB.scala:341:30] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34] wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22] reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20] wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_51 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_51; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_8; // @[TLB.scala:197:28] assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_13; // @[TLB.scala:182:28] assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59] wire _sector_hits_T; // @[package.scala:81:59] assign _sector_hits_T = _GEN_4; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59] wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61] assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _T_176; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59] wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59] wire _sector_hits_T_8; // @[package.scala:81:59] assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59] wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61] assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59] wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59] wire _sector_hits_T_16; // @[package.scala:81:59] assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59] wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61] assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59] wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59] wire _sector_hits_T_24; // @[package.scala:81:59] assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59] wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61] assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59] wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59] wire _sector_hits_T_32; // @[package.scala:81:59] assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59] wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61] assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61] assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59] wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59] wire _sector_hits_T_40; // @[package.scala:81:59] assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59] wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61] assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61] assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59] wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59] wire _sector_hits_T_48; // @[package.scala:81:59] assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59] wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61] assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61] assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59] wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59] wire _sector_hits_T_56; // @[package.scala:81:59] assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59] assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59] wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29] wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61] assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61] assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61] wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52] assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52] assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52] assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52] assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52] assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52] assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52] assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52] assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52] assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28] wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}] wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52] assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52] assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52] assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52] assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52] assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52] assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire _ppn_ignore_T_4; // @[TLB.scala:197:28] assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28] wire _ignore_T_7; // @[TLB.scala:182:28] assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28] wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}] wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52] assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52] assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52] assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52] assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52] assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52] assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire _ppn_ignore_T_6; // @[TLB.scala:197:28] assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28] wire _ignore_T_10; // @[TLB.scala:182:28] assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28] wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}] wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13] wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13] wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13] wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13] wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13] wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44] wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29] wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29] wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13] wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52] assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52] assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52] assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}] wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27] wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27] wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27] wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27] wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24] wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13] wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_23; // @[TLB.scala:170:77] wire _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13] assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77] wire [19:0] _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] wire _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13] assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77] wire [19:0] _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] wire _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13] assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77] wire [19:0] _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] wire _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13] assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77] wire [19:0] _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] wire _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13] assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77] wire [19:0] _entries_T_143; // @[TLB.scala:170:77] wire _entries_T_142; // @[TLB.scala:170:77] wire _entries_T_141; // @[TLB.scala:170:77] wire _entries_T_140; // @[TLB.scala:170:77] wire _entries_T_139; // @[TLB.scala:170:77] wire _entries_T_138; // @[TLB.scala:170:77] wire _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13] assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77] assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77] assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77] assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77] assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77] assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77] assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77] wire [19:0] _entries_T_167; // @[TLB.scala:170:77] wire _entries_T_166; // @[TLB.scala:170:77] wire _entries_T_165; // @[TLB.scala:170:77] wire _entries_T_164; // @[TLB.scala:170:77] wire _entries_T_163; // @[TLB.scala:170:77] wire _entries_T_162; // @[TLB.scala:170:77] wire _entries_T_161; // @[TLB.scala:170:77] wire _entries_T_160; // @[TLB.scala:170:77] wire _entries_T_159; // @[TLB.scala:170:77] wire _entries_T_158; // @[TLB.scala:170:77] wire _entries_T_157; // @[TLB.scala:170:77] wire _entries_T_156; // @[TLB.scala:170:77] wire _entries_T_155; // @[TLB.scala:170:77] wire _entries_T_154; // @[TLB.scala:170:77] wire _entries_T_153; // @[TLB.scala:170:77] wire _entries_T_152; // @[TLB.scala:170:77] wire _entries_T_151; // @[TLB.scala:170:77] wire _entries_T_150; // @[TLB.scala:170:77] wire _entries_T_149; // @[TLB.scala:170:77] wire _entries_T_148; // @[TLB.scala:170:77] wire _entries_T_147; // @[TLB.scala:170:77] wire _entries_T_146; // @[TLB.scala:170:77] wire _entries_T_145; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13] assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77] wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77] assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77] wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77] assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77] wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77] assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77] wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77] assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77] assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77] assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77] assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77] wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77] assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77] assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77] assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77] assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77] wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77] assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77] assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77] assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77] wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77] assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77] wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77] assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77] wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77] assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77] assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77] assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77] wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77] assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77] wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77] assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77] wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77] assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77] wire [19:0] _entries_T_191; // @[TLB.scala:170:77] wire _entries_T_190; // @[TLB.scala:170:77] wire _entries_T_189; // @[TLB.scala:170:77] wire _entries_T_188; // @[TLB.scala:170:77] wire _entries_T_187; // @[TLB.scala:170:77] wire _entries_T_186; // @[TLB.scala:170:77] wire _entries_T_185; // @[TLB.scala:170:77] wire _entries_T_184; // @[TLB.scala:170:77] wire _entries_T_183; // @[TLB.scala:170:77] wire _entries_T_182; // @[TLB.scala:170:77] wire _entries_T_181; // @[TLB.scala:170:77] wire _entries_T_180; // @[TLB.scala:170:77] wire _entries_T_179; // @[TLB.scala:170:77] wire _entries_T_178; // @[TLB.scala:170:77] wire _entries_T_177; // @[TLB.scala:170:77] wire _entries_T_176; // @[TLB.scala:170:77] wire _entries_T_175; // @[TLB.scala:170:77] wire _entries_T_174; // @[TLB.scala:170:77] wire _entries_T_173; // @[TLB.scala:170:77] wire _entries_T_172; // @[TLB.scala:170:77] wire _entries_T_171; // @[TLB.scala:170:77] wire _entries_T_170; // @[TLB.scala:170:77] wire _entries_T_169; // @[TLB.scala:170:77] wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29] wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13] assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77] wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77] assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77] wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77] assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77] wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77] assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77] wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77] assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77] assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77] assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77] assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77] wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77] assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77] assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77] assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77] assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77] wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77] assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77] assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77] assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77] wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77] assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77] wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77] assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77] wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77] assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77] assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77] assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77] wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77] assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77] wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77] assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77] wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77] assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77] wire [19:0] _entries_T_214; // @[TLB.scala:170:77] wire _entries_T_213; // @[TLB.scala:170:77] wire _entries_T_212; // @[TLB.scala:170:77] wire _entries_T_211; // @[TLB.scala:170:77] wire _entries_T_210; // @[TLB.scala:170:77] wire _entries_T_209; // @[TLB.scala:170:77] wire _entries_T_208; // @[TLB.scala:170:77] wire _entries_T_207; // @[TLB.scala:170:77] wire _entries_T_206; // @[TLB.scala:170:77] wire _entries_T_205; // @[TLB.scala:170:77] wire _entries_T_204; // @[TLB.scala:170:77] wire _entries_T_203; // @[TLB.scala:170:77] wire _entries_T_202; // @[TLB.scala:170:77] wire _entries_T_201; // @[TLB.scala:170:77] wire _entries_T_200; // @[TLB.scala:170:77] wire _entries_T_199; // @[TLB.scala:170:77] wire _entries_T_198; // @[TLB.scala:170:77] wire _entries_T_197; // @[TLB.scala:170:77] wire _entries_T_196; // @[TLB.scala:170:77] wire _entries_T_195; // @[TLB.scala:170:77] wire _entries_T_194; // @[TLB.scala:170:77] wire _entries_T_193; // @[TLB.scala:170:77] wire _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77] wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77] assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77] wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77] assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77] wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77] assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77] wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77] assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77] assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77] assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77] assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77] wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77] assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77] assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77] assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77] assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77] wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77] assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77] assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77] assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77] wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77] assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77] wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77] assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77] wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77] assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77] assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77] assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77] wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77] assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77] wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77] assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77] wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77] assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77] wire [19:0] _entries_T_237; // @[TLB.scala:170:77] wire _entries_T_236; // @[TLB.scala:170:77] wire _entries_T_235; // @[TLB.scala:170:77] wire _entries_T_234; // @[TLB.scala:170:77] wire _entries_T_233; // @[TLB.scala:170:77] wire _entries_T_232; // @[TLB.scala:170:77] wire _entries_T_231; // @[TLB.scala:170:77] wire _entries_T_230; // @[TLB.scala:170:77] wire _entries_T_229; // @[TLB.scala:170:77] wire _entries_T_228; // @[TLB.scala:170:77] wire _entries_T_227; // @[TLB.scala:170:77] wire _entries_T_226; // @[TLB.scala:170:77] wire _entries_T_225; // @[TLB.scala:170:77] wire _entries_T_224; // @[TLB.scala:170:77] wire _entries_T_223; // @[TLB.scala:170:77] wire _entries_T_222; // @[TLB.scala:170:77] wire _entries_T_221; // @[TLB.scala:170:77] wire _entries_T_220; // @[TLB.scala:170:77] wire _entries_T_219; // @[TLB.scala:170:77] wire _entries_T_218; // @[TLB.scala:170:77] wire _entries_T_217; // @[TLB.scala:170:77] wire _entries_T_216; // @[TLB.scala:170:77] wire _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77] wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77] assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77] wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77] assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77] wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77] assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77] wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77] assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77] assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77] assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77] assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77] wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77] assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77] assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77] assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77] assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77] wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77] assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77] assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77] assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77] wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77] assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77] wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77] assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77] wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77] assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77] assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77] assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77] wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77] assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77] wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77] assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77] wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77] assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77] wire [19:0] _entries_T_260; // @[TLB.scala:170:77] wire _entries_T_259; // @[TLB.scala:170:77] wire _entries_T_258; // @[TLB.scala:170:77] wire _entries_T_257; // @[TLB.scala:170:77] wire _entries_T_256; // @[TLB.scala:170:77] wire _entries_T_255; // @[TLB.scala:170:77] wire _entries_T_254; // @[TLB.scala:170:77] wire _entries_T_253; // @[TLB.scala:170:77] wire _entries_T_252; // @[TLB.scala:170:77] wire _entries_T_251; // @[TLB.scala:170:77] wire _entries_T_250; // @[TLB.scala:170:77] wire _entries_T_249; // @[TLB.scala:170:77] wire _entries_T_248; // @[TLB.scala:170:77] wire _entries_T_247; // @[TLB.scala:170:77] wire _entries_T_246; // @[TLB.scala:170:77] wire _entries_T_245; // @[TLB.scala:170:77] wire _entries_T_244; // @[TLB.scala:170:77] wire _entries_T_243; // @[TLB.scala:170:77] wire _entries_T_242; // @[TLB.scala:170:77] wire _entries_T_241; // @[TLB.scala:170:77] wire _entries_T_240; // @[TLB.scala:170:77] wire _entries_T_239; // @[TLB.scala:170:77] wire _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77] wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77] assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77] wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77] assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77] wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77] assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77] wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77] assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77] assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77] assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77] assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77] wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77] assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77] assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77] assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77] assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77] wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77] assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77] assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77] assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77] wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77] assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77] wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77] assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77] wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77] assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77] assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77] assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77] wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77] assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77] wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77] assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77] wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77] assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77] wire [19:0] _entries_T_283; // @[TLB.scala:170:77] wire _entries_T_282; // @[TLB.scala:170:77] wire _entries_T_281; // @[TLB.scala:170:77] wire _entries_T_280; // @[TLB.scala:170:77] wire _entries_T_279; // @[TLB.scala:170:77] wire _entries_T_278; // @[TLB.scala:170:77] wire _entries_T_277; // @[TLB.scala:170:77] wire _entries_T_276; // @[TLB.scala:170:77] wire _entries_T_275; // @[TLB.scala:170:77] wire _entries_T_274; // @[TLB.scala:170:77] wire _entries_T_273; // @[TLB.scala:170:77] wire _entries_T_272; // @[TLB.scala:170:77] wire _entries_T_271; // @[TLB.scala:170:77] wire _entries_T_270; // @[TLB.scala:170:77] wire _entries_T_269; // @[TLB.scala:170:77] wire _entries_T_268; // @[TLB.scala:170:77] wire _entries_T_267; // @[TLB.scala:170:77] wire _entries_T_266; // @[TLB.scala:170:77] wire _entries_T_265; // @[TLB.scala:170:77] wire _entries_T_264; // @[TLB.scala:170:77] wire _entries_T_263; // @[TLB.scala:170:77] wire _entries_T_262; // @[TLB.scala:170:77] wire _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77] wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77] assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77] wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77] assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77] wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77] assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77] wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77] assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77] assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77] assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77] assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77] wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77] assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77] assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77] assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77] assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77] wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77] assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77] assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77] assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77] wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77] assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77] wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77] assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77] wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77] assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77] assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77] assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77] wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77] assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77] wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77] assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77] wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77] assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77] wire [19:0] _entries_T_306; // @[TLB.scala:170:77] wire _entries_T_305; // @[TLB.scala:170:77] wire _entries_T_304; // @[TLB.scala:170:77] wire _entries_T_303; // @[TLB.scala:170:77] wire _entries_T_302; // @[TLB.scala:170:77] wire _entries_T_301; // @[TLB.scala:170:77] wire _entries_T_300; // @[TLB.scala:170:77] wire _entries_T_299; // @[TLB.scala:170:77] wire _entries_T_298; // @[TLB.scala:170:77] wire _entries_T_297; // @[TLB.scala:170:77] wire _entries_T_296; // @[TLB.scala:170:77] wire _entries_T_295; // @[TLB.scala:170:77] wire _entries_T_294; // @[TLB.scala:170:77] wire _entries_T_293; // @[TLB.scala:170:77] wire _entries_T_292; // @[TLB.scala:170:77] wire _entries_T_291; // @[TLB.scala:170:77] wire _entries_T_290; // @[TLB.scala:170:77] wire _entries_T_289; // @[TLB.scala:170:77] wire _entries_T_288; // @[TLB.scala:170:77] wire _entries_T_287; // @[TLB.scala:170:77] wire _entries_T_286; // @[TLB.scala:170:77] wire _entries_T_285; // @[TLB.scala:170:77] wire _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77] wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77] assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77] wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77] assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77] wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77] assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77] wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77] assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77] assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77] assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77] assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77] wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77] assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77] assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77] assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77] assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77] wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77] assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77] assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77] assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77] wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77] assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77] wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77] assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77] wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77] assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77] assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77] assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77] wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77] assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77] wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77] assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77] wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77] assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73] wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73] wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73] wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73] wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73] wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73] wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73] wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73] wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73] wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73] wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73] wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73] wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24] wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}] wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27] wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27] wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27] wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27] assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27] wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27] wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27] assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27] wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27] assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27] wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27] assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27] wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27] assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27] assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27] wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27] wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27] wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27] wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27] wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27] assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27] wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27] assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27] wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27] wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27] assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27] wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27] assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27] wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27] wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27] wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104] wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104] wire [13:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104] wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27] assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27] wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27] assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27] wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27] assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27] wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27] wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0]}; // @[TLB.scala:318:7, :550:39] wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}] assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28] wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}] wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}] wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}] wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27] wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [6:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_reg_1; // @[Replacement.scala:168:70] wire [1:0] _GEN_60 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_lo; // @[OneHot.scala:21:45] assign lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_lo = _GEN_60; // @[OneHot.scala:21:45] wire [1:0] _GEN_61 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] lo_hi; // @[OneHot.scala:21:45] assign lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo_hi = _GEN_61; // @[OneHot.scala:21:45] wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45] wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_62 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45] wire [1:0] hi_lo; // @[OneHot.scala:21:45] assign hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_lo = _GEN_62; // @[OneHot.scala:21:45] wire [1:0] _GEN_63 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45] wire [1:0] hi_hi; // @[OneHot.scala:21:45] assign hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi_hi = _GEN_63; // @[OneHot.scala:21:45] wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45] wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13] wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13] wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17] wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17] wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13] wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13] wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13] wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13] wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13] wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13] wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13] wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13] wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13] wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13] wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}] wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16] wire [1:0] _GEN_64 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo_3; // @[OneHot.scala:21:45] assign lo_3 = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_lo = _GEN_64; // @[OneHot.scala:21:45] wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_65 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi_3; // @[OneHot.scala:21:45] assign hi_3 = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45] assign r_superpage_hit_bits_hi = _GEN_65; // @[OneHot.scala:21:45] wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38] wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13] wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16] wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37] wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}] wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27] wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}] wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39] wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39] wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39] wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61] wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}] wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39] wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}] wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16] wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}] wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16] wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}] wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16] wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38] wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27] wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27] wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27] wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70] wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17] wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16] wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59] wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59] wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27] wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59] wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59] wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27] wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45] wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59] wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45] wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18] wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28] wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}] wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59] wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59] wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_172( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_312 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel | (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens | chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_||_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }
module SwitchArbiter_225( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_4_ready, // @[SwitchAllocator.scala:18:14] input io_in_4_valid, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_4_bits_tail, // @[SwitchAllocator.scala:18:14] input io_out_0_ready, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_1, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14] output [4:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [4:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [4:0] unassigned = {io_in_4_valid, 2'h0, io_in_1_valid, 1'h0} & ~lock_0; // @[SwitchAllocator.scala:17:7, :24:38, :25:{23,52,54}] reg [4:0] mask; // @[SwitchAllocator.scala:27:21] wire [4:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [9:0] sel = _sel_T_1[0] ? 10'h1 : _sel_T_1[1] ? 10'h2 : _sel_T_1[2] ? 10'h4 : _sel_T_1[3] ? 10'h8 : _sel_T_1[4] ? 10'h10 : unassigned[0] ? 10'h20 : unassigned[1] ? 10'h40 : unassigned[2] ? 10'h80 : unassigned[3] ? 10'h100 : {unassigned[4], 9'h0}; // @[OneHot.scala:85:71] wire [3:0] _GEN = {io_in_4_valid, 2'h0, io_in_1_valid}; // @[SwitchAllocator.scala:41:24] wire [3:0] _chosen_T_2 = _GEN & lock_0[4:1]; // @[SwitchAllocator.scala:24:38, :41:24, :42:33] wire [4:0] chosen = (|{_chosen_T_2[3], _chosen_T_2[0]}) ? lock_0 : sel[4:0] | sel[9:5]; // @[Mux.scala:50:70] wire [3:0] _io_out_0_valid_T = _GEN & chosen[4:1]; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [1:0] _GEN_0 = {_io_out_0_valid_T[3], _io_out_0_valid_T[0]}; // @[SwitchAllocator.scala:44:35] wire _GEN_1 = io_out_0_ready & (|_GEN_0); // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = chosen[3:0] | chosen[4:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [2:0] _GEN_3 = _GEN_2[2:0] | chosen[4:2]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] wire [1:0] _GEN_4 = _GEN_3[1:0] | chosen[4:3]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 5'h0; // @[SwitchAllocator.scala:24:38] mask <= 5'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (_GEN_1) // @[Decoupled.scala:51:35] lock_0 <= chosen & {~io_in_4_bits_tail, 2'h3, ~io_in_1_bits_tail, 1'h1}; // @[SwitchAllocator.scala:17:7, :24:38, :39:21, :42:21, :53:{25,27}] mask <= _GEN_1 ? {chosen[4], _GEN_2[3], _GEN_3[2], _GEN_4[1], _GEN_4[0] | chosen[4]} : (&mask) ? 5'h0 : {mask[3:0], 1'h1}; // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_109( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_252( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_464 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_39( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ListBuffer.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean) { val queueBits = log2Up(queues) val entryBits = log2Up(entries) } class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle { val index = UInt(params.queueBits.W) val data = Output(params.gen) } class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module { override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}" val io = IO(new Bundle { // push is visible on the same cycle; flow queues val push = Flipped(Decoupled(new ListBufferPush(params))) val valid = UInt(params.queues.W) val pop = Flipped(Valid(UInt(params.queueBits.W))) val data = Output(params.gen) }) val valid = RegInit(0.U(params.queues.W)) val head = Mem(params.queues, UInt(params.entryBits.W)) val tail = Mem(params.queues, UInt(params.entryBits.W)) val used = RegInit(0.U(params.entries.W)) val next = Mem(params.entries, UInt(params.entryBits.W)) val data = Mem(params.entries, params.gen) val freeOH = ~(leftOR(~used) << 1) & ~used val freeIdx = OHToUInt(freeOH) val valid_set = WireDefault(0.U(params.queues.W)) val valid_clr = WireDefault(0.U(params.queues.W)) val used_set = WireDefault(0.U(params.entries.W)) val used_clr = WireDefault(0.U(params.entries.W)) val push_tail = tail.read(io.push.bits.index) val push_valid = valid(io.push.bits.index) io.push.ready := !used.andR when (io.push.fire) { valid_set := UIntToOH(io.push.bits.index, params.queues) used_set := freeOH data.write(freeIdx, io.push.bits.data) when (push_valid) { next.write(push_tail, freeIdx) } .otherwise { head.write(io.push.bits.index, freeIdx) } tail.write(io.push.bits.index, freeIdx) } val pop_head = head.read(io.pop.bits) val pop_valid = valid(io.pop.bits) // Bypass push data to the peek port io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head))) io.valid := (if (!params.bypass) valid else (valid | valid_set)) // It is an error to pop something that is not valid assert (!io.pop.fire || (io.valid)(io.pop.bits)) when (io.pop.fire) { used_clr := UIntToOH(pop_head, params.entries) when (pop_head === tail.read(io.pop.bits)) { valid_clr := UIntToOH(io.pop.bits, params.queues) } head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head))) } // Empty bypass changes no state when ((!params.bypass).B || !io.pop.valid || pop_valid) { used := (used & ~used_clr) | used_set valid := (valid & ~valid_clr) | valid_set } }
module ListBuffer_QueuedRequest_q36_e28( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14] input io_push_bits_data_control, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14] input [6:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14] input [12:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14] output [35:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [5:0] io_pop_bits, // @[ListBuffer.scala:39:14] output io_data_prio_0, // @[ListBuffer.scala:39:14] output io_data_prio_1, // @[ListBuffer.scala:39:14] output io_data_prio_2, // @[ListBuffer.scala:39:14] output io_data_control, // @[ListBuffer.scala:39:14] output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14] output [2:0] io_data_param, // @[ListBuffer.scala:39:14] output [2:0] io_data_size, // @[ListBuffer.scala:39:14] output [6:0] io_data_source, // @[ListBuffer.scala:39:14] output [12:0] io_data_tag, // @[ListBuffer.scala:39:14] output [5:0] io_data_offset, // @[ListBuffer.scala:39:14] output [5:0] io_data_put // @[ListBuffer.scala:39:14] ); wire [44:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [4:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [4:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [4:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [4:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_0_0 = io_push_bits_data_prio_0; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_2_0 = io_push_bits_data_prio_2; // @[ListBuffer.scala:36:7] wire io_push_bits_data_control_0 = io_push_bits_data_control; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_opcode_0 = io_push_bits_data_opcode; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_param_0 = io_push_bits_data_param; // @[ListBuffer.scala:36:7] wire [2:0] io_push_bits_data_size_0 = io_push_bits_data_size; // @[ListBuffer.scala:36:7] wire [6:0] io_push_bits_data_source_0 = io_push_bits_data_source; // @[ListBuffer.scala:36:7] wire [12:0] io_push_bits_data_tag_0 = io_push_bits_data_tag; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_offset_0 = io_push_bits_data_offset; // @[ListBuffer.scala:36:7] wire [5:0] io_push_bits_data_put_0 = io_push_bits_data_put; // @[ListBuffer.scala:36:7] wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7] wire [5:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7] wire io_push_bits_data_prio_1 = 1'h0; // @[ListBuffer.scala:36:7] wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20] wire [5:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49] wire [5:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49] wire io_push_ready_0; // @[ListBuffer.scala:36:7] wire io_data_prio_0_0; // @[ListBuffer.scala:36:7] wire io_data_prio_1_0; // @[ListBuffer.scala:36:7] wire io_data_prio_2_0; // @[ListBuffer.scala:36:7] wire io_data_control_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_opcode_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_param_0; // @[ListBuffer.scala:36:7] wire [2:0] io_data_size_0; // @[ListBuffer.scala:36:7] wire [6:0] io_data_source_0; // @[ListBuffer.scala:36:7] wire [12:0] io_data_tag_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_offset_0; // @[ListBuffer.scala:36:7] wire [5:0] io_data_put_0; // @[ListBuffer.scala:36:7] wire [35:0] io_valid_0; // @[ListBuffer.scala:36:7] reg [35:0] valid; // @[ListBuffer.scala:47:22] assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22] reg [27:0] used; // @[ListBuffer.scala:50:22] assign io_data_prio_0_0 = _data_ext_R0_data[0]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_prio_1_0 = _data_ext_R0_data[1]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_prio_2_0 = _data_ext_R0_data[2]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_control_0 = _data_ext_R0_data[3]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_opcode_0 = _data_ext_R0_data[6:4]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_param_0 = _data_ext_R0_data[9:7]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_size_0 = _data_ext_R0_data[12:10]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_source_0 = _data_ext_R0_data[19:13]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_tag_0 = _data_ext_R0_data[32:20]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_offset_0 = _data_ext_R0_data[38:33]; // @[ListBuffer.scala:36:7, :52:18] assign io_data_put_0 = _data_ext_R0_data[44:39]; // @[ListBuffer.scala:36:7, :52:18] wire [27:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [28:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [27:0] _freeOH_T_2 = _freeOH_T_1[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}] wire [29:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_5 = _freeOH_T_4[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}] wire [31:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_8 = _freeOH_T_7[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}] wire [35:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_11 = _freeOH_T_10[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [27:0] _freeOH_T_14 = _freeOH_T_13[27:0]; // @[package.scala:253:{48,53}] wire [27:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}] wire [27:0] _freeOH_T_16 = _freeOH_T_15; // @[package.scala:253:43, :254:17] wire [28:0] _freeOH_T_17 = {_freeOH_T_16, 1'h0}; // @[package.scala:254:17] wire [28:0] _freeOH_T_18 = ~_freeOH_T_17; // @[ListBuffer.scala:54:{16,32}] wire [27:0] _freeOH_T_19 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}] wire [28:0] freeOH = {1'h0, _freeOH_T_18[27:0] & _freeOH_T_19}; // @[ListBuffer.scala:54:{16,38,40}] wire [12:0] freeIdx_hi = freeOH[28:16]; // @[OneHot.scala:30:18] wire [15:0] freeIdx_lo = freeOH[15:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_1 = {3'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_1 = _freeIdx_T_1[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_1 = _freeIdx_T_1[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_2 = _freeIdx_T_3[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_2 = _freeIdx_T_3[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_3 = _freeIdx_T_5[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_3 = _freeIdx_T_5[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_8 = _freeIdx_T_7[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_9 = {_freeIdx_T_6, _freeIdx_T_8}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_10 = {_freeIdx_T_4, _freeIdx_T_9}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_11 = {_freeIdx_T_2, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [4:0] freeIdx = {_freeIdx_T, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [35:0] valid_set; // @[ListBuffer.scala:57:30] wire [35:0] valid_clr; // @[ListBuffer.scala:58:30] wire [27:0] used_set; // @[ListBuffer.scala:59:30] wire [27:0] used_clr; // @[ListBuffer.scala:60:30] wire [35:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25] wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25] wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26] assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}] assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20] wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35] wire [63:0] _valid_set_T = 64'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [35:0] _valid_set_T_1 = _valid_set_T[35:0]; // @[OneHot.scala:65:{12,27}] assign valid_set = data_MPORT_en ? _valid_set_T_1 : 36'h0; // @[OneHot.scala:65:27] assign used_set = data_MPORT_en ? freeOH[27:0] : 28'h0; // @[Decoupled.scala:51:35] wire [35:0] _GEN = {30'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24] wire [35:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24] wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_55( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_55 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Pipeline.scala: package gemmini import chisel3._ import chisel3.util._ class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module { val io = IO(new Bundle { val in = Flipped(Decoupled(gen)) val out = Decoupled(gen) val busy = Output(Bool()) }) require(comb.size == latency+1, "length of combinational is incorrect") if (latency == 0) { io.in.ready := io.out.ready io.out.valid := io.in.valid io.out.bits := comb.head(io.in.bits) io.busy := io.in.valid } else { val stages = Reg(Vec(latency, gen)) val valids = RegInit(VecInit(Seq.fill(latency)(false.B))) val stalling = VecInit(Seq.fill(latency)(false.B)) io.busy := io.in.valid || valids.reduce(_||_) // Stall signals io.in.ready := !stalling.head stalling.last := valids.last && !io.out.ready (stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) => s1 := v1 && s2 } // Valid signals // When the pipeline stage ahead of you isn't stalling, then make yourself invalid io.out.valid := valids.last when(io.out.ready) { valids.last := false.B } (valids.init, stalling.tail).zipped.foreach { case (v1, s2) => when(!s2) { v1 := false.B } } // When the pipeline stage behind you is valid then become true when(io.in.fire) { valids.head := true.B } (valids.tail, valids.init).zipped.foreach { case (v2, v1) => when(v1) { v2 := true.B } } // Stages when(io.in.fire) { stages.head := comb.head(io.in.bits) } io.out.bits := comb.last(stages.last) ((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) => when(!s2) { st2 := c1(st1) } } } } object Pipeline { def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)(comb)) p.io.in <> in p.io.out } def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = { val p = Module(new Pipeline(in.bits.cloneType, latency)()) p.io.in <> in p.io.out } }
module Pipeline( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_0, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_1, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_2, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_3, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_4, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_5, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_6, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_7, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_8, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_9, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_10, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_11, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_12, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_13, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_14, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_out_15, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_row, // @[Pipeline.scala:7:14] input io_in_bits_last, // @[Pipeline.scala:7:14] input [511:0] io_in_bits_tag_data, // @[Pipeline.scala:7:14] input [13:0] io_in_bits_tag_addr, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_0, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_1, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_2, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_3, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_4, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_5, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_6, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_7, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_8, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_9, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_10, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_11, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_12, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_13, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_14, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_15, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_16, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_17, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_18, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_19, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_20, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_21, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_22, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_23, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_24, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_25, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_26, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_27, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_28, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_29, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_30, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_31, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_32, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_33, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_34, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_35, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_36, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_37, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_38, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_39, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_40, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_41, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_42, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_43, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_44, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_45, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_46, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_47, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_48, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_49, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_50, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_51, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_52, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_53, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_54, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_55, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_56, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_57, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_58, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_59, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_60, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_61, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_62, // @[Pipeline.scala:7:14] input io_in_bits_tag_mask_63, // @[Pipeline.scala:7:14] input io_in_bits_tag_is_acc, // @[Pipeline.scala:7:14] input io_in_bits_tag_accumulate, // @[Pipeline.scala:7:14] input io_in_bits_tag_has_acc_bitwidth, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_tag_scale, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_repeats, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_pixel_repeats, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_tag_len, // @[Pipeline.scala:7:14] input io_in_bits_tag_last, // @[Pipeline.scala:7:14] input [7:0] io_in_bits_tag_bytes_read, // @[Pipeline.scala:7:14] input [7:0] io_in_bits_tag_cmd_id, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_0, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_1, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_2, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_3, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_4, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_5, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_6, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_7, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_8, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_9, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_10, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_11, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_12, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_13, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_14, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_out_15, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_row, // @[Pipeline.scala:7:14] output io_out_bits_last, // @[Pipeline.scala:7:14] output [511:0] io_out_bits_tag_data, // @[Pipeline.scala:7:14] output [13:0] io_out_bits_tag_addr, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_0, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_1, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_2, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_3, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_4, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_5, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_6, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_7, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_8, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_9, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_10, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_11, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_12, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_13, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_14, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_15, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_16, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_17, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_18, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_19, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_20, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_21, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_22, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_23, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_24, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_25, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_26, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_27, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_28, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_29, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_30, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_31, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_32, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_33, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_34, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_35, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_36, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_37, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_38, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_39, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_40, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_41, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_42, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_43, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_44, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_45, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_46, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_47, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_48, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_49, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_50, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_51, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_52, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_53, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_54, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_55, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_56, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_57, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_58, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_59, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_60, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_61, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_62, // @[Pipeline.scala:7:14] output io_out_bits_tag_mask_63, // @[Pipeline.scala:7:14] output io_out_bits_tag_is_acc, // @[Pipeline.scala:7:14] output io_out_bits_tag_accumulate, // @[Pipeline.scala:7:14] output io_out_bits_tag_has_acc_bitwidth, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_tag_scale, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_repeats, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_pixel_repeats, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_tag_len, // @[Pipeline.scala:7:14] output io_out_bits_tag_last, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_tag_bytes_read, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_tag_cmd_id // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_0_0 = io_in_bits_out_0; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_1_0 = io_in_bits_out_1; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_2_0 = io_in_bits_out_2; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_3_0 = io_in_bits_out_3; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_4_0 = io_in_bits_out_4; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_5_0 = io_in_bits_out_5; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_6_0 = io_in_bits_out_6; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_7_0 = io_in_bits_out_7; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_8_0 = io_in_bits_out_8; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_9_0 = io_in_bits_out_9; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_10_0 = io_in_bits_out_10; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_11_0 = io_in_bits_out_11; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_12_0 = io_in_bits_out_12; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_13_0 = io_in_bits_out_13; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_14_0 = io_in_bits_out_14; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_out_15_0 = io_in_bits_out_15; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_row_0 = io_in_bits_row; // @[Pipeline.scala:6:7] wire io_in_bits_last_0 = io_in_bits_last; // @[Pipeline.scala:6:7] wire [511:0] io_in_bits_tag_data_0 = io_in_bits_tag_data; // @[Pipeline.scala:6:7] wire [13:0] io_in_bits_tag_addr_0 = io_in_bits_tag_addr; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_0_0 = io_in_bits_tag_mask_0; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_1_0 = io_in_bits_tag_mask_1; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_2_0 = io_in_bits_tag_mask_2; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_3_0 = io_in_bits_tag_mask_3; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_4_0 = io_in_bits_tag_mask_4; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_5_0 = io_in_bits_tag_mask_5; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_6_0 = io_in_bits_tag_mask_6; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_7_0 = io_in_bits_tag_mask_7; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_8_0 = io_in_bits_tag_mask_8; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_9_0 = io_in_bits_tag_mask_9; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_10_0 = io_in_bits_tag_mask_10; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_11_0 = io_in_bits_tag_mask_11; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_12_0 = io_in_bits_tag_mask_12; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_13_0 = io_in_bits_tag_mask_13; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_14_0 = io_in_bits_tag_mask_14; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_15_0 = io_in_bits_tag_mask_15; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_16_0 = io_in_bits_tag_mask_16; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_17_0 = io_in_bits_tag_mask_17; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_18_0 = io_in_bits_tag_mask_18; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_19_0 = io_in_bits_tag_mask_19; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_20_0 = io_in_bits_tag_mask_20; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_21_0 = io_in_bits_tag_mask_21; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_22_0 = io_in_bits_tag_mask_22; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_23_0 = io_in_bits_tag_mask_23; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_24_0 = io_in_bits_tag_mask_24; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_25_0 = io_in_bits_tag_mask_25; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_26_0 = io_in_bits_tag_mask_26; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_27_0 = io_in_bits_tag_mask_27; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_28_0 = io_in_bits_tag_mask_28; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_29_0 = io_in_bits_tag_mask_29; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_30_0 = io_in_bits_tag_mask_30; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_31_0 = io_in_bits_tag_mask_31; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_32_0 = io_in_bits_tag_mask_32; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_33_0 = io_in_bits_tag_mask_33; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_34_0 = io_in_bits_tag_mask_34; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_35_0 = io_in_bits_tag_mask_35; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_36_0 = io_in_bits_tag_mask_36; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_37_0 = io_in_bits_tag_mask_37; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_38_0 = io_in_bits_tag_mask_38; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_39_0 = io_in_bits_tag_mask_39; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_40_0 = io_in_bits_tag_mask_40; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_41_0 = io_in_bits_tag_mask_41; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_42_0 = io_in_bits_tag_mask_42; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_43_0 = io_in_bits_tag_mask_43; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_44_0 = io_in_bits_tag_mask_44; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_45_0 = io_in_bits_tag_mask_45; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_46_0 = io_in_bits_tag_mask_46; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_47_0 = io_in_bits_tag_mask_47; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_48_0 = io_in_bits_tag_mask_48; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_49_0 = io_in_bits_tag_mask_49; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_50_0 = io_in_bits_tag_mask_50; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_51_0 = io_in_bits_tag_mask_51; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_52_0 = io_in_bits_tag_mask_52; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_53_0 = io_in_bits_tag_mask_53; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_54_0 = io_in_bits_tag_mask_54; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_55_0 = io_in_bits_tag_mask_55; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_56_0 = io_in_bits_tag_mask_56; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_57_0 = io_in_bits_tag_mask_57; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_58_0 = io_in_bits_tag_mask_58; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_59_0 = io_in_bits_tag_mask_59; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_60_0 = io_in_bits_tag_mask_60; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_61_0 = io_in_bits_tag_mask_61; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_62_0 = io_in_bits_tag_mask_62; // @[Pipeline.scala:6:7] wire io_in_bits_tag_mask_63_0 = io_in_bits_tag_mask_63; // @[Pipeline.scala:6:7] wire io_in_bits_tag_is_acc_0 = io_in_bits_tag_is_acc; // @[Pipeline.scala:6:7] wire io_in_bits_tag_accumulate_0 = io_in_bits_tag_accumulate; // @[Pipeline.scala:6:7] wire io_in_bits_tag_has_acc_bitwidth_0 = io_in_bits_tag_has_acc_bitwidth; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_tag_scale_0 = io_in_bits_tag_scale; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_repeats_0 = io_in_bits_tag_repeats; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_pixel_repeats_0 = io_in_bits_tag_pixel_repeats; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_tag_len_0 = io_in_bits_tag_len; // @[Pipeline.scala:6:7] wire io_in_bits_tag_last_0 = io_in_bits_tag_last; // @[Pipeline.scala:6:7] wire [7:0] io_in_bits_tag_bytes_read_0 = io_in_bits_tag_bytes_read; // @[Pipeline.scala:6:7] wire [7:0] io_in_bits_tag_cmd_id_0 = io_in_bits_tag_cmd_id; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire io_out_valid_0 = io_in_valid_0; // @[Pipeline.scala:6:7] wire io_busy = io_in_valid_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_0_0 = io_in_bits_out_0_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_1_0 = io_in_bits_out_1_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_2_0 = io_in_bits_out_2_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_3_0 = io_in_bits_out_3_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_4_0 = io_in_bits_out_4_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_5_0 = io_in_bits_out_5_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_6_0 = io_in_bits_out_6_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_7_0 = io_in_bits_out_7_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_8_0 = io_in_bits_out_8_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_9_0 = io_in_bits_out_9_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_10_0 = io_in_bits_out_10_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_11_0 = io_in_bits_out_11_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_12_0 = io_in_bits_out_12_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_13_0 = io_in_bits_out_13_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_14_0 = io_in_bits_out_14_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_out_15_0 = io_in_bits_out_15_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_row_0 = io_in_bits_row_0; // @[Pipeline.scala:6:7] wire io_out_bits_last_0 = io_in_bits_last_0; // @[Pipeline.scala:6:7] wire [511:0] io_out_bits_tag_data_0 = io_in_bits_tag_data_0; // @[Pipeline.scala:6:7] wire [13:0] io_out_bits_tag_addr_0 = io_in_bits_tag_addr_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_0_0 = io_in_bits_tag_mask_0_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_1_0 = io_in_bits_tag_mask_1_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_2_0 = io_in_bits_tag_mask_2_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_3_0 = io_in_bits_tag_mask_3_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_4_0 = io_in_bits_tag_mask_4_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_5_0 = io_in_bits_tag_mask_5_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_6_0 = io_in_bits_tag_mask_6_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_7_0 = io_in_bits_tag_mask_7_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_8_0 = io_in_bits_tag_mask_8_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_9_0 = io_in_bits_tag_mask_9_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_10_0 = io_in_bits_tag_mask_10_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_11_0 = io_in_bits_tag_mask_11_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_12_0 = io_in_bits_tag_mask_12_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_13_0 = io_in_bits_tag_mask_13_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_14_0 = io_in_bits_tag_mask_14_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_15_0 = io_in_bits_tag_mask_15_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_16_0 = io_in_bits_tag_mask_16_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_17_0 = io_in_bits_tag_mask_17_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_18_0 = io_in_bits_tag_mask_18_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_19_0 = io_in_bits_tag_mask_19_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_20_0 = io_in_bits_tag_mask_20_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_21_0 = io_in_bits_tag_mask_21_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_22_0 = io_in_bits_tag_mask_22_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_23_0 = io_in_bits_tag_mask_23_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_24_0 = io_in_bits_tag_mask_24_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_25_0 = io_in_bits_tag_mask_25_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_26_0 = io_in_bits_tag_mask_26_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_27_0 = io_in_bits_tag_mask_27_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_28_0 = io_in_bits_tag_mask_28_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_29_0 = io_in_bits_tag_mask_29_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_30_0 = io_in_bits_tag_mask_30_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_31_0 = io_in_bits_tag_mask_31_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_32_0 = io_in_bits_tag_mask_32_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_33_0 = io_in_bits_tag_mask_33_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_34_0 = io_in_bits_tag_mask_34_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_35_0 = io_in_bits_tag_mask_35_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_36_0 = io_in_bits_tag_mask_36_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_37_0 = io_in_bits_tag_mask_37_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_38_0 = io_in_bits_tag_mask_38_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_39_0 = io_in_bits_tag_mask_39_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_40_0 = io_in_bits_tag_mask_40_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_41_0 = io_in_bits_tag_mask_41_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_42_0 = io_in_bits_tag_mask_42_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_43_0 = io_in_bits_tag_mask_43_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_44_0 = io_in_bits_tag_mask_44_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_45_0 = io_in_bits_tag_mask_45_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_46_0 = io_in_bits_tag_mask_46_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_47_0 = io_in_bits_tag_mask_47_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_48_0 = io_in_bits_tag_mask_48_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_49_0 = io_in_bits_tag_mask_49_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_50_0 = io_in_bits_tag_mask_50_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_51_0 = io_in_bits_tag_mask_51_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_52_0 = io_in_bits_tag_mask_52_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_53_0 = io_in_bits_tag_mask_53_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_54_0 = io_in_bits_tag_mask_54_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_55_0 = io_in_bits_tag_mask_55_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_56_0 = io_in_bits_tag_mask_56_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_57_0 = io_in_bits_tag_mask_57_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_58_0 = io_in_bits_tag_mask_58_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_59_0 = io_in_bits_tag_mask_59_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_60_0 = io_in_bits_tag_mask_60_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_61_0 = io_in_bits_tag_mask_61_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_62_0 = io_in_bits_tag_mask_62_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_mask_63_0 = io_in_bits_tag_mask_63_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_is_acc_0 = io_in_bits_tag_is_acc_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_accumulate_0 = io_in_bits_tag_accumulate_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_has_acc_bitwidth_0 = io_in_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_tag_scale_0 = io_in_bits_tag_scale_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_repeats_0 = io_in_bits_tag_repeats_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_pixel_repeats_0 = io_in_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_tag_len_0 = io_in_bits_tag_len_0; // @[Pipeline.scala:6:7] wire io_out_bits_tag_last_0 = io_in_bits_tag_last_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_tag_bytes_read_0 = io_in_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_tag_cmd_id_0 = io_in_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7] wire io_in_ready_0 = io_out_ready_0; // @[Pipeline.scala:6:7] assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_0 = io_out_bits_out_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_1 = io_out_bits_out_1_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_2 = io_out_bits_out_2_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_3 = io_out_bits_out_3_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_4 = io_out_bits_out_4_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_5 = io_out_bits_out_5_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_6 = io_out_bits_out_6_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_7 = io_out_bits_out_7_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_8 = io_out_bits_out_8_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_9 = io_out_bits_out_9_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_10 = io_out_bits_out_10_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_11 = io_out_bits_out_11_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_12 = io_out_bits_out_12_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_13 = io_out_bits_out_13_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_14 = io_out_bits_out_14_0; // @[Pipeline.scala:6:7] assign io_out_bits_out_15 = io_out_bits_out_15_0; // @[Pipeline.scala:6:7] assign io_out_bits_row = io_out_bits_row_0; // @[Pipeline.scala:6:7] assign io_out_bits_last = io_out_bits_last_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_data = io_out_bits_tag_data_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_addr = io_out_bits_tag_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_0 = io_out_bits_tag_mask_0_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_1 = io_out_bits_tag_mask_1_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_2 = io_out_bits_tag_mask_2_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_3 = io_out_bits_tag_mask_3_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_4 = io_out_bits_tag_mask_4_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_5 = io_out_bits_tag_mask_5_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_6 = io_out_bits_tag_mask_6_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_7 = io_out_bits_tag_mask_7_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_8 = io_out_bits_tag_mask_8_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_9 = io_out_bits_tag_mask_9_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_10 = io_out_bits_tag_mask_10_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_11 = io_out_bits_tag_mask_11_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_12 = io_out_bits_tag_mask_12_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_13 = io_out_bits_tag_mask_13_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_14 = io_out_bits_tag_mask_14_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_15 = io_out_bits_tag_mask_15_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_16 = io_out_bits_tag_mask_16_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_17 = io_out_bits_tag_mask_17_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_18 = io_out_bits_tag_mask_18_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_19 = io_out_bits_tag_mask_19_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_20 = io_out_bits_tag_mask_20_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_21 = io_out_bits_tag_mask_21_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_22 = io_out_bits_tag_mask_22_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_23 = io_out_bits_tag_mask_23_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_24 = io_out_bits_tag_mask_24_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_25 = io_out_bits_tag_mask_25_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_26 = io_out_bits_tag_mask_26_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_27 = io_out_bits_tag_mask_27_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_28 = io_out_bits_tag_mask_28_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_29 = io_out_bits_tag_mask_29_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_30 = io_out_bits_tag_mask_30_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_31 = io_out_bits_tag_mask_31_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_32 = io_out_bits_tag_mask_32_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_33 = io_out_bits_tag_mask_33_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_34 = io_out_bits_tag_mask_34_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_35 = io_out_bits_tag_mask_35_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_36 = io_out_bits_tag_mask_36_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_37 = io_out_bits_tag_mask_37_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_38 = io_out_bits_tag_mask_38_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_39 = io_out_bits_tag_mask_39_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_40 = io_out_bits_tag_mask_40_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_41 = io_out_bits_tag_mask_41_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_42 = io_out_bits_tag_mask_42_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_43 = io_out_bits_tag_mask_43_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_44 = io_out_bits_tag_mask_44_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_45 = io_out_bits_tag_mask_45_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_46 = io_out_bits_tag_mask_46_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_47 = io_out_bits_tag_mask_47_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_48 = io_out_bits_tag_mask_48_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_49 = io_out_bits_tag_mask_49_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_50 = io_out_bits_tag_mask_50_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_51 = io_out_bits_tag_mask_51_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_52 = io_out_bits_tag_mask_52_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_53 = io_out_bits_tag_mask_53_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_54 = io_out_bits_tag_mask_54_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_55 = io_out_bits_tag_mask_55_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_56 = io_out_bits_tag_mask_56_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_57 = io_out_bits_tag_mask_57_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_58 = io_out_bits_tag_mask_58_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_59 = io_out_bits_tag_mask_59_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_60 = io_out_bits_tag_mask_60_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_61 = io_out_bits_tag_mask_61_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_62 = io_out_bits_tag_mask_62_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_mask_63 = io_out_bits_tag_mask_63_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_is_acc = io_out_bits_tag_is_acc_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_accumulate = io_out_bits_tag_accumulate_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_has_acc_bitwidth = io_out_bits_tag_has_acc_bitwidth_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_scale = io_out_bits_tag_scale_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_repeats = io_out_bits_tag_repeats_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_pixel_repeats = io_out_bits_tag_pixel_repeats_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_len = io_out_bits_tag_len_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_last = io_out_bits_tag_last_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_bytes_read = io_out_bits_tag_bytes_read_0; // @[Pipeline.scala:6:7] assign io_out_bits_tag_cmd_id = io_out_bits_tag_cmd_id_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte || fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 | rocketParams.clockGate.toInt << 1 | rocketParams.clockGate.toInt << 2 | 1 << 3 | // disableSpeculativeICacheRefill haveDCache.toInt << 9 | // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb || take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal || (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') || id_ctrl.amo && !csr.io.status.isa('a'-'a') || id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) || (id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) || id_ctrl.dp && !csr.io.status.isa('d'-'a') || ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') || id_raddr2_illegal && id_ctrl.rxs2 || id_raddr1_illegal && id_ctrl.rxs1 || id_waddr_illegal && id_ctrl.wxd || id_ctrl.rocc && csr.io.decode(0).rocc_illegal || id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) || !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) || (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc || mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) || id_vec_busy && id_ctrl.fence || id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_||_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn || id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready || ex_ctrl.div && !div.io.req.ready || ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack || wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen || ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr || wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr || tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem || io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) || (mem_reg_valid && mem_reg_set_vconfig) || (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked) val ctrl_stalld = id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || id_vconfig_hazard || csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) || id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy || id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy || id_ctrl.fp && id_stall_fpu || id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay !clock_en || id_do_fence || csr.io.csr_stall || id_reg_pause || io.traceStall ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight io.ptw.customCSRs.disableCoreClockGate || // chicken bit !div.io.req.ready || // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight io.dmem.replay_next || // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_||_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens || en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S || sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } } File Configs.scala: package saturn.rocket import chisel3._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile._ import freechips.rocketchip.diplomacy._ import saturn.common._ import saturn.frontend.{EarlyVectorDecode} class WithRocketVectorUnit( vLen: Int = 128, dLen: Int = 64, params: VectorParams = VectorParams(), cores: Option[Seq[Int]] = None, useL1DCache: Boolean = true) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => { val buildVector = cores.map(_.contains(tp.tileParams.tileId)).getOrElse(true) if (buildVector) tp.copy(tileParams = tp.tileParams.copy( core = tp.tileParams.core.copy( vector = Some(RocketCoreVectorParams( build = ((p: Parameters) => new SaturnRocketUnit()(p.alterPartial { case VectorParamsKey => params.copy(dLen=dLen) })), vLen = vLen, vfLen = 64, vfh = true, eLen = 64, vMemDataBits = if (useL1DCache) dLen else 0, decoder = ((p: Parameters) => { val decoder = Module(new EarlyVectorDecode(params.supported_ex_insns)(p)) decoder }), useDCache = true, issueVConfig = false, vExts = Seq("zvbb") )), fpu = (if (params.useScalarFPFMA || params.useScalarFPMisc) { tp.tileParams.core.fpu.map(_.copy( sfmaLatency = params.fmaPipeDepth - 1, dfmaLatency = params.fmaPipeDepth - 1, ifpuLatency = params.fmaPipeDepth - 1, fpmuLatency = params.fmaPipeDepth - 1, )) } else { tp.tileParams.core.fpu }).map(_.copy(minFLen = 16)) ), dcache = if (useL1DCache) tp.tileParams.dcache.map(_.copy(rowBits = dLen)) else tp.tileParams.dcache )) else tp } case other => other } }) File DebugROB.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.{IntParam} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{HasCoreParameters} import freechips.rocketchip.util.DecoupledHelper case class DebugROBParams(size: Int) class WidenedTracedInstruction extends Bundle { val valid = Bool() val iaddr = UInt(64.W) val insn = UInt(64.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(64.W) val tval = UInt(64.W) val wdata = UInt(512.W) } // "DebugROB" classes provide an in-order commit log // with wdata populated. // These is not synthesizable, they use a C++ blackbox to implement the // write-back reordering class DebugROBPushTrace(implicit val p: Parameters) extends BlackBox with HasBlackBoxResource with HasCoreParameters { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val hartid = Input(UInt(32.W)) val should_wb = Input(Bool()) val has_wb = Input(Bool()) val wb_tag = Input(UInt(64.W)) val trace = Input(new WidenedTracedInstruction) }) addResource("/csrc/debug_rob.cc") addResource("/vsrc/debug_rob.v") } class DebugROBPushWb(implicit val p: Parameters) extends BlackBox with HasBlackBoxResource with HasCoreParameters { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val hartid = Input(UInt(32.W)) val valid = Input(Bool()) val wb_tag = Input(UInt(64.W)) val wb_data = Input(UInt(512.W)) }) addResource("/csrc/debug_rob.cc") addResource("/vsrc/debug_rob.v") } class DebugROBPopTrace(implicit val p: Parameters) extends BlackBox with HasBlackBoxResource with HasCoreParameters { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val hartid = Input(UInt(32.W)) val trace = Output(new WidenedTracedInstruction) }) addResource("/csrc/debug_rob.cc") addResource("/vsrc/debug_rob.v") } object DebugROB { def pushTrace(clock: Clock, reset: Reset, hartid: UInt, trace: TracedInstruction, should_wb: Bool, has_wb: Bool, wb_tag: UInt)(implicit p: Parameters) = { val debug_rob_push_trace = Module(new DebugROBPushTrace) debug_rob_push_trace.io.clock := clock debug_rob_push_trace.io.reset := reset debug_rob_push_trace.io.hartid := hartid debug_rob_push_trace.io.should_wb := should_wb debug_rob_push_trace.io.has_wb := has_wb debug_rob_push_trace.io.wb_tag := wb_tag debug_rob_push_trace.io.trace := trace } def popTrace(clock: Clock, reset: Reset, hartid: UInt)(implicit p: Parameters): TracedInstruction = { val debug_rob_pop_trace = Module(new DebugROBPopTrace) debug_rob_pop_trace.io.clock := clock debug_rob_pop_trace.io.reset := reset debug_rob_pop_trace.io.hartid := hartid val trace = Wire(new TracedInstruction) trace := debug_rob_pop_trace.io.trace trace } def pushWb(clock: Clock, reset: Reset, hartid: UInt, valid: Bool, tag: UInt, data: UInt)(implicit p: Parameters) { val debug_rob_push_wb = Module(new DebugROBPushWb) debug_rob_push_wb.io.clock := clock debug_rob_push_wb.io.reset := reset debug_rob_push_wb.io.hartid := hartid debug_rob_push_wb.io.valid := valid debug_rob_push_wb.io.wb_tag := tag debug_rob_push_wb.io.wb_data := data } } class TaggedInstruction(val nXPR: Int)(implicit val p: Parameters) extends Bundle { val insn = new TracedInstruction val tag = UInt(log2Up(nXPR + 1).W) val waiting = Bool() } class TaggedWbData(implicit val p: Parameters) extends Bundle with HasCoreParameters { val valid = Bool() val data = UInt(xLen.W) } class HardDebugROB(val traceRatio: Int, val nXPR: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { val io = IO(new Bundle { val i_insn = Input(new TracedInstruction) val should_wb = Input(Bool()) val has_wb = Input(Bool()) val tag = Input(UInt(log2Up(nXPR + 1).W)) val wb_val = Input(Bool()) val wb_tag = Input(UInt(log2Up(nXPR + 1).W)) val wb_data = Input(UInt(xLen.W)) val o_insn = Output(new TracedInstruction) }) val iq = Module(new Queue(new TaggedInstruction(nXPR), traceRatio * nXPR, flow = true)) // No backpressure assert(iq.io.enq.ready) iq.io.enq.valid := io.i_insn.valid || io.i_insn.exception || io.i_insn.interrupt iq.io.enq.bits.insn := io.i_insn iq.io.enq.bits.tag := io.tag iq.io.enq.bits.waiting := io.should_wb && !io.has_wb val wb_q = Seq.fill(nXPR)(Reg(new TaggedWbData)) for (i <- 0 until nXPR) { when (io.wb_val && i.U === io.wb_tag) { assert(wb_q(i).valid === false.B) wb_q(i).valid := true.B wb_q(i).data := io.wb_data } } val tag_matches = Seq.fill(nXPR)(Wire(Bool())) for (i <- 0 until nXPR) { val is_match = iq.io.deq.bits.waiting && (iq.io.deq.bits.tag === i.U) && wb_q(i).valid when (is_match) { tag_matches(i) := true.B } .otherwise { tag_matches(i) := false.B } } val tag_match = tag_matches.reduce(_ || _) val vinsn_rdy = !iq.io.deq.bits.waiting || (iq.io.deq.bits.tag >= nXPR.U) || // not integer instruction tag_match val maybeFire = Mux(iq.io.deq.bits.insn.valid, vinsn_rdy, true.B) val fireTrace = DecoupledHelper( iq.io.deq.valid, maybeFire) iq.io.deq.ready := fireTrace.fire(iq.io.deq.valid) io.o_insn := iq.io.deq.bits.insn io.o_insn.valid := iq.io.deq.fire && iq.io.deq.bits.insn.valid for (i <- 0 until nXPR) { when (tag_match && fireTrace.fire() && i.U === iq.io.deq.bits.tag) { io.o_insn.wdata.get := wb_q(i).data wb_q(i).valid := false.B } } val qcnt = RegInit(0.U(64.W)) when (iq.io.enq.fire && !iq.io.deq.fire) { qcnt := qcnt + 1.U } .elsewhen (!iq.io.enq.fire && iq.io.deq.fire) { qcnt := qcnt - 1.U } .otherwise { qcnt := qcnt } }
module Rocket( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [7:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [7:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_store_pending, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output io_fpu_hartid, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] output [2:0] io_fpu_v_sew, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_trace_insns_0_valid, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14] output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14] output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14] output io_trace_insns_0_exception, // @[RocketCore.scala:134:14] output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14] output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14] output [127:0] io_trace_insns_0_wdata, // @[RocketCore.scala:134:14] output [63:0] io_trace_time, // @[RocketCore.scala:134:14] output io_wfi, // @[RocketCore.scala:134:14] output io_vector_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_vector_status_prv, // @[RocketCore.scala:134:14] output io_vector_ex_valid, // @[RocketCore.scala:134:14] input io_vector_ex_ready, // @[RocketCore.scala:134:14] output [31:0] io_vector_ex_inst, // @[RocketCore.scala:134:14] output [39:0] io_vector_ex_pc, // @[RocketCore.scala:134:14] output [7:0] io_vector_ex_vconfig_vl, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vill, // @[RocketCore.scala:134:14] output [54:0] io_vector_ex_vconfig_vtype_reserved, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vma, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vta, // @[RocketCore.scala:134:14] output [2:0] io_vector_ex_vconfig_vtype_vsew, // @[RocketCore.scala:134:14] output io_vector_ex_vconfig_vtype_vlmul_sign, // @[RocketCore.scala:134:14] output [1:0] io_vector_ex_vconfig_vtype_vlmul_mag, // @[RocketCore.scala:134:14] output [6:0] io_vector_ex_vstart, // @[RocketCore.scala:134:14] output [63:0] io_vector_ex_rs1, // @[RocketCore.scala:134:14] output [63:0] io_vector_ex_rs2, // @[RocketCore.scala:134:14] output io_vector_killm, // @[RocketCore.scala:134:14] output [63:0] io_vector_mem_frs1, // @[RocketCore.scala:134:14] input io_vector_mem_block_mem, // @[RocketCore.scala:134:14] input io_vector_mem_block_all, // @[RocketCore.scala:134:14] output io_vector_wb_store_pending, // @[RocketCore.scala:134:14] input io_vector_wb_replay, // @[RocketCore.scala:134:14] input io_vector_wb_retire, // @[RocketCore.scala:134:14] input [31:0] io_vector_wb_inst, // @[RocketCore.scala:134:14] input io_vector_wb_rob_should_wb, // @[RocketCore.scala:134:14] input io_vector_wb_rob_should_wb_fp, // @[RocketCore.scala:134:14] input [39:0] io_vector_wb_pc, // @[RocketCore.scala:134:14] input io_vector_wb_xcpt, // @[RocketCore.scala:134:14] input [4:0] io_vector_wb_cause, // @[RocketCore.scala:134:14] input [39:0] io_vector_wb_tval, // @[RocketCore.scala:134:14] output [1:0] io_vector_wb_vxrm, // @[RocketCore.scala:134:14] output [2:0] io_vector_wb_frm, // @[RocketCore.scala:134:14] output io_vector_resp_ready, // @[RocketCore.scala:134:14] input io_vector_resp_valid, // @[RocketCore.scala:134:14] input io_vector_resp_bits_fp, // @[RocketCore.scala:134:14] input [1:0] io_vector_resp_bits_size, // @[RocketCore.scala:134:14] input [4:0] io_vector_resp_bits_rd, // @[RocketCore.scala:134:14] input [63:0] io_vector_resp_bits_data, // @[RocketCore.scala:134:14] input io_vector_set_vstart_valid, // @[RocketCore.scala:134:14] input [6:0] io_vector_set_vstart_bits, // @[RocketCore.scala:134:14] input io_vector_set_vxsat, // @[RocketCore.scala:134:14] input io_vector_set_vconfig_valid, // @[RocketCore.scala:134:14] input [7:0] io_vector_set_vconfig_bits_vl, // @[RocketCore.scala:134:14] input io_vector_set_vconfig_bits_vtype_vill, // @[RocketCore.scala:134:14] input [54:0] io_vector_set_vconfig_bits_vtype_reserved, // @[RocketCore.scala:134:14] input io_vector_set_vconfig_bits_vtype_vma, // @[RocketCore.scala:134:14] input io_vector_set_vconfig_bits_vtype_vta, // @[RocketCore.scala:134:14] input [2:0] io_vector_set_vconfig_bits_vtype_vsew, // @[RocketCore.scala:134:14] input io_vector_set_vconfig_bits_vtype_vlmul_sign, // @[RocketCore.scala:134:14] input [1:0] io_vector_set_vconfig_bits_vtype_vlmul_mag, // @[RocketCore.scala:134:14] input io_vector_trap_check_busy, // @[RocketCore.scala:134:14] input io_vector_backend_busy // @[RocketCore.scala:134:14] ); wire io_dmem_req_valid_0; // @[RocketCore.scala:1130:41] wire wb_xcpt; // @[RocketCore.scala:875:52, :879:40, :880:17, :1278:{14,35}] wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire take_pc_wb; // @[RocketCore.scala:762:{27,38,53}] wire take_pc_mem; // @[RocketCore.scala:629:{32,49}] wire [2:0] id_ctrl_csr; // @[RocketCore.scala:354:30, :371:19] wire [63:0] _io_trace_insns_0_debug_rob_pop_trace_trace_iaddr; // @[DebugROB.scala:85:37] wire [63:0] _io_trace_insns_0_debug_rob_pop_trace_trace_insn; // @[DebugROB.scala:85:37] wire [63:0] _io_trace_insns_0_debug_rob_pop_trace_trace_tval; // @[DebugROB.scala:85:37] wire [511:0] _io_trace_insns_0_debug_rob_pop_trace_trace_wdata; // @[DebugROB.scala:85:37] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_in_2_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [63:0] _ll_arb_io_out_bits_data; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_out; // @[RocketCore.scala:504:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire _v_decode_io_legal; // @[Configs.scala:33:35] wire _v_decode_io_fp; // @[Configs.scala:33:35] wire _v_decode_io_read_rs1; // @[Configs.scala:33:35] wire _v_decode_io_read_rs2; // @[Configs.scala:33:35] wire _v_decode_io_read_frs1; // @[Configs.scala:33:35] wire _v_decode_io_write_rd; // @[Configs.scala:33:35] wire _v_decode_io_write_frd; // @[Configs.scala:33:35] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_vector_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_vector_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_fcsr_rm; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_trace_0_cause; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_tval; // @[RocketCore.scala:341:19] wire [7:0] _csr_io_vector_vconfig_vl; // @[RocketCore.scala:341:19] wire _csr_io_vector_vconfig_vtype_vill; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_vector_vconfig_vtype_vsew; // @[RocketCore.scala:341:19] wire [6:0] _csr_io_vector_vstart; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_customCSRs_0_value; // @[RocketCore.scala:341:19] wire [63:0] _rf_ext_R0_data; // @[RocketCore.scala:1319:15] wire [63:0] _rf_ext_R1_data; // @[RocketCore.scala:1319:15] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs3; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg ex_ctrl_vec; // @[RocketCore.scala:243:20] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg ex_reg_set_vconfig; // @[RocketCore.scala:262:36] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_mem_cmd_bh; // @[RocketCore.scala:272:36] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] reg [71:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] reg [71:0] wb_reg_rs2; // @[RocketCore.scala:303:23] wire ibuf_io_kill = take_pc_wb | take_pc_mem; // @[RocketCore.scala:307:35, :629:{32,49}, :762:{27,38,53}] wire [29:0] id_ctrl_decoder_decoded_invInputs = ~(_ibuf_io_inst_0_bits_inst_bits[31:2]); // @[pla.scala:78:21] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[11]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[13]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[14]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12], _ibuf_io_inst_0_bits_inst_bits[13], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[20], _ibuf_io_inst_0_bits_inst_bits[21], _ibuf_io_inst_0_bits_inst_bits[22], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[3], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[20], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], _ibuf_io_inst_0_bits_inst_bits[26], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], _ibuf_io_inst_0_bits_inst_bits[23], _ibuf_io_inst_0_bits_inst_bits[24], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12], _ibuf_io_inst_0_bits_inst_bits[13], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], _ibuf_io_inst_0_bits_inst_bits[12], _ibuf_io_inst_0_bits_inst_bits[13], _ibuf_io_inst_0_bits_inst_bits[14], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_195 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_196 = {_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] reg id_reg_fence; // @[RocketCore.scala:333:29] wire _id_csr_ren_T = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire id_csr_en = _id_csr_ren_T | (&id_ctrl_csr) | id_ctrl_csr == 3'h5; // @[package.scala:16:47, :81:59] wire id_ctrl_fp = _v_decode_io_legal ? _v_decode_io_fp : (|{&_id_ctrl_decoder_decoded_andMatrixOutputs_T_17, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[12]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[13], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[18], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[30], _ibuf_io_inst_0_bits_inst_bits[31]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] wire id_ctrl_rxs2 = _v_decode_io_legal ? _v_decode_io_read_rs2 : (|{&_id_ctrl_decoder_decoded_andMatrixOutputs_T_9, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[14], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] wire id_ctrl_rxs1 = _v_decode_io_legal ? _v_decode_io_read_rs1 : (|{&_id_ctrl_decoder_decoded_andMatrixOutputs_T, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_195, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_196}); // @[pla.scala:98:{53,70}, :114:{19,36}] wire id_ctrl_mem = ~_v_decode_io_legal & (|{&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] wire id_ctrl_div = ~_v_decode_io_legal & (|{&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] wire id_ctrl_wxd = _v_decode_io_legal ? _v_decode_io_write_rd : (|{&_id_ctrl_decoder_decoded_andMatrixOutputs_T, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], id_ctrl_decoder_decoded_invInputs[12]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], id_ctrl_decoder_decoded_invInputs[0], id_ctrl_decoder_decoded_invInputs[1], _ibuf_io_inst_0_bits_inst_bits[4], id_ctrl_decoder_decoded_invInputs[3], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], _ibuf_io_inst_0_bits_inst_bits[29], id_ctrl_decoder_decoded_invInputs[28], _ibuf_io_inst_0_bits_inst_bits[31]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign id_ctrl_csr = _v_decode_io_legal ? 3'h0 : {|{&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[19], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], id_ctrl_decoder_decoded_invInputs[26], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &{_ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], _ibuf_io_inst_0_bits_inst_bits[20], id_ctrl_decoder_decoded_invInputs[19], _ibuf_io_inst_0_bits_inst_bits[22], id_ctrl_decoder_decoded_invInputs[21], id_ctrl_decoder_decoded_invInputs[22], id_ctrl_decoder_decoded_invInputs[23], id_ctrl_decoder_decoded_invInputs[24], id_ctrl_decoder_decoded_invInputs[25], _ibuf_io_inst_0_bits_inst_bits[28], id_ctrl_decoder_decoded_invInputs[27], id_ctrl_decoder_decoded_invInputs[28], id_ctrl_decoder_decoded_invInputs[29]}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102, &{_ibuf_io_inst_0_bits_inst_bits[4], _ibuf_io_inst_0_bits_inst_bits[5], _ibuf_io_inst_0_bits_inst_bits[6], id_ctrl_decoder_decoded_invInputs[5], id_ctrl_decoder_decoded_invInputs[6], id_ctrl_decoder_decoded_invInputs[7], id_ctrl_decoder_decoded_invInputs[8], id_ctrl_decoder_decoded_invInputs[9], id_ctrl_decoder_decoded_invInputs[10], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12], id_ctrl_decoder_decoded_invInputs[13], id_ctrl_decoder_decoded_invInputs[14], id_ctrl_decoder_decoded_invInputs[15], id_ctrl_decoder_decoded_invInputs[16], id_ctrl_decoder_decoded_invInputs[17], id_ctrl_decoder_decoded_invInputs[18], _ibuf_io_inst_0_bits_inst_bits[21], id_ctrl_decoder_decoded_invInputs[20], id_ctrl_decoder_decoded_invInputs[21], _ibuf_io_inst_0_bits_inst_bits[24], _ibuf_io_inst_0_bits_inst_bits[25], id_ctrl_decoder_decoded_invInputs[24], _ibuf_io_inst_0_bits_inst_bits[27], _ibuf_io_inst_0_bits_inst_bits[28], _ibuf_io_inst_0_bits_inst_bits[29], _ibuf_io_inst_0_bits_inst_bits[30], id_ctrl_decoder_decoded_invInputs[29]}}, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] wire id_ctrl_fence_i = ~_v_decode_io_legal & (&{_ibuf_io_inst_0_bits_inst_bits[0], _ibuf_io_inst_0_bits_inst_bits[1], _ibuf_io_inst_0_bits_inst_bits[2], _ibuf_io_inst_0_bits_inst_bits[3], id_ctrl_decoder_decoded_invInputs[2], id_ctrl_decoder_decoded_invInputs[3], id_ctrl_decoder_decoded_invInputs[4], _ibuf_io_inst_0_bits_inst_bits[12], id_ctrl_decoder_decoded_invInputs[11], id_ctrl_decoder_decoded_invInputs[12]}); // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] wire id_ctrl_fence = ~_v_decode_io_legal & (&_id_ctrl_decoder_decoded_andMatrixOutputs_T_5); // @[pla.scala:98:{53,70}] wire id_ctrl_amo = ~_v_decode_io_legal & (|{&_id_ctrl_decoder_decoded_andMatrixOutputs_T_52, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91, &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96}); // @[pla.scala:98:{53,70}, :114:{19,36}] wire id_mem_busy = ~io_dmem_ordered | io_dmem_req_valid_0; // @[RocketCore.scala:403:{21,38}, :1130:41] wire _io_rocc_cmd_valid_T = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire id_vec_busy = io_vector_backend_busy | io_vector_trap_check_busy; // @[RocketCore.scala:409:55] wire bypass_sources_3_1 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _fp_data_hazard_ex_T_1 = ex_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:259:24, :311:20, :453:29, :461:82] wire _fp_data_hazard_mem_T_1 = mem_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:278:25, :311:20, :454:31, :461:82] wire _fp_data_hazard_ex_T_3 = ex_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:259:24, :311:20, :453:29, :461:82] wire _fp_data_hazard_mem_T_3 = mem_reg_inst[11:7] == _ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala:278:25, :311:20, :454:31, :461:82] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire [3:0][63:0] _GEN = {{io_dmem_resp_bits_data_word_bypass}, {wb_reg_wdata}, {mem_reg_wdata}, {64'h0}}; // @[package.scala:39:{76,86}] wire [63:0] ex_rs_0 = ex_reg_rs_bypass_0 ? _GEN[ex_reg_rs_lsb_0] : {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[package.scala:39:{76,86}] wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _GEN[ex_reg_rs_lsb_1] : {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[package.scala:39:{76,86}] wire _ex_imm_b0_T_4 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire ex_imm_sign = ~_ex_imm_b0_T_4 & ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:{19,24,44}] wire _ex_imm_b4_1_T = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b4_1_T_2 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b0_T = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire [66:0] ex_rs1shl = {3'h0, ex_reg_inst[3] ? {32'h0, ex_rs_0[31:0]} : ex_rs_0} << ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :469:14, :471:{22,34,47,65,79}] wire [3:0][63:0] _GEN_0 = {{ex_rs1shl[63:0]}, {{{24{ex_reg_pc[39]}}, ex_reg_pc}}, {ex_rs_0}, {64'h0}}; // @[RocketCore.scala:256:22, :469:14, :471:65, :472:48] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire div_io_req_valid = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire ex_pc_valid = ex_reg_valid | ex_reg_replay | ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :248:35, :255:26, :595:{34,51}] wire wb_dcache_miss = wb_ctrl_mem & ~io_dmem_resp_valid; // @[RocketCore.scala:245:20, :596:{36,39}] wire replay_ex = ex_reg_replay | ex_reg_valid & (ex_ctrl_mem & ~io_dmem_req_ready | ex_ctrl_div & ~_div_io_req_ready | ex_ctrl_vec & ~io_vector_ex_ready | wb_dcache_miss & ex_reg_load_use); // @[RocketCore.scala:243:20, :248:35, :253:35, :255:26, :511:19, :596:36, :597:{42,45,64}, :598:{42,45,63}, :599:{42,45}, :600:43, :601:{33,50,75}] wire ctrl_killx = ibuf_io_kill | replay_ex | ~ex_reg_valid; // @[RocketCore.scala:248:35, :307:35, :601:33, :602:{35,48,51}] wire _mem_cfi_taken_T = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_8 = _mem_cfi_taken_T ? {{20{mem_reg_inst[31]}}, mem_reg_inst[7], mem_reg_inst[30:25], mem_reg_inst[11:8], 1'h0} : mem_ctrl_jal ? {{12{mem_reg_inst[31]}}, mem_reg_inst[19:12], mem_reg_inst[20], mem_reg_inst[30:21], 1'h0} : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :278:25, :616:{8,25}, :617:8, :618:8, :1341:44, :1343:65, :1345:39, :1346:39, :1347:62, :1349:57, :1355:8] wire [39:0] _mem_br_target_T_9 = mem_reg_pc + {{8{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:277:23, :615:41, :616:8] wire [39:0] _mem_npc_T_4 = mem_ctrl_jalr | mem_reg_sfence ? {mem_reg_wdata[63:39] == 25'h0 | (&(mem_reg_wdata[63:39])) ? mem_reg_wdata[39] : ~(mem_reg_wdata[38]), mem_reg_wdata[38:0]} : _mem_br_target_T_9; // @[RocketCore.scala:244:21, :276:27, :282:26, :615:41, :619:{21,36}, :1293:{17,23}, :1294:{18,21,29,34,46,51,54}, :1295:{8,16}] wire [39:0] mem_npc = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire mem_wrong_npc = ex_pc_valid ? mem_npc != ex_reg_pc : ~(_ibuf_io_inst_0_valid | io_imem_resp_valid) | mem_npc != _ibuf_io_pc; // @[RocketCore.scala:256:22, :311:20, :595:{34,51}, :619:129, :621:{8,30}, :622:{8,31,62}] wire mem_cfi = mem_ctrl_branch | mem_ctrl_jalr | mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign take_pc_mem = mem_reg_valid & ~mem_reg_xcpt & (mem_wrong_npc | mem_reg_sfence); // @[RocketCore.scala:265:36, :268:36, :276:27, :621:8, :624:27, :629:{32,49,71}] wire mem_debug_breakpoint = mem_reg_load & _bpu_io_debug_ld | mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:273:36, :274:36, :414:19, :678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint | mem_reg_load & _bpu_io_xcpt_ld | mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:273:36, :274:36, :414:19, :677:{38,57,75}, :678:64, :1278:35] wire dcache_kill_mem = bypass_sources_3_1 & io_dmem_replay_next; // @[RocketCore.scala:459:20, :695:55] wire fpu_kill_mem = mem_reg_valid & mem_ctrl_fp & io_fpu_nack_mem; // @[RocketCore.scala:244:21, :265:36, :696:{36,51}] wire vec_kill_mem = mem_reg_valid & mem_ctrl_mem & io_vector_mem_block_mem; // @[RocketCore.scala:244:21, :265:36, :697:{36,52}] wire killm_common = dcache_kill_mem | take_pc_wb | mem_reg_xcpt | ~mem_reg_valid; // @[RocketCore.scala:265:36, :268:36, :695:55, :700:{38,52,68,71}, :762:{27,38,53}] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _GEN_1 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _GEN_2 = _GEN_1 & io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:730:{19,34}] wire _GEN_3 = _GEN_1 & io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:730:19, :731:34] wire _GEN_4 = _GEN_1 & io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:730:19, :734:34] wire _GEN_5 = _GEN_1 & io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:730:19, :735:34] wire _GEN_6 = _GEN_1 & io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:730:19, :736:34] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire wb_set_sboard = wb_ctrl_div | wb_dcache_miss | wb_ctrl_rocc | wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :756:{35,53,69}] wire replay_wb_common = io_dmem_s2_nack | wb_reg_replay; // @[RocketCore.scala:290:35, :757:42] wire replay_wb = replay_wb_common | _io_rocc_cmd_valid_T | wb_reg_valid & io_vector_wb_replay; // @[RocketCore.scala:288:35, :407:53, :757:42, :760:36, :761:{36,71}] assign take_pc_wb = replay_wb | wb_xcpt | _csr_io_eret | wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :341:19, :761:{36,71}, :762:{27,38,53}, :875:52, :879:40, :880:17, :1278:{14,35}] wire dmem_resp_valid = io_dmem_resp_valid & io_dmem_resp_bits_has_data; // @[RocketCore.scala:768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay; // @[RocketCore.scala:768:44, :769:42] wire _io_fpu_ll_resp_val_T = dmem_resp_valid & io_dmem_resp_bits_tag[0]; // @[RocketCore.scala:765:45, :768:44, :801:59] wire io_vector_resp_ready_0 = io_vector_resp_bits_fp ? ~_io_fpu_ll_resp_val_T : _ll_arb_io_in_2_ready; // @[RocketCore.scala:776:22, :801:{24,41,59}] wire _GEN_7 = dmem_resp_replay & ~(io_dmem_resp_bits_tag[0]); // @[RocketCore.scala:765:{23,45}, :769:42, :809:26] assign ll_arb_io_out_ready = ~_GEN_7 & ~wb_wxd; // @[RocketCore.scala:755:29, :782:{23,26}, :809:{26,44}, :810:25] wire [4:0] ll_waddr = _GEN_7 ? io_dmem_resp_bits_tag[5:1] : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] wire ll_wen = _GEN_7 | ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire wb_valid = wb_reg_valid & ~replay_wb & ~wb_xcpt; // @[RocketCore.scala:288:35, :761:{36,71}, :815:{31,34,45,48}, :875:52, :879:40, :880:17, :1278:{14,35}] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:{31,45}, :816:25] wire rf_wen = wb_wen | ll_wen; // @[RocketCore.scala:781:24, :809:44, :812:12, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29, :780:26, :781:24, :809:44, :811:14, :812:12, :818:21] wire [63:0] rf_wdata = dmem_resp_valid & ~(io_dmem_resp_bits_tag[0]) ? io_dmem_resp_bits_data : ll_wen ? _ll_arb_io_out_bits_data : (|wb_ctrl_csr) ? _csr_io_rw_rdata : wb_reg_wdata; // @[RocketCore.scala:245:20, :302:25, :341:19, :765:{23,45}, :768:44, :776:22, :781:24, :809:44, :812:12, :819:{21,38}, :820:21, :821:{21,34}] wire [63:0] id_rs_0 = rf_wen & (|rf_waddr) & rf_waddr == _ibuf_io_inst_0_bits_inst_rs1 ? rf_wdata : _rf_ext_R1_data; // @[RocketCore.scala:311:20, :817:23, :818:21, :819:21, :824:17, :1319:15, :1326:19, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] id_rs_1 = rf_wen & (|rf_waddr) & rf_waddr == _ibuf_io_inst_0_bits_inst_rs2 ? rf_wdata : _rf_ext_R0_data; // @[RocketCore.scala:311:20, :817:23, :818:21, :819:21, :824:17, :1319:15, :1326:19, :1331:{16,25}, :1334:{20,31,39}] wire _htval_valid_imem_T = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire tval_any_addr = ~wb_reg_xcpt | wb_reg_cause == 64'h3 | wb_reg_cause == 64'h1 | wb_reg_cause == 64'hC | _htval_valid_imem_T; // @[package.scala:16:47, :81:59] wire _id_vconfig_hazard_T_3 = wb_reg_set_vconfig & wb_reg_valid; // @[RocketCore.scala:288:35, :293:35, :867:47] wire _GEN_8 = io_vector_wb_retire | io_vector_wb_xcpt | wb_ctrl_vec; // @[RocketCore.scala:245:20, :875:{23,36}] wire _GEN_9 = _GEN_8 & io_vector_wb_xcpt & ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24, :875:{23,36,52}, :879:{23,40}, :880:17, :1278:14] assign wb_xcpt = _GEN_9 | wb_reg_xcpt | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_1 & io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :875:52, :879:{23,40}, :880:17, :1278:{14,35}] wire [31:0] _GEN_10 = {31'h0, io_hartid}; // @[DebugROB.scala:77:36] wire hazard_targets_0_1 = id_ctrl_rxs1 & (|_ibuf_io_inst_0_bits_inst_rs1); // @[RocketCore.scala:311:20, :354:30, :362:20, :969:{42,55}] wire hazard_targets_1_1 = id_ctrl_rxs2 & (|_ibuf_io_inst_0_bits_inst_rs2); // @[RocketCore.scala:311:20, :354:30, :361:20, :970:{42,55}] wire hazard_targets_2_1 = id_ctrl_wxd & (|_ibuf_io_inst_0_bits_inst_rd); // @[RocketCore.scala:311:20, :354:30, :370:19, :971:{42,55}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [31:0] r = {_r[31:1], 1'h0}; // @[RocketCore.scala:1305:29, :1306:{35,40}] wire [31:0] _GEN_11 = {27'h0, _ibuf_io_inst_0_bits_inst_rs1}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_11; // @[RocketCore.scala:1302:35, :1306:40] wire [31:0] _GEN_12 = {27'h0, _ibuf_io_inst_0_bits_inst_rs2}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_12; // @[RocketCore.scala:1302:35, :1306:40] wire [31:0] _GEN_13 = {27'h0, _ibuf_io_inst_0_bits_inst_rd}; // @[RocketCore.scala:311:20, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_13; // @[RocketCore.scala:1302:35, :1306:40] wire _fp_data_hazard_ex_T_7 = _ibuf_io_inst_0_bits_inst_rd == ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :311:20, :453:29, :989:70] wire _fp_data_hazard_mem_T_7 = _ibuf_io_inst_0_bits_inst_rd == mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :311:20, :454:31, :998:72] wire data_hazard_mem = mem_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_mem_T_1 | hazard_targets_1_1 & _fp_data_hazard_mem_T_3 | hazard_targets_2_1 & _fp_data_hazard_mem_T_7); // @[RocketCore.scala:244:21, :461:82, :969:42, :970:42, :971:42, :998:{38,72}, :1287:{27,50}] wire _fp_data_hazard_wb_T_1 = _ibuf_io_inst_0_bits_inst_rs1 == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] wire _fp_data_hazard_wb_T_3 = _ibuf_io_inst_0_bits_inst_rs2 == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] wire _fp_data_hazard_wb_T_7 = _ibuf_io_inst_0_bits_inst_rd == wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :311:20, :455:29, :1008:70] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_11; // @[RocketCore.scala:1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_12; // @[RocketCore.scala:1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> _ibuf_io_inst_0_bits_inst_rs3; // @[RocketCore.scala:311:20, :1302:35, :1305:29] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_13; // @[RocketCore.scala:1302:35, :1305:29] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _ctrl_stalld_T_32 = ex_reg_valid & (ex_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_ex_T_1 | hazard_targets_1_1 & _fp_data_hazard_ex_T_3 | hazard_targets_2_1 & _fp_data_hazard_ex_T_7) & ((|ex_ctrl_csr) | ex_ctrl_jalr | ex_ctrl_mem | ex_ctrl_mul | ex_ctrl_div | ex_ctrl_fp | ex_ctrl_rocc | ex_ctrl_vec) | id_ctrl_fp & ex_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_ex_T_1 | io_fpu_dec_ren2 & _fp_data_hazard_ex_T_3 | io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == ex_reg_inst[11:7] | io_fpu_dec_wen & _fp_data_hazard_ex_T_7)) | mem_reg_valid & (data_hazard_mem & ((|mem_ctrl_csr) | mem_ctrl_mem & mem_mem_cmd_bh | mem_ctrl_mul | mem_ctrl_div | mem_ctrl_fp | mem_ctrl_rocc | mem_ctrl_vec) | id_ctrl_fp & mem_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_mem_T_1 | io_fpu_dec_ren2 & _fp_data_hazard_mem_T_3 | io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == mem_reg_inst[11:7] | io_fpu_dec_wen & _fp_data_hazard_mem_T_7)) | wb_reg_valid & (wb_ctrl_wxd & (hazard_targets_0_1 & _fp_data_hazard_wb_T_1 | hazard_targets_1_1 & _fp_data_hazard_wb_T_3 | hazard_targets_2_1 & _fp_data_hazard_wb_T_7) & wb_set_sboard | id_ctrl_fp & wb_ctrl_wfd & (io_fpu_dec_ren1 & _fp_data_hazard_wb_T_1 | io_fpu_dec_ren2 & _fp_data_hazard_wb_T_3 | io_fpu_dec_ren3 & _ibuf_io_inst_0_bits_inst_rs3 == wb_reg_inst[11:7] | io_fpu_dec_wen & _fp_data_hazard_wb_T_7)) | hazard_targets_0_1 & _id_sboard_hazard_T[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rs1) | hazard_targets_1_1 & _id_sboard_hazard_T_7[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rs2) | hazard_targets_2_1 & _id_sboard_hazard_T_14[0] & ~(ll_wen & ll_waddr == _ibuf_io_inst_0_bits_inst_rd) | _v_decode_io_legal & (ex_reg_valid & ex_reg_set_vconfig | mem_reg_valid & mem_reg_set_vconfig | _id_vconfig_hazard_T_3) | _csr_io_singleStep & (ex_reg_valid | mem_reg_valid | wb_reg_valid) | id_csr_en & _csr_io_decode_0_fp_csr & ~io_fpu_fcsr_rdy | id_csr_en & _csr_io_decode_0_vector_csr & id_vec_busy | id_ctrl_fp & (io_fpu_dec_ren1 & _id_stall_fpu_T_20[0] | io_fpu_dec_ren2 & _id_stall_fpu_T_23[0] | io_fpu_dec_ren3 & _id_stall_fpu_T_26[0] | io_fpu_dec_wen & _id_stall_fpu_T_29[0]) | id_ctrl_mem & dcache_blocked_blocked & ~io_dmem_perf_grant | id_ctrl_div & (~(_div_io_req_ready | _div_io_resp_valid & ~wb_wxd) | div_io_req_valid) | id_vec_busy & id_ctrl_fence | id_mem_busy & (id_ctrl_amo & _ibuf_io_inst_0_bits_inst_bits[25] | id_ctrl_fence_i | id_reg_fence & id_ctrl_mem) | _csr_io_csr_stall | id_reg_pause; // @[Configs.scala:33:35] wire ctrl_killd = ~_ibuf_io_inst_0_valid | _ibuf_io_inst_0_bits_replay | ibuf_io_kill | _ctrl_stalld_T_32 | _csr_io_interrupt; // @[RocketCore.scala:307:35, :311:20, :341:19, :411:34, :1032:{18,35,51,71}, :1033:23, :1034:74, :1035:62, :1036:61, :1037:32, :1039:34, :1041:15, :1042:17, :1043:22, :1046:{17,40,71,89,104}, :1287:50] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] wire io_ptw_sfence_valid_0 = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] wire _io_imem_btb_update_bits_cfiType_T_9 = mem_ctrl_jal | mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire [38:0] _io_imem_btb_update_bits_br_pc_T_1 = mem_reg_pc[38:0] + {37'h0, ~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :277:23, :1079:{69,74}] wire [38:0] io_imem_bht_update_bits_pc_0 = {_io_imem_btb_update_bits_br_pc_T_1[38:2], 2'h0}; // @[RocketCore.scala:1079:69, :1080:66] wire [4:0] io_fpu_ll_resp_tag_0 = _io_fpu_ll_resp_val_T ? io_dmem_resp_bits_tag[5:1] : io_vector_resp_bits_rd; // @[RocketCore.scala:767:46, :801:59, :1102:22, :1108:48, :1112:26] assign io_dmem_req_valid_0 = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_65( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [14:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [14:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [14:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [14:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_14( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_28( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_28 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundRawFNToRecFN_e8_s24_25( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_25 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_115( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_195 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_243( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_408( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }
module EgressUnit_1( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_EntryData_28( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae = io_x_ae_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RegisterFile.scala: package saturn.backend import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.tile.{CoreModule} import freechips.rocketchip.util._ import saturn.common._ class OldestRRArbiter(val n: Int)(implicit p: Parameters) extends Module { val io = IO(new ArbiterIO(new VectorReadReq, n)) val arb = Module(new RRArbiter(new VectorReadReq, n)) io <> arb.io val oldest_oh = io.in.map(i => i.valid && i.bits.oldest) //assert(PopCount(oldest_oh) <= 1.U) when (oldest_oh.orR) { io.chosen := VecInit(oldest_oh).asUInt io.out.valid := true.B io.out.bits := Mux1H(oldest_oh, io.in.map(_.bits)) for (i <- 0 until n) { io.in(i).ready := oldest_oh(i) && io.out.ready } } } class RegisterReadXbar(n: Int, banks: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val in = Vec(n, Flipped(new VectorReadIO)) val out = Vec(banks, new VectorReadIO) }) val arbs = Seq.fill(banks) { Module(new OldestRRArbiter(n)) } for (i <- 0 until banks) { io.out(i).req <> arbs(i).io.out } val bankOffset = log2Ceil(banks) for (i <- 0 until n) { val bank_sel = if (bankOffset == 0) true.B else UIntToOH(io.in(i).req.bits.eg(bankOffset-1,0)) for (j <- 0 until banks) { arbs(j).io.in(i).valid := io.in(i).req.valid && bank_sel(j) arbs(j).io.in(i).bits.eg := io.in(i).req.bits.eg >> bankOffset arbs(j).io.in(i).bits.oldest := io.in(i).req.bits.oldest } io.in(i).req.ready := Mux1H(bank_sel, arbs.map(_.io.in(i).ready)) io.in(i).resp := Mux1H(bank_sel, io.out.map(_.resp)) } } class RegisterFileBank(reads: Int, maskReads: Int, rows: Int, maskRows: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val io = IO(new Bundle { val read = Vec(reads, Flipped(new VectorReadIO)) val mask_read = Vec(maskReads, Flipped(new VectorReadIO)) val write = Input(Valid(new VectorWrite(dLen))) val ll_write = Flipped(Decoupled(new VectorWrite(dLen))) }) val ll_write_valid = RegInit(false.B) val ll_write_bits = Reg(new VectorWrite(dLen)) val vrf = Mem(rows, Vec(dLen, Bool())) val v0_mask = Mem(maskRows, Vec(dLen, Bool())) for (read <- io.read) { read.req.ready := !(ll_write_valid && read.req.bits.eg === ll_write_bits.eg) read.resp := DontCare when (read.req.valid) { read.resp := vrf.read(read.req.bits.eg).asUInt } } for (mask_read <- io.mask_read) { mask_read.req.ready := !(ll_write_valid && mask_read.req.bits.eg === ll_write_bits.eg) mask_read.resp := DontCare when (mask_read.req.valid) { mask_read.resp := v0_mask.read(mask_read.req.bits.eg).asUInt } } val write = WireInit(io.write) io.ll_write.ready := false.B if (vParams.vrfHiccupBuffer) { when (!io.write.valid) { // drain hiccup buffer write.valid := ll_write_valid || io.ll_write.valid write.bits := Mux(ll_write_valid, ll_write_bits, io.ll_write.bits) ll_write_valid := false.B when (io.ll_write.valid && ll_write_valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } .elsewhen (!ll_write_valid) { // fill hiccup buffer when (io.ll_write.valid) { ll_write_valid := true.B ll_write_bits := io.ll_write.bits } io.ll_write.ready := true.B } } else { when (!io.write.valid) { io.ll_write.ready := true.B write.valid := io.ll_write.valid write.bits := io.ll_write.bits } } when (write.valid) { vrf.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) when (write.bits.eg < maskRows.U) { v0_mask.write( write.bits.eg, VecInit(write.bits.data.asBools), write.bits.mask.asBools) } } } class RegisterFile(reads: Seq[Int], maskReads: Seq[Int], pipeWrites: Int, llWrites: Int)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams { val nBanks = vParams.vrfBanking // Support 1, 2, and 4 banks for the VRF require(nBanks == 1 || nBanks == 2 || nBanks == 4) val io = IO(new Bundle { val read = MixedVec(reads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val mask_read = MixedVec(maskReads.map(rc => Vec(rc, Flipped(new VectorReadIO)))) val pipe_writes = Vec(pipeWrites, Input(Valid(new VectorWrite(dLen)))) val ll_writes = Vec(llWrites, Flipped(Decoupled(new VectorWrite(dLen)))) }) val vrf = Seq.fill(nBanks) { Module(new RegisterFileBank(reads.size, maskReads.size, egsTotal/nBanks, if (egsPerVReg < nBanks) 1 else egsPerVReg / nBanks)) } reads.zipWithIndex.foreach { case (rc, i) => val xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.read(i) <> xbar.io.out(j) } xbar.io.in <> io.read(i) } maskReads.zipWithIndex.foreach { case (rc, i) => val mask_xbar = Module(new RegisterReadXbar(rc, nBanks)) vrf.zipWithIndex.foreach { case (bank, j) => bank.io.mask_read(i) <> mask_xbar.io.out(j) } mask_xbar.io.in <> io.mask_read(i) } io.ll_writes.foreach(_.ready := false.B) vrf.zipWithIndex.foreach { case (rf, i) => val bank_match = io.pipe_writes.map { w => (w.bits.bankId === i.U) && w.valid } val bank_write_data = Mux1H(bank_match, io.pipe_writes.map(_.bits.data)) val bank_write_mask = Mux1H(bank_match, io.pipe_writes.map(_.bits.mask)) val bank_write_eg = Mux1H(bank_match, io.pipe_writes.map(_.bits.eg)) val bank_write_valid = bank_match.orR rf.io.write.valid := bank_write_valid rf.io.write.bits.data := bank_write_data rf.io.write.bits.mask := bank_write_mask rf.io.write.bits.eg := bank_write_eg >> vrfBankBits when (bank_write_valid) { PopCount(bank_match) === 1.U } val ll_arb = Module(new Arbiter(new VectorWrite(dLen), llWrites)) rf.io.ll_write <> ll_arb.io.out io.ll_writes.zipWithIndex.foreach { case (w, j) => ll_arb.io.in(j).valid := w.valid && w.bits.bankId === i.U ll_arb.io.in(j).bits.eg := w.bits.eg >> vrfBankBits ll_arb.io.in(j).bits.data := w.bits.data ll_arb.io.in(j).bits.mask := w.bits.mask when (ll_arb.io.in(j).ready && w.bits.bankId === i.U) { w.ready := true.B } } } }
module RegisterFileBank( // @[RegisterFile.scala:52:7] input clock, // @[RegisterFile.scala:52:7] input reset, // @[RegisterFile.scala:52:7] output io_read_0_req_ready, // @[RegisterFile.scala:53:14] input io_read_0_req_valid, // @[RegisterFile.scala:53:14] input [4:0] io_read_0_req_bits_eg, // @[RegisterFile.scala:53:14] output [127:0] io_read_0_resp, // @[RegisterFile.scala:53:14] output io_read_1_req_ready, // @[RegisterFile.scala:53:14] input io_read_1_req_valid, // @[RegisterFile.scala:53:14] input [4:0] io_read_1_req_bits_eg, // @[RegisterFile.scala:53:14] output [127:0] io_read_1_resp, // @[RegisterFile.scala:53:14] output io_read_2_req_ready, // @[RegisterFile.scala:53:14] input io_read_2_req_valid, // @[RegisterFile.scala:53:14] input [4:0] io_read_2_req_bits_eg, // @[RegisterFile.scala:53:14] output [127:0] io_read_2_resp, // @[RegisterFile.scala:53:14] output io_mask_read_0_req_ready, // @[RegisterFile.scala:53:14] input [4:0] io_mask_read_0_req_bits_eg, // @[RegisterFile.scala:53:14] output [127:0] io_mask_read_0_resp, // @[RegisterFile.scala:53:14] input io_write_valid, // @[RegisterFile.scala:53:14] input [4:0] io_write_bits_eg, // @[RegisterFile.scala:53:14] input [127:0] io_write_bits_data, // @[RegisterFile.scala:53:14] input [127:0] io_write_bits_mask, // @[RegisterFile.scala:53:14] output io_ll_write_ready, // @[RegisterFile.scala:53:14] input io_ll_write_valid, // @[RegisterFile.scala:53:14] input [4:0] io_ll_write_bits_eg, // @[RegisterFile.scala:53:14] input [127:0] io_ll_write_bits_data, // @[RegisterFile.scala:53:14] input [127:0] io_ll_write_bits_mask // @[RegisterFile.scala:53:14] ); reg ll_write_valid; // @[RegisterFile.scala:59:31] reg [4:0] ll_write_bits_eg; // @[RegisterFile.scala:60:26] reg [127:0] ll_write_bits_data; // @[RegisterFile.scala:60:26] reg [127:0] ll_write_bits_mask; // @[RegisterFile.scala:60:26] reg [127:0] v0_mask; // @[RegisterFile.scala:63:20] wire write_valid = io_write_valid ? io_write_valid : ll_write_valid | io_ll_write_valid; // @[RegisterFile.scala:59:31, :79:23, :82:28, :83:{19,37}] wire [127:0] write_bits_mask = io_write_valid ? io_write_bits_mask : ll_write_valid ? ll_write_bits_mask : io_ll_write_bits_mask; // @[RegisterFile.scala:59:31, :60:26, :79:23, :82:28, :84:{18,24}] wire [127:0] write_bits_data = io_write_valid ? io_write_bits_data : ll_write_valid ? ll_write_bits_data : io_ll_write_bits_data; // @[RegisterFile.scala:59:31, :60:26, :79:23, :82:28, :84:{18,24}] wire [4:0] write_bits_eg = io_write_valid ? io_write_bits_eg : ll_write_valid ? ll_write_bits_eg : io_ll_write_bits_eg; // @[RegisterFile.scala:59:31, :60:26, :79:23, :82:28, :84:{18,24}] wire [127:0] _GEN = {write_bits_mask[127] ? write_bits_data[127] : v0_mask[127], write_bits_mask[126] ? write_bits_data[126] : v0_mask[126], write_bits_mask[125] ? write_bits_data[125] : v0_mask[125], write_bits_mask[124] ? write_bits_data[124] : v0_mask[124], write_bits_mask[123] ? write_bits_data[123] : v0_mask[123], write_bits_mask[122] ? write_bits_data[122] : v0_mask[122], write_bits_mask[121] ? write_bits_data[121] : v0_mask[121], write_bits_mask[120] ? write_bits_data[120] : v0_mask[120], write_bits_mask[119] ? write_bits_data[119] : v0_mask[119], write_bits_mask[118] ? write_bits_data[118] : v0_mask[118], write_bits_mask[117] ? write_bits_data[117] : v0_mask[117], write_bits_mask[116] ? write_bits_data[116] : v0_mask[116], write_bits_mask[115] ? write_bits_data[115] : v0_mask[115], write_bits_mask[114] ? write_bits_data[114] : v0_mask[114], write_bits_mask[113] ? write_bits_data[113] : v0_mask[113], write_bits_mask[112] ? write_bits_data[112] : v0_mask[112], write_bits_mask[111] ? write_bits_data[111] : v0_mask[111], write_bits_mask[110] ? write_bits_data[110] : v0_mask[110], write_bits_mask[109] ? write_bits_data[109] : v0_mask[109], write_bits_mask[108] ? write_bits_data[108] : v0_mask[108], write_bits_mask[107] ? write_bits_data[107] : v0_mask[107], write_bits_mask[106] ? write_bits_data[106] : v0_mask[106], write_bits_mask[105] ? write_bits_data[105] : v0_mask[105], write_bits_mask[104] ? write_bits_data[104] : v0_mask[104], write_bits_mask[103] ? write_bits_data[103] : v0_mask[103], write_bits_mask[102] ? write_bits_data[102] : v0_mask[102], write_bits_mask[101] ? write_bits_data[101] : v0_mask[101], write_bits_mask[100] ? write_bits_data[100] : v0_mask[100], write_bits_mask[99] ? write_bits_data[99] : v0_mask[99], write_bits_mask[98] ? write_bits_data[98] : v0_mask[98], write_bits_mask[97] ? write_bits_data[97] : v0_mask[97], write_bits_mask[96] ? write_bits_data[96] : v0_mask[96], write_bits_mask[95] ? write_bits_data[95] : v0_mask[95], write_bits_mask[94] ? write_bits_data[94] : v0_mask[94], write_bits_mask[93] ? write_bits_data[93] : v0_mask[93], write_bits_mask[92] ? write_bits_data[92] : v0_mask[92], write_bits_mask[91] ? write_bits_data[91] : v0_mask[91], write_bits_mask[90] ? write_bits_data[90] : v0_mask[90], write_bits_mask[89] ? write_bits_data[89] : v0_mask[89], write_bits_mask[88] ? write_bits_data[88] : v0_mask[88], write_bits_mask[87] ? write_bits_data[87] : v0_mask[87], write_bits_mask[86] ? write_bits_data[86] : v0_mask[86], write_bits_mask[85] ? write_bits_data[85] : v0_mask[85], write_bits_mask[84] ? write_bits_data[84] : v0_mask[84], write_bits_mask[83] ? write_bits_data[83] : v0_mask[83], write_bits_mask[82] ? write_bits_data[82] : v0_mask[82], write_bits_mask[81] ? write_bits_data[81] : v0_mask[81], write_bits_mask[80] ? write_bits_data[80] : v0_mask[80], write_bits_mask[79] ? write_bits_data[79] : v0_mask[79], write_bits_mask[78] ? write_bits_data[78] : v0_mask[78], write_bits_mask[77] ? write_bits_data[77] : v0_mask[77], write_bits_mask[76] ? write_bits_data[76] : v0_mask[76], write_bits_mask[75] ? write_bits_data[75] : v0_mask[75], write_bits_mask[74] ? write_bits_data[74] : v0_mask[74], write_bits_mask[73] ? write_bits_data[73] : v0_mask[73], write_bits_mask[72] ? write_bits_data[72] : v0_mask[72], write_bits_mask[71] ? write_bits_data[71] : v0_mask[71], write_bits_mask[70] ? write_bits_data[70] : v0_mask[70], write_bits_mask[69] ? write_bits_data[69] : v0_mask[69], write_bits_mask[68] ? write_bits_data[68] : v0_mask[68], write_bits_mask[67] ? write_bits_data[67] : v0_mask[67], write_bits_mask[66] ? write_bits_data[66] : v0_mask[66], write_bits_mask[65] ? write_bits_data[65] : v0_mask[65], write_bits_mask[64] ? write_bits_data[64] : v0_mask[64], write_bits_mask[63] ? write_bits_data[63] : v0_mask[63], write_bits_mask[62] ? write_bits_data[62] : v0_mask[62], write_bits_mask[61] ? write_bits_data[61] : v0_mask[61], write_bits_mask[60] ? write_bits_data[60] : v0_mask[60], write_bits_mask[59] ? write_bits_data[59] : v0_mask[59], write_bits_mask[58] ? write_bits_data[58] : v0_mask[58], write_bits_mask[57] ? write_bits_data[57] : v0_mask[57], write_bits_mask[56] ? write_bits_data[56] : v0_mask[56], write_bits_mask[55] ? write_bits_data[55] : v0_mask[55], write_bits_mask[54] ? write_bits_data[54] : v0_mask[54], write_bits_mask[53] ? write_bits_data[53] : v0_mask[53], write_bits_mask[52] ? write_bits_data[52] : v0_mask[52], write_bits_mask[51] ? write_bits_data[51] : v0_mask[51], write_bits_mask[50] ? write_bits_data[50] : v0_mask[50], write_bits_mask[49] ? write_bits_data[49] : v0_mask[49], write_bits_mask[48] ? write_bits_data[48] : v0_mask[48], write_bits_mask[47] ? write_bits_data[47] : v0_mask[47], write_bits_mask[46] ? write_bits_data[46] : v0_mask[46], write_bits_mask[45] ? write_bits_data[45] : v0_mask[45], write_bits_mask[44] ? write_bits_data[44] : v0_mask[44], write_bits_mask[43] ? write_bits_data[43] : v0_mask[43], write_bits_mask[42] ? write_bits_data[42] : v0_mask[42], write_bits_mask[41] ? write_bits_data[41] : v0_mask[41], write_bits_mask[40] ? write_bits_data[40] : v0_mask[40], write_bits_mask[39] ? write_bits_data[39] : v0_mask[39], write_bits_mask[38] ? write_bits_data[38] : v0_mask[38], write_bits_mask[37] ? write_bits_data[37] : v0_mask[37], write_bits_mask[36] ? write_bits_data[36] : v0_mask[36], write_bits_mask[35] ? write_bits_data[35] : v0_mask[35], write_bits_mask[34] ? write_bits_data[34] : v0_mask[34], write_bits_mask[33] ? write_bits_data[33] : v0_mask[33], write_bits_mask[32] ? write_bits_data[32] : v0_mask[32], write_bits_mask[31] ? write_bits_data[31] : v0_mask[31], write_bits_mask[30] ? write_bits_data[30] : v0_mask[30], write_bits_mask[29] ? write_bits_data[29] : v0_mask[29], write_bits_mask[28] ? write_bits_data[28] : v0_mask[28], write_bits_mask[27] ? write_bits_data[27] : v0_mask[27], write_bits_mask[26] ? write_bits_data[26] : v0_mask[26], write_bits_mask[25] ? write_bits_data[25] : v0_mask[25], write_bits_mask[24] ? write_bits_data[24] : v0_mask[24], write_bits_mask[23] ? write_bits_data[23] : v0_mask[23], write_bits_mask[22] ? write_bits_data[22] : v0_mask[22], write_bits_mask[21] ? write_bits_data[21] : v0_mask[21], write_bits_mask[20] ? write_bits_data[20] : v0_mask[20], write_bits_mask[19] ? write_bits_data[19] : v0_mask[19], write_bits_mask[18] ? write_bits_data[18] : v0_mask[18], write_bits_mask[17] ? write_bits_data[17] : v0_mask[17], write_bits_mask[16] ? write_bits_data[16] : v0_mask[16], write_bits_mask[15] ? write_bits_data[15] : v0_mask[15], write_bits_mask[14] ? write_bits_data[14] : v0_mask[14], write_bits_mask[13] ? write_bits_data[13] : v0_mask[13], write_bits_mask[12] ? write_bits_data[12] : v0_mask[12], write_bits_mask[11] ? write_bits_data[11] : v0_mask[11], write_bits_mask[10] ? write_bits_data[10] : v0_mask[10], write_bits_mask[9] ? write_bits_data[9] : v0_mask[9], write_bits_mask[8] ? write_bits_data[8] : v0_mask[8], write_bits_mask[7] ? write_bits_data[7] : v0_mask[7], write_bits_mask[6] ? write_bits_data[6] : v0_mask[6], write_bits_mask[5] ? write_bits_data[5] : v0_mask[5], write_bits_mask[4] ? write_bits_data[4] : v0_mask[4], write_bits_mask[3] ? write_bits_data[3] : v0_mask[3], write_bits_mask[2] ? write_bits_data[2] : v0_mask[2], write_bits_mask[1] ? write_bits_data[1] : v0_mask[1], write_bits_mask[0] ? write_bits_data[0] : v0_mask[0]}; // @[RegisterFile.scala:63:20, :79:23, :82:28, :84:18] wire _GEN_0 = io_ll_write_valid & ll_write_valid; // @[RegisterFile.scala:59:31, :86:31] wire _GEN_1 = ~ll_write_valid & io_ll_write_valid; // @[RegisterFile.scala:59:31, :91:{18,35}, :92:32, :93:24] always @(posedge clock) begin // @[RegisterFile.scala:52:7] if (reset) // @[RegisterFile.scala:52:7] ll_write_valid <= 1'h0; // @[RegisterFile.scala:59:31] else // @[RegisterFile.scala:52:7] ll_write_valid <= io_write_valid ? _GEN_1 | ll_write_valid : _GEN_0; // @[RegisterFile.scala:59:31, :82:28, :86:{31,50}, :91:35, :92:32, :93:24] if (io_write_valid ? _GEN_1 : _GEN_0) begin // @[RegisterFile.scala:59:31, :60:26, :82:28, :86:{31,50}, :88:23, :91:35, :92:32, :93:24, :94:23] ll_write_bits_eg <= io_ll_write_bits_eg; // @[RegisterFile.scala:60:26] ll_write_bits_data <= io_ll_write_bits_data; // @[RegisterFile.scala:60:26] ll_write_bits_mask <= io_ll_write_bits_mask; // @[RegisterFile.scala:60:26] end if (write_valid & write_bits_eg == 5'h0) // @[RegisterFile.scala:63:20, :79:23, :82:28, :83:19, :84:18, :106:22, :111:{25,39}] v0_mask <= _GEN; // @[RegisterFile.scala:63:20] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_49( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_305 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File DMA.scala: package gemmini import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters} import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket.MStatus import freechips.rocketchip.rocket.constants.MemoryOpConstants import Util._ import midas.targetutils.PerfCounter import midas.targetutils.SynthesizePrintf class StreamReadRequest[U <: Data](spad_rows: Int, acc_rows: Int, mvin_scale_t_bits: Int)(implicit p: Parameters) extends CoreBundle { val vaddr = UInt(coreMaxAddrBits.W) val spaddr = UInt(log2Up(spad_rows max acc_rows).W) // TODO use LocalAddr in DMA val is_acc = Bool() val accumulate = Bool() val has_acc_bitwidth = Bool() val scale = UInt(mvin_scale_t_bits.W) val status = new MStatus val len = UInt(16.W) // TODO magic number val repeats = UInt(16.W) // TODO magic number val pixel_repeats = UInt(8.W) // TODO magic number val block_stride = UInt(16.W) // TODO magic number val cmd_id = UInt(8.W) // TODO magic number } class StreamReadResponse[U <: Data](spadWidth: Int, accWidth: Int, spad_rows: Int, acc_rows: Int, aligned_to: Int, mvin_scale_t_bits: Int) (implicit p: Parameters) extends CoreBundle { val data = UInt((spadWidth max accWidth).W) val addr = UInt(log2Up(spad_rows max acc_rows).W) val mask = Vec((spadWidth max accWidth) / (aligned_to * 8) max 1, Bool()) val is_acc = Bool() val accumulate = Bool() val has_acc_bitwidth = Bool() val scale = UInt(mvin_scale_t_bits.W) val repeats = UInt(16.W) // TODO magic number val pixel_repeats = UInt(16.W) // TODO magic number val len = UInt(16.W) // TODO magic number val last = Bool() val bytes_read = UInt(8.W) // TODO magic number val cmd_id = UInt(8.W) // TODO magic number } class StreamReader[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T, U, V], nXacts: Int, beatBits: Int, maxBytes: Int, spadWidth: Int, accWidth: Int, aligned_to: Int, spad_rows: Int, acc_rows: Int, meshRows: Int, use_tlb_register_filter: Boolean, use_firesim_simulation_counters: Boolean) (implicit p: Parameters) extends LazyModule { val core = LazyModule(new StreamReaderCore(config, nXacts, beatBits, maxBytes, spadWidth, accWidth, aligned_to, spad_rows, acc_rows, meshRows, use_tlb_register_filter, use_firesim_simulation_counters)) val node = core.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val req = Flipped(Decoupled(new StreamReadRequest(spad_rows, acc_rows, config.mvin_scale_t_bits))) val resp = Decoupled(new StreamReadResponse(spadWidth, accWidth, spad_rows, acc_rows, aligned_to, config.mvin_scale_t_bits)) val tlb = new FrontendTLBIO val busy = Output(Bool()) val flush = Input(Bool()) val counter = new CounterEventIO() }) val nCmds = (nXacts / meshRows) + 1 val xactTracker = Module(new XactTracker(nXacts, maxBytes, spadWidth, accWidth, spad_rows, acc_rows, maxBytes, config.mvin_scale_t_bits, nCmds, use_firesim_simulation_counters)) val beatPacker = Module(new BeatMerger(beatBits, maxBytes, spadWidth, accWidth, spad_rows, acc_rows, maxBytes, aligned_to, meshRows, config.mvin_scale_t_bits, nCmds)) core.module.io.req <> io.req io.tlb <> core.module.io.tlb io.busy := xactTracker.io.busy core.module.io.flush := io.flush xactTracker.io.alloc <> core.module.io.reserve xactTracker.io.peek.xactid := RegEnableThru(core.module.io.beatData.bits.xactid, beatPacker.io.req.fire) xactTracker.io.peek.pop := beatPacker.io.in.fire && core.module.io.beatData.bits.last core.module.io.beatData.ready := beatPacker.io.in.ready beatPacker.io.req.valid := core.module.io.beatData.valid beatPacker.io.req.bits := xactTracker.io.peek.entry beatPacker.io.req.bits.lg_len_req := core.module.io.beatData.bits.lg_len_req beatPacker.io.in.valid := core.module.io.beatData.valid beatPacker.io.in.bits := core.module.io.beatData.bits.data beatPacker.io.out.ready := io.resp.ready io.resp.valid := beatPacker.io.out.valid io.resp.bits.data := beatPacker.io.out.bits.data io.resp.bits.addr := beatPacker.io.out.bits.addr io.resp.bits.mask := beatPacker.io.out.bits.mask io.resp.bits.is_acc := beatPacker.io.out.bits.is_acc io.resp.bits.accumulate := beatPacker.io.out.bits.accumulate io.resp.bits.has_acc_bitwidth := beatPacker.io.out.bits.has_acc_bitwidth io.resp.bits.scale := RegEnable(xactTracker.io.peek.entry.scale, beatPacker.io.req.fire) io.resp.bits.repeats := RegEnable(xactTracker.io.peek.entry.repeats, beatPacker.io.req.fire) io.resp.bits.pixel_repeats := RegEnable(xactTracker.io.peek.entry.pixel_repeats, beatPacker.io.req.fire) io.resp.bits.len := RegEnable(xactTracker.io.peek.entry.len, beatPacker.io.req.fire) io.resp.bits.cmd_id := RegEnable(xactTracker.io.peek.entry.cmd_id, beatPacker.io.req.fire) io.resp.bits.bytes_read := RegEnable(xactTracker.io.peek.entry.bytes_to_read, beatPacker.io.req.fire) io.resp.bits.last := beatPacker.io.out.bits.last io.counter := DontCare io.counter.collect(core.module.io.counter) io.counter.collect(xactTracker.io.counter) } } class StreamReadBeat (val nXacts: Int, val beatBits: Int, val maxReqBytes: Int) extends Bundle { val xactid = UInt(log2Up(nXacts).W) val data = UInt(beatBits.W) val lg_len_req = UInt(log2Up(log2Up(maxReqBytes+1)+1).W) val last = Bool() } // TODO StreamReaderCore and StreamWriter are actually very alike. Is there some parent class they could both inherit from? class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T, U, V], nXacts: Int, beatBits: Int, maxBytes: Int, spadWidth: Int, accWidth: Int, aligned_to: Int, spad_rows: Int, acc_rows: Int, meshRows: Int, use_tlb_register_filter: Boolean, use_firesim_simulation_counters: Boolean) (implicit p: Parameters) extends LazyModule { val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = "stream-reader", sourceId = IdRange(0, nXacts)))))) require(isPow2(aligned_to)) // TODO when we request data from multiple rows which are actually contiguous in main memory, we should merge them into fewer requests lazy val module = new Impl class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants { val (tl, edge) = node.out(0) val spadWidthBytes = spadWidth / 8 val accWidthBytes = accWidth / 8 val beatBytes = beatBits / 8 val nCmds = (nXacts / meshRows) + 1 val io = IO(new Bundle { val req = Flipped(Decoupled(new StreamReadRequest(spad_rows, acc_rows, config.mvin_scale_t_bits))) val reserve = new XactTrackerAllocIO(nXacts, maxBytes, spadWidth, accWidth, spad_rows, acc_rows, maxBytes, config.mvin_scale_t_bits, nCmds) val beatData = Decoupled(new StreamReadBeat(nXacts, beatBits, maxBytes)) val tlb = new FrontendTLBIO val flush = Input(Bool()) val counter = new CounterEventIO() }) val s_idle :: s_req_new_block :: Nil = Enum(2) val state = RegInit(s_idle) val req = Reg(new StreamReadRequest(spad_rows, acc_rows, config.mvin_scale_t_bits)) val vaddr = req.vaddr val bytesRequested = Reg(UInt(log2Ceil(spadWidthBytes max accWidthBytes max maxBytes).W)) // TODO this only needs to count up to (dataBytes/aligned_to), right? val bytesLeft = Mux(req.has_acc_bitwidth, req.len * (config.accType.getWidth / 8).U, req.len * (config.inputType.getWidth / 8).U) - bytesRequested val state_machine_ready_for_req = WireInit(state === s_idle) io.req.ready := state_machine_ready_for_req // Select the size and mask of the TileLink request class Packet extends Bundle { val size = UInt(log2Up(maxBytes+1).W) val lg_size = UInt(log2Ceil(log2Ceil(maxBytes+1)).W) val bytes_read = UInt(log2Up(maxBytes+1).W) val shift = UInt(log2Up(maxBytes).W) //val paddr = UInt(paddrBits.W) val vaddr = UInt(vaddrBits.W) } // TODO Can we filter out the larger read_sizes here if the systolic array is small, in the same way that we do so // for the write_sizes down below? val read_sizes = ((aligned_to max beatBytes) to maxBytes by aligned_to). filter(s => isPow2(s)). filter(s => s % beatBytes == 0) val read_packets = read_sizes.map { s => val lg_s = log2Ceil(s) val vaddr_aligned_to_size = if (s == 1) vaddr else Cat(vaddr(vaddrBits-1, lg_s), 0.U(lg_s.W)) val vaddr_offset = if (s > 1) vaddr(lg_s-1, 0) else 0.U val packet = Wire(new Packet()) packet.size := s.U packet.lg_size := lg_s.U packet.bytes_read := minOf(s.U - vaddr_offset, bytesLeft) packet.shift := vaddr_offset packet.vaddr := vaddr_aligned_to_size packet } val read_packet = read_packets.reduce { (acc, p) => Mux(p.bytes_read > acc.bytes_read, p, acc) } val read_vaddr = read_packet.vaddr val read_lg_size = read_packet.lg_size val read_bytes_read = read_packet.bytes_read val read_shift = read_packet.shift // Firing off TileLink read requests and allocating space inside the reservation buffer for them val get = edge.Get( fromSource = io.reserve.xactid, toAddress = 0.U, //read_paddr, lgSize = read_lg_size )._2 class TLBundleAWithInfo extends Bundle { val tl_a = tl.a.bits.cloneType val vaddr = Output(UInt(vaddrBits.W)) val status = Output(new MStatus) } val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) untranslated_a.valid := state === s_req_new_block && io.reserve.ready untranslated_a.bits.tl_a := get untranslated_a.bits.vaddr := read_vaddr untranslated_a.bits.status := req.status // 0 goes to retries, 1 goes to state machine val retry_a = Wire(Decoupled(new TLBundleAWithInfo)) val tlb_arb = Module(new Arbiter(new TLBundleAWithInfo, 2)) tlb_arb.io.in(0) <> retry_a tlb_arb.io.in(1) <> untranslated_a val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true)) tlb_q.io.enq <> tlb_arb.io.out io.tlb.req.valid := tlb_q.io.deq.valid io.tlb.req.bits := DontCare io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr io.tlb.req.bits.tlb_req.passthrough := false.B io.tlb.req.bits.tlb_req.size := 0.U // send_size io.tlb.req.bits.tlb_req.cmd := M_XRD io.tlb.req.bits.status := tlb_q.io.deq.bits.status val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true)) translate_q.io.enq <> tlb_q.io.deq translate_q.io.deq.ready := true.B retry_a.valid := translate_q.io.deq.valid && (io.tlb.resp.miss || !tl.a.ready) retry_a.bits := translate_q.io.deq.bits assert(retry_a.ready) tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.miss tl.a.bits := translate_q.io.deq.bits.tl_a tl.a.bits.address := io.tlb.resp.paddr io.reserve.valid := state === s_req_new_block && untranslated_a.ready // TODO decouple "reserve.valid" from "tl.a.ready" io.reserve.entry.shift := read_shift io.reserve.entry.is_acc := req.is_acc io.reserve.entry.accumulate := req.accumulate io.reserve.entry.has_acc_bitwidth := req.has_acc_bitwidth io.reserve.entry.scale := req.scale io.reserve.entry.repeats := req.repeats io.reserve.entry.pixel_repeats := req.pixel_repeats io.reserve.entry.len := req.len io.reserve.entry.block_stride := req.block_stride io.reserve.entry.lg_len_req := DontCare // TODO just remove this from the IO completely io.reserve.entry.bytes_to_read := read_bytes_read io.reserve.entry.cmd_id := req.cmd_id io.reserve.entry.addr := req.spaddr + req.block_stride * Mux(req.has_acc_bitwidth, // We only add "if" statements here to satisfy the Verilator linter. The code would be cleaner without the // "if" condition and the "else" clause. Similarly, the width expansions are also there to satisfy the Verilator // linter, despite making the code uglier. if (bytesRequested.getWidth >= log2Up(accWidthBytes+1)) bytesRequested / accWidthBytes.U(bytesRequested.getWidth.W) else 0.U, if (bytesRequested.getWidth >= log2Up(spadWidthBytes+1)) bytesRequested / spadWidthBytes.U(bytesRequested.getWidth.W) else 0.U) io.reserve.entry.spad_row_offset := Mux(req.has_acc_bitwidth, bytesRequested % accWidthBytes.U, bytesRequested % spadWidthBytes.U) when (untranslated_a.fire) { val next_vaddr = req.vaddr + read_bytes_read // send_size val new_page = next_vaddr(pgIdxBits-1, 0) === 0.U req.vaddr := next_vaddr bytesRequested := bytesRequested + read_bytes_read // send_size // when (send_size >= bytesLeft) { when (read_bytes_read >= bytesLeft) { // We're done with this request at this point state_machine_ready_for_req := true.B state := s_idle } } // Forward TileLink read responses to the reservation buffer tl.d.ready := io.beatData.ready io.beatData.valid := tl.d.valid io.beatData.bits.xactid := tl.d.bits.source io.beatData.bits.data := tl.d.bits.data io.beatData.bits.lg_len_req := tl.d.bits.size io.beatData.bits.last := edge.last(tl.d) // TODO the size data is already returned from TileLink, so there's no need for us to store it in the XactTracker ourselves // Accepting requests to kick-start the state machine when (io.req.fire) { req := io.req.bits bytesRequested := 0.U state := s_req_new_block } // Performance counter io.counter := DontCare CounterEventIO.init(io.counter) io.counter.connectEventSignal(CounterEvent.RDMA_ACTIVE_CYCLE, state =/= s_idle) io.counter.connectEventSignal(CounterEvent.RDMA_TLB_WAIT_CYCLES, io.tlb.resp.miss) io.counter.connectEventSignal(CounterEvent.RDMA_TL_WAIT_CYCLES, tl.a.valid && !tl.a.ready) // External counters val total_bytes_read = RegInit(0.U(CounterExternal.EXTERNAL_WIDTH.W)) when (io.counter.external_reset) { total_bytes_read := 0.U }.elsewhen (tl.d.fire) { total_bytes_read := total_bytes_read + (1.U << tl.d.bits.size) } io.counter.connectExternalCounter(CounterExternal.RDMA_BYTES_REC, total_bytes_read) if (use_firesim_simulation_counters) { PerfCounter(state =/= s_idle, "rdma_active_cycles", "cycles during which the read dma is active") PerfCounter(tl.a.ready && translate_q.io.deq.valid && io.tlb.resp.miss, "rdma_tlb_wait_cycles", "cycles during which the read dma is stalling as it waits for a TLB response") PerfCounter(tl.a.valid && !tl.a.ready, "rdma_tl_wait_cycles", "cycles during which the read dma is stalling as it waits for the TileLink port to be available") val cntr = Counter(500000) when (cntr.inc()) { printf(SynthesizePrintf("RDMA bytes rec: %d\n", total_bytes_read)) } } } } class StreamWriteRequest(val dataWidth: Int, val maxBytes: Int)(implicit p: Parameters) extends CoreBundle { val vaddr = UInt(coreMaxAddrBits.W) val data = UInt(dataWidth.W) val len = UInt(log2Up((dataWidth/8 max maxBytes)+1).W) // The number of bytes to write val block = UInt(8.W) // TODO magic number val status = new MStatus // Pooling variables val pool_en = Bool() val store_en = Bool() } class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes: Int, dataWidth: Int, aligned_to: Int, inputType: T, block_cols: Int, use_tlb_register_filter: Boolean, use_firesim_simulation_counters: Boolean) (implicit p: Parameters) extends LazyModule { val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = "stream-writer", sourceId = IdRange(0, nXacts)))))) require(isPow2(aligned_to)) lazy val module = new Impl class Impl extends LazyModuleImp(this) with HasCoreParameters with MemoryOpConstants { val (tl, edge) = node.out(0) val dataBytes = dataWidth / 8 val beatBytes = beatBits / 8 val lgBeatBytes = log2Ceil(beatBytes) val maxBeatsPerReq = maxBytes / beatBytes val inputTypeRowBytes = block_cols * inputType.getWidth / 8 val maxBlocks = maxBytes / inputTypeRowBytes require(beatBytes > 0) val io = IO(new Bundle { val req = Flipped(Decoupled(new StreamWriteRequest(dataWidth, maxBytes))) val tlb = new FrontendTLBIO val busy = Output(Bool()) val flush = Input(Bool()) val counter = new CounterEventIO() }) val (s_idle :: s_writing_new_block :: s_writing_beats :: Nil) = Enum(3) val state = RegInit(s_idle) val req = Reg(new StreamWriteRequest(dataWidth, maxBytes)) // TODO use the same register to hold data_blocks and data_single_block, so that this Mux here is not necessary val data_blocks = Reg(Vec(maxBlocks, UInt((inputTypeRowBytes * 8).W))) val data_single_block = Reg(UInt(dataWidth.W)) // For data that's just one-block-wide val data = Mux(req.block === 0.U, data_single_block, data_blocks.asUInt) val bytesSent = Reg(UInt(log2Ceil((dataBytes max maxBytes)+1).W)) // TODO this only needs to count up to (dataBytes/aligned_to), right? val bytesLeft = req.len - bytesSent val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) val xactId = OHToUInt(xactOnehot) val xactBusy_fire = WireInit(false.B) val xactBusy_add = Mux(xactBusy_fire, (1.U << xactId).asUInt, 0.U) val xactBusy_remove = ~Mux(tl.d.fire, (1.U << tl.d.bits.source).asUInt, 0.U) xactBusy := (xactBusy | xactBusy_add) & xactBusy_remove.asUInt val state_machine_ready_for_req = WireInit(state === s_idle) io.req.ready := state_machine_ready_for_req io.busy := xactBusy.orR || (state =/= s_idle) val vaddr = req.vaddr // Select the size and mask of the TileLink request class Packet extends Bundle { val size = UInt(log2Ceil(maxBytes+1).W) val lg_size = UInt(log2Ceil(log2Ceil(maxBytes+1)+1).W) val mask = Vec(maxBeatsPerReq, Vec(beatBytes, Bool())) val vaddr = UInt(vaddrBits.W) val is_full = Bool() val bytes_written = UInt(log2Up(maxBytes+1).W) val bytes_written_per_beat = Vec(maxBeatsPerReq, UInt(log2Up(beatBytes+1).W)) def total_beats(dummy: Int = 0) = Mux(size < beatBytes.U, 1.U, size / beatBytes.U(size.getWidth.W)) // The width expansion is added here solely to satsify Verilator's linter } val smallest_write_size = aligned_to max beatBytes val write_sizes = (smallest_write_size to maxBytes by aligned_to). filter(s => isPow2(s)). filter(s => s % beatBytes == 0) /*. filter(s => s <= dataBytes*2 || s == smallest_write_size)*/ val write_packets = write_sizes.map { s => val lg_s = log2Ceil(s) val vaddr_aligned_to_size = if (s == 1) vaddr else Cat(vaddr(vaddrBits-1, lg_s), 0.U(lg_s.W)) val vaddr_offset = if (s > 1) vaddr(lg_s - 1, 0) else 0.U val mask = (0 until maxBytes).map { i => i.U >= vaddr_offset && i.U < vaddr_offset +& bytesLeft && (i < s).B } val bytes_written = { Mux(vaddr_offset +& bytesLeft > s.U, s.U - vaddr_offset, bytesLeft) } val packet = Wire(new Packet()) packet.size := s.U packet.lg_size := lg_s.U packet.mask := VecInit(mask.grouped(beatBytes).map(v => VecInit(v)).toSeq) packet.vaddr := vaddr_aligned_to_size packet.is_full := mask.take(s).reduce(_ && _) packet.bytes_written := bytes_written packet.bytes_written_per_beat.zipWithIndex.foreach { case (b, i) => val start_of_beat = i * beatBytes val end_of_beat = (i+1) * beatBytes val left_shift = Mux(vaddr_offset >= start_of_beat.U && vaddr_offset < end_of_beat.U, vaddr_offset - start_of_beat.U, 0.U) val right_shift = Mux(vaddr_offset +& bytesLeft >= start_of_beat.U && vaddr_offset +& bytesLeft < end_of_beat.U, end_of_beat.U - (vaddr_offset +& bytesLeft), 0.U) val too_early = vaddr_offset >= end_of_beat.U val too_late = vaddr_offset +& bytesLeft <= start_of_beat.U b := Mux(too_early || too_late, 0.U, beatBytes.U - (left_shift +& right_shift)) } packet } val best_write_packet = write_packets.reduce { (acc, p) => Mux(p.bytes_written > acc.bytes_written, p, acc) } val write_packet = RegEnableThru(best_write_packet, state === s_writing_new_block) val write_size = write_packet.size val lg_write_size = write_packet.lg_size val write_beats = write_packet.total_beats() val write_vaddr = write_packet.vaddr val write_full = write_packet.is_full val beatsLeft = Reg(UInt(log2Up(maxBytes/aligned_to).W)) val beatsSent = Mux(state === s_writing_new_block, 0.U, write_beats - beatsLeft) val write_mask = write_packet.mask(beatsSent) val write_shift = PriorityEncoder(write_mask) val bytes_written_this_beat = write_packet.bytes_written_per_beat(beatsSent) // Firing off TileLink write requests val putFull = edge.Put( fromSource = RegEnableThru(xactId, state === s_writing_new_block), toAddress = 0.U, lgSize = lg_write_size, data = (data >> (bytesSent * 8.U)).asUInt )._2 val putPartial = edge.Put( fromSource = RegEnableThru(xactId, state === s_writing_new_block), toAddress = 0.U, lgSize = lg_write_size, data = ((data >> (bytesSent * 8.U)) << (write_shift * 8.U)).asUInt, mask = write_mask.asUInt )._2 class TLBundleAWithInfo extends Bundle { val tl_a = tl.a.bits.cloneType val vaddr = Output(UInt(vaddrBits.W)) val status = Output(new MStatus) } val untranslated_a = Wire(Decoupled(new TLBundleAWithInfo)) xactBusy_fire := untranslated_a.fire && state === s_writing_new_block untranslated_a.valid := (state === s_writing_new_block || state === s_writing_beats) && !xactBusy.andR untranslated_a.bits.tl_a := Mux(write_full, putFull, putPartial) untranslated_a.bits.vaddr := write_vaddr untranslated_a.bits.status := req.status // 0 goes to retries, 1 goes to state machine val retry_a = Wire(Decoupled(new TLBundleAWithInfo)) val shadow_retry_a = Module(new Queue(new TLBundleAWithInfo, 1)) shadow_retry_a.io.enq.valid := false.B shadow_retry_a.io.enq.bits := DontCare val tlb_arb = Module(new Arbiter(new TLBundleAWithInfo, 3)) tlb_arb.io.in(0) <> retry_a tlb_arb.io.in(1) <> shadow_retry_a.io.deq tlb_arb.io.in(2) <> untranslated_a val tlb_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true)) tlb_q.io.enq <> tlb_arb.io.out io.tlb.req.valid := tlb_q.io.deq.fire io.tlb.req.bits := DontCare io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr io.tlb.req.bits.tlb_req.passthrough := false.B io.tlb.req.bits.tlb_req.size := 0.U // send_size io.tlb.req.bits.tlb_req.cmd := M_XWR io.tlb.req.bits.status := tlb_q.io.deq.bits.status val translate_q = Module(new Queue(new TLBundleAWithInfo, 1, pipe=true)) translate_q.io.enq <> tlb_q.io.deq when (retry_a.valid) { translate_q.io.enq.valid := false.B shadow_retry_a.io.enq.valid := tlb_q.io.deq.valid shadow_retry_a.io.enq.bits := tlb_q.io.deq.bits } translate_q.io.deq.ready := tl.a.ready || io.tlb.resp.miss retry_a.valid := translate_q.io.deq.valid && io.tlb.resp.miss retry_a.bits := translate_q.io.deq.bits assert(!(retry_a.valid && !retry_a.ready)) tl.a.valid := translate_q.io.deq.valid && !io.tlb.resp.miss tl.a.bits := translate_q.io.deq.bits.tl_a tl.a.bits.address := RegEnableThru(io.tlb.resp.paddr, RegNext(io.tlb.req.fire)) tl.d.ready := xactBusy.orR when (untranslated_a.fire) { when (state === s_writing_new_block) { beatsLeft := write_beats - 1.U val next_vaddr = req.vaddr + write_packet.bytes_written req.vaddr := next_vaddr bytesSent := bytesSent + bytes_written_this_beat when (write_beats === 1.U) { when (bytes_written_this_beat >= bytesLeft) { // We're done with this request at this point state_machine_ready_for_req := true.B state := s_idle } }.otherwise { state := s_writing_beats } }.elsewhen(state === s_writing_beats) { beatsLeft := beatsLeft - 1.U bytesSent := bytesSent + bytes_written_this_beat assert(beatsLeft > 0.U) when (beatsLeft === 1.U) { when (bytes_written_this_beat >= bytesLeft) { // We're done with this request at this point state_machine_ready_for_req := true.B state := s_idle }.otherwise { state := s_writing_new_block } } } } // Accepting requests to kick-start the state machine when (io.req.fire) { val pooled = { val cols = dataWidth / inputType.getWidth val v1 = io.req.bits.data.asTypeOf(Vec(cols, inputType)) val v2 = data_single_block.asTypeOf(Vec(cols, inputType)) val m = v1.zip(v2) VecInit(m.zipWithIndex.map{case ((x, y), i) => if (i < block_cols) maxOf(x, y) else y}).asUInt } req := io.req.bits req.len := io.req.bits.block * inputTypeRowBytes.U + io.req.bits.len data_single_block := Mux(io.req.bits.pool_en, pooled, io.req.bits.data) data_blocks(io.req.bits.block) := io.req.bits.data bytesSent := 0.U state := Mux(io.req.bits.store_en, s_writing_new_block, s_idle) assert(io.req.bits.len <= (block_cols * inputType.getWidth / 8).U || io.req.bits.block === 0.U, "DMA can't write multiple blocks to main memory when writing full accumulator output") assert(!io.req.bits.pool_en || io.req.bits.block === 0.U, "Can't pool with block-mvout") } // Performance counter CounterEventIO.init(io.counter) io.counter.connectEventSignal(CounterEvent.WDMA_ACTIVE_CYCLE, state =/= s_idle) io.counter.connectEventSignal(CounterEvent.WDMA_TLB_WAIT_CYCLES, io.tlb.resp.miss) io.counter.connectEventSignal(CounterEvent.WDMA_TL_WAIT_CYCLES, tl.a.valid && !tl.a.ready) // External counters val total_bytes_sent = RegInit(0.U(CounterExternal.EXTERNAL_WIDTH.W)) when (tl.d.fire) { total_bytes_sent := total_bytes_sent + (1.U << tl.d.bits.size) } val total_latency = RegInit(0.U(CounterExternal.EXTERNAL_WIDTH.W)) total_latency := total_latency + PopCount(xactBusy) when (io.counter.external_reset) { total_bytes_sent := 0.U total_latency := 0.U } io.counter.connectExternalCounter(CounterExternal.WDMA_BYTES_SENT, total_bytes_sent) io.counter.connectExternalCounter(CounterExternal.WDMA_TOTAL_LATENCY, total_latency) if (use_firesim_simulation_counters) { PerfCounter(state =/= s_idle, "wdma_active_cycles", "cycles during which write read dma is active") PerfCounter(tl.a.ready && translate_q.io.deq.valid && io.tlb.resp.miss, "wdma_tlb_wait_cycles", "cycles during which the write dma is stalling as it waits for a TLB response") PerfCounter(tl.a.valid && !tl.a.ready, "wdma_tl_wait_cycles", "cycles during which the write dma is stalling as it waits for the TileLink port to be available") val cntr = Counter(500000) when(cntr.inc()) { printf(SynthesizePrintf("WDMA bytes sent: %d\n", total_bytes_sent)) printf(SynthesizePrintf("WDMA total latency: %d\n", total_latency)) } } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Util.scala: package gemmini import chisel3._ import chisel3.util._ object Util { def wrappingAdd(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 if (max == 0) { 0.U } else { assert(n <= max.U, "cannot wrapAdd when n is larger than max") Mux(u >= max.U - n + 1.U && n =/= 0.U, n - (max.U - u) - 1.U, u + n) } } def wrappingAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U assert(n <= max || max === 0.U, "cannot wrapAdd when n is larger than max, unless max is 0") /* Mux(!en, u, Mux (max === 0.U, 0.U, Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n))) */ MuxCase(u + n, Seq( (!en) -> u, (max === 0.U) -> 0.U, (u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U) )) } def satAdd(u: UInt, v: UInt, max: UInt): UInt = { Mux(u +& v > max, max, u + v) } def floorAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U MuxCase(u + n, Seq( (!en) -> u, ((u +& n) > max) -> 0.U )) } def sFloorAdd(s: SInt, n: UInt, max_plus_one: SInt, min: SInt, en: Bool = true.B): SInt = { val max = max_plus_one - 1.S MuxCase(s + n.zext, Seq( (!en) -> s, ((s +& n.zext) > max) -> min )) } def wrappingSub(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 assert(n <= max.U, "cannot wrapSub when n is larger than max") Mux(u < n, max.U - (n-u) + 1.U, u - n) } def ceilingDivide(numer: Int, denom: Int): Int = { if (numer % denom == 0) { numer / denom } else { numer / denom + 1} } def closestLowerPowerOf2(u: UInt): UInt = { // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } def closestAlignedLowerPowerOf2(u: UInt, addr: UInt, stride: UInt, rowBytes: Int): UInt = { val lgRowBytes = log2Ceil(rowBytes) // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } // This function will return "next" with a 0-cycle delay when the "enable" signal is high. It's like a queue with // the "pipe" and "flow" parameters set to "true" def RegEnableThru[T <: Data](next: T, enable: Bool): T = { val buf = RegEnable(next, enable) Mux(enable, next, buf) } def RegEnableThru[T <: Data](next: T, init: T, enable: Bool): T = { val buf = RegEnable(next, init, enable) Mux(enable, next, buf) } def maxOf(u1: UInt, u2: UInt): UInt = { Mux(u1 > u2, u1, u2) } def maxOf[T <: Data](x: T, y: T)(implicit ev: Arithmetic[T]): T = { import ev._ Mux(x > y, x, y) } def minOf(u1: UInt, u2: UInt): UInt = { Mux(u1 < u2, u1, u2) } def accumulateTree[T <: Data](xs: Seq[T])(implicit ev: Arithmetic[T]): T = { import ev._ assert(xs.nonEmpty, "can't accumulate 0 elements") if (xs.length == 1) { xs.head } else { val upperRowLen = 1 << log2Ceil(xs.length) val upperRow = xs.padTo(upperRowLen, xs.head.zero) val pairs = upperRow.grouped(2) val lowerRow = pairs.map { case Seq(a, b) => a + b } accumulateTree(lowerRow.toSeq) } } // An undirectioned Valid bundle class UDValid[T <: Data](t: T) extends Bundle { val valid = Bool() val bits = t.cloneType def push(b: T): Unit = { valid := true.B bits := b } def pop(dummy: Int = 0): T = { valid := false.B bits } } object UDValid { def apply[T <: Data](t: T): UDValid[T] = new UDValid(t) } // creates a Reg and the next-state Wire, and returns both def regwire(bits: Int) = { val wire = Wire(UInt(bits.W)) val reg = RegNext(wire) wire := reg // default wire to read from reg (reg, wire) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module StreamWriter( // @[DMA.scala:360:9] input clock, // @[DMA.scala:360:9] input reset, // @[DMA.scala:360:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_req_ready, // @[DMA.scala:371:16] input io_req_valid, // @[DMA.scala:371:16] input [39:0] io_req_bits_vaddr, // @[DMA.scala:371:16] input [127:0] io_req_bits_data, // @[DMA.scala:371:16] input [6:0] io_req_bits_len, // @[DMA.scala:371:16] input [7:0] io_req_bits_block, // @[DMA.scala:371:16] input io_req_bits_status_debug, // @[DMA.scala:371:16] input io_req_bits_status_cease, // @[DMA.scala:371:16] input io_req_bits_status_wfi, // @[DMA.scala:371:16] input [31:0] io_req_bits_status_isa, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_dprv, // @[DMA.scala:371:16] input io_req_bits_status_dv, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_prv, // @[DMA.scala:371:16] input io_req_bits_status_v, // @[DMA.scala:371:16] input io_req_bits_status_sd, // @[DMA.scala:371:16] input [22:0] io_req_bits_status_zero2, // @[DMA.scala:371:16] input io_req_bits_status_mpv, // @[DMA.scala:371:16] input io_req_bits_status_gva, // @[DMA.scala:371:16] input io_req_bits_status_mbe, // @[DMA.scala:371:16] input io_req_bits_status_sbe, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_sxl, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_uxl, // @[DMA.scala:371:16] input io_req_bits_status_sd_rv32, // @[DMA.scala:371:16] input [7:0] io_req_bits_status_zero1, // @[DMA.scala:371:16] input io_req_bits_status_tsr, // @[DMA.scala:371:16] input io_req_bits_status_tw, // @[DMA.scala:371:16] input io_req_bits_status_tvm, // @[DMA.scala:371:16] input io_req_bits_status_mxr, // @[DMA.scala:371:16] input io_req_bits_status_sum, // @[DMA.scala:371:16] input io_req_bits_status_mprv, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_xs, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_fs, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_mpp, // @[DMA.scala:371:16] input [1:0] io_req_bits_status_vs, // @[DMA.scala:371:16] input io_req_bits_status_spp, // @[DMA.scala:371:16] input io_req_bits_status_mpie, // @[DMA.scala:371:16] input io_req_bits_status_ube, // @[DMA.scala:371:16] input io_req_bits_status_spie, // @[DMA.scala:371:16] input io_req_bits_status_upie, // @[DMA.scala:371:16] input io_req_bits_status_mie, // @[DMA.scala:371:16] input io_req_bits_status_hie, // @[DMA.scala:371:16] input io_req_bits_status_sie, // @[DMA.scala:371:16] input io_req_bits_status_uie, // @[DMA.scala:371:16] input io_req_bits_pool_en, // @[DMA.scala:371:16] input io_req_bits_store_en, // @[DMA.scala:371:16] output io_tlb_req_valid, // @[DMA.scala:371:16] output [39:0] io_tlb_req_bits_tlb_req_vaddr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_debug, // @[DMA.scala:371:16] output io_tlb_req_bits_status_cease, // @[DMA.scala:371:16] output io_tlb_req_bits_status_wfi, // @[DMA.scala:371:16] output [31:0] io_tlb_req_bits_status_isa, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_dprv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_dv, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_prv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_v, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sd, // @[DMA.scala:371:16] output [22:0] io_tlb_req_bits_status_zero2, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mpv, // @[DMA.scala:371:16] output io_tlb_req_bits_status_gva, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mbe, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sbe, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_sxl, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_uxl, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sd_rv32, // @[DMA.scala:371:16] output [7:0] io_tlb_req_bits_status_zero1, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tsr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tw, // @[DMA.scala:371:16] output io_tlb_req_bits_status_tvm, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mxr, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sum, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mprv, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_xs, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_fs, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_mpp, // @[DMA.scala:371:16] output [1:0] io_tlb_req_bits_status_vs, // @[DMA.scala:371:16] output io_tlb_req_bits_status_spp, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mpie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_ube, // @[DMA.scala:371:16] output io_tlb_req_bits_status_spie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_upie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_mie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_hie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_sie, // @[DMA.scala:371:16] output io_tlb_req_bits_status_uie, // @[DMA.scala:371:16] input io_tlb_resp_miss, // @[DMA.scala:371:16] input [31:0] io_tlb_resp_paddr, // @[DMA.scala:371:16] input [39:0] io_tlb_resp_gpa, // @[DMA.scala:371:16] input io_tlb_resp_pf_ld, // @[DMA.scala:371:16] input io_tlb_resp_pf_st, // @[DMA.scala:371:16] input io_tlb_resp_pf_inst, // @[DMA.scala:371:16] input io_tlb_resp_ae_ld, // @[DMA.scala:371:16] input io_tlb_resp_ae_st, // @[DMA.scala:371:16] input io_tlb_resp_ae_inst, // @[DMA.scala:371:16] input io_tlb_resp_cacheable, // @[DMA.scala:371:16] input io_tlb_resp_must_alloc, // @[DMA.scala:371:16] input io_tlb_resp_prefetchable, // @[DMA.scala:371:16] input [4:0] io_tlb_resp_cmd, // @[DMA.scala:371:16] output io_busy, // @[DMA.scala:371:16] input io_flush, // @[DMA.scala:371:16] output io_counter_event_signal_21, // @[DMA.scala:371:16] output io_counter_event_signal_22, // @[DMA.scala:371:16] output io_counter_event_signal_23, // @[DMA.scala:371:16] output [31:0] io_counter_external_values_5, // @[DMA.scala:371:16] output [31:0] io_counter_external_values_7, // @[DMA.scala:371:16] input io_counter_external_reset // @[DMA.scala:371:16] ); reg [1:0] state; // @[DMA.scala:380:24] wire _translate_q_io_enq_ready; // @[DMA.scala:534:29] wire _translate_q_io_deq_valid; // @[DMA.scala:534:29] wire [2:0] _translate_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:534:29] wire [2:0] _translate_q_io_deq_bits_tl_a_param; // @[DMA.scala:534:29] wire [3:0] _translate_q_io_deq_bits_tl_a_size; // @[DMA.scala:534:29] wire [5:0] _translate_q_io_deq_bits_tl_a_source; // @[DMA.scala:534:29] wire [15:0] _translate_q_io_deq_bits_tl_a_mask; // @[DMA.scala:534:29] wire [127:0] _translate_q_io_deq_bits_tl_a_data; // @[DMA.scala:534:29] wire _translate_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:534:29] wire _tlb_q_io_enq_ready; // @[DMA.scala:523:23] wire _tlb_q_io_deq_valid; // @[DMA.scala:523:23] wire [2:0] _tlb_q_io_deq_bits_tl_a_opcode; // @[DMA.scala:523:23] wire [2:0] _tlb_q_io_deq_bits_tl_a_param; // @[DMA.scala:523:23] wire [3:0] _tlb_q_io_deq_bits_tl_a_size; // @[DMA.scala:523:23] wire [5:0] _tlb_q_io_deq_bits_tl_a_source; // @[DMA.scala:523:23] wire [31:0] _tlb_q_io_deq_bits_tl_a_address; // @[DMA.scala:523:23] wire [15:0] _tlb_q_io_deq_bits_tl_a_mask; // @[DMA.scala:523:23] wire [127:0] _tlb_q_io_deq_bits_tl_a_data; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_tl_a_corrupt; // @[DMA.scala:523:23] wire [38:0] _tlb_q_io_deq_bits_vaddr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_debug; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_cease; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_wfi; // @[DMA.scala:523:23] wire [31:0] _tlb_q_io_deq_bits_status_isa; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_dprv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_dv; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_prv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_v; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sd; // @[DMA.scala:523:23] wire [22:0] _tlb_q_io_deq_bits_status_zero2; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mpv; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_gva; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mbe; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sbe; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_sxl; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_uxl; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sd_rv32; // @[DMA.scala:523:23] wire [7:0] _tlb_q_io_deq_bits_status_zero1; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tsr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tw; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_tvm; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mxr; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sum; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mprv; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_xs; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_fs; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_mpp; // @[DMA.scala:523:23] wire [1:0] _tlb_q_io_deq_bits_status_vs; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_spp; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mpie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_ube; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_spie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_upie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_mie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_hie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_sie; // @[DMA.scala:523:23] wire _tlb_q_io_deq_bits_status_uie; // @[DMA.scala:523:23] wire _tlb_arb_io_in_1_ready; // @[DMA.scala:518:25] wire _tlb_arb_io_out_valid; // @[DMA.scala:518:25] wire [2:0] _tlb_arb_io_out_bits_tl_a_opcode; // @[DMA.scala:518:25] wire [2:0] _tlb_arb_io_out_bits_tl_a_param; // @[DMA.scala:518:25] wire [3:0] _tlb_arb_io_out_bits_tl_a_size; // @[DMA.scala:518:25] wire [5:0] _tlb_arb_io_out_bits_tl_a_source; // @[DMA.scala:518:25] wire [31:0] _tlb_arb_io_out_bits_tl_a_address; // @[DMA.scala:518:25] wire [15:0] _tlb_arb_io_out_bits_tl_a_mask; // @[DMA.scala:518:25] wire [127:0] _tlb_arb_io_out_bits_tl_a_data; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_tl_a_corrupt; // @[DMA.scala:518:25] wire [38:0] _tlb_arb_io_out_bits_vaddr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_debug; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_cease; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_wfi; // @[DMA.scala:518:25] wire [31:0] _tlb_arb_io_out_bits_status_isa; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_dprv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_dv; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_prv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_v; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sd; // @[DMA.scala:518:25] wire [22:0] _tlb_arb_io_out_bits_status_zero2; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mpv; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_gva; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mbe; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sbe; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_sxl; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_uxl; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sd_rv32; // @[DMA.scala:518:25] wire [7:0] _tlb_arb_io_out_bits_status_zero1; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tsr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tw; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_tvm; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mxr; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sum; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mprv; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_xs; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_fs; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_mpp; // @[DMA.scala:518:25] wire [1:0] _tlb_arb_io_out_bits_status_vs; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_spp; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mpie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_ube; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_spie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_upie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_mie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_hie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_sie; // @[DMA.scala:518:25] wire _tlb_arb_io_out_bits_status_uie; // @[DMA.scala:518:25] wire _shadow_retry_a_io_deq_valid; // @[DMA.scala:515:32] wire [2:0] _shadow_retry_a_io_deq_bits_tl_a_opcode; // @[DMA.scala:515:32] wire [2:0] _shadow_retry_a_io_deq_bits_tl_a_param; // @[DMA.scala:515:32] wire [3:0] _shadow_retry_a_io_deq_bits_tl_a_size; // @[DMA.scala:515:32] wire [5:0] _shadow_retry_a_io_deq_bits_tl_a_source; // @[DMA.scala:515:32] wire [31:0] _shadow_retry_a_io_deq_bits_tl_a_address; // @[DMA.scala:515:32] wire [15:0] _shadow_retry_a_io_deq_bits_tl_a_mask; // @[DMA.scala:515:32] wire [127:0] _shadow_retry_a_io_deq_bits_tl_a_data; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_tl_a_corrupt; // @[DMA.scala:515:32] wire [38:0] _shadow_retry_a_io_deq_bits_vaddr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_debug; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_cease; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_wfi; // @[DMA.scala:515:32] wire [31:0] _shadow_retry_a_io_deq_bits_status_isa; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_dprv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_dv; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_prv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_v; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sd; // @[DMA.scala:515:32] wire [22:0] _shadow_retry_a_io_deq_bits_status_zero2; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mpv; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_gva; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mbe; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sbe; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_sxl; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_uxl; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sd_rv32; // @[DMA.scala:515:32] wire [7:0] _shadow_retry_a_io_deq_bits_status_zero1; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tsr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tw; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_tvm; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mxr; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sum; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mprv; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_xs; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_fs; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_mpp; // @[DMA.scala:515:32] wire [1:0] _shadow_retry_a_io_deq_bits_status_vs; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_spp; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mpie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_ube; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_spie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_upie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_mie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_hie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_sie; // @[DMA.scala:515:32] wire _shadow_retry_a_io_deq_bits_status_uie; // @[DMA.scala:515:32] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DMA.scala:360:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DMA.scala:360:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DMA.scala:360:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DMA.scala:360:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DMA.scala:360:9] wire [5:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DMA.scala:360:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DMA.scala:360:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DMA.scala:360:9] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DMA.scala:360:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DMA.scala:360:9] wire io_req_valid_0 = io_req_valid; // @[DMA.scala:360:9] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[DMA.scala:360:9] wire [127:0] io_req_bits_data_0 = io_req_bits_data; // @[DMA.scala:360:9] wire [6:0] io_req_bits_len_0 = io_req_bits_len; // @[DMA.scala:360:9] wire [7:0] io_req_bits_block_0 = io_req_bits_block; // @[DMA.scala:360:9] wire io_req_bits_status_debug_0 = io_req_bits_status_debug; // @[DMA.scala:360:9] wire io_req_bits_status_cease_0 = io_req_bits_status_cease; // @[DMA.scala:360:9] wire io_req_bits_status_wfi_0 = io_req_bits_status_wfi; // @[DMA.scala:360:9] wire [31:0] io_req_bits_status_isa_0 = io_req_bits_status_isa; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_dprv_0 = io_req_bits_status_dprv; // @[DMA.scala:360:9] wire io_req_bits_status_dv_0 = io_req_bits_status_dv; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_prv_0 = io_req_bits_status_prv; // @[DMA.scala:360:9] wire io_req_bits_status_v_0 = io_req_bits_status_v; // @[DMA.scala:360:9] wire io_req_bits_status_sd_0 = io_req_bits_status_sd; // @[DMA.scala:360:9] wire [22:0] io_req_bits_status_zero2_0 = io_req_bits_status_zero2; // @[DMA.scala:360:9] wire io_req_bits_status_mpv_0 = io_req_bits_status_mpv; // @[DMA.scala:360:9] wire io_req_bits_status_gva_0 = io_req_bits_status_gva; // @[DMA.scala:360:9] wire io_req_bits_status_mbe_0 = io_req_bits_status_mbe; // @[DMA.scala:360:9] wire io_req_bits_status_sbe_0 = io_req_bits_status_sbe; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_sxl_0 = io_req_bits_status_sxl; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_uxl_0 = io_req_bits_status_uxl; // @[DMA.scala:360:9] wire io_req_bits_status_sd_rv32_0 = io_req_bits_status_sd_rv32; // @[DMA.scala:360:9] wire [7:0] io_req_bits_status_zero1_0 = io_req_bits_status_zero1; // @[DMA.scala:360:9] wire io_req_bits_status_tsr_0 = io_req_bits_status_tsr; // @[DMA.scala:360:9] wire io_req_bits_status_tw_0 = io_req_bits_status_tw; // @[DMA.scala:360:9] wire io_req_bits_status_tvm_0 = io_req_bits_status_tvm; // @[DMA.scala:360:9] wire io_req_bits_status_mxr_0 = io_req_bits_status_mxr; // @[DMA.scala:360:9] wire io_req_bits_status_sum_0 = io_req_bits_status_sum; // @[DMA.scala:360:9] wire io_req_bits_status_mprv_0 = io_req_bits_status_mprv; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_xs_0 = io_req_bits_status_xs; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_fs_0 = io_req_bits_status_fs; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_mpp_0 = io_req_bits_status_mpp; // @[DMA.scala:360:9] wire [1:0] io_req_bits_status_vs_0 = io_req_bits_status_vs; // @[DMA.scala:360:9] wire io_req_bits_status_spp_0 = io_req_bits_status_spp; // @[DMA.scala:360:9] wire io_req_bits_status_mpie_0 = io_req_bits_status_mpie; // @[DMA.scala:360:9] wire io_req_bits_status_ube_0 = io_req_bits_status_ube; // @[DMA.scala:360:9] wire io_req_bits_status_spie_0 = io_req_bits_status_spie; // @[DMA.scala:360:9] wire io_req_bits_status_upie_0 = io_req_bits_status_upie; // @[DMA.scala:360:9] wire io_req_bits_status_mie_0 = io_req_bits_status_mie; // @[DMA.scala:360:9] wire io_req_bits_status_hie_0 = io_req_bits_status_hie; // @[DMA.scala:360:9] wire io_req_bits_status_sie_0 = io_req_bits_status_sie; // @[DMA.scala:360:9] wire io_req_bits_status_uie_0 = io_req_bits_status_uie; // @[DMA.scala:360:9] wire io_req_bits_pool_en_0 = io_req_bits_pool_en; // @[DMA.scala:360:9] wire io_req_bits_store_en_0 = io_req_bits_store_en; // @[DMA.scala:360:9] wire io_tlb_resp_miss_0 = io_tlb_resp_miss; // @[DMA.scala:360:9] wire [31:0] io_tlb_resp_paddr_0 = io_tlb_resp_paddr; // @[DMA.scala:360:9] wire [39:0] io_tlb_resp_gpa_0 = io_tlb_resp_gpa; // @[DMA.scala:360:9] wire io_tlb_resp_pf_ld_0 = io_tlb_resp_pf_ld; // @[DMA.scala:360:9] wire io_tlb_resp_pf_st_0 = io_tlb_resp_pf_st; // @[DMA.scala:360:9] wire io_tlb_resp_pf_inst_0 = io_tlb_resp_pf_inst; // @[DMA.scala:360:9] wire io_tlb_resp_ae_ld_0 = io_tlb_resp_ae_ld; // @[DMA.scala:360:9] wire io_tlb_resp_ae_st_0 = io_tlb_resp_ae_st; // @[DMA.scala:360:9] wire io_tlb_resp_ae_inst_0 = io_tlb_resp_ae_inst; // @[DMA.scala:360:9] wire io_tlb_resp_cacheable_0 = io_tlb_resp_cacheable; // @[DMA.scala:360:9] wire io_tlb_resp_must_alloc_0 = io_tlb_resp_must_alloc; // @[DMA.scala:360:9] wire io_tlb_resp_prefetchable_0 = io_tlb_resp_prefetchable; // @[DMA.scala:360:9] wire [4:0] io_tlb_resp_cmd_0 = io_tlb_resp_cmd; // @[DMA.scala:360:9] wire io_flush_0 = io_flush; // @[DMA.scala:360:9] wire io_counter_external_reset_0 = io_counter_external_reset; // @[DMA.scala:360:9] wire io_tlb_req_bits_tlb_req_passthrough = 1'h0; // @[DMA.scala:360:9] wire io_tlb_req_bits_tlb_req_v = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gpa_is_pte = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_ld = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_st = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_gf_inst = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_ld = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_st = 1'h0; // @[DMA.scala:360:9] wire io_tlb_resp_ma_inst = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_0 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_1 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_2 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_3 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_4 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_5 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_6 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_7 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_8 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_9 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_10 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_11 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_12 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_13 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_14 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_15 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_16 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_17 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_18 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_19 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_20 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_24 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_25 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_26 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_27 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_28 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_29 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_30 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_31 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_32 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_33 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_34 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_35 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_36 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_37 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_38 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_39 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_40 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_41 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_42 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_43 = 1'h0; // @[DMA.scala:360:9] wire io_counter_event_signal_44 = 1'h0; // @[DMA.scala:360:9] wire write_packets_mask_16 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_17 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_18 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_19 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_20 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_21 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_22 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_23 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_24 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_25 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_26 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_27 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_28 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_29 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_30 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_31 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_32 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_33 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_34 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_35 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_36 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_37 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_38 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_39 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_40 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_41 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_42 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_43 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_44 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_45 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_46 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_47 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_48 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_49 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_50 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_51 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_52 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_53 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_54 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_55 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_56 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_57 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_58 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_59 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_60 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_61 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_62 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_63 = 1'h0; // @[DMA.scala:431:103] wire write_packets_0_mask_1_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_1_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_2_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_0_mask_3_15 = 1'h0; // @[DMA.scala:437:24] wire _write_packets_WIRE_1_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_1_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_2_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_3_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_4_1_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_1_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_2_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_3_15 = 1'h0; // @[DMA.scala:440:29] wire write_packets_too_early = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_5 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_7 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_1 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_10 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_12 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_2 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_15 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_17 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_3 = 1'h0; // @[DMA.scala:457:38] wire write_packets_mask_32_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_33_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_34_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_35_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_36_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_37_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_38_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_39_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_40_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_41_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_42_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_43_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_44_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_45_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_46_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_47_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_48_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_49_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_50_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_51_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_52_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_53_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_54_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_55_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_56_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_57_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_58_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_59_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_60_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_61_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_62_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_mask_63_1 = 1'h0; // @[DMA.scala:431:103] wire write_packets_1_mask_2_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_2_15 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_0 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_1 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_2 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_3 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_4 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_5 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_6 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_7 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_8 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_9 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_10 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_11 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_12 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_13 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_14 = 1'h0; // @[DMA.scala:437:24] wire write_packets_1_mask_3_15 = 1'h0; // @[DMA.scala:437:24] wire _write_packets_WIRE_7_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_7_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_0 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_1 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_2 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_3 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_4 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_5 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_6 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_7 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_8 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_9 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_10 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_11 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_12 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_13 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_14 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_8_15 = 1'h0; // @[DMA.scala:440:70] wire _write_packets_WIRE_9_2_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_2_15 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_0 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_1 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_2 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_3 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_4 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_5 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_6 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_7 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_8 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_9 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_10 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_11 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_12 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_13 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_14 = 1'h0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_3_15 = 1'h0; // @[DMA.scala:440:29] wire write_packets_too_early_5 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_30 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_32 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_6 = 1'h0; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_35 = 1'h0; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_37 = 1'h0; // @[DMA.scala:449:62] wire write_packets_too_early_7 = 1'h0; // @[DMA.scala:457:38] wire write_packets_too_early_11 = 1'h0; // @[DMA.scala:457:38] wire _best_write_packet_T_1_mask_2_0 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_1 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_2 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_3 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_4 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_5 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_6 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_7 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_8 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_9 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_10 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_11 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_12 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_13 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_14 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_2_15 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_0 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_1 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_2 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_3 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_4 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_5 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_6 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_7 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_8 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_9 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_10 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_11 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_12 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_13 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_14 = 1'h0; // @[DMA.scala:466:10] wire _best_write_packet_T_1_mask_3_15 = 1'h0; // @[DMA.scala:466:10] wire _putFull_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _putFull_legal_T_14 = 1'h0; // @[Parameters.scala:137:31] wire _putFull_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_48 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_53 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putFull_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _putFull_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _putFull_legal_T_69 = 1'h0; // @[Parameters.scala:686:26] wire putFull_corrupt = 1'h0; // @[Edges.scala:480:17] wire putFull_a_mask_sub_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_4_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_5_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_6_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_sub_7_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_8 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_8 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire putFull_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _putFull_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire _putPartial_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _putPartial_legal_T_14 = 1'h0; // @[Parameters.scala:137:31] wire _putPartial_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_48 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_53 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putPartial_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _putPartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _putPartial_legal_T_69 = 1'h0; // @[Parameters.scala:686:26] wire putPartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire untranslated_a_bits_tl_a_corrupt = 1'h0; // @[DMA.scala:506:30] wire _untranslated_a_bits_tl_a_T_corrupt = 1'h0; // @[DMA.scala:509:36] wire [1:0] io_tlb_req_bits_tlb_req_size = 2'h0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_tlb_req_prv = 2'h0; // @[DMA.scala:360:9] wire [1:0] io_tlb_resp_size = 2'h0; // @[DMA.scala:360:9] wire [1:0] _putFull_legal_T_15 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _putPartial_legal_T_15 = 2'h0; // @[Parameters.scala:137:41] wire [4:0] io_tlb_req_bits_tlb_req_cmd = 5'h1; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_0 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_1 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_2 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_3 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_4 = 32'h0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_6 = 32'h0; // @[DMA.scala:360:9] wire [31:0] putFull_address = 32'h0; // @[Edges.scala:480:17] wire [31:0] putPartial_address = 32'h0; // @[Edges.scala:500:17] wire [31:0] untranslated_a_bits_tl_a_address = 32'h0; // @[DMA.scala:506:30] wire [31:0] _untranslated_a_bits_tl_a_T_address = 32'h0; // @[DMA.scala:509:36] wire [2:0] putFull_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] putFull_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putPartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] untranslated_a_bits_tl_a_param = 3'h0; // @[DMA.scala:506:30] wire [2:0] _untranslated_a_bits_tl_a_T_param = 3'h0; // @[DMA.scala:509:36] wire [2:0] putPartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [32:0] _putFull_legal_T_65 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_66 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_65 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_66 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _putFull_legal_T_64 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _putPartial_legal_T_64 = 18'h10000; // @[Parameters.scala:137:41] wire _write_packets_mask_T_60 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_64 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_68 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_72 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_76 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_80 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_84 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_88 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_92 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_96 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_100 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_104 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_108 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_112 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_116 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_120 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_124 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_128 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_132 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_136 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_140 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_144 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_148 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_152 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_156 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_160 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_164 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_168 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_172 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_176 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_180 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_184 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_188 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_192 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_196 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_200 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_204 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_208 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_212 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_216 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_220 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_224 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_228 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_232 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_236 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_240 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_244 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_248 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_252 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T = 1'h1; // @[DMA.scala:449:43] wire _write_packets_left_shift_T_1 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_2 = 1'h1; // @[DMA.scala:449:62] wire _write_packets_right_shift_T_1 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_6 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_11 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_16 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_mask_T_380 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_384 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_388 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_392 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_396 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_400 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_404 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_408 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_412 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_416 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_420 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_424 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_428 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_432 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_436 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_440 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_444 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_448 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_452 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_456 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_460 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_464 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_468 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_472 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_476 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_480 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_484 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_488 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_492 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_496 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_500 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_504 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_mask_T_508 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_20 = 1'h1; // @[DMA.scala:449:43] wire _write_packets_right_shift_T_33 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_26 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_31 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_left_shift_T_36 = 1'h1; // @[DMA.scala:449:78] wire _write_packets_mask_T_764 = 1'h1; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_40 = 1'h1; // @[DMA.scala:449:43] wire _write_packets_right_shift_T_65 = 1'h1; // @[DMA.scala:453:57] wire _write_packets_left_shift_T_56 = 1'h1; // @[DMA.scala:449:78] wire _putFull_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putFull_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putFull_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putFull_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putFull_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putFull_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _putFull_legal_T_54 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_55 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_56 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_57 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_58 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_59 = 1'h1; // @[Parameters.scala:685:42] wire _putFull_legal_T_60 = 1'h1; // @[Parameters.scala:685:42] wire putFull_a_mask_sub_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire putFull_a_mask_nbit = 1'h1; // @[Misc.scala:211:20] wire putFull_a_mask_eq = 1'h1; // @[Misc.scala:214:27] wire _putPartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putPartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putPartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putPartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putPartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putPartial_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _putPartial_legal_T_54 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_55 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_56 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_57 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_58 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_59 = 1'h1; // @[Parameters.scala:685:42] wire _putPartial_legal_T_60 = 1'h1; // @[Parameters.scala:685:42] wire [32:0] _putFull_legal_T_50 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_51 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_52 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_50 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _putPartial_legal_T_51 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_52 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_46 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_47 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_46 = 33'h10000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_47 = 33'h10000000; // @[Parameters.scala:137:46] wire [29:0] _putFull_legal_T_45 = 30'h10000000; // @[Parameters.scala:137:41] wire [29:0] _putPartial_legal_T_45 = 30'h10000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_36 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_37 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_41 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_42 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_36 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_37 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_41 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_42 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _putFull_legal_T_35 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putFull_legal_T_40 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putPartial_legal_T_35 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _putPartial_legal_T_40 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_31 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_32 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_31 = 33'h2010000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_32 = 33'h2010000; // @[Parameters.scala:137:46] wire [26:0] _putFull_legal_T_30 = 27'h2010000; // @[Parameters.scala:137:41] wire [26:0] _putPartial_legal_T_30 = 27'h2010000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_26 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_27 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_26 = 33'h2000000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_27 = 33'h2000000; // @[Parameters.scala:137:46] wire [26:0] _putFull_legal_T_25 = 27'h2000000; // @[Parameters.scala:137:41] wire [26:0] _putPartial_legal_T_25 = 27'h2000000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_21 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_22 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_21 = 33'h100000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_22 = 33'h100000; // @[Parameters.scala:137:46] wire [21:0] _putFull_legal_T_20 = 22'h100000; // @[Parameters.scala:137:41] wire [21:0] _putPartial_legal_T_20 = 22'h100000; // @[Parameters.scala:137:41] wire [32:0] _putFull_legal_T_16 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_16 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_17 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_6 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putFull_legal_T_7 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_6 = 33'h3000; // @[Parameters.scala:137:46] wire [32:0] _putPartial_legal_T_7 = 33'h3000; // @[Parameters.scala:137:46] wire [14:0] _putFull_legal_T_5 = 15'h3000; // @[Parameters.scala:137:41] wire [14:0] _putPartial_legal_T_5 = 15'h3000; // @[Parameters.scala:137:41] wire [2:0] write_packets_2_lg_size = 3'h6; // @[DMA.scala:437:24] wire [6:0] write_packets_2_size = 7'h40; // @[DMA.scala:437:24] wire [5:0] write_packets_left_shift_2 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_3 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_6 = 6'h0; // @[DMA.scala:449:29] wire [5:0] write_packets_left_shift_7 = 6'h0; // @[DMA.scala:449:29] wire [2:0] write_packets_1_lg_size = 3'h5; // @[DMA.scala:437:24] wire [6:0] write_packets_1_size = 7'h20; // @[DMA.scala:437:24] wire [4:0] write_packets_left_shift_1 = 5'h0; // @[DMA.scala:449:29] wire [2:0] write_packets_0_lg_size = 3'h4; // @[DMA.scala:437:24] wire [6:0] write_packets_0_size = 7'h10; // @[DMA.scala:437:24] wire [16:0] _putFull_legal_T_63 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _putPartial_legal_T_63 = 17'h10000; // @[Parameters.scala:137:31] wire [31:0] _putFull_legal_T_49 = 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _putPartial_legal_T_49 = 32'h80000000; // @[Parameters.scala:137:31] wire [28:0] _putFull_legal_T_44 = 29'h10000000; // @[Parameters.scala:137:31] wire [28:0] _putPartial_legal_T_44 = 29'h10000000; // @[Parameters.scala:137:31] wire [27:0] _putFull_legal_T_34 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putFull_legal_T_39 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putPartial_legal_T_34 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _putPartial_legal_T_39 = 28'h8000000; // @[Parameters.scala:137:31] wire [25:0] _putFull_legal_T_29 = 26'h2010000; // @[Parameters.scala:137:31] wire [25:0] _putPartial_legal_T_29 = 26'h2010000; // @[Parameters.scala:137:31] wire [25:0] _putFull_legal_T_24 = 26'h2000000; // @[Parameters.scala:137:31] wire [25:0] _putPartial_legal_T_24 = 26'h2000000; // @[Parameters.scala:137:31] wire [20:0] _putFull_legal_T_19 = 21'h100000; // @[Parameters.scala:137:31] wire [20:0] _putPartial_legal_T_19 = 21'h100000; // @[Parameters.scala:137:31] wire [13:0] _putFull_legal_T_4 = 14'h3000; // @[Parameters.scala:137:31] wire [13:0] _putPartial_legal_T_4 = 14'h3000; // @[Parameters.scala:137:31] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DMA.scala:360:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DMA.scala:360:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DMA.scala:360:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DMA.scala:360:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DMA.scala:360:9] wire [5:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DMA.scala:360:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DMA.scala:360:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DMA.scala:360:9] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DMA.scala:360:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DMA.scala:360:9] wire state_machine_ready_for_req; // @[DMA.scala:401:47] wire [127:0] _pooled_v1_WIRE = io_req_bits_data_0; // @[DMA.scala:360:9, :593:43] wire _io_tlb_req_valid_T; // @[Decoupled.scala:51:35] wire io_counter_event_signal_22_0 = io_tlb_resp_miss_0; // @[DMA.scala:360:9] wire _io_busy_T_2; // @[DMA.scala:403:29] wire io_counter_event_signal_21_0 = |state; // @[DMA.scala:360:9, :380:24, :403:39] wire [2:0] auto_out_a_bits_opcode_0; // @[DMA.scala:360:9] wire [2:0] auto_out_a_bits_param_0; // @[DMA.scala:360:9] wire [3:0] auto_out_a_bits_size_0; // @[DMA.scala:360:9] wire [5:0] auto_out_a_bits_source_0; // @[DMA.scala:360:9] wire [31:0] auto_out_a_bits_address_0; // @[DMA.scala:360:9] wire [15:0] auto_out_a_bits_mask_0; // @[DMA.scala:360:9] wire [127:0] auto_out_a_bits_data_0; // @[DMA.scala:360:9] wire auto_out_a_bits_corrupt_0; // @[DMA.scala:360:9] wire auto_out_a_valid_0; // @[DMA.scala:360:9] wire auto_out_d_ready_0; // @[DMA.scala:360:9] wire io_req_ready_0; // @[DMA.scala:360:9] wire [39:0] io_tlb_req_bits_tlb_req_vaddr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_debug_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_cease_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_wfi_0; // @[DMA.scala:360:9] wire [31:0] io_tlb_req_bits_status_isa_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_dprv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_dv_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_prv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_v_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sd_0; // @[DMA.scala:360:9] wire [22:0] io_tlb_req_bits_status_zero2_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mpv_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_gva_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mbe_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sbe_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_sxl_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_uxl_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sd_rv32_0; // @[DMA.scala:360:9] wire [7:0] io_tlb_req_bits_status_zero1_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tsr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tw_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_tvm_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mxr_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sum_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mprv_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_xs_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_fs_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_mpp_0; // @[DMA.scala:360:9] wire [1:0] io_tlb_req_bits_status_vs_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_spp_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mpie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_ube_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_spie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_upie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_mie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_hie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_sie_0; // @[DMA.scala:360:9] wire io_tlb_req_bits_status_uie_0; // @[DMA.scala:360:9] wire io_tlb_req_valid_0; // @[DMA.scala:360:9] wire io_counter_event_signal_23_0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_5_0; // @[DMA.scala:360:9] wire [31:0] io_counter_external_values_7_0; // @[DMA.scala:360:9] wire io_busy_0; // @[DMA.scala:360:9] wire _nodeOut_a_valid_T_1; // @[DMA.scala:547:44] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DMA.scala:360:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DMA.scala:360:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DMA.scala:360:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DMA.scala:360:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DMA.scala:360:9] wire [31:0] _nodeOut_a_bits_address_T; // @[Util.scala:91:8] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DMA.scala:360:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DMA.scala:360:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DMA.scala:360:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[DMA.scala:360:9] wire _nodeOut_d_ready_T; // @[DMA.scala:551:28] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DMA.scala:360:9] reg [39:0] req_vaddr; // @[DMA.scala:382:18] reg [127:0] req_data; // @[DMA.scala:382:18] reg [6:0] req_len; // @[DMA.scala:382:18] reg [7:0] req_block; // @[DMA.scala:382:18] reg req_status_debug; // @[DMA.scala:382:18] wire untranslated_a_bits_status_debug = req_status_debug; // @[DMA.scala:382:18, :506:30] reg req_status_cease; // @[DMA.scala:382:18] wire untranslated_a_bits_status_cease = req_status_cease; // @[DMA.scala:382:18, :506:30] reg req_status_wfi; // @[DMA.scala:382:18] wire untranslated_a_bits_status_wfi = req_status_wfi; // @[DMA.scala:382:18, :506:30] reg [31:0] req_status_isa; // @[DMA.scala:382:18] wire [31:0] untranslated_a_bits_status_isa = req_status_isa; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_dprv; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_dprv = req_status_dprv; // @[DMA.scala:382:18, :506:30] reg req_status_dv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_dv = req_status_dv; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_prv; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_prv = req_status_prv; // @[DMA.scala:382:18, :506:30] reg req_status_v; // @[DMA.scala:382:18] wire untranslated_a_bits_status_v = req_status_v; // @[DMA.scala:382:18, :506:30] reg req_status_sd; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sd = req_status_sd; // @[DMA.scala:382:18, :506:30] reg [22:0] req_status_zero2; // @[DMA.scala:382:18] wire [22:0] untranslated_a_bits_status_zero2 = req_status_zero2; // @[DMA.scala:382:18, :506:30] reg req_status_mpv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mpv = req_status_mpv; // @[DMA.scala:382:18, :506:30] reg req_status_gva; // @[DMA.scala:382:18] wire untranslated_a_bits_status_gva = req_status_gva; // @[DMA.scala:382:18, :506:30] reg req_status_mbe; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mbe = req_status_mbe; // @[DMA.scala:382:18, :506:30] reg req_status_sbe; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sbe = req_status_sbe; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_sxl; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_sxl = req_status_sxl; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_uxl; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_uxl = req_status_uxl; // @[DMA.scala:382:18, :506:30] reg req_status_sd_rv32; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sd_rv32 = req_status_sd_rv32; // @[DMA.scala:382:18, :506:30] reg [7:0] req_status_zero1; // @[DMA.scala:382:18] wire [7:0] untranslated_a_bits_status_zero1 = req_status_zero1; // @[DMA.scala:382:18, :506:30] reg req_status_tsr; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tsr = req_status_tsr; // @[DMA.scala:382:18, :506:30] reg req_status_tw; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tw = req_status_tw; // @[DMA.scala:382:18, :506:30] reg req_status_tvm; // @[DMA.scala:382:18] wire untranslated_a_bits_status_tvm = req_status_tvm; // @[DMA.scala:382:18, :506:30] reg req_status_mxr; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mxr = req_status_mxr; // @[DMA.scala:382:18, :506:30] reg req_status_sum; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sum = req_status_sum; // @[DMA.scala:382:18, :506:30] reg req_status_mprv; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mprv = req_status_mprv; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_xs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_xs = req_status_xs; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_fs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_fs = req_status_fs; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_mpp; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_mpp = req_status_mpp; // @[DMA.scala:382:18, :506:30] reg [1:0] req_status_vs; // @[DMA.scala:382:18] wire [1:0] untranslated_a_bits_status_vs = req_status_vs; // @[DMA.scala:382:18, :506:30] reg req_status_spp; // @[DMA.scala:382:18] wire untranslated_a_bits_status_spp = req_status_spp; // @[DMA.scala:382:18, :506:30] reg req_status_mpie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mpie = req_status_mpie; // @[DMA.scala:382:18, :506:30] reg req_status_ube; // @[DMA.scala:382:18] wire untranslated_a_bits_status_ube = req_status_ube; // @[DMA.scala:382:18, :506:30] reg req_status_spie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_spie = req_status_spie; // @[DMA.scala:382:18, :506:30] reg req_status_upie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_upie = req_status_upie; // @[DMA.scala:382:18, :506:30] reg req_status_mie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_mie = req_status_mie; // @[DMA.scala:382:18, :506:30] reg req_status_hie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_hie = req_status_hie; // @[DMA.scala:382:18, :506:30] reg req_status_sie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_sie = req_status_sie; // @[DMA.scala:382:18, :506:30] reg req_status_uie; // @[DMA.scala:382:18] wire untranslated_a_bits_status_uie = req_status_uie; // @[DMA.scala:382:18, :506:30] reg req_pool_en; // @[DMA.scala:382:18] reg req_store_en; // @[DMA.scala:382:18] reg [127:0] data_blocks_0; // @[DMA.scala:385:26] reg [127:0] data_blocks_1; // @[DMA.scala:385:26] reg [127:0] data_blocks_2; // @[DMA.scala:385:26] reg [127:0] data_blocks_3; // @[DMA.scala:385:26] reg [127:0] data_single_block; // @[DMA.scala:386:32] wire [127:0] _pooled_v2_WIRE = data_single_block; // @[DMA.scala:386:32, :594:44] wire _data_T = req_block == 8'h0; // @[DMA.scala:382:18, :387:30] wire [255:0] data_lo = {data_blocks_1, data_blocks_0}; // @[DMA.scala:385:26, :387:70] wire [255:0] data_hi = {data_blocks_3, data_blocks_2}; // @[DMA.scala:385:26, :387:70] wire [511:0] _data_T_1 = {data_hi, data_lo}; // @[DMA.scala:387:70] wire [511:0] data = _data_T ? {384'h0, data_single_block} : _data_T_1; // @[DMA.scala:386:32, :387:{19,30,70}] reg [6:0] bytesSent; // @[DMA.scala:389:24] wire [7:0] _GEN = {1'h0, bytesSent}; // @[DMA.scala:389:24, :390:29] wire [7:0] _bytesLeft_T = {1'h0, req_len} - _GEN; // @[DMA.scala:382:18, :390:29] wire [6:0] bytesLeft = _bytesLeft_T[6:0]; // @[DMA.scala:390:29] reg [63:0] xactBusy; // @[DMA.scala:392:27] wire [63:0] _xactOnehot_T = ~xactBusy; // @[DMA.scala:392:27, :393:40] wire _xactOnehot_T_1 = _xactOnehot_T[0]; // @[OneHot.scala:85:71] wire _xactOnehot_T_2 = _xactOnehot_T[1]; // @[OneHot.scala:85:71] wire _xactOnehot_T_3 = _xactOnehot_T[2]; // @[OneHot.scala:85:71] wire _xactOnehot_T_4 = _xactOnehot_T[3]; // @[OneHot.scala:85:71] wire _xactOnehot_T_5 = _xactOnehot_T[4]; // @[OneHot.scala:85:71] wire _xactOnehot_T_6 = _xactOnehot_T[5]; // @[OneHot.scala:85:71] wire _xactOnehot_T_7 = _xactOnehot_T[6]; // @[OneHot.scala:85:71] wire _xactOnehot_T_8 = _xactOnehot_T[7]; // @[OneHot.scala:85:71] wire _xactOnehot_T_9 = _xactOnehot_T[8]; // @[OneHot.scala:85:71] wire _xactOnehot_T_10 = _xactOnehot_T[9]; // @[OneHot.scala:85:71] wire _xactOnehot_T_11 = _xactOnehot_T[10]; // @[OneHot.scala:85:71] wire _xactOnehot_T_12 = _xactOnehot_T[11]; // @[OneHot.scala:85:71] wire _xactOnehot_T_13 = _xactOnehot_T[12]; // @[OneHot.scala:85:71] wire _xactOnehot_T_14 = _xactOnehot_T[13]; // @[OneHot.scala:85:71] wire _xactOnehot_T_15 = _xactOnehot_T[14]; // @[OneHot.scala:85:71] wire _xactOnehot_T_16 = _xactOnehot_T[15]; // @[OneHot.scala:85:71] wire _xactOnehot_T_17 = _xactOnehot_T[16]; // @[OneHot.scala:85:71] wire _xactOnehot_T_18 = _xactOnehot_T[17]; // @[OneHot.scala:85:71] wire _xactOnehot_T_19 = _xactOnehot_T[18]; // @[OneHot.scala:85:71] wire _xactOnehot_T_20 = _xactOnehot_T[19]; // @[OneHot.scala:85:71] wire _xactOnehot_T_21 = _xactOnehot_T[20]; // @[OneHot.scala:85:71] wire _xactOnehot_T_22 = _xactOnehot_T[21]; // @[OneHot.scala:85:71] wire _xactOnehot_T_23 = _xactOnehot_T[22]; // @[OneHot.scala:85:71] wire _xactOnehot_T_24 = _xactOnehot_T[23]; // @[OneHot.scala:85:71] wire _xactOnehot_T_25 = _xactOnehot_T[24]; // @[OneHot.scala:85:71] wire _xactOnehot_T_26 = _xactOnehot_T[25]; // @[OneHot.scala:85:71] wire _xactOnehot_T_27 = _xactOnehot_T[26]; // @[OneHot.scala:85:71] wire _xactOnehot_T_28 = _xactOnehot_T[27]; // @[OneHot.scala:85:71] wire _xactOnehot_T_29 = _xactOnehot_T[28]; // @[OneHot.scala:85:71] wire _xactOnehot_T_30 = _xactOnehot_T[29]; // @[OneHot.scala:85:71] wire _xactOnehot_T_31 = _xactOnehot_T[30]; // @[OneHot.scala:85:71] wire _xactOnehot_T_32 = _xactOnehot_T[31]; // @[OneHot.scala:85:71] wire _xactOnehot_T_33 = _xactOnehot_T[32]; // @[OneHot.scala:85:71] wire _xactOnehot_T_34 = _xactOnehot_T[33]; // @[OneHot.scala:85:71] wire _xactOnehot_T_35 = _xactOnehot_T[34]; // @[OneHot.scala:85:71] wire _xactOnehot_T_36 = _xactOnehot_T[35]; // @[OneHot.scala:85:71] wire _xactOnehot_T_37 = _xactOnehot_T[36]; // @[OneHot.scala:85:71] wire _xactOnehot_T_38 = _xactOnehot_T[37]; // @[OneHot.scala:85:71] wire _xactOnehot_T_39 = _xactOnehot_T[38]; // @[OneHot.scala:85:71] wire _xactOnehot_T_40 = _xactOnehot_T[39]; // @[OneHot.scala:85:71] wire _xactOnehot_T_41 = _xactOnehot_T[40]; // @[OneHot.scala:85:71] wire _xactOnehot_T_42 = _xactOnehot_T[41]; // @[OneHot.scala:85:71] wire _xactOnehot_T_43 = _xactOnehot_T[42]; // @[OneHot.scala:85:71] wire _xactOnehot_T_44 = _xactOnehot_T[43]; // @[OneHot.scala:85:71] wire _xactOnehot_T_45 = _xactOnehot_T[44]; // @[OneHot.scala:85:71] wire _xactOnehot_T_46 = _xactOnehot_T[45]; // @[OneHot.scala:85:71] wire _xactOnehot_T_47 = _xactOnehot_T[46]; // @[OneHot.scala:85:71] wire _xactOnehot_T_48 = _xactOnehot_T[47]; // @[OneHot.scala:85:71] wire _xactOnehot_T_49 = _xactOnehot_T[48]; // @[OneHot.scala:85:71] wire _xactOnehot_T_50 = _xactOnehot_T[49]; // @[OneHot.scala:85:71] wire _xactOnehot_T_51 = _xactOnehot_T[50]; // @[OneHot.scala:85:71] wire _xactOnehot_T_52 = _xactOnehot_T[51]; // @[OneHot.scala:85:71] wire _xactOnehot_T_53 = _xactOnehot_T[52]; // @[OneHot.scala:85:71] wire _xactOnehot_T_54 = _xactOnehot_T[53]; // @[OneHot.scala:85:71] wire _xactOnehot_T_55 = _xactOnehot_T[54]; // @[OneHot.scala:85:71] wire _xactOnehot_T_56 = _xactOnehot_T[55]; // @[OneHot.scala:85:71] wire _xactOnehot_T_57 = _xactOnehot_T[56]; // @[OneHot.scala:85:71] wire _xactOnehot_T_58 = _xactOnehot_T[57]; // @[OneHot.scala:85:71] wire _xactOnehot_T_59 = _xactOnehot_T[58]; // @[OneHot.scala:85:71] wire _xactOnehot_T_60 = _xactOnehot_T[59]; // @[OneHot.scala:85:71] wire _xactOnehot_T_61 = _xactOnehot_T[60]; // @[OneHot.scala:85:71] wire _xactOnehot_T_62 = _xactOnehot_T[61]; // @[OneHot.scala:85:71] wire _xactOnehot_T_63 = _xactOnehot_T[62]; // @[OneHot.scala:85:71] wire _xactOnehot_T_64 = _xactOnehot_T[63]; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_65 = {_xactOnehot_T_64, 63'h0}; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_66 = _xactOnehot_T_63 ? 64'h4000000000000000 : _xactOnehot_T_65; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_67 = _xactOnehot_T_62 ? 64'h2000000000000000 : _xactOnehot_T_66; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_68 = _xactOnehot_T_61 ? 64'h1000000000000000 : _xactOnehot_T_67; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_69 = _xactOnehot_T_60 ? 64'h800000000000000 : _xactOnehot_T_68; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_70 = _xactOnehot_T_59 ? 64'h400000000000000 : _xactOnehot_T_69; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_71 = _xactOnehot_T_58 ? 64'h200000000000000 : _xactOnehot_T_70; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_72 = _xactOnehot_T_57 ? 64'h100000000000000 : _xactOnehot_T_71; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_73 = _xactOnehot_T_56 ? 64'h80000000000000 : _xactOnehot_T_72; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_74 = _xactOnehot_T_55 ? 64'h40000000000000 : _xactOnehot_T_73; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_75 = _xactOnehot_T_54 ? 64'h20000000000000 : _xactOnehot_T_74; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_76 = _xactOnehot_T_53 ? 64'h10000000000000 : _xactOnehot_T_75; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_77 = _xactOnehot_T_52 ? 64'h8000000000000 : _xactOnehot_T_76; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_78 = _xactOnehot_T_51 ? 64'h4000000000000 : _xactOnehot_T_77; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_79 = _xactOnehot_T_50 ? 64'h2000000000000 : _xactOnehot_T_78; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_80 = _xactOnehot_T_49 ? 64'h1000000000000 : _xactOnehot_T_79; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_81 = _xactOnehot_T_48 ? 64'h800000000000 : _xactOnehot_T_80; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_82 = _xactOnehot_T_47 ? 64'h400000000000 : _xactOnehot_T_81; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_83 = _xactOnehot_T_46 ? 64'h200000000000 : _xactOnehot_T_82; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_84 = _xactOnehot_T_45 ? 64'h100000000000 : _xactOnehot_T_83; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_85 = _xactOnehot_T_44 ? 64'h80000000000 : _xactOnehot_T_84; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_86 = _xactOnehot_T_43 ? 64'h40000000000 : _xactOnehot_T_85; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_87 = _xactOnehot_T_42 ? 64'h20000000000 : _xactOnehot_T_86; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_88 = _xactOnehot_T_41 ? 64'h10000000000 : _xactOnehot_T_87; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_89 = _xactOnehot_T_40 ? 64'h8000000000 : _xactOnehot_T_88; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_90 = _xactOnehot_T_39 ? 64'h4000000000 : _xactOnehot_T_89; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_91 = _xactOnehot_T_38 ? 64'h2000000000 : _xactOnehot_T_90; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_92 = _xactOnehot_T_37 ? 64'h1000000000 : _xactOnehot_T_91; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_93 = _xactOnehot_T_36 ? 64'h800000000 : _xactOnehot_T_92; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_94 = _xactOnehot_T_35 ? 64'h400000000 : _xactOnehot_T_93; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_95 = _xactOnehot_T_34 ? 64'h200000000 : _xactOnehot_T_94; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_96 = _xactOnehot_T_33 ? 64'h100000000 : _xactOnehot_T_95; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_97 = _xactOnehot_T_32 ? 64'h80000000 : _xactOnehot_T_96; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_98 = _xactOnehot_T_31 ? 64'h40000000 : _xactOnehot_T_97; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_99 = _xactOnehot_T_30 ? 64'h20000000 : _xactOnehot_T_98; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_100 = _xactOnehot_T_29 ? 64'h10000000 : _xactOnehot_T_99; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_101 = _xactOnehot_T_28 ? 64'h8000000 : _xactOnehot_T_100; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_102 = _xactOnehot_T_27 ? 64'h4000000 : _xactOnehot_T_101; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_103 = _xactOnehot_T_26 ? 64'h2000000 : _xactOnehot_T_102; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_104 = _xactOnehot_T_25 ? 64'h1000000 : _xactOnehot_T_103; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_105 = _xactOnehot_T_24 ? 64'h800000 : _xactOnehot_T_104; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_106 = _xactOnehot_T_23 ? 64'h400000 : _xactOnehot_T_105; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_107 = _xactOnehot_T_22 ? 64'h200000 : _xactOnehot_T_106; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_108 = _xactOnehot_T_21 ? 64'h100000 : _xactOnehot_T_107; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_109 = _xactOnehot_T_20 ? 64'h80000 : _xactOnehot_T_108; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_110 = _xactOnehot_T_19 ? 64'h40000 : _xactOnehot_T_109; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_111 = _xactOnehot_T_18 ? 64'h20000 : _xactOnehot_T_110; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_112 = _xactOnehot_T_17 ? 64'h10000 : _xactOnehot_T_111; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_113 = _xactOnehot_T_16 ? 64'h8000 : _xactOnehot_T_112; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_114 = _xactOnehot_T_15 ? 64'h4000 : _xactOnehot_T_113; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_115 = _xactOnehot_T_14 ? 64'h2000 : _xactOnehot_T_114; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_116 = _xactOnehot_T_13 ? 64'h1000 : _xactOnehot_T_115; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_117 = _xactOnehot_T_12 ? 64'h800 : _xactOnehot_T_116; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_118 = _xactOnehot_T_11 ? 64'h400 : _xactOnehot_T_117; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_119 = _xactOnehot_T_10 ? 64'h200 : _xactOnehot_T_118; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_120 = _xactOnehot_T_9 ? 64'h100 : _xactOnehot_T_119; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_121 = _xactOnehot_T_8 ? 64'h80 : _xactOnehot_T_120; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_122 = _xactOnehot_T_7 ? 64'h40 : _xactOnehot_T_121; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_123 = _xactOnehot_T_6 ? 64'h20 : _xactOnehot_T_122; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_124 = _xactOnehot_T_5 ? 64'h10 : _xactOnehot_T_123; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_125 = _xactOnehot_T_4 ? 64'h8 : _xactOnehot_T_124; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_126 = _xactOnehot_T_3 ? 64'h4 : _xactOnehot_T_125; // @[OneHot.scala:85:71] wire [63:0] _xactOnehot_T_127 = _xactOnehot_T_2 ? 64'h2 : _xactOnehot_T_126; // @[OneHot.scala:85:71] wire [63:0] xactOnehot = _xactOnehot_T_1 ? 64'h1 : _xactOnehot_T_127; // @[OneHot.scala:85:71] wire [31:0] xactId_hi = xactOnehot[63:32]; // @[OneHot.scala:30:18] wire [31:0] xactId_lo = xactOnehot[31:0]; // @[OneHot.scala:31:18] wire _xactId_T = |xactId_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _xactId_T_1 = xactId_hi | xactId_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] xactId_hi_1 = _xactId_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] xactId_lo_1 = _xactId_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_2 = |xactId_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _xactId_T_3 = xactId_hi_1 | xactId_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] xactId_hi_2 = _xactId_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] xactId_lo_2 = _xactId_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_4 = |xactId_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _xactId_T_5 = xactId_hi_2 | xactId_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] xactId_hi_3 = _xactId_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] xactId_lo_3 = _xactId_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_6 = |xactId_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _xactId_T_7 = xactId_hi_3 | xactId_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] xactId_hi_4 = _xactId_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] xactId_lo_4 = _xactId_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_8 = |xactId_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _xactId_T_9 = xactId_hi_4 | xactId_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _xactId_T_10 = _xactId_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _xactId_T_11 = {_xactId_T_8, _xactId_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _xactId_T_12 = {_xactId_T_6, _xactId_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _xactId_T_13 = {_xactId_T_4, _xactId_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _xactId_T_14 = {_xactId_T_2, _xactId_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] xactId = {_xactId_T, _xactId_T_14}; // @[OneHot.scala:32:{10,14}] wire _xactBusy_fire_T_2; // @[DMA.scala:507:42] wire xactBusy_fire; // @[DMA.scala:396:33] wire [63:0] _xactBusy_add_T = 64'h1 << xactId; // @[OneHot.scala:32:10] wire [63:0] xactBusy_add = xactBusy_fire ? _xactBusy_add_T : 64'h0; // @[DMA.scala:396:33, :397:{27,48}] wire _xactBusy_remove_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire [63:0] _xactBusy_remove_T_1 = 64'h1 << nodeOut_d_bits_source; // @[DMA.scala:398:48] wire [63:0] _xactBusy_remove_T_2 = _xactBusy_remove_T ? _xactBusy_remove_T_1 : 64'h0; // @[Decoupled.scala:51:35] wire [63:0] xactBusy_remove = ~_xactBusy_remove_T_2; // @[DMA.scala:398:{27,31}] wire [63:0] _xactBusy_T = xactBusy | xactBusy_add; // @[DMA.scala:392:27, :397:27, :399:27] wire [63:0] _xactBusy_T_1 = _xactBusy_T & xactBusy_remove; // @[DMA.scala:398:27, :399:{27,43}] wire _state_machine_ready_for_req_T = state == 2'h0; // @[DMA.scala:380:24, :401:54] assign io_req_ready_0 = state_machine_ready_for_req; // @[DMA.scala:360:9, :401:47] wire _io_busy_T = |xactBusy; // @[DMA.scala:392:27, :403:25] wire _io_busy_T_1 = |state; // @[DMA.scala:380:24, :403:39] assign _io_busy_T_2 = _io_busy_T | _io_busy_T_1; // @[DMA.scala:403:{25,29,39}] assign io_busy_0 = _io_busy_T_2; // @[DMA.scala:360:9, :403:29] wire [34:0] _write_packets_vaddr_aligned_to_size_T = req_vaddr[38:4]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size = {_write_packets_vaddr_aligned_to_size_T, 4'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_0_vaddr = write_packets_vaddr_aligned_to_size; // @[DMA.scala:428:61, :437:24] wire [3:0] write_packets_vaddr_offset = req_vaddr[3:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T = write_packets_vaddr_offset == 4'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_0 = {1'h0, bytesLeft}; // @[DMA.scala:390:29, :431:90] wire [7:0] _GEN_1 = {4'h0, write_packets_vaddr_offset} + _GEN_0; // @[DMA.scala:429:42, :431:90] wire [7:0] _write_packets_mask_T_1; // @[DMA.scala:431:90] assign _write_packets_mask_T_1 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_5; // @[DMA.scala:431:90] assign _write_packets_mask_T_5 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_9; // @[DMA.scala:431:90] assign _write_packets_mask_T_9 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_13; // @[DMA.scala:431:90] assign _write_packets_mask_T_13 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_17; // @[DMA.scala:431:90] assign _write_packets_mask_T_17 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_21; // @[DMA.scala:431:90] assign _write_packets_mask_T_21 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_25; // @[DMA.scala:431:90] assign _write_packets_mask_T_25 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_29; // @[DMA.scala:431:90] assign _write_packets_mask_T_29 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_33; // @[DMA.scala:431:90] assign _write_packets_mask_T_33 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_37; // @[DMA.scala:431:90] assign _write_packets_mask_T_37 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_41; // @[DMA.scala:431:90] assign _write_packets_mask_T_41 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_45; // @[DMA.scala:431:90] assign _write_packets_mask_T_45 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_49; // @[DMA.scala:431:90] assign _write_packets_mask_T_49 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_53; // @[DMA.scala:431:90] assign _write_packets_mask_T_53 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_57; // @[DMA.scala:431:90] assign _write_packets_mask_T_57 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_61; // @[DMA.scala:431:90] assign _write_packets_mask_T_61 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_65; // @[DMA.scala:431:90] assign _write_packets_mask_T_65 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_69; // @[DMA.scala:431:90] assign _write_packets_mask_T_69 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_73; // @[DMA.scala:431:90] assign _write_packets_mask_T_73 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_77; // @[DMA.scala:431:90] assign _write_packets_mask_T_77 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_81; // @[DMA.scala:431:90] assign _write_packets_mask_T_81 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_85; // @[DMA.scala:431:90] assign _write_packets_mask_T_85 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_89; // @[DMA.scala:431:90] assign _write_packets_mask_T_89 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_93; // @[DMA.scala:431:90] assign _write_packets_mask_T_93 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_97; // @[DMA.scala:431:90] assign _write_packets_mask_T_97 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_101; // @[DMA.scala:431:90] assign _write_packets_mask_T_101 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_105; // @[DMA.scala:431:90] assign _write_packets_mask_T_105 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_109; // @[DMA.scala:431:90] assign _write_packets_mask_T_109 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_113; // @[DMA.scala:431:90] assign _write_packets_mask_T_113 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_117; // @[DMA.scala:431:90] assign _write_packets_mask_T_117 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_121; // @[DMA.scala:431:90] assign _write_packets_mask_T_121 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_125; // @[DMA.scala:431:90] assign _write_packets_mask_T_125 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_129; // @[DMA.scala:431:90] assign _write_packets_mask_T_129 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_133; // @[DMA.scala:431:90] assign _write_packets_mask_T_133 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_137; // @[DMA.scala:431:90] assign _write_packets_mask_T_137 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_141; // @[DMA.scala:431:90] assign _write_packets_mask_T_141 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_145; // @[DMA.scala:431:90] assign _write_packets_mask_T_145 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_149; // @[DMA.scala:431:90] assign _write_packets_mask_T_149 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_153; // @[DMA.scala:431:90] assign _write_packets_mask_T_153 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_157; // @[DMA.scala:431:90] assign _write_packets_mask_T_157 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_161; // @[DMA.scala:431:90] assign _write_packets_mask_T_161 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_165; // @[DMA.scala:431:90] assign _write_packets_mask_T_165 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_169; // @[DMA.scala:431:90] assign _write_packets_mask_T_169 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_173; // @[DMA.scala:431:90] assign _write_packets_mask_T_173 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_177; // @[DMA.scala:431:90] assign _write_packets_mask_T_177 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_181; // @[DMA.scala:431:90] assign _write_packets_mask_T_181 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_185; // @[DMA.scala:431:90] assign _write_packets_mask_T_185 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_189; // @[DMA.scala:431:90] assign _write_packets_mask_T_189 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_193; // @[DMA.scala:431:90] assign _write_packets_mask_T_193 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_197; // @[DMA.scala:431:90] assign _write_packets_mask_T_197 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_201; // @[DMA.scala:431:90] assign _write_packets_mask_T_201 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_205; // @[DMA.scala:431:90] assign _write_packets_mask_T_205 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_209; // @[DMA.scala:431:90] assign _write_packets_mask_T_209 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_213; // @[DMA.scala:431:90] assign _write_packets_mask_T_213 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_217; // @[DMA.scala:431:90] assign _write_packets_mask_T_217 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_221; // @[DMA.scala:431:90] assign _write_packets_mask_T_221 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_225; // @[DMA.scala:431:90] assign _write_packets_mask_T_225 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_229; // @[DMA.scala:431:90] assign _write_packets_mask_T_229 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_233; // @[DMA.scala:431:90] assign _write_packets_mask_T_233 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_237; // @[DMA.scala:431:90] assign _write_packets_mask_T_237 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_241; // @[DMA.scala:431:90] assign _write_packets_mask_T_241 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_245; // @[DMA.scala:431:90] assign _write_packets_mask_T_245 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_249; // @[DMA.scala:431:90] assign _write_packets_mask_T_249 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_253; // @[DMA.scala:431:90] assign _write_packets_mask_T_253 = _GEN_1; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T = _GEN_1; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T; // @[DMA.scala:453:44] assign _write_packets_right_shift_T = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_2; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_2 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_5; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_5 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T; // @[DMA.scala:458:37] assign _write_packets_too_late_T = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_8; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_8 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_10; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_10 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_13; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_13 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_1; // @[DMA.scala:458:37] assign _write_packets_too_late_T_1 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_16; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_16 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_18; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_18 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_21; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_21 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_2; // @[DMA.scala:458:37] assign _write_packets_too_late_T_2 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_24; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_24 = _GEN_1; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_26; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_26 = _GEN_1; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_29; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_29 = _GEN_1; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_3; // @[DMA.scala:458:37] assign _write_packets_too_late_T_3 = _GEN_1; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_2 = |_write_packets_mask_T_1; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_3 = _write_packets_mask_T & _write_packets_mask_T_2; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0 = _write_packets_mask_T_3; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_0 = write_packets_mask_0; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_4 = write_packets_vaddr_offset < 4'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_6 = |(_write_packets_mask_T_5[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_7 = _write_packets_mask_T_4 & _write_packets_mask_T_6; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1 = _write_packets_mask_T_7; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_1 = write_packets_mask_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_8 = write_packets_vaddr_offset < 4'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_10 = _write_packets_mask_T_9 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_11 = _write_packets_mask_T_8 & _write_packets_mask_T_10; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2 = _write_packets_mask_T_11; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_2 = write_packets_mask_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_12 = write_packets_vaddr_offset < 4'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_14 = |(_write_packets_mask_T_13[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_15 = _write_packets_mask_T_12 & _write_packets_mask_T_14; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3 = _write_packets_mask_T_15; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_3 = write_packets_mask_3; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_16 = write_packets_vaddr_offset < 4'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_18 = _write_packets_mask_T_17 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_19 = _write_packets_mask_T_16 & _write_packets_mask_T_18; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4 = _write_packets_mask_T_19; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_4 = write_packets_mask_4; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_20 = write_packets_vaddr_offset < 4'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_22 = _write_packets_mask_T_21 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_23 = _write_packets_mask_T_20 & _write_packets_mask_T_22; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5 = _write_packets_mask_T_23; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5 = write_packets_mask_5; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_24 = write_packets_vaddr_offset < 4'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_26 = _write_packets_mask_T_25 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_27 = _write_packets_mask_T_24 & _write_packets_mask_T_26; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6 = _write_packets_mask_T_27; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6 = write_packets_mask_6; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_28 = ~(write_packets_vaddr_offset[3]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_30 = |(_write_packets_mask_T_29[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_31 = _write_packets_mask_T_28 & _write_packets_mask_T_30; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7 = _write_packets_mask_T_31; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_7 = write_packets_mask_7; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_32 = write_packets_vaddr_offset < 4'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_34 = _write_packets_mask_T_33 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_35 = _write_packets_mask_T_32 & _write_packets_mask_T_34; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8 = _write_packets_mask_T_35; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_8 = write_packets_mask_8; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_36 = write_packets_vaddr_offset < 4'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_38 = _write_packets_mask_T_37 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_39 = _write_packets_mask_T_36 & _write_packets_mask_T_38; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9 = _write_packets_mask_T_39; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_9 = write_packets_mask_9; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_40 = write_packets_vaddr_offset < 4'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_42 = _write_packets_mask_T_41 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_43 = _write_packets_mask_T_40 & _write_packets_mask_T_42; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10 = _write_packets_mask_T_43; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10 = write_packets_mask_10; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_44 = write_packets_vaddr_offset[3:2] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_46 = _write_packets_mask_T_45 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_47 = _write_packets_mask_T_44 & _write_packets_mask_T_46; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11 = _write_packets_mask_T_47; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11 = write_packets_mask_11; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_48 = write_packets_vaddr_offset < 4'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_50 = _write_packets_mask_T_49 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_51 = _write_packets_mask_T_48 & _write_packets_mask_T_50; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12 = _write_packets_mask_T_51; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12 = write_packets_mask_12; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_52 = write_packets_vaddr_offset[3:1] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_54 = _write_packets_mask_T_53 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_55 = _write_packets_mask_T_52 & _write_packets_mask_T_54; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13 = _write_packets_mask_T_55; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13 = write_packets_mask_13; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_56 = write_packets_vaddr_offset != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_58 = _write_packets_mask_T_57 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_59 = _write_packets_mask_T_56 & _write_packets_mask_T_58; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14 = _write_packets_mask_T_59; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_14 = write_packets_mask_14; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_62 = |(_write_packets_mask_T_61[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_63 = _write_packets_mask_T_62; // @[DMA.scala:431:{68,75}] wire write_packets_mask_15 = _write_packets_mask_T_63; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_15 = write_packets_mask_15; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_66 = _write_packets_mask_T_65 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_67 = _write_packets_mask_T_66; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_70 = _write_packets_mask_T_69 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_71 = _write_packets_mask_T_70; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_74 = _write_packets_mask_T_73 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_75 = _write_packets_mask_T_74; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_78 = _write_packets_mask_T_77 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_79 = _write_packets_mask_T_78; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_82 = _write_packets_mask_T_81 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_83 = _write_packets_mask_T_82; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_86 = _write_packets_mask_T_85 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_87 = _write_packets_mask_T_86; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_90 = _write_packets_mask_T_89 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_91 = _write_packets_mask_T_90; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_94 = _write_packets_mask_T_93 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_95 = _write_packets_mask_T_94; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_98 = _write_packets_mask_T_97 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_99 = _write_packets_mask_T_98; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_102 = _write_packets_mask_T_101 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_103 = _write_packets_mask_T_102; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_106 = _write_packets_mask_T_105 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_107 = _write_packets_mask_T_106; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_110 = _write_packets_mask_T_109 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_111 = _write_packets_mask_T_110; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_114 = _write_packets_mask_T_113 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_115 = _write_packets_mask_T_114; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_118 = _write_packets_mask_T_117 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_119 = _write_packets_mask_T_118; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_122 = _write_packets_mask_T_121 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_123 = _write_packets_mask_T_122; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_126 = |(_write_packets_mask_T_125[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_127 = _write_packets_mask_T_126; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_130 = _write_packets_mask_T_129 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_131 = _write_packets_mask_T_130; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_134 = _write_packets_mask_T_133 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_135 = _write_packets_mask_T_134; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_138 = _write_packets_mask_T_137 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_139 = _write_packets_mask_T_138; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_142 = _write_packets_mask_T_141 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_143 = _write_packets_mask_T_142; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_146 = _write_packets_mask_T_145 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_147 = _write_packets_mask_T_146; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_150 = _write_packets_mask_T_149 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_151 = _write_packets_mask_T_150; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_154 = _write_packets_mask_T_153 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_155 = _write_packets_mask_T_154; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_158 = _write_packets_mask_T_157 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_159 = _write_packets_mask_T_158; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_162 = _write_packets_mask_T_161 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_163 = _write_packets_mask_T_162; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_166 = _write_packets_mask_T_165 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_167 = _write_packets_mask_T_166; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_170 = _write_packets_mask_T_169 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_171 = _write_packets_mask_T_170; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_174 = _write_packets_mask_T_173 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_175 = _write_packets_mask_T_174; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_178 = _write_packets_mask_T_177 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_179 = _write_packets_mask_T_178; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_182 = _write_packets_mask_T_181 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_183 = _write_packets_mask_T_182; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_186 = _write_packets_mask_T_185 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_187 = _write_packets_mask_T_186; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_190 = _write_packets_mask_T_189 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_191 = _write_packets_mask_T_190; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_194 = _write_packets_mask_T_193 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_195 = _write_packets_mask_T_194; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_198 = _write_packets_mask_T_197 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_199 = _write_packets_mask_T_198; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_202 = _write_packets_mask_T_201 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_203 = _write_packets_mask_T_202; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_206 = _write_packets_mask_T_205 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_207 = _write_packets_mask_T_206; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_210 = _write_packets_mask_T_209 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_211 = _write_packets_mask_T_210; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_214 = _write_packets_mask_T_213 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_215 = _write_packets_mask_T_214; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_218 = _write_packets_mask_T_217 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_219 = _write_packets_mask_T_218; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_222 = _write_packets_mask_T_221 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_223 = _write_packets_mask_T_222; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_226 = _write_packets_mask_T_225 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_227 = _write_packets_mask_T_226; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_230 = _write_packets_mask_T_229 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_231 = _write_packets_mask_T_230; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_234 = _write_packets_mask_T_233 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_235 = _write_packets_mask_T_234; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_238 = _write_packets_mask_T_237 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_239 = _write_packets_mask_T_238; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_242 = _write_packets_mask_T_241 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_243 = _write_packets_mask_T_242; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_246 = _write_packets_mask_T_245 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_247 = _write_packets_mask_T_246; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_250 = _write_packets_mask_T_249 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_251 = _write_packets_mask_T_250; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_254 = |(_write_packets_mask_T_253[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_255 = _write_packets_mask_T_254; // @[DMA.scala:431:{68,75}] wire _write_packets_bytes_written_T_1 = _write_packets_bytes_written_T > 8'h10; // @[DMA.scala:434:{26,39}] wire [5:0] _GEN_2 = {2'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :434:50] wire [5:0] _write_packets_bytes_written_T_2 = 6'h10 - _GEN_2; // @[DMA.scala:434:50] wire [4:0] _write_packets_bytes_written_T_3 = _write_packets_bytes_written_T_2[4:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written = _write_packets_bytes_written_T_1 ? {2'h0, _write_packets_bytes_written_T_3} : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_0_bytes_written = write_packets_bytes_written; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_4_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_4_0_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_14; // @[DMA.scala:442:47] wire write_packets_0_mask_0_0; // @[DMA.scala:437:24] wire write_packets_0_mask_0_1; // @[DMA.scala:437:24] wire write_packets_0_mask_0_2; // @[DMA.scala:437:24] wire write_packets_0_mask_0_3; // @[DMA.scala:437:24] wire write_packets_0_mask_0_4; // @[DMA.scala:437:24] wire write_packets_0_mask_0_5; // @[DMA.scala:437:24] wire write_packets_0_mask_0_6; // @[DMA.scala:437:24] wire write_packets_0_mask_0_7; // @[DMA.scala:437:24] wire write_packets_0_mask_0_8; // @[DMA.scala:437:24] wire write_packets_0_mask_0_9; // @[DMA.scala:437:24] wire write_packets_0_mask_0_10; // @[DMA.scala:437:24] wire write_packets_0_mask_0_11; // @[DMA.scala:437:24] wire write_packets_0_mask_0_12; // @[DMA.scala:437:24] wire write_packets_0_mask_0_13; // @[DMA.scala:437:24] wire write_packets_0_mask_0_14; // @[DMA.scala:437:24] wire write_packets_0_mask_0_15; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_0_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_0_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_4_0_0 = _write_packets_WIRE_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_1 = _write_packets_WIRE_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_2 = _write_packets_WIRE_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_3 = _write_packets_WIRE_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_4 = _write_packets_WIRE_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_5 = _write_packets_WIRE_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_6 = _write_packets_WIRE_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_7 = _write_packets_WIRE_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_8 = _write_packets_WIRE_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_9 = _write_packets_WIRE_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_10 = _write_packets_WIRE_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_11 = _write_packets_WIRE_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_12 = _write_packets_WIRE_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_13 = _write_packets_WIRE_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_14 = _write_packets_WIRE_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_4_0_15 = _write_packets_WIRE_15; // @[DMA.scala:440:{29,70}] assign write_packets_0_mask_0_0 = _write_packets_WIRE_4_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_1 = _write_packets_WIRE_4_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_2 = _write_packets_WIRE_4_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_3 = _write_packets_WIRE_4_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_4 = _write_packets_WIRE_4_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_5 = _write_packets_WIRE_4_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_6 = _write_packets_WIRE_4_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_7 = _write_packets_WIRE_4_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_8 = _write_packets_WIRE_4_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_9 = _write_packets_WIRE_4_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_10 = _write_packets_WIRE_4_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_11 = _write_packets_WIRE_4_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_12 = _write_packets_WIRE_4_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_13 = _write_packets_WIRE_4_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_14 = _write_packets_WIRE_4_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_0_mask_0_15 = _write_packets_WIRE_4_0_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T = write_packets_mask_0 & write_packets_mask_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_1 = _write_packets_packet_is_full_T & write_packets_mask_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_2 = _write_packets_packet_is_full_T_1 & write_packets_mask_3; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_3 = _write_packets_packet_is_full_T_2 & write_packets_mask_4; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_4 = _write_packets_packet_is_full_T_3 & write_packets_mask_5; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_5 = _write_packets_packet_is_full_T_4 & write_packets_mask_6; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_6 = _write_packets_packet_is_full_T_5 & write_packets_mask_7; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_7 = _write_packets_packet_is_full_T_6 & write_packets_mask_8; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_8 = _write_packets_packet_is_full_T_7 & write_packets_mask_9; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_9 = _write_packets_packet_is_full_T_8 & write_packets_mask_10; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_10 = _write_packets_packet_is_full_T_9 & write_packets_mask_11; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_11 = _write_packets_packet_is_full_T_10 & write_packets_mask_12; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_12 = _write_packets_packet_is_full_T_11 & write_packets_mask_13; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_13 = _write_packets_packet_is_full_T_12 & write_packets_mask_14; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_14 = _write_packets_packet_is_full_T_13 & write_packets_mask_15; // @[DMA.scala:431:103, :442:47] assign write_packets_0_is_full = _write_packets_packet_is_full_T_14; // @[DMA.scala:437:24, :442:47] wire [4:0] _write_packets_left_shift_T_3 = {1'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :450:24] wire [3:0] _write_packets_left_shift_T_4 = _write_packets_left_shift_T_3[3:0]; // @[DMA.scala:450:24] wire [3:0] write_packets_left_shift = _write_packets_left_shift_T_4; // @[DMA.scala:449:29, :450:24] wire _write_packets_right_shift_T_3 = _write_packets_right_shift_T_2 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_4 = _write_packets_right_shift_T_3; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_6 = 9'h10 - {1'h0, _write_packets_right_shift_T_5}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_7 = _write_packets_right_shift_T_6[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift = _write_packets_right_shift_T_4 ? _write_packets_right_shift_T_7 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late = _write_packets_too_late_T == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T = write_packets_too_late; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_1 = {5'h0, write_packets_left_shift} + {1'h0, write_packets_right_shift}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_3 = _write_packets_packet_bytes_written_per_beat_0_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_4 = _write_packets_packet_bytes_written_per_beat_0_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [5:0] _write_packets_left_shift_T_8 = _GEN_2 - 6'h10; // @[DMA.scala:434:50, :450:24] wire [4:0] _write_packets_left_shift_T_9 = _write_packets_left_shift_T_8[4:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_9 = |(_write_packets_right_shift_T_8[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_11 = _write_packets_right_shift_T_10 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_12 = _write_packets_right_shift_T_9 & _write_packets_right_shift_T_11; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_14 = 9'h20 - {1'h0, _write_packets_right_shift_T_13}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_15 = _write_packets_right_shift_T_14[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_1 = _write_packets_right_shift_T_12 ? _write_packets_right_shift_T_15 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_1 = _write_packets_too_late_T_1 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T = write_packets_too_late_1; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_1 = {1'h0, write_packets_right_shift_1}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_3 = _write_packets_packet_bytes_written_per_beat_1_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_4 = _write_packets_packet_bytes_written_per_beat_1_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _GEN_3 = {3'h0, write_packets_vaddr_offset}; // @[DMA.scala:429:42, :450:24] wire [6:0] _write_packets_left_shift_T_13 = _GEN_3 - 7'h20; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_14 = _write_packets_left_shift_T_13[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_17 = |(_write_packets_right_shift_T_16[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_19 = _write_packets_right_shift_T_18 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_20 = _write_packets_right_shift_T_17 & _write_packets_right_shift_T_19; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_22 = 9'h30 - {1'h0, _write_packets_right_shift_T_21}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_23 = _write_packets_right_shift_T_22[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_2 = _write_packets_right_shift_T_20 ? _write_packets_right_shift_T_23 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_2 = _write_packets_too_late_T_2 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T = write_packets_too_late_2; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_1 = {1'h0, write_packets_right_shift_2}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_3 = _write_packets_packet_bytes_written_per_beat_2_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_4 = _write_packets_packet_bytes_written_per_beat_2_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_18 = _GEN_3 - 7'h30; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_19 = _write_packets_left_shift_T_18[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_25 = _write_packets_right_shift_T_24 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_27 = _write_packets_right_shift_T_26 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_28 = _write_packets_right_shift_T_25 & _write_packets_right_shift_T_27; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_30 = 9'h40 - {1'h0, _write_packets_right_shift_T_29}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_31 = _write_packets_right_shift_T_30[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_3 = _write_packets_right_shift_T_28 ? _write_packets_right_shift_T_31 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_3 = _write_packets_too_late_T_3 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T = write_packets_too_late_3; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_1 = {1'h0, write_packets_right_shift_3}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_2 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_1}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_3 = _write_packets_packet_bytes_written_per_beat_3_T_2[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_4 = _write_packets_packet_bytes_written_per_beat_3_T ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_3; // @[DMA.scala:460:{17,28,58}] assign write_packets_0_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_4[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [33:0] _write_packets_vaddr_aligned_to_size_T_1 = req_vaddr[38:5]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size_1 = {_write_packets_vaddr_aligned_to_size_T_1, 5'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_1_vaddr = write_packets_vaddr_aligned_to_size_1; // @[DMA.scala:428:61, :437:24] wire [4:0] write_packets_vaddr_offset_1 = req_vaddr[4:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T_256 = write_packets_vaddr_offset_1 == 5'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_4 = {3'h0, write_packets_vaddr_offset_1} + _GEN_0; // @[DMA.scala:429:42, :431:90] wire [7:0] _write_packets_mask_T_257; // @[DMA.scala:431:90] assign _write_packets_mask_T_257 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_261; // @[DMA.scala:431:90] assign _write_packets_mask_T_261 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_265; // @[DMA.scala:431:90] assign _write_packets_mask_T_265 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_269; // @[DMA.scala:431:90] assign _write_packets_mask_T_269 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_273; // @[DMA.scala:431:90] assign _write_packets_mask_T_273 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_277; // @[DMA.scala:431:90] assign _write_packets_mask_T_277 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_281; // @[DMA.scala:431:90] assign _write_packets_mask_T_281 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_285; // @[DMA.scala:431:90] assign _write_packets_mask_T_285 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_289; // @[DMA.scala:431:90] assign _write_packets_mask_T_289 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_293; // @[DMA.scala:431:90] assign _write_packets_mask_T_293 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_297; // @[DMA.scala:431:90] assign _write_packets_mask_T_297 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_301; // @[DMA.scala:431:90] assign _write_packets_mask_T_301 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_305; // @[DMA.scala:431:90] assign _write_packets_mask_T_305 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_309; // @[DMA.scala:431:90] assign _write_packets_mask_T_309 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_313; // @[DMA.scala:431:90] assign _write_packets_mask_T_313 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_317; // @[DMA.scala:431:90] assign _write_packets_mask_T_317 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_321; // @[DMA.scala:431:90] assign _write_packets_mask_T_321 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_325; // @[DMA.scala:431:90] assign _write_packets_mask_T_325 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_329; // @[DMA.scala:431:90] assign _write_packets_mask_T_329 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_333; // @[DMA.scala:431:90] assign _write_packets_mask_T_333 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_337; // @[DMA.scala:431:90] assign _write_packets_mask_T_337 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_341; // @[DMA.scala:431:90] assign _write_packets_mask_T_341 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_345; // @[DMA.scala:431:90] assign _write_packets_mask_T_345 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_349; // @[DMA.scala:431:90] assign _write_packets_mask_T_349 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_353; // @[DMA.scala:431:90] assign _write_packets_mask_T_353 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_357; // @[DMA.scala:431:90] assign _write_packets_mask_T_357 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_361; // @[DMA.scala:431:90] assign _write_packets_mask_T_361 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_365; // @[DMA.scala:431:90] assign _write_packets_mask_T_365 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_369; // @[DMA.scala:431:90] assign _write_packets_mask_T_369 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_373; // @[DMA.scala:431:90] assign _write_packets_mask_T_373 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_377; // @[DMA.scala:431:90] assign _write_packets_mask_T_377 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_381; // @[DMA.scala:431:90] assign _write_packets_mask_T_381 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_385; // @[DMA.scala:431:90] assign _write_packets_mask_T_385 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_389; // @[DMA.scala:431:90] assign _write_packets_mask_T_389 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_393; // @[DMA.scala:431:90] assign _write_packets_mask_T_393 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_397; // @[DMA.scala:431:90] assign _write_packets_mask_T_397 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_401; // @[DMA.scala:431:90] assign _write_packets_mask_T_401 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_405; // @[DMA.scala:431:90] assign _write_packets_mask_T_405 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_409; // @[DMA.scala:431:90] assign _write_packets_mask_T_409 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_413; // @[DMA.scala:431:90] assign _write_packets_mask_T_413 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_417; // @[DMA.scala:431:90] assign _write_packets_mask_T_417 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_421; // @[DMA.scala:431:90] assign _write_packets_mask_T_421 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_425; // @[DMA.scala:431:90] assign _write_packets_mask_T_425 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_429; // @[DMA.scala:431:90] assign _write_packets_mask_T_429 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_433; // @[DMA.scala:431:90] assign _write_packets_mask_T_433 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_437; // @[DMA.scala:431:90] assign _write_packets_mask_T_437 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_441; // @[DMA.scala:431:90] assign _write_packets_mask_T_441 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_445; // @[DMA.scala:431:90] assign _write_packets_mask_T_445 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_449; // @[DMA.scala:431:90] assign _write_packets_mask_T_449 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_453; // @[DMA.scala:431:90] assign _write_packets_mask_T_453 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_457; // @[DMA.scala:431:90] assign _write_packets_mask_T_457 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_461; // @[DMA.scala:431:90] assign _write_packets_mask_T_461 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_465; // @[DMA.scala:431:90] assign _write_packets_mask_T_465 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_469; // @[DMA.scala:431:90] assign _write_packets_mask_T_469 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_473; // @[DMA.scala:431:90] assign _write_packets_mask_T_473 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_477; // @[DMA.scala:431:90] assign _write_packets_mask_T_477 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_481; // @[DMA.scala:431:90] assign _write_packets_mask_T_481 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_485; // @[DMA.scala:431:90] assign _write_packets_mask_T_485 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_489; // @[DMA.scala:431:90] assign _write_packets_mask_T_489 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_493; // @[DMA.scala:431:90] assign _write_packets_mask_T_493 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_497; // @[DMA.scala:431:90] assign _write_packets_mask_T_497 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_501; // @[DMA.scala:431:90] assign _write_packets_mask_T_501 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_505; // @[DMA.scala:431:90] assign _write_packets_mask_T_505 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_509; // @[DMA.scala:431:90] assign _write_packets_mask_T_509 = _GEN_4; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T_4; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T_4 = _GEN_4; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T_32; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_32 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_34; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_34 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_37; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_37 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_4; // @[DMA.scala:458:37] assign _write_packets_too_late_T_4 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_40; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_40 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_42; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_42 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_45; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_45 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_5; // @[DMA.scala:458:37] assign _write_packets_too_late_T_5 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_48; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_48 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_50; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_50 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_53; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_53 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_6; // @[DMA.scala:458:37] assign _write_packets_too_late_T_6 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_56; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_56 = _GEN_4; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_58; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_58 = _GEN_4; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_61; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_61 = _GEN_4; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_7; // @[DMA.scala:458:37] assign _write_packets_too_late_T_7 = _GEN_4; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_258 = |_write_packets_mask_T_257; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_259 = _write_packets_mask_T_256 & _write_packets_mask_T_258; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0_1 = _write_packets_mask_T_259; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_0 = write_packets_mask_0_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_260 = write_packets_vaddr_offset_1 < 5'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_262 = |(_write_packets_mask_T_261[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_263 = _write_packets_mask_T_260 & _write_packets_mask_T_262; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1_1 = _write_packets_mask_T_263; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_1 = write_packets_mask_1_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_264 = write_packets_vaddr_offset_1 < 5'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_266 = _write_packets_mask_T_265 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_267 = _write_packets_mask_T_264 & _write_packets_mask_T_266; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2_1 = _write_packets_mask_T_267; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_2 = write_packets_mask_2_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_268 = write_packets_vaddr_offset_1 < 5'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_270 = |(_write_packets_mask_T_269[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_271 = _write_packets_mask_T_268 & _write_packets_mask_T_270; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3_1 = _write_packets_mask_T_271; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_3 = write_packets_mask_3_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_272 = write_packets_vaddr_offset_1 < 5'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_274 = _write_packets_mask_T_273 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_275 = _write_packets_mask_T_272 & _write_packets_mask_T_274; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4_1 = _write_packets_mask_T_275; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_4 = write_packets_mask_4_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_276 = write_packets_vaddr_offset_1 < 5'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_278 = _write_packets_mask_T_277 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_279 = _write_packets_mask_T_276 & _write_packets_mask_T_278; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5_1 = _write_packets_mask_T_279; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_5 = write_packets_mask_5_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_280 = write_packets_vaddr_offset_1 < 5'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_282 = _write_packets_mask_T_281 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_283 = _write_packets_mask_T_280 & _write_packets_mask_T_282; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6_1 = _write_packets_mask_T_283; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_6 = write_packets_mask_6_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_284 = write_packets_vaddr_offset_1 < 5'h8; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_286 = |(_write_packets_mask_T_285[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_287 = _write_packets_mask_T_284 & _write_packets_mask_T_286; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7_1 = _write_packets_mask_T_287; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_7 = write_packets_mask_7_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_288 = write_packets_vaddr_offset_1 < 5'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_290 = _write_packets_mask_T_289 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_291 = _write_packets_mask_T_288 & _write_packets_mask_T_290; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8_1 = _write_packets_mask_T_291; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_8 = write_packets_mask_8_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_292 = write_packets_vaddr_offset_1 < 5'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_294 = _write_packets_mask_T_293 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_295 = _write_packets_mask_T_292 & _write_packets_mask_T_294; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9_1 = _write_packets_mask_T_295; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_9 = write_packets_mask_9_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_296 = write_packets_vaddr_offset_1 < 5'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_298 = _write_packets_mask_T_297 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_299 = _write_packets_mask_T_296 & _write_packets_mask_T_298; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10_1 = _write_packets_mask_T_299; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_10 = write_packets_mask_10_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_300 = write_packets_vaddr_offset_1 < 5'hC; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_302 = _write_packets_mask_T_301 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_303 = _write_packets_mask_T_300 & _write_packets_mask_T_302; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11_1 = _write_packets_mask_T_303; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_11 = write_packets_mask_11_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_304 = write_packets_vaddr_offset_1 < 5'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_306 = _write_packets_mask_T_305 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_307 = _write_packets_mask_T_304 & _write_packets_mask_T_306; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12_1 = _write_packets_mask_T_307; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_12 = write_packets_mask_12_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_308 = write_packets_vaddr_offset_1 < 5'hE; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_310 = _write_packets_mask_T_309 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_311 = _write_packets_mask_T_308 & _write_packets_mask_T_310; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13_1 = _write_packets_mask_T_311; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_13 = write_packets_mask_13_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_312 = write_packets_vaddr_offset_1 < 5'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_314 = _write_packets_mask_T_313 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_315 = _write_packets_mask_T_312 & _write_packets_mask_T_314; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14_1 = _write_packets_mask_T_315; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_14 = write_packets_mask_14_1; // @[DMA.scala:431:103, :440:70] wire write_packets_too_early_4 = write_packets_vaddr_offset_1[4]; // @[DMA.scala:429:42, :431:52, :457:38] wire _write_packets_left_shift_T_25 = write_packets_vaddr_offset_1[4]; // @[DMA.scala:429:42, :431:52, :449:43] wire _write_packets_mask_T_316 = ~(write_packets_vaddr_offset_1[4]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_318 = |(_write_packets_mask_T_317[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_319 = _write_packets_mask_T_316 & _write_packets_mask_T_318; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_15_1 = _write_packets_mask_T_319; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_5_15 = write_packets_mask_15_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_320 = write_packets_vaddr_offset_1 < 5'h11; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_322 = _write_packets_mask_T_321 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_323 = _write_packets_mask_T_320 & _write_packets_mask_T_322; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_16_1 = _write_packets_mask_T_323; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_0 = write_packets_mask_16_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_324 = write_packets_vaddr_offset_1 < 5'h12; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_326 = _write_packets_mask_T_325 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_327 = _write_packets_mask_T_324 & _write_packets_mask_T_326; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_17_1 = _write_packets_mask_T_327; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_1 = write_packets_mask_17_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_328 = write_packets_vaddr_offset_1 < 5'h13; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_330 = _write_packets_mask_T_329 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_331 = _write_packets_mask_T_328 & _write_packets_mask_T_330; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_18_1 = _write_packets_mask_T_331; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_2 = write_packets_mask_18_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_332 = write_packets_vaddr_offset_1 < 5'h14; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_334 = _write_packets_mask_T_333 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_335 = _write_packets_mask_T_332 & _write_packets_mask_T_334; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_19_1 = _write_packets_mask_T_335; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_3 = write_packets_mask_19_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_336 = write_packets_vaddr_offset_1 < 5'h15; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_338 = _write_packets_mask_T_337 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_339 = _write_packets_mask_T_336 & _write_packets_mask_T_338; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_20_1 = _write_packets_mask_T_339; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_4 = write_packets_mask_20_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_340 = write_packets_vaddr_offset_1 < 5'h16; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_342 = _write_packets_mask_T_341 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_343 = _write_packets_mask_T_340 & _write_packets_mask_T_342; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_21_1 = _write_packets_mask_T_343; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_5 = write_packets_mask_21_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_344 = write_packets_vaddr_offset_1 < 5'h17; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_346 = _write_packets_mask_T_345 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_347 = _write_packets_mask_T_344 & _write_packets_mask_T_346; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_22_1 = _write_packets_mask_T_347; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_6 = write_packets_mask_22_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_348 = write_packets_vaddr_offset_1[4:3] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_350 = _write_packets_mask_T_349 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_351 = _write_packets_mask_T_348 & _write_packets_mask_T_350; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_23_1 = _write_packets_mask_T_351; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_7 = write_packets_mask_23_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_352 = write_packets_vaddr_offset_1 < 5'h19; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_354 = _write_packets_mask_T_353 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_355 = _write_packets_mask_T_352 & _write_packets_mask_T_354; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_24_1 = _write_packets_mask_T_355; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_8 = write_packets_mask_24_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_356 = write_packets_vaddr_offset_1 < 5'h1A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_358 = _write_packets_mask_T_357 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_359 = _write_packets_mask_T_356 & _write_packets_mask_T_358; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_25_1 = _write_packets_mask_T_359; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_9 = write_packets_mask_25_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_360 = write_packets_vaddr_offset_1 < 5'h1B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_362 = _write_packets_mask_T_361 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_363 = _write_packets_mask_T_360 & _write_packets_mask_T_362; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_26_1 = _write_packets_mask_T_363; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_10 = write_packets_mask_26_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_364 = write_packets_vaddr_offset_1[4:2] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_366 = _write_packets_mask_T_365 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_367 = _write_packets_mask_T_364 & _write_packets_mask_T_366; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_27_1 = _write_packets_mask_T_367; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_11 = write_packets_mask_27_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_368 = write_packets_vaddr_offset_1 < 5'h1D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_370 = _write_packets_mask_T_369 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_371 = _write_packets_mask_T_368 & _write_packets_mask_T_370; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_28_1 = _write_packets_mask_T_371; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_12 = write_packets_mask_28_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_372 = write_packets_vaddr_offset_1[4:1] != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_374 = _write_packets_mask_T_373 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_375 = _write_packets_mask_T_372 & _write_packets_mask_T_374; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_29_1 = _write_packets_mask_T_375; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_13 = write_packets_mask_29_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_376 = write_packets_vaddr_offset_1 != 5'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_378 = _write_packets_mask_T_377 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_379 = _write_packets_mask_T_376 & _write_packets_mask_T_378; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_30_1 = _write_packets_mask_T_379; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_14 = write_packets_mask_30_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_382 = |(_write_packets_mask_T_381[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_383 = _write_packets_mask_T_382; // @[DMA.scala:431:{68,75}] wire write_packets_mask_31_1 = _write_packets_mask_T_383; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_6_15 = write_packets_mask_31_1; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_386 = _write_packets_mask_T_385 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_387 = _write_packets_mask_T_386; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_390 = _write_packets_mask_T_389 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_391 = _write_packets_mask_T_390; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_394 = _write_packets_mask_T_393 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_395 = _write_packets_mask_T_394; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_398 = _write_packets_mask_T_397 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_399 = _write_packets_mask_T_398; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_402 = _write_packets_mask_T_401 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_403 = _write_packets_mask_T_402; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_406 = _write_packets_mask_T_405 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_407 = _write_packets_mask_T_406; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_410 = _write_packets_mask_T_409 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_411 = _write_packets_mask_T_410; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_414 = _write_packets_mask_T_413 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_415 = _write_packets_mask_T_414; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_418 = _write_packets_mask_T_417 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_419 = _write_packets_mask_T_418; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_422 = _write_packets_mask_T_421 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_423 = _write_packets_mask_T_422; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_426 = _write_packets_mask_T_425 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_427 = _write_packets_mask_T_426; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_430 = _write_packets_mask_T_429 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_431 = _write_packets_mask_T_430; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_434 = _write_packets_mask_T_433 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_435 = _write_packets_mask_T_434; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_438 = _write_packets_mask_T_437 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_439 = _write_packets_mask_T_438; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_442 = _write_packets_mask_T_441 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_443 = _write_packets_mask_T_442; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_446 = _write_packets_mask_T_445 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_447 = _write_packets_mask_T_446; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_450 = _write_packets_mask_T_449 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_451 = _write_packets_mask_T_450; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_454 = _write_packets_mask_T_453 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_455 = _write_packets_mask_T_454; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_458 = _write_packets_mask_T_457 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_459 = _write_packets_mask_T_458; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_462 = _write_packets_mask_T_461 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_463 = _write_packets_mask_T_462; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_466 = _write_packets_mask_T_465 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_467 = _write_packets_mask_T_466; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_470 = _write_packets_mask_T_469 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_471 = _write_packets_mask_T_470; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_474 = _write_packets_mask_T_473 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_475 = _write_packets_mask_T_474; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_478 = _write_packets_mask_T_477 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_479 = _write_packets_mask_T_478; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_482 = _write_packets_mask_T_481 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_483 = _write_packets_mask_T_482; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_486 = _write_packets_mask_T_485 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_487 = _write_packets_mask_T_486; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_490 = _write_packets_mask_T_489 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_491 = _write_packets_mask_T_490; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_494 = _write_packets_mask_T_493 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_495 = _write_packets_mask_T_494; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_498 = _write_packets_mask_T_497 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_499 = _write_packets_mask_T_498; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_502 = _write_packets_mask_T_501 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_503 = _write_packets_mask_T_502; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_506 = _write_packets_mask_T_505 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_507 = _write_packets_mask_T_506; // @[DMA.scala:431:{68,75}] wire _write_packets_mask_T_510 = |(_write_packets_mask_T_509[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_511 = _write_packets_mask_T_510; // @[DMA.scala:431:{68,75}] wire _write_packets_bytes_written_T_5 = _write_packets_bytes_written_T_4 > 8'h20; // @[DMA.scala:434:{26,39}] wire [6:0] _GEN_5 = {2'h0, write_packets_vaddr_offset_1}; // @[DMA.scala:429:42, :434:50] wire [6:0] _write_packets_bytes_written_T_6 = 7'h20 - _GEN_5; // @[DMA.scala:434:50] wire [5:0] _write_packets_bytes_written_T_7 = _write_packets_bytes_written_T_6[5:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written_1 = _write_packets_bytes_written_T_5 ? {1'h0, _write_packets_bytes_written_T_7} : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_1_bytes_written = write_packets_bytes_written_1; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_9_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_0_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_9_1_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_45; // @[DMA.scala:442:47] wire write_packets_1_mask_0_0; // @[DMA.scala:437:24] wire write_packets_1_mask_0_1; // @[DMA.scala:437:24] wire write_packets_1_mask_0_2; // @[DMA.scala:437:24] wire write_packets_1_mask_0_3; // @[DMA.scala:437:24] wire write_packets_1_mask_0_4; // @[DMA.scala:437:24] wire write_packets_1_mask_0_5; // @[DMA.scala:437:24] wire write_packets_1_mask_0_6; // @[DMA.scala:437:24] wire write_packets_1_mask_0_7; // @[DMA.scala:437:24] wire write_packets_1_mask_0_8; // @[DMA.scala:437:24] wire write_packets_1_mask_0_9; // @[DMA.scala:437:24] wire write_packets_1_mask_0_10; // @[DMA.scala:437:24] wire write_packets_1_mask_0_11; // @[DMA.scala:437:24] wire write_packets_1_mask_0_12; // @[DMA.scala:437:24] wire write_packets_1_mask_0_13; // @[DMA.scala:437:24] wire write_packets_1_mask_0_14; // @[DMA.scala:437:24] wire write_packets_1_mask_0_15; // @[DMA.scala:437:24] wire write_packets_1_mask_1_0; // @[DMA.scala:437:24] wire write_packets_1_mask_1_1; // @[DMA.scala:437:24] wire write_packets_1_mask_1_2; // @[DMA.scala:437:24] wire write_packets_1_mask_1_3; // @[DMA.scala:437:24] wire write_packets_1_mask_1_4; // @[DMA.scala:437:24] wire write_packets_1_mask_1_5; // @[DMA.scala:437:24] wire write_packets_1_mask_1_6; // @[DMA.scala:437:24] wire write_packets_1_mask_1_7; // @[DMA.scala:437:24] wire write_packets_1_mask_1_8; // @[DMA.scala:437:24] wire write_packets_1_mask_1_9; // @[DMA.scala:437:24] wire write_packets_1_mask_1_10; // @[DMA.scala:437:24] wire write_packets_1_mask_1_11; // @[DMA.scala:437:24] wire write_packets_1_mask_1_12; // @[DMA.scala:437:24] wire write_packets_1_mask_1_13; // @[DMA.scala:437:24] wire write_packets_1_mask_1_14; // @[DMA.scala:437:24] wire write_packets_1_mask_1_15; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_1_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_1_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_9_0_0 = _write_packets_WIRE_5_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_1 = _write_packets_WIRE_5_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_2 = _write_packets_WIRE_5_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_3 = _write_packets_WIRE_5_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_4 = _write_packets_WIRE_5_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_5 = _write_packets_WIRE_5_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_6 = _write_packets_WIRE_5_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_7 = _write_packets_WIRE_5_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_8 = _write_packets_WIRE_5_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_9 = _write_packets_WIRE_5_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_10 = _write_packets_WIRE_5_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_11 = _write_packets_WIRE_5_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_12 = _write_packets_WIRE_5_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_13 = _write_packets_WIRE_5_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_14 = _write_packets_WIRE_5_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_0_15 = _write_packets_WIRE_5_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_0 = _write_packets_WIRE_6_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_1 = _write_packets_WIRE_6_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_2 = _write_packets_WIRE_6_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_3 = _write_packets_WIRE_6_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_4 = _write_packets_WIRE_6_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_5 = _write_packets_WIRE_6_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_6 = _write_packets_WIRE_6_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_7 = _write_packets_WIRE_6_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_8 = _write_packets_WIRE_6_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_9 = _write_packets_WIRE_6_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_10 = _write_packets_WIRE_6_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_11 = _write_packets_WIRE_6_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_12 = _write_packets_WIRE_6_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_13 = _write_packets_WIRE_6_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_14 = _write_packets_WIRE_6_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_9_1_15 = _write_packets_WIRE_6_15; // @[DMA.scala:440:{29,70}] assign write_packets_1_mask_0_0 = _write_packets_WIRE_9_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_1 = _write_packets_WIRE_9_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_2 = _write_packets_WIRE_9_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_3 = _write_packets_WIRE_9_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_4 = _write_packets_WIRE_9_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_5 = _write_packets_WIRE_9_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_6 = _write_packets_WIRE_9_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_7 = _write_packets_WIRE_9_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_8 = _write_packets_WIRE_9_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_9 = _write_packets_WIRE_9_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_10 = _write_packets_WIRE_9_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_11 = _write_packets_WIRE_9_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_12 = _write_packets_WIRE_9_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_13 = _write_packets_WIRE_9_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_14 = _write_packets_WIRE_9_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_0_15 = _write_packets_WIRE_9_0_15; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_0 = _write_packets_WIRE_9_1_0; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_1 = _write_packets_WIRE_9_1_1; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_2 = _write_packets_WIRE_9_1_2; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_3 = _write_packets_WIRE_9_1_3; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_4 = _write_packets_WIRE_9_1_4; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_5 = _write_packets_WIRE_9_1_5; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_6 = _write_packets_WIRE_9_1_6; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_7 = _write_packets_WIRE_9_1_7; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_8 = _write_packets_WIRE_9_1_8; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_9 = _write_packets_WIRE_9_1_9; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_10 = _write_packets_WIRE_9_1_10; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_11 = _write_packets_WIRE_9_1_11; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_12 = _write_packets_WIRE_9_1_12; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_13 = _write_packets_WIRE_9_1_13; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_14 = _write_packets_WIRE_9_1_14; // @[DMA.scala:437:24, :440:29] assign write_packets_1_mask_1_15 = _write_packets_WIRE_9_1_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T_15 = write_packets_mask_0_1 & write_packets_mask_1_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_16 = _write_packets_packet_is_full_T_15 & write_packets_mask_2_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_17 = _write_packets_packet_is_full_T_16 & write_packets_mask_3_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_18 = _write_packets_packet_is_full_T_17 & write_packets_mask_4_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_19 = _write_packets_packet_is_full_T_18 & write_packets_mask_5_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_20 = _write_packets_packet_is_full_T_19 & write_packets_mask_6_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_21 = _write_packets_packet_is_full_T_20 & write_packets_mask_7_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_22 = _write_packets_packet_is_full_T_21 & write_packets_mask_8_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_23 = _write_packets_packet_is_full_T_22 & write_packets_mask_9_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_24 = _write_packets_packet_is_full_T_23 & write_packets_mask_10_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_25 = _write_packets_packet_is_full_T_24 & write_packets_mask_11_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_26 = _write_packets_packet_is_full_T_25 & write_packets_mask_12_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_27 = _write_packets_packet_is_full_T_26 & write_packets_mask_13_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_28 = _write_packets_packet_is_full_T_27 & write_packets_mask_14_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_29 = _write_packets_packet_is_full_T_28 & write_packets_mask_15_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_30 = _write_packets_packet_is_full_T_29 & write_packets_mask_16_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_31 = _write_packets_packet_is_full_T_30 & write_packets_mask_17_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_32 = _write_packets_packet_is_full_T_31 & write_packets_mask_18_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_33 = _write_packets_packet_is_full_T_32 & write_packets_mask_19_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_34 = _write_packets_packet_is_full_T_33 & write_packets_mask_20_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_35 = _write_packets_packet_is_full_T_34 & write_packets_mask_21_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_36 = _write_packets_packet_is_full_T_35 & write_packets_mask_22_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_37 = _write_packets_packet_is_full_T_36 & write_packets_mask_23_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_38 = _write_packets_packet_is_full_T_37 & write_packets_mask_24_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_39 = _write_packets_packet_is_full_T_38 & write_packets_mask_25_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_40 = _write_packets_packet_is_full_T_39 & write_packets_mask_26_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_41 = _write_packets_packet_is_full_T_40 & write_packets_mask_27_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_42 = _write_packets_packet_is_full_T_41 & write_packets_mask_28_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_43 = _write_packets_packet_is_full_T_42 & write_packets_mask_29_1; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_44 = _write_packets_packet_is_full_T_43 & write_packets_mask_30_1; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_45 = _write_packets_packet_is_full_T_44 & write_packets_mask_31_1; // @[DMA.scala:431:103, :442:47] assign write_packets_1_is_full = _write_packets_packet_is_full_T_45; // @[DMA.scala:437:24, :442:47] wire _write_packets_left_shift_T_21 = ~(write_packets_vaddr_offset_1[4]); // @[DMA.scala:429:42, :431:52, :449:78] wire _write_packets_left_shift_T_22 = _write_packets_left_shift_T_21; // @[DMA.scala:449:{62,78}] wire [5:0] _write_packets_left_shift_T_23 = {1'h0, write_packets_vaddr_offset_1}; // @[DMA.scala:429:42, :450:24] wire [4:0] _write_packets_left_shift_T_24 = _write_packets_left_shift_T_23[4:0]; // @[DMA.scala:450:24] wire [4:0] write_packets_left_shift_4 = _write_packets_left_shift_T_22 ? _write_packets_left_shift_T_24 : 5'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_35 = _write_packets_right_shift_T_34 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_36 = _write_packets_right_shift_T_35; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_38 = 9'h10 - {1'h0, _write_packets_right_shift_T_37}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_39 = _write_packets_right_shift_T_38[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_4 = _write_packets_right_shift_T_36 ? _write_packets_right_shift_T_39 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_4 = _write_packets_too_late_T_4 == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T_5 = write_packets_too_early_4 | write_packets_too_late_4; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_6 = {4'h0, write_packets_left_shift_4} + {1'h0, write_packets_right_shift_4}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_8 = _write_packets_packet_bytes_written_per_beat_0_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_9 = _write_packets_packet_bytes_written_per_beat_0_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_27 = _write_packets_left_shift_T_25; // @[DMA.scala:449:{43,62}] wire [5:0] _write_packets_left_shift_T_28 = _write_packets_left_shift_T_23 - 6'h10; // @[DMA.scala:450:24] wire [4:0] _write_packets_left_shift_T_29 = _write_packets_left_shift_T_28[4:0]; // @[DMA.scala:450:24] wire [4:0] write_packets_left_shift_5 = _write_packets_left_shift_T_27 ? _write_packets_left_shift_T_29 : 5'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_41 = |(_write_packets_right_shift_T_40[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_43 = _write_packets_right_shift_T_42 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_44 = _write_packets_right_shift_T_41 & _write_packets_right_shift_T_43; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_46 = 9'h20 - {1'h0, _write_packets_right_shift_T_45}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_47 = _write_packets_right_shift_T_46[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_5 = _write_packets_right_shift_T_44 ? _write_packets_right_shift_T_47 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_5 = _write_packets_too_late_T_5 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T_5 = write_packets_too_late_5; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_6 = {4'h0, write_packets_left_shift_5} + {1'h0, write_packets_right_shift_5}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_8 = _write_packets_packet_bytes_written_per_beat_1_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_9 = _write_packets_packet_bytes_written_per_beat_1_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_33 = _GEN_5 - 7'h20; // @[DMA.scala:434:50, :450:24] wire [5:0] _write_packets_left_shift_T_34 = _write_packets_left_shift_T_33[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_49 = |(_write_packets_right_shift_T_48[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_51 = _write_packets_right_shift_T_50 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_52 = _write_packets_right_shift_T_49 & _write_packets_right_shift_T_51; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_54 = 9'h30 - {1'h0, _write_packets_right_shift_T_53}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_55 = _write_packets_right_shift_T_54[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_6 = _write_packets_right_shift_T_52 ? _write_packets_right_shift_T_55 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_6 = _write_packets_too_late_T_6 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T_5 = write_packets_too_late_6; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_6 = {1'h0, write_packets_right_shift_6}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_8 = _write_packets_packet_bytes_written_per_beat_2_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_9 = _write_packets_packet_bytes_written_per_beat_2_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [6:0] _write_packets_left_shift_T_38 = _GEN_5 - 7'h30; // @[DMA.scala:434:50, :450:24] wire [5:0] _write_packets_left_shift_T_39 = _write_packets_left_shift_T_38[5:0]; // @[DMA.scala:450:24] wire _write_packets_right_shift_T_57 = _write_packets_right_shift_T_56 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_59 = _write_packets_right_shift_T_58 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_60 = _write_packets_right_shift_T_57 & _write_packets_right_shift_T_59; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_62 = 9'h40 - {1'h0, _write_packets_right_shift_T_61}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_63 = _write_packets_right_shift_T_62[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_7 = _write_packets_right_shift_T_60 ? _write_packets_right_shift_T_63 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_7 = _write_packets_too_late_T_7 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T_5 = write_packets_too_late_7; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_6 = {1'h0, write_packets_right_shift_7}; // @[DMA.scala:453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_7 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_6}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_8 = _write_packets_packet_bytes_written_per_beat_3_T_7[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_9 = _write_packets_packet_bytes_written_per_beat_3_T_5 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_8; // @[DMA.scala:460:{17,28,58}] assign write_packets_1_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_9[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire [32:0] _write_packets_vaddr_aligned_to_size_T_2 = req_vaddr[38:6]; // @[DMA.scala:382:18, :428:67] wire [38:0] write_packets_vaddr_aligned_to_size_2 = {_write_packets_vaddr_aligned_to_size_T_2, 6'h0}; // @[DMA.scala:428:{61,67}] wire [38:0] write_packets_2_vaddr = write_packets_vaddr_aligned_to_size_2; // @[DMA.scala:428:61, :437:24] wire [5:0] write_packets_vaddr_offset_2 = req_vaddr[5:0]; // @[DMA.scala:382:18, :429:42] wire _write_packets_mask_T_512 = write_packets_vaddr_offset_2 == 6'h0; // @[DMA.scala:429:42, :431:52] wire [7:0] _GEN_6 = {2'h0, write_packets_vaddr_offset_2}; // @[DMA.scala:429:42, :431:90] wire [7:0] _GEN_7 = _GEN_6 + _GEN_0; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_513; // @[DMA.scala:431:90] assign _write_packets_mask_T_513 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_517; // @[DMA.scala:431:90] assign _write_packets_mask_T_517 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_521; // @[DMA.scala:431:90] assign _write_packets_mask_T_521 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_525; // @[DMA.scala:431:90] assign _write_packets_mask_T_525 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_529; // @[DMA.scala:431:90] assign _write_packets_mask_T_529 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_533; // @[DMA.scala:431:90] assign _write_packets_mask_T_533 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_537; // @[DMA.scala:431:90] assign _write_packets_mask_T_537 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_541; // @[DMA.scala:431:90] assign _write_packets_mask_T_541 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_545; // @[DMA.scala:431:90] assign _write_packets_mask_T_545 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_549; // @[DMA.scala:431:90] assign _write_packets_mask_T_549 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_553; // @[DMA.scala:431:90] assign _write_packets_mask_T_553 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_557; // @[DMA.scala:431:90] assign _write_packets_mask_T_557 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_561; // @[DMA.scala:431:90] assign _write_packets_mask_T_561 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_565; // @[DMA.scala:431:90] assign _write_packets_mask_T_565 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_569; // @[DMA.scala:431:90] assign _write_packets_mask_T_569 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_573; // @[DMA.scala:431:90] assign _write_packets_mask_T_573 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_577; // @[DMA.scala:431:90] assign _write_packets_mask_T_577 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_581; // @[DMA.scala:431:90] assign _write_packets_mask_T_581 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_585; // @[DMA.scala:431:90] assign _write_packets_mask_T_585 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_589; // @[DMA.scala:431:90] assign _write_packets_mask_T_589 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_593; // @[DMA.scala:431:90] assign _write_packets_mask_T_593 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_597; // @[DMA.scala:431:90] assign _write_packets_mask_T_597 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_601; // @[DMA.scala:431:90] assign _write_packets_mask_T_601 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_605; // @[DMA.scala:431:90] assign _write_packets_mask_T_605 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_609; // @[DMA.scala:431:90] assign _write_packets_mask_T_609 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_613; // @[DMA.scala:431:90] assign _write_packets_mask_T_613 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_617; // @[DMA.scala:431:90] assign _write_packets_mask_T_617 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_621; // @[DMA.scala:431:90] assign _write_packets_mask_T_621 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_625; // @[DMA.scala:431:90] assign _write_packets_mask_T_625 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_629; // @[DMA.scala:431:90] assign _write_packets_mask_T_629 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_633; // @[DMA.scala:431:90] assign _write_packets_mask_T_633 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_637; // @[DMA.scala:431:90] assign _write_packets_mask_T_637 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_641; // @[DMA.scala:431:90] assign _write_packets_mask_T_641 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_645; // @[DMA.scala:431:90] assign _write_packets_mask_T_645 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_649; // @[DMA.scala:431:90] assign _write_packets_mask_T_649 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_653; // @[DMA.scala:431:90] assign _write_packets_mask_T_653 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_657; // @[DMA.scala:431:90] assign _write_packets_mask_T_657 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_661; // @[DMA.scala:431:90] assign _write_packets_mask_T_661 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_665; // @[DMA.scala:431:90] assign _write_packets_mask_T_665 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_669; // @[DMA.scala:431:90] assign _write_packets_mask_T_669 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_673; // @[DMA.scala:431:90] assign _write_packets_mask_T_673 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_677; // @[DMA.scala:431:90] assign _write_packets_mask_T_677 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_681; // @[DMA.scala:431:90] assign _write_packets_mask_T_681 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_685; // @[DMA.scala:431:90] assign _write_packets_mask_T_685 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_689; // @[DMA.scala:431:90] assign _write_packets_mask_T_689 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_693; // @[DMA.scala:431:90] assign _write_packets_mask_T_693 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_697; // @[DMA.scala:431:90] assign _write_packets_mask_T_697 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_701; // @[DMA.scala:431:90] assign _write_packets_mask_T_701 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_705; // @[DMA.scala:431:90] assign _write_packets_mask_T_705 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_709; // @[DMA.scala:431:90] assign _write_packets_mask_T_709 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_713; // @[DMA.scala:431:90] assign _write_packets_mask_T_713 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_717; // @[DMA.scala:431:90] assign _write_packets_mask_T_717 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_721; // @[DMA.scala:431:90] assign _write_packets_mask_T_721 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_725; // @[DMA.scala:431:90] assign _write_packets_mask_T_725 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_729; // @[DMA.scala:431:90] assign _write_packets_mask_T_729 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_733; // @[DMA.scala:431:90] assign _write_packets_mask_T_733 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_737; // @[DMA.scala:431:90] assign _write_packets_mask_T_737 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_741; // @[DMA.scala:431:90] assign _write_packets_mask_T_741 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_745; // @[DMA.scala:431:90] assign _write_packets_mask_T_745 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_749; // @[DMA.scala:431:90] assign _write_packets_mask_T_749 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_753; // @[DMA.scala:431:90] assign _write_packets_mask_T_753 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_757; // @[DMA.scala:431:90] assign _write_packets_mask_T_757 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_761; // @[DMA.scala:431:90] assign _write_packets_mask_T_761 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_mask_T_765; // @[DMA.scala:431:90] assign _write_packets_mask_T_765 = _GEN_7; // @[DMA.scala:431:90] wire [7:0] _write_packets_bytes_written_T_8; // @[DMA.scala:434:26] assign _write_packets_bytes_written_T_8 = _GEN_7; // @[DMA.scala:431:90, :434:26] wire [7:0] _write_packets_right_shift_T_64; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_64 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_66; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_66 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_69; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_69 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_8; // @[DMA.scala:458:37] assign _write_packets_too_late_T_8 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_72; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_72 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_74; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_74 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_77; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_77 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_9; // @[DMA.scala:458:37] assign _write_packets_too_late_T_9 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_80; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_80 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_82; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_82 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_85; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_85 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_10; // @[DMA.scala:458:37] assign _write_packets_too_late_T_10 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire [7:0] _write_packets_right_shift_T_88; // @[DMA.scala:453:44] assign _write_packets_right_shift_T_88 = _GEN_7; // @[DMA.scala:431:90, :453:44] wire [7:0] _write_packets_right_shift_T_90; // @[DMA.scala:453:92] assign _write_packets_right_shift_T_90 = _GEN_7; // @[DMA.scala:431:90, :453:92] wire [7:0] _write_packets_right_shift_T_93; // @[DMA.scala:454:41] assign _write_packets_right_shift_T_93 = _GEN_7; // @[DMA.scala:431:90, :454:41] wire [7:0] _write_packets_too_late_T_11; // @[DMA.scala:458:37] assign _write_packets_too_late_T_11 = _GEN_7; // @[DMA.scala:431:90, :458:37] wire _write_packets_mask_T_514 = |_write_packets_mask_T_513; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_515 = _write_packets_mask_T_512 & _write_packets_mask_T_514; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_0_2 = _write_packets_mask_T_515; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_0 = write_packets_mask_0_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_516 = write_packets_vaddr_offset_2 < 6'h2; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_518 = |(_write_packets_mask_T_517[7:1]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_519 = _write_packets_mask_T_516 & _write_packets_mask_T_518; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_1_2 = _write_packets_mask_T_519; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_1 = write_packets_mask_1_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_520 = write_packets_vaddr_offset_2 < 6'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_522 = _write_packets_mask_T_521 > 8'h2; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_523 = _write_packets_mask_T_520 & _write_packets_mask_T_522; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_2_2 = _write_packets_mask_T_523; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_2 = write_packets_mask_2_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_524 = write_packets_vaddr_offset_2 < 6'h4; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_526 = |(_write_packets_mask_T_525[7:2]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_527 = _write_packets_mask_T_524 & _write_packets_mask_T_526; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_3_2 = _write_packets_mask_T_527; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_3 = write_packets_mask_3_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_528 = write_packets_vaddr_offset_2 < 6'h5; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_530 = _write_packets_mask_T_529 > 8'h4; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_531 = _write_packets_mask_T_528 & _write_packets_mask_T_530; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_4_2 = _write_packets_mask_T_531; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_4 = write_packets_mask_4_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_532 = write_packets_vaddr_offset_2 < 6'h6; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_534 = _write_packets_mask_T_533 > 8'h5; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_535 = _write_packets_mask_T_532 & _write_packets_mask_T_534; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_5_2 = _write_packets_mask_T_535; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_5 = write_packets_mask_5_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_536 = write_packets_vaddr_offset_2 < 6'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_538 = _write_packets_mask_T_537 > 8'h6; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_539 = _write_packets_mask_T_536 & _write_packets_mask_T_538; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_6_2 = _write_packets_mask_T_539; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_6 = write_packets_mask_6_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_540 = write_packets_vaddr_offset_2 < 6'h8; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_542 = |(_write_packets_mask_T_541[7:3]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_543 = _write_packets_mask_T_540 & _write_packets_mask_T_542; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_7_2 = _write_packets_mask_T_543; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_7 = write_packets_mask_7_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_544 = write_packets_vaddr_offset_2 < 6'h9; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_546 = _write_packets_mask_T_545 > 8'h8; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_547 = _write_packets_mask_T_544 & _write_packets_mask_T_546; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_8_2 = _write_packets_mask_T_547; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_8 = write_packets_mask_8_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_548 = write_packets_vaddr_offset_2 < 6'hA; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_550 = _write_packets_mask_T_549 > 8'h9; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_551 = _write_packets_mask_T_548 & _write_packets_mask_T_550; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_9_2 = _write_packets_mask_T_551; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_9 = write_packets_mask_9_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_552 = write_packets_vaddr_offset_2 < 6'hB; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_554 = _write_packets_mask_T_553 > 8'hA; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_555 = _write_packets_mask_T_552 & _write_packets_mask_T_554; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_10_2 = _write_packets_mask_T_555; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_10 = write_packets_mask_10_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_556 = write_packets_vaddr_offset_2 < 6'hC; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_558 = _write_packets_mask_T_557 > 8'hB; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_559 = _write_packets_mask_T_556 & _write_packets_mask_T_558; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_11_2 = _write_packets_mask_T_559; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_11 = write_packets_mask_11_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_560 = write_packets_vaddr_offset_2 < 6'hD; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_562 = _write_packets_mask_T_561 > 8'hC; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_563 = _write_packets_mask_T_560 & _write_packets_mask_T_562; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_12_2 = _write_packets_mask_T_563; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_12 = write_packets_mask_12_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_564 = write_packets_vaddr_offset_2 < 6'hE; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_566 = _write_packets_mask_T_565 > 8'hD; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_567 = _write_packets_mask_T_564 & _write_packets_mask_T_566; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_13_2 = _write_packets_mask_T_567; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_13 = write_packets_mask_13_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_568 = write_packets_vaddr_offset_2 < 6'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_570 = _write_packets_mask_T_569 > 8'hE; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_571 = _write_packets_mask_T_568 & _write_packets_mask_T_570; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_14_2 = _write_packets_mask_T_571; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_14 = write_packets_mask_14_2; // @[DMA.scala:431:103, :440:70] wire _GEN_8 = write_packets_vaddr_offset_2 < 6'h10; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_572; // @[DMA.scala:431:52] assign _write_packets_mask_T_572 = _GEN_8; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_41; // @[DMA.scala:449:78] assign _write_packets_left_shift_T_41 = _GEN_8; // @[DMA.scala:431:52, :449:78] wire _write_packets_mask_T_574 = |(_write_packets_mask_T_573[7:4]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_575 = _write_packets_mask_T_572 & _write_packets_mask_T_574; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_15_2 = _write_packets_mask_T_575; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_10_15 = write_packets_mask_15_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_576 = write_packets_vaddr_offset_2 < 6'h11; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_578 = _write_packets_mask_T_577 > 8'h10; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_579 = _write_packets_mask_T_576 & _write_packets_mask_T_578; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_16_2 = _write_packets_mask_T_579; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_0 = write_packets_mask_16_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_580 = write_packets_vaddr_offset_2 < 6'h12; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_582 = _write_packets_mask_T_581 > 8'h11; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_583 = _write_packets_mask_T_580 & _write_packets_mask_T_582; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_17_2 = _write_packets_mask_T_583; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_1 = write_packets_mask_17_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_584 = write_packets_vaddr_offset_2 < 6'h13; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_586 = _write_packets_mask_T_585 > 8'h12; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_587 = _write_packets_mask_T_584 & _write_packets_mask_T_586; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_18_2 = _write_packets_mask_T_587; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_2 = write_packets_mask_18_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_588 = write_packets_vaddr_offset_2 < 6'h14; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_590 = _write_packets_mask_T_589 > 8'h13; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_591 = _write_packets_mask_T_588 & _write_packets_mask_T_590; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_19_2 = _write_packets_mask_T_591; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_3 = write_packets_mask_19_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_592 = write_packets_vaddr_offset_2 < 6'h15; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_594 = _write_packets_mask_T_593 > 8'h14; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_595 = _write_packets_mask_T_592 & _write_packets_mask_T_594; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_20_2 = _write_packets_mask_T_595; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_4 = write_packets_mask_20_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_596 = write_packets_vaddr_offset_2 < 6'h16; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_598 = _write_packets_mask_T_597 > 8'h15; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_599 = _write_packets_mask_T_596 & _write_packets_mask_T_598; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_21_2 = _write_packets_mask_T_599; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_5 = write_packets_mask_21_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_600 = write_packets_vaddr_offset_2 < 6'h17; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_602 = _write_packets_mask_T_601 > 8'h16; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_603 = _write_packets_mask_T_600 & _write_packets_mask_T_602; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_22_2 = _write_packets_mask_T_603; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_6 = write_packets_mask_22_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_604 = write_packets_vaddr_offset_2 < 6'h18; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_606 = _write_packets_mask_T_605 > 8'h17; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_607 = _write_packets_mask_T_604 & _write_packets_mask_T_606; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_23_2 = _write_packets_mask_T_607; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_7 = write_packets_mask_23_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_608 = write_packets_vaddr_offset_2 < 6'h19; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_610 = _write_packets_mask_T_609 > 8'h18; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_611 = _write_packets_mask_T_608 & _write_packets_mask_T_610; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_24_2 = _write_packets_mask_T_611; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_8 = write_packets_mask_24_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_612 = write_packets_vaddr_offset_2 < 6'h1A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_614 = _write_packets_mask_T_613 > 8'h19; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_615 = _write_packets_mask_T_612 & _write_packets_mask_T_614; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_25_2 = _write_packets_mask_T_615; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_9 = write_packets_mask_25_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_616 = write_packets_vaddr_offset_2 < 6'h1B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_618 = _write_packets_mask_T_617 > 8'h1A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_619 = _write_packets_mask_T_616 & _write_packets_mask_T_618; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_26_2 = _write_packets_mask_T_619; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_10 = write_packets_mask_26_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_620 = write_packets_vaddr_offset_2 < 6'h1C; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_622 = _write_packets_mask_T_621 > 8'h1B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_623 = _write_packets_mask_T_620 & _write_packets_mask_T_622; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_27_2 = _write_packets_mask_T_623; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_11 = write_packets_mask_27_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_624 = write_packets_vaddr_offset_2 < 6'h1D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_626 = _write_packets_mask_T_625 > 8'h1C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_627 = _write_packets_mask_T_624 & _write_packets_mask_T_626; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_28_2 = _write_packets_mask_T_627; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_12 = write_packets_mask_28_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_628 = write_packets_vaddr_offset_2 < 6'h1E; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_630 = _write_packets_mask_T_629 > 8'h1D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_631 = _write_packets_mask_T_628 & _write_packets_mask_T_630; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_29_2 = _write_packets_mask_T_631; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_13 = write_packets_mask_29_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_632 = write_packets_vaddr_offset_2 < 6'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_634 = _write_packets_mask_T_633 > 8'h1E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_635 = _write_packets_mask_T_632 & _write_packets_mask_T_634; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_30_2 = _write_packets_mask_T_635; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_14 = write_packets_mask_30_2; // @[DMA.scala:431:103, :440:70] wire write_packets_too_early_9 = write_packets_vaddr_offset_2[5]; // @[DMA.scala:429:42, :431:52, :457:38] wire _write_packets_left_shift_T_50 = write_packets_vaddr_offset_2[5]; // @[DMA.scala:429:42, :431:52, :449:43] wire _write_packets_mask_T_636 = ~(write_packets_vaddr_offset_2[5]); // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_638 = |(_write_packets_mask_T_637[7:5]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_639 = _write_packets_mask_T_636 & _write_packets_mask_T_638; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_31_2 = _write_packets_mask_T_639; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_11_15 = write_packets_mask_31_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_640 = write_packets_vaddr_offset_2 < 6'h21; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_642 = _write_packets_mask_T_641 > 8'h20; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_643 = _write_packets_mask_T_640 & _write_packets_mask_T_642; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_32_2 = _write_packets_mask_T_643; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_0 = write_packets_mask_32_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_644 = write_packets_vaddr_offset_2 < 6'h22; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_646 = _write_packets_mask_T_645 > 8'h21; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_647 = _write_packets_mask_T_644 & _write_packets_mask_T_646; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_33_2 = _write_packets_mask_T_647; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_1 = write_packets_mask_33_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_648 = write_packets_vaddr_offset_2 < 6'h23; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_650 = _write_packets_mask_T_649 > 8'h22; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_651 = _write_packets_mask_T_648 & _write_packets_mask_T_650; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_34_2 = _write_packets_mask_T_651; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_2 = write_packets_mask_34_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_652 = write_packets_vaddr_offset_2 < 6'h24; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_654 = _write_packets_mask_T_653 > 8'h23; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_655 = _write_packets_mask_T_652 & _write_packets_mask_T_654; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_35_2 = _write_packets_mask_T_655; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_3 = write_packets_mask_35_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_656 = write_packets_vaddr_offset_2 < 6'h25; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_658 = _write_packets_mask_T_657 > 8'h24; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_659 = _write_packets_mask_T_656 & _write_packets_mask_T_658; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_36_2 = _write_packets_mask_T_659; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_4 = write_packets_mask_36_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_660 = write_packets_vaddr_offset_2 < 6'h26; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_662 = _write_packets_mask_T_661 > 8'h25; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_663 = _write_packets_mask_T_660 & _write_packets_mask_T_662; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_37_2 = _write_packets_mask_T_663; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_5 = write_packets_mask_37_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_664 = write_packets_vaddr_offset_2 < 6'h27; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_666 = _write_packets_mask_T_665 > 8'h26; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_667 = _write_packets_mask_T_664 & _write_packets_mask_T_666; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_38_2 = _write_packets_mask_T_667; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_6 = write_packets_mask_38_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_668 = write_packets_vaddr_offset_2 < 6'h28; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_670 = _write_packets_mask_T_669 > 8'h27; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_671 = _write_packets_mask_T_668 & _write_packets_mask_T_670; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_39_2 = _write_packets_mask_T_671; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_7 = write_packets_mask_39_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_672 = write_packets_vaddr_offset_2 < 6'h29; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_674 = _write_packets_mask_T_673 > 8'h28; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_675 = _write_packets_mask_T_672 & _write_packets_mask_T_674; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_40_2 = _write_packets_mask_T_675; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_8 = write_packets_mask_40_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_676 = write_packets_vaddr_offset_2 < 6'h2A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_678 = _write_packets_mask_T_677 > 8'h29; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_679 = _write_packets_mask_T_676 & _write_packets_mask_T_678; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_41_2 = _write_packets_mask_T_679; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_9 = write_packets_mask_41_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_680 = write_packets_vaddr_offset_2 < 6'h2B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_682 = _write_packets_mask_T_681 > 8'h2A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_683 = _write_packets_mask_T_680 & _write_packets_mask_T_682; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_42_2 = _write_packets_mask_T_683; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_10 = write_packets_mask_42_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_684 = write_packets_vaddr_offset_2 < 6'h2C; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_686 = _write_packets_mask_T_685 > 8'h2B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_687 = _write_packets_mask_T_684 & _write_packets_mask_T_686; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_43_2 = _write_packets_mask_T_687; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_11 = write_packets_mask_43_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_688 = write_packets_vaddr_offset_2 < 6'h2D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_690 = _write_packets_mask_T_689 > 8'h2C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_691 = _write_packets_mask_T_688 & _write_packets_mask_T_690; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_44_2 = _write_packets_mask_T_691; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_12 = write_packets_mask_44_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_692 = write_packets_vaddr_offset_2 < 6'h2E; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_694 = _write_packets_mask_T_693 > 8'h2D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_695 = _write_packets_mask_T_692 & _write_packets_mask_T_694; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_45_2 = _write_packets_mask_T_695; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_13 = write_packets_mask_45_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_696 = write_packets_vaddr_offset_2 < 6'h2F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_698 = _write_packets_mask_T_697 > 8'h2E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_699 = _write_packets_mask_T_696 & _write_packets_mask_T_698; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_46_2 = _write_packets_mask_T_699; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_14 = write_packets_mask_46_2; // @[DMA.scala:431:103, :440:70] wire _GEN_9 = write_packets_vaddr_offset_2[5:4] != 2'h3; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_700; // @[DMA.scala:431:52] assign _write_packets_mask_T_700 = _GEN_9; // @[DMA.scala:431:52] wire _write_packets_left_shift_T_51; // @[DMA.scala:449:78] assign _write_packets_left_shift_T_51 = _GEN_9; // @[DMA.scala:431:52, :449:78] wire _write_packets_mask_T_702 = _write_packets_mask_T_701 > 8'h2F; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_703 = _write_packets_mask_T_700 & _write_packets_mask_T_702; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_47_2 = _write_packets_mask_T_703; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_12_15 = write_packets_mask_47_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_704 = write_packets_vaddr_offset_2 < 6'h31; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_706 = _write_packets_mask_T_705 > 8'h30; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_707 = _write_packets_mask_T_704 & _write_packets_mask_T_706; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_48_2 = _write_packets_mask_T_707; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_0 = write_packets_mask_48_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_708 = write_packets_vaddr_offset_2 < 6'h32; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_710 = _write_packets_mask_T_709 > 8'h31; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_711 = _write_packets_mask_T_708 & _write_packets_mask_T_710; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_49_2 = _write_packets_mask_T_711; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_1 = write_packets_mask_49_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_712 = write_packets_vaddr_offset_2 < 6'h33; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_714 = _write_packets_mask_T_713 > 8'h32; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_715 = _write_packets_mask_T_712 & _write_packets_mask_T_714; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_50_2 = _write_packets_mask_T_715; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_2 = write_packets_mask_50_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_716 = write_packets_vaddr_offset_2 < 6'h34; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_718 = _write_packets_mask_T_717 > 8'h33; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_719 = _write_packets_mask_T_716 & _write_packets_mask_T_718; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_51_2 = _write_packets_mask_T_719; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_3 = write_packets_mask_51_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_720 = write_packets_vaddr_offset_2 < 6'h35; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_722 = _write_packets_mask_T_721 > 8'h34; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_723 = _write_packets_mask_T_720 & _write_packets_mask_T_722; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_52_2 = _write_packets_mask_T_723; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_4 = write_packets_mask_52_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_724 = write_packets_vaddr_offset_2 < 6'h36; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_726 = _write_packets_mask_T_725 > 8'h35; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_727 = _write_packets_mask_T_724 & _write_packets_mask_T_726; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_53_2 = _write_packets_mask_T_727; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_5 = write_packets_mask_53_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_728 = write_packets_vaddr_offset_2 < 6'h37; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_730 = _write_packets_mask_T_729 > 8'h36; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_731 = _write_packets_mask_T_728 & _write_packets_mask_T_730; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_54_2 = _write_packets_mask_T_731; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_6 = write_packets_mask_54_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_732 = write_packets_vaddr_offset_2[5:3] != 3'h7; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_734 = _write_packets_mask_T_733 > 8'h37; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_735 = _write_packets_mask_T_732 & _write_packets_mask_T_734; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_55_2 = _write_packets_mask_T_735; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_7 = write_packets_mask_55_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_736 = write_packets_vaddr_offset_2 < 6'h39; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_738 = _write_packets_mask_T_737 > 8'h38; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_739 = _write_packets_mask_T_736 & _write_packets_mask_T_738; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_56_2 = _write_packets_mask_T_739; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_8 = write_packets_mask_56_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_740 = write_packets_vaddr_offset_2 < 6'h3A; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_742 = _write_packets_mask_T_741 > 8'h39; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_743 = _write_packets_mask_T_740 & _write_packets_mask_T_742; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_57_2 = _write_packets_mask_T_743; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_9 = write_packets_mask_57_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_744 = write_packets_vaddr_offset_2 < 6'h3B; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_746 = _write_packets_mask_T_745 > 8'h3A; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_747 = _write_packets_mask_T_744 & _write_packets_mask_T_746; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_58_2 = _write_packets_mask_T_747; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_10 = write_packets_mask_58_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_748 = write_packets_vaddr_offset_2[5:2] != 4'hF; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_750 = _write_packets_mask_T_749 > 8'h3B; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_751 = _write_packets_mask_T_748 & _write_packets_mask_T_750; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_59_2 = _write_packets_mask_T_751; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_11 = write_packets_mask_59_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_752 = write_packets_vaddr_offset_2 < 6'h3D; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_754 = _write_packets_mask_T_753 > 8'h3C; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_755 = _write_packets_mask_T_752 & _write_packets_mask_T_754; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_60_2 = _write_packets_mask_T_755; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_12 = write_packets_mask_60_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_756 = write_packets_vaddr_offset_2[5:1] != 5'h1F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_758 = _write_packets_mask_T_757 > 8'h3D; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_759 = _write_packets_mask_T_756 & _write_packets_mask_T_758; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_61_2 = _write_packets_mask_T_759; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_13 = write_packets_mask_61_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_760 = write_packets_vaddr_offset_2 != 6'h3F; // @[DMA.scala:429:42, :431:52] wire _write_packets_mask_T_762 = _write_packets_mask_T_761 > 8'h3E; // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_763 = _write_packets_mask_T_760 & _write_packets_mask_T_762; // @[DMA.scala:431:{52,68,75}] wire write_packets_mask_62_2 = _write_packets_mask_T_763; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_14 = write_packets_mask_62_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_mask_T_766 = |(_write_packets_mask_T_765[7:6]); // @[DMA.scala:431:{75,90}] wire _write_packets_mask_T_767 = _write_packets_mask_T_766; // @[DMA.scala:431:{68,75}] wire write_packets_mask_63_2 = _write_packets_mask_T_767; // @[DMA.scala:431:{68,103}] wire _write_packets_WIRE_13_15 = write_packets_mask_63_2; // @[DMA.scala:431:103, :440:70] wire _write_packets_bytes_written_T_9 = _write_packets_bytes_written_T_8 > 8'h40; // @[DMA.scala:434:{26,39}] wire [7:0] _write_packets_bytes_written_T_10 = 8'h40 - _GEN_6; // @[DMA.scala:431:90, :434:50] wire [6:0] _write_packets_bytes_written_T_11 = _write_packets_bytes_written_T_10[6:0]; // @[DMA.scala:434:50] wire [6:0] write_packets_bytes_written_2 = _write_packets_bytes_written_T_9 ? _write_packets_bytes_written_T_11 : bytesLeft; // @[DMA.scala:390:29, :434:{12,39,50}] wire [6:0] write_packets_2_bytes_written = write_packets_bytes_written_2; // @[DMA.scala:434:12, :437:24] wire _write_packets_WIRE_14_0_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_0_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_1_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_2_15; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_0; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_1; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_2; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_3; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_4; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_5; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_6; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_7; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_8; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_9; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_10; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_11; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_12; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_13; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_14; // @[DMA.scala:440:29] wire _write_packets_WIRE_14_3_15; // @[DMA.scala:440:29] wire _write_packets_packet_is_full_T_108; // @[DMA.scala:442:47] wire write_packets_2_mask_0_0; // @[DMA.scala:437:24] wire write_packets_2_mask_0_1; // @[DMA.scala:437:24] wire write_packets_2_mask_0_2; // @[DMA.scala:437:24] wire write_packets_2_mask_0_3; // @[DMA.scala:437:24] wire write_packets_2_mask_0_4; // @[DMA.scala:437:24] wire write_packets_2_mask_0_5; // @[DMA.scala:437:24] wire write_packets_2_mask_0_6; // @[DMA.scala:437:24] wire write_packets_2_mask_0_7; // @[DMA.scala:437:24] wire write_packets_2_mask_0_8; // @[DMA.scala:437:24] wire write_packets_2_mask_0_9; // @[DMA.scala:437:24] wire write_packets_2_mask_0_10; // @[DMA.scala:437:24] wire write_packets_2_mask_0_11; // @[DMA.scala:437:24] wire write_packets_2_mask_0_12; // @[DMA.scala:437:24] wire write_packets_2_mask_0_13; // @[DMA.scala:437:24] wire write_packets_2_mask_0_14; // @[DMA.scala:437:24] wire write_packets_2_mask_0_15; // @[DMA.scala:437:24] wire write_packets_2_mask_1_0; // @[DMA.scala:437:24] wire write_packets_2_mask_1_1; // @[DMA.scala:437:24] wire write_packets_2_mask_1_2; // @[DMA.scala:437:24] wire write_packets_2_mask_1_3; // @[DMA.scala:437:24] wire write_packets_2_mask_1_4; // @[DMA.scala:437:24] wire write_packets_2_mask_1_5; // @[DMA.scala:437:24] wire write_packets_2_mask_1_6; // @[DMA.scala:437:24] wire write_packets_2_mask_1_7; // @[DMA.scala:437:24] wire write_packets_2_mask_1_8; // @[DMA.scala:437:24] wire write_packets_2_mask_1_9; // @[DMA.scala:437:24] wire write_packets_2_mask_1_10; // @[DMA.scala:437:24] wire write_packets_2_mask_1_11; // @[DMA.scala:437:24] wire write_packets_2_mask_1_12; // @[DMA.scala:437:24] wire write_packets_2_mask_1_13; // @[DMA.scala:437:24] wire write_packets_2_mask_1_14; // @[DMA.scala:437:24] wire write_packets_2_mask_1_15; // @[DMA.scala:437:24] wire write_packets_2_mask_2_0; // @[DMA.scala:437:24] wire write_packets_2_mask_2_1; // @[DMA.scala:437:24] wire write_packets_2_mask_2_2; // @[DMA.scala:437:24] wire write_packets_2_mask_2_3; // @[DMA.scala:437:24] wire write_packets_2_mask_2_4; // @[DMA.scala:437:24] wire write_packets_2_mask_2_5; // @[DMA.scala:437:24] wire write_packets_2_mask_2_6; // @[DMA.scala:437:24] wire write_packets_2_mask_2_7; // @[DMA.scala:437:24] wire write_packets_2_mask_2_8; // @[DMA.scala:437:24] wire write_packets_2_mask_2_9; // @[DMA.scala:437:24] wire write_packets_2_mask_2_10; // @[DMA.scala:437:24] wire write_packets_2_mask_2_11; // @[DMA.scala:437:24] wire write_packets_2_mask_2_12; // @[DMA.scala:437:24] wire write_packets_2_mask_2_13; // @[DMA.scala:437:24] wire write_packets_2_mask_2_14; // @[DMA.scala:437:24] wire write_packets_2_mask_2_15; // @[DMA.scala:437:24] wire write_packets_2_mask_3_0; // @[DMA.scala:437:24] wire write_packets_2_mask_3_1; // @[DMA.scala:437:24] wire write_packets_2_mask_3_2; // @[DMA.scala:437:24] wire write_packets_2_mask_3_3; // @[DMA.scala:437:24] wire write_packets_2_mask_3_4; // @[DMA.scala:437:24] wire write_packets_2_mask_3_5; // @[DMA.scala:437:24] wire write_packets_2_mask_3_6; // @[DMA.scala:437:24] wire write_packets_2_mask_3_7; // @[DMA.scala:437:24] wire write_packets_2_mask_3_8; // @[DMA.scala:437:24] wire write_packets_2_mask_3_9; // @[DMA.scala:437:24] wire write_packets_2_mask_3_10; // @[DMA.scala:437:24] wire write_packets_2_mask_3_11; // @[DMA.scala:437:24] wire write_packets_2_mask_3_12; // @[DMA.scala:437:24] wire write_packets_2_mask_3_13; // @[DMA.scala:437:24] wire write_packets_2_mask_3_14; // @[DMA.scala:437:24] wire write_packets_2_mask_3_15; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_0; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_1; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_2; // @[DMA.scala:437:24] wire [4:0] write_packets_2_bytes_written_per_beat_3; // @[DMA.scala:437:24] wire write_packets_2_is_full; // @[DMA.scala:437:24] assign _write_packets_WIRE_14_0_0 = _write_packets_WIRE_10_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_1 = _write_packets_WIRE_10_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_2 = _write_packets_WIRE_10_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_3 = _write_packets_WIRE_10_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_4 = _write_packets_WIRE_10_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_5 = _write_packets_WIRE_10_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_6 = _write_packets_WIRE_10_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_7 = _write_packets_WIRE_10_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_8 = _write_packets_WIRE_10_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_9 = _write_packets_WIRE_10_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_10 = _write_packets_WIRE_10_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_11 = _write_packets_WIRE_10_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_12 = _write_packets_WIRE_10_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_13 = _write_packets_WIRE_10_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_14 = _write_packets_WIRE_10_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_0_15 = _write_packets_WIRE_10_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_0 = _write_packets_WIRE_11_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_1 = _write_packets_WIRE_11_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_2 = _write_packets_WIRE_11_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_3 = _write_packets_WIRE_11_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_4 = _write_packets_WIRE_11_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_5 = _write_packets_WIRE_11_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_6 = _write_packets_WIRE_11_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_7 = _write_packets_WIRE_11_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_8 = _write_packets_WIRE_11_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_9 = _write_packets_WIRE_11_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_10 = _write_packets_WIRE_11_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_11 = _write_packets_WIRE_11_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_12 = _write_packets_WIRE_11_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_13 = _write_packets_WIRE_11_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_14 = _write_packets_WIRE_11_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_1_15 = _write_packets_WIRE_11_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_0 = _write_packets_WIRE_12_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_1 = _write_packets_WIRE_12_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_2 = _write_packets_WIRE_12_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_3 = _write_packets_WIRE_12_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_4 = _write_packets_WIRE_12_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_5 = _write_packets_WIRE_12_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_6 = _write_packets_WIRE_12_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_7 = _write_packets_WIRE_12_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_8 = _write_packets_WIRE_12_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_9 = _write_packets_WIRE_12_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_10 = _write_packets_WIRE_12_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_11 = _write_packets_WIRE_12_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_12 = _write_packets_WIRE_12_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_13 = _write_packets_WIRE_12_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_14 = _write_packets_WIRE_12_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_2_15 = _write_packets_WIRE_12_15; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_0 = _write_packets_WIRE_13_0; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_1 = _write_packets_WIRE_13_1; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_2 = _write_packets_WIRE_13_2; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_3 = _write_packets_WIRE_13_3; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_4 = _write_packets_WIRE_13_4; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_5 = _write_packets_WIRE_13_5; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_6 = _write_packets_WIRE_13_6; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_7 = _write_packets_WIRE_13_7; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_8 = _write_packets_WIRE_13_8; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_9 = _write_packets_WIRE_13_9; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_10 = _write_packets_WIRE_13_10; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_11 = _write_packets_WIRE_13_11; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_12 = _write_packets_WIRE_13_12; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_13 = _write_packets_WIRE_13_13; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_14 = _write_packets_WIRE_13_14; // @[DMA.scala:440:{29,70}] assign _write_packets_WIRE_14_3_15 = _write_packets_WIRE_13_15; // @[DMA.scala:440:{29,70}] assign write_packets_2_mask_0_0 = _write_packets_WIRE_14_0_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_1 = _write_packets_WIRE_14_0_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_2 = _write_packets_WIRE_14_0_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_3 = _write_packets_WIRE_14_0_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_4 = _write_packets_WIRE_14_0_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_5 = _write_packets_WIRE_14_0_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_6 = _write_packets_WIRE_14_0_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_7 = _write_packets_WIRE_14_0_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_8 = _write_packets_WIRE_14_0_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_9 = _write_packets_WIRE_14_0_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_10 = _write_packets_WIRE_14_0_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_11 = _write_packets_WIRE_14_0_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_12 = _write_packets_WIRE_14_0_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_13 = _write_packets_WIRE_14_0_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_14 = _write_packets_WIRE_14_0_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_0_15 = _write_packets_WIRE_14_0_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_0 = _write_packets_WIRE_14_1_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_1 = _write_packets_WIRE_14_1_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_2 = _write_packets_WIRE_14_1_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_3 = _write_packets_WIRE_14_1_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_4 = _write_packets_WIRE_14_1_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_5 = _write_packets_WIRE_14_1_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_6 = _write_packets_WIRE_14_1_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_7 = _write_packets_WIRE_14_1_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_8 = _write_packets_WIRE_14_1_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_9 = _write_packets_WIRE_14_1_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_10 = _write_packets_WIRE_14_1_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_11 = _write_packets_WIRE_14_1_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_12 = _write_packets_WIRE_14_1_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_13 = _write_packets_WIRE_14_1_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_14 = _write_packets_WIRE_14_1_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_1_15 = _write_packets_WIRE_14_1_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_0 = _write_packets_WIRE_14_2_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_1 = _write_packets_WIRE_14_2_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_2 = _write_packets_WIRE_14_2_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_3 = _write_packets_WIRE_14_2_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_4 = _write_packets_WIRE_14_2_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_5 = _write_packets_WIRE_14_2_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_6 = _write_packets_WIRE_14_2_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_7 = _write_packets_WIRE_14_2_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_8 = _write_packets_WIRE_14_2_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_9 = _write_packets_WIRE_14_2_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_10 = _write_packets_WIRE_14_2_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_11 = _write_packets_WIRE_14_2_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_12 = _write_packets_WIRE_14_2_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_13 = _write_packets_WIRE_14_2_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_14 = _write_packets_WIRE_14_2_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_2_15 = _write_packets_WIRE_14_2_15; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_0 = _write_packets_WIRE_14_3_0; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_1 = _write_packets_WIRE_14_3_1; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_2 = _write_packets_WIRE_14_3_2; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_3 = _write_packets_WIRE_14_3_3; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_4 = _write_packets_WIRE_14_3_4; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_5 = _write_packets_WIRE_14_3_5; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_6 = _write_packets_WIRE_14_3_6; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_7 = _write_packets_WIRE_14_3_7; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_8 = _write_packets_WIRE_14_3_8; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_9 = _write_packets_WIRE_14_3_9; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_10 = _write_packets_WIRE_14_3_10; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_11 = _write_packets_WIRE_14_3_11; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_12 = _write_packets_WIRE_14_3_12; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_13 = _write_packets_WIRE_14_3_13; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_14 = _write_packets_WIRE_14_3_14; // @[DMA.scala:437:24, :440:29] assign write_packets_2_mask_3_15 = _write_packets_WIRE_14_3_15; // @[DMA.scala:437:24, :440:29] wire _write_packets_packet_is_full_T_46 = write_packets_mask_0_2 & write_packets_mask_1_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_47 = _write_packets_packet_is_full_T_46 & write_packets_mask_2_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_48 = _write_packets_packet_is_full_T_47 & write_packets_mask_3_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_49 = _write_packets_packet_is_full_T_48 & write_packets_mask_4_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_50 = _write_packets_packet_is_full_T_49 & write_packets_mask_5_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_51 = _write_packets_packet_is_full_T_50 & write_packets_mask_6_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_52 = _write_packets_packet_is_full_T_51 & write_packets_mask_7_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_53 = _write_packets_packet_is_full_T_52 & write_packets_mask_8_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_54 = _write_packets_packet_is_full_T_53 & write_packets_mask_9_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_55 = _write_packets_packet_is_full_T_54 & write_packets_mask_10_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_56 = _write_packets_packet_is_full_T_55 & write_packets_mask_11_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_57 = _write_packets_packet_is_full_T_56 & write_packets_mask_12_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_58 = _write_packets_packet_is_full_T_57 & write_packets_mask_13_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_59 = _write_packets_packet_is_full_T_58 & write_packets_mask_14_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_60 = _write_packets_packet_is_full_T_59 & write_packets_mask_15_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_61 = _write_packets_packet_is_full_T_60 & write_packets_mask_16_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_62 = _write_packets_packet_is_full_T_61 & write_packets_mask_17_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_63 = _write_packets_packet_is_full_T_62 & write_packets_mask_18_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_64 = _write_packets_packet_is_full_T_63 & write_packets_mask_19_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_65 = _write_packets_packet_is_full_T_64 & write_packets_mask_20_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_66 = _write_packets_packet_is_full_T_65 & write_packets_mask_21_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_67 = _write_packets_packet_is_full_T_66 & write_packets_mask_22_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_68 = _write_packets_packet_is_full_T_67 & write_packets_mask_23_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_69 = _write_packets_packet_is_full_T_68 & write_packets_mask_24_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_70 = _write_packets_packet_is_full_T_69 & write_packets_mask_25_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_71 = _write_packets_packet_is_full_T_70 & write_packets_mask_26_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_72 = _write_packets_packet_is_full_T_71 & write_packets_mask_27_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_73 = _write_packets_packet_is_full_T_72 & write_packets_mask_28_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_74 = _write_packets_packet_is_full_T_73 & write_packets_mask_29_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_75 = _write_packets_packet_is_full_T_74 & write_packets_mask_30_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_76 = _write_packets_packet_is_full_T_75 & write_packets_mask_31_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_77 = _write_packets_packet_is_full_T_76 & write_packets_mask_32_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_78 = _write_packets_packet_is_full_T_77 & write_packets_mask_33_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_79 = _write_packets_packet_is_full_T_78 & write_packets_mask_34_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_80 = _write_packets_packet_is_full_T_79 & write_packets_mask_35_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_81 = _write_packets_packet_is_full_T_80 & write_packets_mask_36_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_82 = _write_packets_packet_is_full_T_81 & write_packets_mask_37_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_83 = _write_packets_packet_is_full_T_82 & write_packets_mask_38_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_84 = _write_packets_packet_is_full_T_83 & write_packets_mask_39_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_85 = _write_packets_packet_is_full_T_84 & write_packets_mask_40_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_86 = _write_packets_packet_is_full_T_85 & write_packets_mask_41_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_87 = _write_packets_packet_is_full_T_86 & write_packets_mask_42_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_88 = _write_packets_packet_is_full_T_87 & write_packets_mask_43_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_89 = _write_packets_packet_is_full_T_88 & write_packets_mask_44_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_90 = _write_packets_packet_is_full_T_89 & write_packets_mask_45_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_91 = _write_packets_packet_is_full_T_90 & write_packets_mask_46_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_92 = _write_packets_packet_is_full_T_91 & write_packets_mask_47_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_93 = _write_packets_packet_is_full_T_92 & write_packets_mask_48_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_94 = _write_packets_packet_is_full_T_93 & write_packets_mask_49_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_95 = _write_packets_packet_is_full_T_94 & write_packets_mask_50_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_96 = _write_packets_packet_is_full_T_95 & write_packets_mask_51_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_97 = _write_packets_packet_is_full_T_96 & write_packets_mask_52_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_98 = _write_packets_packet_is_full_T_97 & write_packets_mask_53_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_99 = _write_packets_packet_is_full_T_98 & write_packets_mask_54_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_100 = _write_packets_packet_is_full_T_99 & write_packets_mask_55_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_101 = _write_packets_packet_is_full_T_100 & write_packets_mask_56_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_102 = _write_packets_packet_is_full_T_101 & write_packets_mask_57_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_103 = _write_packets_packet_is_full_T_102 & write_packets_mask_58_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_104 = _write_packets_packet_is_full_T_103 & write_packets_mask_59_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_105 = _write_packets_packet_is_full_T_104 & write_packets_mask_60_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_106 = _write_packets_packet_is_full_T_105 & write_packets_mask_61_2; // @[DMA.scala:431:103, :442:47] wire _write_packets_packet_is_full_T_107 = _write_packets_packet_is_full_T_106 & write_packets_mask_62_2; // @[DMA.scala:431:103, :442:47] assign _write_packets_packet_is_full_T_108 = _write_packets_packet_is_full_T_107 & write_packets_mask_63_2; // @[DMA.scala:431:103, :442:47] assign write_packets_2_is_full = _write_packets_packet_is_full_T_108; // @[DMA.scala:437:24, :442:47] wire _write_packets_left_shift_T_42 = _write_packets_left_shift_T_41; // @[DMA.scala:449:{62,78}] wire [6:0] _write_packets_left_shift_T_43 = {1'h0, write_packets_vaddr_offset_2}; // @[DMA.scala:429:42, :450:24] wire [5:0] _write_packets_left_shift_T_44 = _write_packets_left_shift_T_43[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_8 = _write_packets_left_shift_T_42 ? _write_packets_left_shift_T_44 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_67 = _write_packets_right_shift_T_66 < 8'h10; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_68 = _write_packets_right_shift_T_67; // @[DMA.scala:453:{76,105}] wire [8:0] _write_packets_right_shift_T_70 = 9'h10 - {1'h0, _write_packets_right_shift_T_69}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_71 = _write_packets_right_shift_T_70[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_8 = _write_packets_right_shift_T_68 ? _write_packets_right_shift_T_71 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_early_8 = |(write_packets_vaddr_offset_2[5:4]); // @[DMA.scala:429:42, :431:52, :457:38] wire write_packets_too_late_8 = _write_packets_too_late_T_8 == 8'h0; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_0_T_10 = write_packets_too_early_8 | write_packets_too_late_8; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_11 = {3'h0, write_packets_left_shift_8} + {1'h0, write_packets_right_shift_8}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_0_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_0_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_13 = _write_packets_packet_bytes_written_per_beat_0_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_0_T_14 = _write_packets_packet_bytes_written_per_beat_0_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_0_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_0 = _write_packets_packet_bytes_written_per_beat_0_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_45 = |(write_packets_vaddr_offset_2[5:4]); // @[DMA.scala:429:42, :431:52, :449:43, :457:38] wire _write_packets_left_shift_T_46 = ~(write_packets_vaddr_offset_2[5]); // @[DMA.scala:429:42, :431:52, :449:78] wire _write_packets_left_shift_T_47 = _write_packets_left_shift_T_45 & _write_packets_left_shift_T_46; // @[DMA.scala:449:{43,62,78}] wire [6:0] _write_packets_left_shift_T_48 = _write_packets_left_shift_T_43 - 7'h10; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_49 = _write_packets_left_shift_T_48[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_9 = _write_packets_left_shift_T_47 ? _write_packets_left_shift_T_49 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_73 = |(_write_packets_right_shift_T_72[7:4]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_75 = _write_packets_right_shift_T_74 < 8'h20; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_76 = _write_packets_right_shift_T_73 & _write_packets_right_shift_T_75; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_78 = 9'h20 - {1'h0, _write_packets_right_shift_T_77}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_79 = _write_packets_right_shift_T_78[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_9 = _write_packets_right_shift_T_76 ? _write_packets_right_shift_T_79 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_9 = _write_packets_too_late_T_9 < 8'h11; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_1_T_10 = write_packets_too_early_9 | write_packets_too_late_9; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_11 = {3'h0, write_packets_left_shift_9} + {1'h0, write_packets_right_shift_9}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_1_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_1_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_13 = _write_packets_packet_bytes_written_per_beat_1_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_1_T_14 = _write_packets_packet_bytes_written_per_beat_1_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_1_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_1 = _write_packets_packet_bytes_written_per_beat_1_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_52 = _write_packets_left_shift_T_50 & _write_packets_left_shift_T_51; // @[DMA.scala:449:{43,62,78}] wire [6:0] _write_packets_left_shift_T_53 = _write_packets_left_shift_T_43 - 7'h20; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_54 = _write_packets_left_shift_T_53[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_10 = _write_packets_left_shift_T_52 ? _write_packets_left_shift_T_54 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_81 = |(_write_packets_right_shift_T_80[7:5]); // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_83 = _write_packets_right_shift_T_82 < 8'h30; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_84 = _write_packets_right_shift_T_81 & _write_packets_right_shift_T_83; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_86 = 9'h30 - {1'h0, _write_packets_right_shift_T_85}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_87 = _write_packets_right_shift_T_86[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_10 = _write_packets_right_shift_T_84 ? _write_packets_right_shift_T_87 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire _GEN_10 = write_packets_vaddr_offset_2 > 6'h2F; // @[DMA.scala:429:42, :457:38] wire write_packets_too_early_10; // @[DMA.scala:457:38] assign write_packets_too_early_10 = _GEN_10; // @[DMA.scala:457:38] wire _write_packets_left_shift_T_55; // @[DMA.scala:449:43] assign _write_packets_left_shift_T_55 = _GEN_10; // @[DMA.scala:449:43, :457:38] wire write_packets_too_late_10 = _write_packets_too_late_T_10 < 8'h21; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_2_T_10 = write_packets_too_early_10 | write_packets_too_late_10; // @[DMA.scala:457:38, :458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_11 = {3'h0, write_packets_left_shift_10} + {1'h0, write_packets_right_shift_10}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_2_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_2_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_13 = _write_packets_packet_bytes_written_per_beat_2_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_2_T_14 = _write_packets_packet_bytes_written_per_beat_2_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_2_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_2 = _write_packets_packet_bytes_written_per_beat_2_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _write_packets_left_shift_T_57 = _write_packets_left_shift_T_55; // @[DMA.scala:449:{43,62}] wire [6:0] _write_packets_left_shift_T_58 = _write_packets_left_shift_T_43 - 7'h30; // @[DMA.scala:450:24] wire [5:0] _write_packets_left_shift_T_59 = _write_packets_left_shift_T_58[5:0]; // @[DMA.scala:450:24] wire [5:0] write_packets_left_shift_11 = _write_packets_left_shift_T_57 ? _write_packets_left_shift_T_59 : 6'h0; // @[DMA.scala:449:{29,62}, :450:24] wire _write_packets_right_shift_T_89 = _write_packets_right_shift_T_88 > 8'h2F; // @[DMA.scala:453:{44,57}] wire _write_packets_right_shift_T_91 = _write_packets_right_shift_T_90 < 8'h40; // @[DMA.scala:453:{92,105}] wire _write_packets_right_shift_T_92 = _write_packets_right_shift_T_89 & _write_packets_right_shift_T_91; // @[DMA.scala:453:{57,76,105}] wire [8:0] _write_packets_right_shift_T_94 = 9'h40 - {1'h0, _write_packets_right_shift_T_93}; // @[DMA.scala:454:{25,41}] wire [7:0] _write_packets_right_shift_T_95 = _write_packets_right_shift_T_94[7:0]; // @[DMA.scala:454:25] wire [7:0] write_packets_right_shift_11 = _write_packets_right_shift_T_92 ? _write_packets_right_shift_T_95 : 8'h0; // @[DMA.scala:453:{30,76}, :454:25] wire write_packets_too_late_11 = _write_packets_too_late_T_11 < 8'h31; // @[DMA.scala:458:{37,50}] wire _write_packets_packet_bytes_written_per_beat_3_T_10 = write_packets_too_late_11; // @[DMA.scala:458:50, :460:28] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_11 = {3'h0, write_packets_left_shift_11} + {1'h0, write_packets_right_shift_11}; // @[DMA.scala:449:29, :453:30, :460:72] wire [9:0] _write_packets_packet_bytes_written_per_beat_3_T_12 = 10'h10 - {1'h0, _write_packets_packet_bytes_written_per_beat_3_T_11}; // @[DMA.scala:460:{58,72}] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_13 = _write_packets_packet_bytes_written_per_beat_3_T_12[8:0]; // @[DMA.scala:460:58] wire [8:0] _write_packets_packet_bytes_written_per_beat_3_T_14 = _write_packets_packet_bytes_written_per_beat_3_T_10 ? 9'h0 : _write_packets_packet_bytes_written_per_beat_3_T_13; // @[DMA.scala:460:{17,28,58}] assign write_packets_2_bytes_written_per_beat_3 = _write_packets_packet_bytes_written_per_beat_3_T_14[4:0]; // @[DMA.scala:437:24, :460:{11,17}] wire _best_write_packet_T = write_packets_1_bytes_written > write_packets_0_bytes_written; // @[DMA.scala:437:24, :466:27] wire [6:0] _best_write_packet_T_1_size = _best_write_packet_T ? 7'h20 : 7'h10; // @[DMA.scala:466:{10,27}] wire [2:0] _best_write_packet_T_1_lg_size = {2'h2, _best_write_packet_T}; // @[DMA.scala:466:{10,27}] wire _best_write_packet_T_1_mask_0_0 = _best_write_packet_T ? write_packets_1_mask_0_0 : write_packets_0_mask_0_0; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_1 = _best_write_packet_T ? write_packets_1_mask_0_1 : write_packets_0_mask_0_1; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_2 = _best_write_packet_T ? write_packets_1_mask_0_2 : write_packets_0_mask_0_2; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_3 = _best_write_packet_T ? write_packets_1_mask_0_3 : write_packets_0_mask_0_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_4 = _best_write_packet_T ? write_packets_1_mask_0_4 : write_packets_0_mask_0_4; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_5 = _best_write_packet_T ? write_packets_1_mask_0_5 : write_packets_0_mask_0_5; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_6 = _best_write_packet_T ? write_packets_1_mask_0_6 : write_packets_0_mask_0_6; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_7 = _best_write_packet_T ? write_packets_1_mask_0_7 : write_packets_0_mask_0_7; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_8 = _best_write_packet_T ? write_packets_1_mask_0_8 : write_packets_0_mask_0_8; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_9 = _best_write_packet_T ? write_packets_1_mask_0_9 : write_packets_0_mask_0_9; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_10 = _best_write_packet_T ? write_packets_1_mask_0_10 : write_packets_0_mask_0_10; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_11 = _best_write_packet_T ? write_packets_1_mask_0_11 : write_packets_0_mask_0_11; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_12 = _best_write_packet_T ? write_packets_1_mask_0_12 : write_packets_0_mask_0_12; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_13 = _best_write_packet_T ? write_packets_1_mask_0_13 : write_packets_0_mask_0_13; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_14 = _best_write_packet_T ? write_packets_1_mask_0_14 : write_packets_0_mask_0_14; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_0_15 = _best_write_packet_T ? write_packets_1_mask_0_15 : write_packets_0_mask_0_15; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_0 = _best_write_packet_T & write_packets_1_mask_1_0; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_1 = _best_write_packet_T & write_packets_1_mask_1_1; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_2 = _best_write_packet_T & write_packets_1_mask_1_2; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_3 = _best_write_packet_T & write_packets_1_mask_1_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_4 = _best_write_packet_T & write_packets_1_mask_1_4; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_5 = _best_write_packet_T & write_packets_1_mask_1_5; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_6 = _best_write_packet_T & write_packets_1_mask_1_6; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_7 = _best_write_packet_T & write_packets_1_mask_1_7; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_8 = _best_write_packet_T & write_packets_1_mask_1_8; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_9 = _best_write_packet_T & write_packets_1_mask_1_9; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_10 = _best_write_packet_T & write_packets_1_mask_1_10; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_11 = _best_write_packet_T & write_packets_1_mask_1_11; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_12 = _best_write_packet_T & write_packets_1_mask_1_12; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_13 = _best_write_packet_T & write_packets_1_mask_1_13; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_14 = _best_write_packet_T & write_packets_1_mask_1_14; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_mask_1_15 = _best_write_packet_T & write_packets_1_mask_1_15; // @[DMA.scala:437:24, :466:{10,27}] wire [38:0] _best_write_packet_T_1_vaddr = _best_write_packet_T ? write_packets_1_vaddr : write_packets_0_vaddr; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_1_is_full = _best_write_packet_T ? write_packets_1_is_full : write_packets_0_is_full; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] _best_write_packet_T_1_bytes_written = _best_write_packet_T ? write_packets_1_bytes_written : write_packets_0_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_0 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_0 : write_packets_0_bytes_written_per_beat_0; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_1 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_1 : write_packets_0_bytes_written_per_beat_1; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_2 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_2 : write_packets_0_bytes_written_per_beat_2; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] _best_write_packet_T_1_bytes_written_per_beat_3 = _best_write_packet_T ? write_packets_1_bytes_written_per_beat_3 : write_packets_0_bytes_written_per_beat_3; // @[DMA.scala:437:24, :466:{10,27}] wire _best_write_packet_T_2 = write_packets_2_bytes_written > _best_write_packet_T_1_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] best_write_packet_size = _best_write_packet_T_2 ? 7'h40 : _best_write_packet_T_1_size; // @[DMA.scala:466:{10,27}] wire [2:0] best_write_packet_lg_size = _best_write_packet_T_2 ? 3'h6 : _best_write_packet_T_1_lg_size; // @[DMA.scala:466:{10,27}] wire best_write_packet_mask_0_0 = _best_write_packet_T_2 ? write_packets_2_mask_0_0 : _best_write_packet_T_1_mask_0_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_1 = _best_write_packet_T_2 ? write_packets_2_mask_0_1 : _best_write_packet_T_1_mask_0_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_2 = _best_write_packet_T_2 ? write_packets_2_mask_0_2 : _best_write_packet_T_1_mask_0_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_3 = _best_write_packet_T_2 ? write_packets_2_mask_0_3 : _best_write_packet_T_1_mask_0_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_4 = _best_write_packet_T_2 ? write_packets_2_mask_0_4 : _best_write_packet_T_1_mask_0_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_5 = _best_write_packet_T_2 ? write_packets_2_mask_0_5 : _best_write_packet_T_1_mask_0_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_6 = _best_write_packet_T_2 ? write_packets_2_mask_0_6 : _best_write_packet_T_1_mask_0_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_7 = _best_write_packet_T_2 ? write_packets_2_mask_0_7 : _best_write_packet_T_1_mask_0_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_8 = _best_write_packet_T_2 ? write_packets_2_mask_0_8 : _best_write_packet_T_1_mask_0_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_9 = _best_write_packet_T_2 ? write_packets_2_mask_0_9 : _best_write_packet_T_1_mask_0_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_10 = _best_write_packet_T_2 ? write_packets_2_mask_0_10 : _best_write_packet_T_1_mask_0_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_11 = _best_write_packet_T_2 ? write_packets_2_mask_0_11 : _best_write_packet_T_1_mask_0_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_12 = _best_write_packet_T_2 ? write_packets_2_mask_0_12 : _best_write_packet_T_1_mask_0_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_13 = _best_write_packet_T_2 ? write_packets_2_mask_0_13 : _best_write_packet_T_1_mask_0_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_14 = _best_write_packet_T_2 ? write_packets_2_mask_0_14 : _best_write_packet_T_1_mask_0_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_0_15 = _best_write_packet_T_2 ? write_packets_2_mask_0_15 : _best_write_packet_T_1_mask_0_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_0 = _best_write_packet_T_2 ? write_packets_2_mask_1_0 : _best_write_packet_T_1_mask_1_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_1 = _best_write_packet_T_2 ? write_packets_2_mask_1_1 : _best_write_packet_T_1_mask_1_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_2 = _best_write_packet_T_2 ? write_packets_2_mask_1_2 : _best_write_packet_T_1_mask_1_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_3 = _best_write_packet_T_2 ? write_packets_2_mask_1_3 : _best_write_packet_T_1_mask_1_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_4 = _best_write_packet_T_2 ? write_packets_2_mask_1_4 : _best_write_packet_T_1_mask_1_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_5 = _best_write_packet_T_2 ? write_packets_2_mask_1_5 : _best_write_packet_T_1_mask_1_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_6 = _best_write_packet_T_2 ? write_packets_2_mask_1_6 : _best_write_packet_T_1_mask_1_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_7 = _best_write_packet_T_2 ? write_packets_2_mask_1_7 : _best_write_packet_T_1_mask_1_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_8 = _best_write_packet_T_2 ? write_packets_2_mask_1_8 : _best_write_packet_T_1_mask_1_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_9 = _best_write_packet_T_2 ? write_packets_2_mask_1_9 : _best_write_packet_T_1_mask_1_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_10 = _best_write_packet_T_2 ? write_packets_2_mask_1_10 : _best_write_packet_T_1_mask_1_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_11 = _best_write_packet_T_2 ? write_packets_2_mask_1_11 : _best_write_packet_T_1_mask_1_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_12 = _best_write_packet_T_2 ? write_packets_2_mask_1_12 : _best_write_packet_T_1_mask_1_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_13 = _best_write_packet_T_2 ? write_packets_2_mask_1_13 : _best_write_packet_T_1_mask_1_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_14 = _best_write_packet_T_2 ? write_packets_2_mask_1_14 : _best_write_packet_T_1_mask_1_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_1_15 = _best_write_packet_T_2 ? write_packets_2_mask_1_15 : _best_write_packet_T_1_mask_1_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_0 = _best_write_packet_T_2 & write_packets_2_mask_2_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_1 = _best_write_packet_T_2 & write_packets_2_mask_2_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_2 = _best_write_packet_T_2 & write_packets_2_mask_2_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_3 = _best_write_packet_T_2 & write_packets_2_mask_2_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_4 = _best_write_packet_T_2 & write_packets_2_mask_2_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_5 = _best_write_packet_T_2 & write_packets_2_mask_2_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_6 = _best_write_packet_T_2 & write_packets_2_mask_2_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_7 = _best_write_packet_T_2 & write_packets_2_mask_2_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_8 = _best_write_packet_T_2 & write_packets_2_mask_2_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_9 = _best_write_packet_T_2 & write_packets_2_mask_2_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_10 = _best_write_packet_T_2 & write_packets_2_mask_2_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_11 = _best_write_packet_T_2 & write_packets_2_mask_2_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_12 = _best_write_packet_T_2 & write_packets_2_mask_2_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_13 = _best_write_packet_T_2 & write_packets_2_mask_2_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_14 = _best_write_packet_T_2 & write_packets_2_mask_2_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_2_15 = _best_write_packet_T_2 & write_packets_2_mask_2_15; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_0 = _best_write_packet_T_2 & write_packets_2_mask_3_0; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_1 = _best_write_packet_T_2 & write_packets_2_mask_3_1; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_2 = _best_write_packet_T_2 & write_packets_2_mask_3_2; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_3 = _best_write_packet_T_2 & write_packets_2_mask_3_3; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_4 = _best_write_packet_T_2 & write_packets_2_mask_3_4; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_5 = _best_write_packet_T_2 & write_packets_2_mask_3_5; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_6 = _best_write_packet_T_2 & write_packets_2_mask_3_6; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_7 = _best_write_packet_T_2 & write_packets_2_mask_3_7; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_8 = _best_write_packet_T_2 & write_packets_2_mask_3_8; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_9 = _best_write_packet_T_2 & write_packets_2_mask_3_9; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_10 = _best_write_packet_T_2 & write_packets_2_mask_3_10; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_11 = _best_write_packet_T_2 & write_packets_2_mask_3_11; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_12 = _best_write_packet_T_2 & write_packets_2_mask_3_12; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_13 = _best_write_packet_T_2 & write_packets_2_mask_3_13; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_14 = _best_write_packet_T_2 & write_packets_2_mask_3_14; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_mask_3_15 = _best_write_packet_T_2 & write_packets_2_mask_3_15; // @[DMA.scala:437:24, :466:{10,27}] wire [38:0] best_write_packet_vaddr = _best_write_packet_T_2 ? write_packets_2_vaddr : _best_write_packet_T_1_vaddr; // @[DMA.scala:437:24, :466:{10,27}] wire best_write_packet_is_full = _best_write_packet_T_2 ? write_packets_2_is_full : _best_write_packet_T_1_is_full; // @[DMA.scala:437:24, :466:{10,27}] wire [6:0] best_write_packet_bytes_written = _best_write_packet_T_2 ? write_packets_2_bytes_written : _best_write_packet_T_1_bytes_written; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_0 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_0 : _best_write_packet_T_1_bytes_written_per_beat_0; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_1 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_1 : _best_write_packet_T_1_bytes_written_per_beat_1; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_2 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_2 : _best_write_packet_T_1_bytes_written_per_beat_2; // @[DMA.scala:437:24, :466:{10,27}] wire [4:0] best_write_packet_bytes_written_per_beat_3 = _best_write_packet_T_2 ? write_packets_2_bytes_written_per_beat_3 : _best_write_packet_T_1_bytes_written_per_beat_3; // @[DMA.scala:437:24, :466:{10,27}] wire _T_7 = state == 2'h1; // @[DMA.scala:380:24, :468:63] wire _write_packet_T; // @[DMA.scala:468:63] assign _write_packet_T = _T_7; // @[DMA.scala:468:63] wire _beatsSent_T; // @[DMA.scala:477:31] assign _beatsSent_T = _T_7; // @[DMA.scala:468:63, :477:31] wire _putFull_T; // @[DMA.scala:486:48] assign _putFull_T = _T_7; // @[DMA.scala:468:63, :486:48] wire _putPartial_T; // @[DMA.scala:493:48] assign _putPartial_T = _T_7; // @[DMA.scala:468:63, :493:48] wire _xactBusy_fire_T_1; // @[DMA.scala:507:51] assign _xactBusy_fire_T_1 = _T_7; // @[DMA.scala:468:63, :507:51] wire _untranslated_a_valid_T; // @[DMA.scala:508:36] assign _untranslated_a_valid_T = _T_7; // @[DMA.scala:468:63, :508:36] reg [6:0] write_packet_buf_size; // @[Util.scala:90:24] reg [2:0] write_packet_buf_lg_size; // @[Util.scala:90:24] reg write_packet_buf_mask_0_0; // @[Util.scala:90:24] reg write_packet_buf_mask_0_1; // @[Util.scala:90:24] reg write_packet_buf_mask_0_2; // @[Util.scala:90:24] reg write_packet_buf_mask_0_3; // @[Util.scala:90:24] reg write_packet_buf_mask_0_4; // @[Util.scala:90:24] reg write_packet_buf_mask_0_5; // @[Util.scala:90:24] reg write_packet_buf_mask_0_6; // @[Util.scala:90:24] reg write_packet_buf_mask_0_7; // @[Util.scala:90:24] reg write_packet_buf_mask_0_8; // @[Util.scala:90:24] reg write_packet_buf_mask_0_9; // @[Util.scala:90:24] reg write_packet_buf_mask_0_10; // @[Util.scala:90:24] reg write_packet_buf_mask_0_11; // @[Util.scala:90:24] reg write_packet_buf_mask_0_12; // @[Util.scala:90:24] reg write_packet_buf_mask_0_13; // @[Util.scala:90:24] reg write_packet_buf_mask_0_14; // @[Util.scala:90:24] reg write_packet_buf_mask_0_15; // @[Util.scala:90:24] reg write_packet_buf_mask_1_0; // @[Util.scala:90:24] reg write_packet_buf_mask_1_1; // @[Util.scala:90:24] reg write_packet_buf_mask_1_2; // @[Util.scala:90:24] reg write_packet_buf_mask_1_3; // @[Util.scala:90:24] reg write_packet_buf_mask_1_4; // @[Util.scala:90:24] reg write_packet_buf_mask_1_5; // @[Util.scala:90:24] reg write_packet_buf_mask_1_6; // @[Util.scala:90:24] reg write_packet_buf_mask_1_7; // @[Util.scala:90:24] reg write_packet_buf_mask_1_8; // @[Util.scala:90:24] reg write_packet_buf_mask_1_9; // @[Util.scala:90:24] reg write_packet_buf_mask_1_10; // @[Util.scala:90:24] reg write_packet_buf_mask_1_11; // @[Util.scala:90:24] reg write_packet_buf_mask_1_12; // @[Util.scala:90:24] reg write_packet_buf_mask_1_13; // @[Util.scala:90:24] reg write_packet_buf_mask_1_14; // @[Util.scala:90:24] reg write_packet_buf_mask_1_15; // @[Util.scala:90:24] reg write_packet_buf_mask_2_0; // @[Util.scala:90:24] reg write_packet_buf_mask_2_1; // @[Util.scala:90:24] reg write_packet_buf_mask_2_2; // @[Util.scala:90:24] reg write_packet_buf_mask_2_3; // @[Util.scala:90:24] reg write_packet_buf_mask_2_4; // @[Util.scala:90:24] reg write_packet_buf_mask_2_5; // @[Util.scala:90:24] reg write_packet_buf_mask_2_6; // @[Util.scala:90:24] reg write_packet_buf_mask_2_7; // @[Util.scala:90:24] reg write_packet_buf_mask_2_8; // @[Util.scala:90:24] reg write_packet_buf_mask_2_9; // @[Util.scala:90:24] reg write_packet_buf_mask_2_10; // @[Util.scala:90:24] reg write_packet_buf_mask_2_11; // @[Util.scala:90:24] reg write_packet_buf_mask_2_12; // @[Util.scala:90:24] reg write_packet_buf_mask_2_13; // @[Util.scala:90:24] reg write_packet_buf_mask_2_14; // @[Util.scala:90:24] reg write_packet_buf_mask_2_15; // @[Util.scala:90:24] reg write_packet_buf_mask_3_0; // @[Util.scala:90:24] reg write_packet_buf_mask_3_1; // @[Util.scala:90:24] reg write_packet_buf_mask_3_2; // @[Util.scala:90:24] reg write_packet_buf_mask_3_3; // @[Util.scala:90:24] reg write_packet_buf_mask_3_4; // @[Util.scala:90:24] reg write_packet_buf_mask_3_5; // @[Util.scala:90:24] reg write_packet_buf_mask_3_6; // @[Util.scala:90:24] reg write_packet_buf_mask_3_7; // @[Util.scala:90:24] reg write_packet_buf_mask_3_8; // @[Util.scala:90:24] reg write_packet_buf_mask_3_9; // @[Util.scala:90:24] reg write_packet_buf_mask_3_10; // @[Util.scala:90:24] reg write_packet_buf_mask_3_11; // @[Util.scala:90:24] reg write_packet_buf_mask_3_12; // @[Util.scala:90:24] reg write_packet_buf_mask_3_13; // @[Util.scala:90:24] reg write_packet_buf_mask_3_14; // @[Util.scala:90:24] reg write_packet_buf_mask_3_15; // @[Util.scala:90:24] reg [38:0] write_packet_buf_vaddr; // @[Util.scala:90:24] reg write_packet_buf_is_full; // @[Util.scala:90:24] reg [6:0] write_packet_buf_bytes_written; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_0; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_1; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_2; // @[Util.scala:90:24] reg [4:0] write_packet_buf_bytes_written_per_beat_3; // @[Util.scala:90:24] wire [6:0] write_packet_size = _write_packet_T ? best_write_packet_size : write_packet_buf_size; // @[Util.scala:90:24, :91:8] wire [2:0] write_packet_lg_size = _write_packet_T ? best_write_packet_lg_size : write_packet_buf_lg_size; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_0 = _write_packet_T ? best_write_packet_mask_0_0 : write_packet_buf_mask_0_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_1 = _write_packet_T ? best_write_packet_mask_0_1 : write_packet_buf_mask_0_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_2 = _write_packet_T ? best_write_packet_mask_0_2 : write_packet_buf_mask_0_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_3 = _write_packet_T ? best_write_packet_mask_0_3 : write_packet_buf_mask_0_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_4 = _write_packet_T ? best_write_packet_mask_0_4 : write_packet_buf_mask_0_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_5 = _write_packet_T ? best_write_packet_mask_0_5 : write_packet_buf_mask_0_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_6 = _write_packet_T ? best_write_packet_mask_0_6 : write_packet_buf_mask_0_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_7 = _write_packet_T ? best_write_packet_mask_0_7 : write_packet_buf_mask_0_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_8 = _write_packet_T ? best_write_packet_mask_0_8 : write_packet_buf_mask_0_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_9 = _write_packet_T ? best_write_packet_mask_0_9 : write_packet_buf_mask_0_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_10 = _write_packet_T ? best_write_packet_mask_0_10 : write_packet_buf_mask_0_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_11 = _write_packet_T ? best_write_packet_mask_0_11 : write_packet_buf_mask_0_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_12 = _write_packet_T ? best_write_packet_mask_0_12 : write_packet_buf_mask_0_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_13 = _write_packet_T ? best_write_packet_mask_0_13 : write_packet_buf_mask_0_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_14 = _write_packet_T ? best_write_packet_mask_0_14 : write_packet_buf_mask_0_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_0_15 = _write_packet_T ? best_write_packet_mask_0_15 : write_packet_buf_mask_0_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_0 = _write_packet_T ? best_write_packet_mask_1_0 : write_packet_buf_mask_1_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_1 = _write_packet_T ? best_write_packet_mask_1_1 : write_packet_buf_mask_1_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_2 = _write_packet_T ? best_write_packet_mask_1_2 : write_packet_buf_mask_1_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_3 = _write_packet_T ? best_write_packet_mask_1_3 : write_packet_buf_mask_1_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_4 = _write_packet_T ? best_write_packet_mask_1_4 : write_packet_buf_mask_1_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_5 = _write_packet_T ? best_write_packet_mask_1_5 : write_packet_buf_mask_1_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_6 = _write_packet_T ? best_write_packet_mask_1_6 : write_packet_buf_mask_1_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_7 = _write_packet_T ? best_write_packet_mask_1_7 : write_packet_buf_mask_1_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_8 = _write_packet_T ? best_write_packet_mask_1_8 : write_packet_buf_mask_1_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_9 = _write_packet_T ? best_write_packet_mask_1_9 : write_packet_buf_mask_1_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_10 = _write_packet_T ? best_write_packet_mask_1_10 : write_packet_buf_mask_1_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_11 = _write_packet_T ? best_write_packet_mask_1_11 : write_packet_buf_mask_1_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_12 = _write_packet_T ? best_write_packet_mask_1_12 : write_packet_buf_mask_1_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_13 = _write_packet_T ? best_write_packet_mask_1_13 : write_packet_buf_mask_1_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_14 = _write_packet_T ? best_write_packet_mask_1_14 : write_packet_buf_mask_1_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_1_15 = _write_packet_T ? best_write_packet_mask_1_15 : write_packet_buf_mask_1_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_0 = _write_packet_T ? best_write_packet_mask_2_0 : write_packet_buf_mask_2_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_1 = _write_packet_T ? best_write_packet_mask_2_1 : write_packet_buf_mask_2_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_2 = _write_packet_T ? best_write_packet_mask_2_2 : write_packet_buf_mask_2_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_3 = _write_packet_T ? best_write_packet_mask_2_3 : write_packet_buf_mask_2_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_4 = _write_packet_T ? best_write_packet_mask_2_4 : write_packet_buf_mask_2_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_5 = _write_packet_T ? best_write_packet_mask_2_5 : write_packet_buf_mask_2_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_6 = _write_packet_T ? best_write_packet_mask_2_6 : write_packet_buf_mask_2_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_7 = _write_packet_T ? best_write_packet_mask_2_7 : write_packet_buf_mask_2_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_8 = _write_packet_T ? best_write_packet_mask_2_8 : write_packet_buf_mask_2_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_9 = _write_packet_T ? best_write_packet_mask_2_9 : write_packet_buf_mask_2_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_10 = _write_packet_T ? best_write_packet_mask_2_10 : write_packet_buf_mask_2_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_11 = _write_packet_T ? best_write_packet_mask_2_11 : write_packet_buf_mask_2_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_12 = _write_packet_T ? best_write_packet_mask_2_12 : write_packet_buf_mask_2_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_13 = _write_packet_T ? best_write_packet_mask_2_13 : write_packet_buf_mask_2_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_14 = _write_packet_T ? best_write_packet_mask_2_14 : write_packet_buf_mask_2_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_2_15 = _write_packet_T ? best_write_packet_mask_2_15 : write_packet_buf_mask_2_15; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_0 = _write_packet_T ? best_write_packet_mask_3_0 : write_packet_buf_mask_3_0; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_1 = _write_packet_T ? best_write_packet_mask_3_1 : write_packet_buf_mask_3_1; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_2 = _write_packet_T ? best_write_packet_mask_3_2 : write_packet_buf_mask_3_2; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_3 = _write_packet_T ? best_write_packet_mask_3_3 : write_packet_buf_mask_3_3; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_4 = _write_packet_T ? best_write_packet_mask_3_4 : write_packet_buf_mask_3_4; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_5 = _write_packet_T ? best_write_packet_mask_3_5 : write_packet_buf_mask_3_5; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_6 = _write_packet_T ? best_write_packet_mask_3_6 : write_packet_buf_mask_3_6; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_7 = _write_packet_T ? best_write_packet_mask_3_7 : write_packet_buf_mask_3_7; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_8 = _write_packet_T ? best_write_packet_mask_3_8 : write_packet_buf_mask_3_8; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_9 = _write_packet_T ? best_write_packet_mask_3_9 : write_packet_buf_mask_3_9; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_10 = _write_packet_T ? best_write_packet_mask_3_10 : write_packet_buf_mask_3_10; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_11 = _write_packet_T ? best_write_packet_mask_3_11 : write_packet_buf_mask_3_11; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_12 = _write_packet_T ? best_write_packet_mask_3_12 : write_packet_buf_mask_3_12; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_13 = _write_packet_T ? best_write_packet_mask_3_13 : write_packet_buf_mask_3_13; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_14 = _write_packet_T ? best_write_packet_mask_3_14 : write_packet_buf_mask_3_14; // @[Util.scala:90:24, :91:8] wire write_packet_mask_3_15 = _write_packet_T ? best_write_packet_mask_3_15 : write_packet_buf_mask_3_15; // @[Util.scala:90:24, :91:8] wire [38:0] write_packet_vaddr = _write_packet_T ? best_write_packet_vaddr : write_packet_buf_vaddr; // @[Util.scala:90:24, :91:8] wire write_packet_is_full = _write_packet_T ? best_write_packet_is_full : write_packet_buf_is_full; // @[Util.scala:90:24, :91:8] wire [6:0] write_packet_bytes_written = _write_packet_T ? best_write_packet_bytes_written : write_packet_buf_bytes_written; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_0 = _write_packet_T ? best_write_packet_bytes_written_per_beat_0 : write_packet_buf_bytes_written_per_beat_0; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_1 = _write_packet_T ? best_write_packet_bytes_written_per_beat_1 : write_packet_buf_bytes_written_per_beat_1; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_2 = _write_packet_T ? best_write_packet_bytes_written_per_beat_2 : write_packet_buf_bytes_written_per_beat_2; // @[Util.scala:90:24, :91:8] wire [4:0] write_packet_bytes_written_per_beat_3 = _write_packet_T ? best_write_packet_bytes_written_per_beat_3 : write_packet_buf_bytes_written_per_beat_3; // @[Util.scala:90:24, :91:8] wire [38:0] untranslated_a_bits_vaddr = write_packet_vaddr; // @[Util.scala:91:8] wire _write_beats_T = write_packet_size < 7'h10; // @[Util.scala:91:8] wire [6:0] _write_beats_T_1 = write_packet_size / 7'h10; // @[Util.scala:91:8] wire [6:0] write_beats = _write_beats_T ? 7'h1 : _write_beats_T_1; // @[DMA.scala:418:{44,50,75}] reg [5:0] beatsLeft; // @[DMA.scala:476:24] wire [7:0] _GEN_11 = {1'h0, write_beats}; // @[DMA.scala:418:44, :477:73] wire [7:0] _beatsSent_T_1 = _GEN_11 - {2'h0, beatsLeft}; // @[DMA.scala:476:24, :477:73] wire [6:0] _beatsSent_T_2 = _beatsSent_T_1[6:0]; // @[DMA.scala:477:73] wire [6:0] beatsSent = _beatsSent_T ? 7'h0 : _beatsSent_T_2; // @[DMA.scala:477:{24,31,73}] wire [1:0] _write_mask_T = beatsSent[1:0]; // @[DMA.scala:477:24] wire [1:0] _bytes_written_this_beat_T = beatsSent[1:0]; // @[DMA.scala:477:24] wire [3:0] _GEN_12 = {{write_packet_mask_3_0}, {write_packet_mask_2_0}, {write_packet_mask_1_0}, {write_packet_mask_0_0}}; // @[Mux.scala:50:70] wire [3:0] _GEN_13 = {{write_packet_mask_3_1}, {write_packet_mask_2_1}, {write_packet_mask_1_1}, {write_packet_mask_0_1}}; // @[Mux.scala:50:70] wire [3:0] _GEN_14 = {{write_packet_mask_3_2}, {write_packet_mask_2_2}, {write_packet_mask_1_2}, {write_packet_mask_0_2}}; // @[Mux.scala:50:70] wire [3:0] _GEN_15 = {{write_packet_mask_3_3}, {write_packet_mask_2_3}, {write_packet_mask_1_3}, {write_packet_mask_0_3}}; // @[Mux.scala:50:70] wire [3:0] _GEN_16 = {{write_packet_mask_3_4}, {write_packet_mask_2_4}, {write_packet_mask_1_4}, {write_packet_mask_0_4}}; // @[Mux.scala:50:70] wire [3:0] _GEN_17 = {{write_packet_mask_3_5}, {write_packet_mask_2_5}, {write_packet_mask_1_5}, {write_packet_mask_0_5}}; // @[Mux.scala:50:70] wire [3:0] _GEN_18 = {{write_packet_mask_3_6}, {write_packet_mask_2_6}, {write_packet_mask_1_6}, {write_packet_mask_0_6}}; // @[Mux.scala:50:70] wire [3:0] _GEN_19 = {{write_packet_mask_3_7}, {write_packet_mask_2_7}, {write_packet_mask_1_7}, {write_packet_mask_0_7}}; // @[Mux.scala:50:70] wire [3:0] _GEN_20 = {{write_packet_mask_3_8}, {write_packet_mask_2_8}, {write_packet_mask_1_8}, {write_packet_mask_0_8}}; // @[Mux.scala:50:70] wire [3:0] _GEN_21 = {{write_packet_mask_3_9}, {write_packet_mask_2_9}, {write_packet_mask_1_9}, {write_packet_mask_0_9}}; // @[Mux.scala:50:70] wire [3:0] _GEN_22 = {{write_packet_mask_3_10}, {write_packet_mask_2_10}, {write_packet_mask_1_10}, {write_packet_mask_0_10}}; // @[Mux.scala:50:70] wire [3:0] _GEN_23 = {{write_packet_mask_3_11}, {write_packet_mask_2_11}, {write_packet_mask_1_11}, {write_packet_mask_0_11}}; // @[Mux.scala:50:70] wire [3:0] _GEN_24 = {{write_packet_mask_3_12}, {write_packet_mask_2_12}, {write_packet_mask_1_12}, {write_packet_mask_0_12}}; // @[Mux.scala:50:70] wire [3:0] _GEN_25 = {{write_packet_mask_3_13}, {write_packet_mask_2_13}, {write_packet_mask_1_13}, {write_packet_mask_0_13}}; // @[Mux.scala:50:70] wire [3:0] _GEN_26 = {{write_packet_mask_3_14}, {write_packet_mask_2_14}, {write_packet_mask_1_14}, {write_packet_mask_0_14}}; // @[Mux.scala:50:70] wire [3:0] _GEN_27 = {{write_packet_mask_3_15}, {write_packet_mask_2_15}, {write_packet_mask_1_15}, {write_packet_mask_0_15}}; // @[Mux.scala:50:70] wire [3:0] _write_shift_T = {3'h7, ~_GEN_26[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_1 = _GEN_25[_write_mask_T] ? 4'hD : _write_shift_T; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_2 = _GEN_24[_write_mask_T] ? 4'hC : _write_shift_T_1; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_3 = _GEN_23[_write_mask_T] ? 4'hB : _write_shift_T_2; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_4 = _GEN_22[_write_mask_T] ? 4'hA : _write_shift_T_3; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_5 = _GEN_21[_write_mask_T] ? 4'h9 : _write_shift_T_4; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_6 = _GEN_20[_write_mask_T] ? 4'h8 : _write_shift_T_5; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_7 = _GEN_19[_write_mask_T] ? 4'h7 : _write_shift_T_6; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_8 = _GEN_18[_write_mask_T] ? 4'h6 : _write_shift_T_7; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_9 = _GEN_17[_write_mask_T] ? 4'h5 : _write_shift_T_8; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_10 = _GEN_16[_write_mask_T] ? 4'h4 : _write_shift_T_9; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_11 = _GEN_15[_write_mask_T] ? 4'h3 : _write_shift_T_10; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_12 = _GEN_14[_write_mask_T] ? 4'h2 : _write_shift_T_11; // @[Mux.scala:50:70] wire [3:0] _write_shift_T_13 = _GEN_13[_write_mask_T] ? 4'h1 : _write_shift_T_12; // @[Mux.scala:50:70] wire [3:0] write_shift = _GEN_12[_write_mask_T] ? 4'h0 : _write_shift_T_13; // @[Mux.scala:50:70] reg [5:0] putFull_buf; // @[Util.scala:90:24] wire [5:0] _putFull_T_1 = _putFull_T ? xactId : putFull_buf; // @[OneHot.scala:32:10] wire [5:0] putFull_source = _putFull_T_1; // @[Edges.scala:480:17] wire [10:0] _GEN_28 = {1'h0, bytesSent, 3'h0}; // @[DMA.scala:389:24, :489:34] wire [10:0] _putFull_T_2; // @[DMA.scala:489:34] assign _putFull_T_2 = _GEN_28; // @[DMA.scala:489:34] wire [10:0] _putPartial_T_2; // @[DMA.scala:496:35] assign _putPartial_T_2 = _GEN_28; // @[DMA.scala:489:34, :496:35] wire [511:0] _putFull_T_3 = data >> _putFull_T_2; // @[DMA.scala:387:19, :489:{20,34}] wire _GEN_29 = write_packet_lg_size != 3'h7; // @[Parameters.scala:92:38] wire _putFull_legal_T_11; // @[Parameters.scala:92:38] assign _putFull_legal_T_11 = _GEN_29; // @[Parameters.scala:92:38] wire _putPartial_legal_T_11; // @[Parameters.scala:92:38] assign _putPartial_legal_T_11 = _GEN_29; // @[Parameters.scala:92:38] wire _putFull_legal_T_12 = _putFull_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _putFull_legal_T_13 = _putFull_legal_T_12; // @[Parameters.scala:684:29] wire _putFull_legal_T_61 = _putFull_legal_T_13; // @[Parameters.scala:684:{29,54}] wire _putFull_legal_T_70 = _putFull_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putFull_legal = _putFull_legal_T_70; // @[Parameters.scala:686:26] wire [15:0] _putFull_a_mask_T; // @[Misc.scala:222:10] wire [3:0] putFull_size; // @[Edges.scala:480:17] wire [15:0] putFull_mask; // @[Edges.scala:480:17] wire [127:0] putFull_data; // @[Edges.scala:480:17] wire [3:0] _GEN_30 = {1'h0, write_packet_lg_size}; // @[Edges.scala:483:15] assign putFull_size = _GEN_30; // @[Edges.scala:480:17, :483:15] wire [3:0] _putFull_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _putFull_a_mask_sizeOH_T = _GEN_30; // @[Misc.scala:202:34] wire [3:0] putPartial_size; // @[Edges.scala:500:17] assign putPartial_size = _GEN_30; // @[Edges.scala:483:15, :500:17] wire [1:0] putFull_a_mask_sizeOH_shiftAmount = _putFull_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _putFull_a_mask_sizeOH_T_1 = 4'h1 << putFull_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _putFull_a_mask_sizeOH_T_2 = _putFull_a_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] putFull_a_mask_sizeOH = {_putFull_a_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire putFull_a_mask_sub_sub_sub_sub_0_1 = write_packet_lg_size[2]; // @[Misc.scala:206:21] wire putFull_a_mask_sub_sub_sub_1_1 = putFull_a_mask_sub_sub_sub_sub_0_1; // @[Misc.scala:206:21, :215:29] wire putFull_a_mask_sub_sub_sub_size = putFull_a_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_sub_sub_acc_T = putFull_a_mask_sub_sub_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_sub_sub_0_1 = putFull_a_mask_sub_sub_sub_sub_0_1 | _putFull_a_mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire putFull_a_mask_sub_sub_1_1 = putFull_a_mask_sub_sub_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_2_1 = putFull_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_3_1 = putFull_a_mask_sub_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_sub_size = putFull_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_sub_acc_T = putFull_a_mask_sub_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_sub_0_1 = putFull_a_mask_sub_sub_sub_0_1 | _putFull_a_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_sub_1_1 = putFull_a_mask_sub_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_2_1 = putFull_a_mask_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_3_1 = putFull_a_mask_sub_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_4_1 = putFull_a_mask_sub_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_5_1 = putFull_a_mask_sub_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_6_1 = putFull_a_mask_sub_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_7_1 = putFull_a_mask_sub_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_sub_size = putFull_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_sub_acc_T = putFull_a_mask_sub_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_sub_0_1 = putFull_a_mask_sub_sub_0_1 | _putFull_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_acc_1 = putFull_a_mask_sub_0_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_2 = putFull_a_mask_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_3 = putFull_a_mask_sub_1_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_4 = putFull_a_mask_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_5 = putFull_a_mask_sub_2_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_6 = putFull_a_mask_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_7 = putFull_a_mask_sub_3_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_8 = putFull_a_mask_sub_4_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_9 = putFull_a_mask_sub_4_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_10 = putFull_a_mask_sub_5_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_11 = putFull_a_mask_sub_5_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_12 = putFull_a_mask_sub_6_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_13 = putFull_a_mask_sub_6_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_14 = putFull_a_mask_sub_7_1; // @[Misc.scala:215:29] wire putFull_a_mask_acc_15 = putFull_a_mask_sub_7_1; // @[Misc.scala:215:29] wire putFull_a_mask_size = putFull_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire _putFull_a_mask_acc_T = putFull_a_mask_size; // @[Misc.scala:209:26, :215:38] wire putFull_a_mask_acc = putFull_a_mask_sub_0_1 | _putFull_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire [1:0] putFull_a_mask_lo_lo_lo = {putFull_a_mask_acc_1, putFull_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_lo_lo_hi = {putFull_a_mask_acc_3, putFull_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_lo_lo = {putFull_a_mask_lo_lo_hi, putFull_a_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_lo_hi_lo = {putFull_a_mask_acc_5, putFull_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_lo_hi_hi = {putFull_a_mask_acc_7, putFull_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_lo_hi = {putFull_a_mask_lo_hi_hi, putFull_a_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] putFull_a_mask_lo = {putFull_a_mask_lo_hi, putFull_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_hi_lo_lo = {putFull_a_mask_acc_9, putFull_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_hi_lo_hi = {putFull_a_mask_acc_11, putFull_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_hi_lo = {putFull_a_mask_hi_lo_hi, putFull_a_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_hi_hi_lo = {putFull_a_mask_acc_13, putFull_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_hi_hi_hi = {putFull_a_mask_acc_15, putFull_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_hi_hi = {putFull_a_mask_hi_hi_hi, putFull_a_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] putFull_a_mask_hi = {putFull_a_mask_hi_hi, putFull_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _putFull_a_mask_T = {putFull_a_mask_hi, putFull_a_mask_lo}; // @[Misc.scala:222:10] assign putFull_mask = _putFull_a_mask_T; // @[Misc.scala:222:10] assign putFull_data = _putFull_T_3[127:0]; // @[Edges.scala:480:17, :489:15] reg [5:0] putPartial_buf; // @[Util.scala:90:24] wire [5:0] _putPartial_T_1 = _putPartial_T ? xactId : putPartial_buf; // @[OneHot.scala:32:10] wire [5:0] putPartial_source = _putPartial_T_1; // @[Edges.scala:500:17] wire [511:0] _putPartial_T_3 = data >> _putPartial_T_2; // @[DMA.scala:387:19, :496:{21,35}] wire [7:0] _putPartial_T_4 = {1'h0, write_shift, 3'h0}; // @[Mux.scala:50:70] wire [766:0] _putPartial_T_5 = {255'h0, _putPartial_T_3} << _putPartial_T_4; // @[DMA.scala:496:{21,43,59}] wire [1:0] putPartial_lo_lo_lo = {_GEN_13[_write_mask_T], _GEN_12[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_lo_lo_hi = {_GEN_15[_write_mask_T], _GEN_14[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_lo_lo = {putPartial_lo_lo_hi, putPartial_lo_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_lo_hi_lo = {_GEN_17[_write_mask_T], _GEN_16[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_lo_hi_hi = {_GEN_19[_write_mask_T], _GEN_18[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_lo_hi = {putPartial_lo_hi_hi, putPartial_lo_hi_lo}; // @[DMA.scala:497:25] wire [7:0] putPartial_lo = {putPartial_lo_hi, putPartial_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_hi_lo_lo = {_GEN_21[_write_mask_T], _GEN_20[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_hi_lo_hi = {_GEN_23[_write_mask_T], _GEN_22[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_hi_lo = {putPartial_hi_lo_hi, putPartial_hi_lo_lo}; // @[DMA.scala:497:25] wire [1:0] putPartial_hi_hi_lo = {_GEN_25[_write_mask_T], _GEN_24[_write_mask_T]}; // @[Mux.scala:50:70] wire [1:0] putPartial_hi_hi_hi = {_GEN_27[_write_mask_T], _GEN_26[_write_mask_T]}; // @[Mux.scala:50:70] wire [3:0] putPartial_hi_hi = {putPartial_hi_hi_hi, putPartial_hi_hi_lo}; // @[DMA.scala:497:25] wire [7:0] putPartial_hi = {putPartial_hi_hi, putPartial_hi_lo}; // @[DMA.scala:497:25] wire [15:0] _putPartial_T_6 = {putPartial_hi, putPartial_lo}; // @[DMA.scala:497:25] wire [15:0] putPartial_mask = _putPartial_T_6; // @[Edges.scala:500:17] wire _putPartial_legal_T_12 = _putPartial_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _putPartial_legal_T_13 = _putPartial_legal_T_12; // @[Parameters.scala:684:29] wire _putPartial_legal_T_61 = _putPartial_legal_T_13; // @[Parameters.scala:684:{29,54}] wire _putPartial_legal_T_70 = _putPartial_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putPartial_legal = _putPartial_legal_T_70; // @[Parameters.scala:686:26] wire [127:0] putPartial_data; // @[Edges.scala:500:17] assign putPartial_data = _putPartial_T_5[127:0]; // @[Edges.scala:500:17, :509:15] wire _untranslated_a_valid_T_5; // @[DMA.scala:508:90] wire [2:0] _untranslated_a_bits_tl_a_T_opcode; // @[DMA.scala:509:36] wire [3:0] _untranslated_a_bits_tl_a_T_size; // @[DMA.scala:509:36] wire [5:0] _untranslated_a_bits_tl_a_T_source; // @[DMA.scala:509:36] wire [15:0] _untranslated_a_bits_tl_a_T_mask; // @[DMA.scala:509:36] wire [127:0] _untranslated_a_bits_tl_a_T_data; // @[DMA.scala:509:36] wire [2:0] untranslated_a_bits_tl_a_opcode; // @[DMA.scala:506:30] wire [3:0] untranslated_a_bits_tl_a_size; // @[DMA.scala:506:30] wire [5:0] untranslated_a_bits_tl_a_source; // @[DMA.scala:506:30] wire [15:0] untranslated_a_bits_tl_a_mask; // @[DMA.scala:506:30] wire [127:0] untranslated_a_bits_tl_a_data; // @[DMA.scala:506:30] wire untranslated_a_ready; // @[DMA.scala:506:30] wire untranslated_a_valid; // @[DMA.scala:506:30] wire _xactBusy_fire_T = untranslated_a_ready & untranslated_a_valid; // @[Decoupled.scala:51:35] assign _xactBusy_fire_T_2 = _xactBusy_fire_T & _xactBusy_fire_T_1; // @[Decoupled.scala:51:35] assign xactBusy_fire = _xactBusy_fire_T_2; // @[DMA.scala:396:33, :507:42] wire _untranslated_a_valid_T_1 = state == 2'h2; // @[DMA.scala:380:24, :508:69] wire _untranslated_a_valid_T_2 = _untranslated_a_valid_T | _untranslated_a_valid_T_1; // @[DMA.scala:508:{36,60,69}] wire _untranslated_a_valid_T_3 = &xactBusy; // @[DMA.scala:392:27, :508:103] wire _untranslated_a_valid_T_4 = ~_untranslated_a_valid_T_3; // @[DMA.scala:508:{93,103}] assign _untranslated_a_valid_T_5 = _untranslated_a_valid_T_2 & _untranslated_a_valid_T_4; // @[DMA.scala:508:{60,90,93}] assign untranslated_a_valid = _untranslated_a_valid_T_5; // @[DMA.scala:506:30, :508:90] assign _untranslated_a_bits_tl_a_T_opcode = {2'h0, ~write_packet_is_full}; // @[Util.scala:91:8] assign _untranslated_a_bits_tl_a_T_size = write_packet_is_full ? putFull_size : putPartial_size; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_source = write_packet_is_full ? putFull_source : putPartial_source; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_mask = write_packet_is_full ? putFull_mask : putPartial_mask; // @[Edges.scala:480:17, :500:17] assign _untranslated_a_bits_tl_a_T_data = write_packet_is_full ? putFull_data : putPartial_data; // @[Edges.scala:480:17, :500:17] assign untranslated_a_bits_tl_a_opcode = _untranslated_a_bits_tl_a_T_opcode; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_size = _untranslated_a_bits_tl_a_T_size; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_source = _untranslated_a_bits_tl_a_T_source; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_mask = _untranslated_a_bits_tl_a_T_mask; // @[DMA.scala:506:30, :509:36] assign untranslated_a_bits_tl_a_data = _untranslated_a_bits_tl_a_T_data; // @[DMA.scala:506:30, :509:36] wire _retry_a_valid_T; // @[DMA.scala:543:47] wire [2:0] retry_a_bits_tl_a_opcode; // @[DMA.scala:514:23] wire [2:0] retry_a_bits_tl_a_param; // @[DMA.scala:514:23] wire [3:0] retry_a_bits_tl_a_size; // @[DMA.scala:514:23] wire [5:0] retry_a_bits_tl_a_source; // @[DMA.scala:514:23] wire [31:0] retry_a_bits_tl_a_address; // @[DMA.scala:514:23] wire [15:0] retry_a_bits_tl_a_mask; // @[DMA.scala:514:23] wire [127:0] retry_a_bits_tl_a_data; // @[DMA.scala:514:23] wire retry_a_bits_tl_a_corrupt; // @[DMA.scala:514:23] wire retry_a_bits_status_debug; // @[DMA.scala:514:23] wire retry_a_bits_status_cease; // @[DMA.scala:514:23] wire retry_a_bits_status_wfi; // @[DMA.scala:514:23] wire [31:0] retry_a_bits_status_isa; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_dprv; // @[DMA.scala:514:23] wire retry_a_bits_status_dv; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_prv; // @[DMA.scala:514:23] wire retry_a_bits_status_v; // @[DMA.scala:514:23] wire retry_a_bits_status_sd; // @[DMA.scala:514:23] wire [22:0] retry_a_bits_status_zero2; // @[DMA.scala:514:23] wire retry_a_bits_status_mpv; // @[DMA.scala:514:23] wire retry_a_bits_status_gva; // @[DMA.scala:514:23] wire retry_a_bits_status_mbe; // @[DMA.scala:514:23] wire retry_a_bits_status_sbe; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_sxl; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_uxl; // @[DMA.scala:514:23] wire retry_a_bits_status_sd_rv32; // @[DMA.scala:514:23] wire [7:0] retry_a_bits_status_zero1; // @[DMA.scala:514:23] wire retry_a_bits_status_tsr; // @[DMA.scala:514:23] wire retry_a_bits_status_tw; // @[DMA.scala:514:23] wire retry_a_bits_status_tvm; // @[DMA.scala:514:23] wire retry_a_bits_status_mxr; // @[DMA.scala:514:23] wire retry_a_bits_status_sum; // @[DMA.scala:514:23] wire retry_a_bits_status_mprv; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_xs; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_fs; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_mpp; // @[DMA.scala:514:23] wire [1:0] retry_a_bits_status_vs; // @[DMA.scala:514:23] wire retry_a_bits_status_spp; // @[DMA.scala:514:23] wire retry_a_bits_status_mpie; // @[DMA.scala:514:23] wire retry_a_bits_status_ube; // @[DMA.scala:514:23] wire retry_a_bits_status_spie; // @[DMA.scala:514:23] wire retry_a_bits_status_upie; // @[DMA.scala:514:23] wire retry_a_bits_status_mie; // @[DMA.scala:514:23] wire retry_a_bits_status_hie; // @[DMA.scala:514:23] wire retry_a_bits_status_sie; // @[DMA.scala:514:23] wire retry_a_bits_status_uie; // @[DMA.scala:514:23] wire [38:0] retry_a_bits_vaddr; // @[DMA.scala:514:23] wire retry_a_ready; // @[DMA.scala:514:23] wire retry_a_valid; // @[DMA.scala:514:23] assign _io_tlb_req_valid_T = _translate_q_io_enq_ready & _tlb_q_io_deq_valid; // @[Decoupled.scala:51:35] assign io_tlb_req_valid_0 = _io_tlb_req_valid_T; // @[Decoupled.scala:51:35] assign io_tlb_req_bits_tlb_req_vaddr_0 = {1'h0, _tlb_q_io_deq_bits_vaddr}; // @[DMA.scala:360:9, :523:23, :528:35] wire _translate_q_io_deq_ready_T = nodeOut_a_ready | io_tlb_resp_miss_0; // @[DMA.scala:360:9, :541:44] assign _retry_a_valid_T = _translate_q_io_deq_valid & io_tlb_resp_miss_0; // @[DMA.scala:360:9, :534:29, :543:47] assign retry_a_valid = _retry_a_valid_T; // @[DMA.scala:514:23, :543:47] wire _nodeOut_a_valid_T = ~io_tlb_resp_miss_0; // @[DMA.scala:360:9, :547:47] assign _nodeOut_a_valid_T_1 = _translate_q_io_deq_valid & _nodeOut_a_valid_T; // @[DMA.scala:534:29, :547:{44,47}] assign nodeOut_a_valid = _nodeOut_a_valid_T_1; // @[DMA.scala:547:44] reg nodeOut_a_bits_address_REG; // @[DMA.scala:549:66] reg [31:0] nodeOut_a_bits_address_buf; // @[Util.scala:90:24] assign _nodeOut_a_bits_address_T = nodeOut_a_bits_address_REG ? io_tlb_resp_paddr_0 : nodeOut_a_bits_address_buf; // @[Util.scala:90:24, :91:8] assign nodeOut_a_bits_address = _nodeOut_a_bits_address_T; // @[Util.scala:91:8] assign _nodeOut_d_ready_T = |xactBusy; // @[DMA.scala:392:27, :403:25, :551:28] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[DMA.scala:551:28] wire [7:0] _beatsLeft_T = _GEN_11 - 8'h1; // @[DMA.scala:477:73, :555:34] wire [6:0] _beatsLeft_T_1 = _beatsLeft_T[6:0]; // @[DMA.scala:555:34] wire [40:0] _next_vaddr_T = {1'h0, req_vaddr} + {34'h0, write_packet_bytes_written}; // @[Util.scala:91:8] wire [39:0] next_vaddr = _next_vaddr_T[39:0]; // @[DMA.scala:557:36] wire [3:0][4:0] _GEN_31 = {{write_packet_bytes_written_per_beat_3}, {write_packet_bytes_written_per_beat_2}, {write_packet_bytes_written_per_beat_1}, {write_packet_bytes_written_per_beat_0}}; // @[Util.scala:91:8] wire [7:0] _GEN_32 = _GEN + {3'h0, _GEN_31[_bytes_written_this_beat_T]}; // @[DMA.scala:390:29, :560:32] wire [7:0] _bytesSent_T; // @[DMA.scala:560:32] assign _bytesSent_T = _GEN_32; // @[DMA.scala:560:32] wire [7:0] _bytesSent_T_2; // @[DMA.scala:573:32] assign _bytesSent_T_2 = _GEN_32; // @[DMA.scala:560:32, :573:32] wire [6:0] _bytesSent_T_1 = _bytesSent_T[6:0]; // @[DMA.scala:560:32] wire _T_8 = write_beats == 7'h1; // @[DMA.scala:418:44, :562:27] wire [6:0] _GEN_33 = {2'h0, _GEN_31[_bytes_written_this_beat_T]}; // @[DMA.scala:560:32, :563:41] wire _T_9 = _GEN_33 >= bytesLeft; // @[DMA.scala:390:29, :563:41] wire [6:0] _beatsLeft_T_2 = {1'h0, beatsLeft} - 7'h1; // @[DMA.scala:476:24, :572:32] wire [5:0] _beatsLeft_T_3 = _beatsLeft_T_2[5:0]; // @[DMA.scala:572:32] wire [6:0] _bytesSent_T_3 = _bytesSent_T_2[6:0]; // @[DMA.scala:573:32] wire _T_15 = beatsLeft == 6'h1; // @[DMA.scala:476:24, :577:25] wire _T_16 = _GEN_33 >= bytesLeft; // @[DMA.scala:390:29, :563:41, :578:41] assign state_machine_ready_for_req = _xactBusy_fire_T ? (_T_7 ? _T_8 & _T_9 | _state_machine_ready_for_req_T : _untranslated_a_valid_T_1 & _T_15 & _T_16 | _state_machine_ready_for_req_T) : _state_machine_ready_for_req_T; // @[Decoupled.scala:51:35] wire _T_17 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _pooled_v1_T_1; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_3; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_5; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_7; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_9; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_11; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_13; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_15; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_17; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_19; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_21; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_23; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_25; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_27; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_29; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_31; // @[DMA.scala:593:43] wire [7:0] pooled_v1_0; // @[DMA.scala:593:43] wire [7:0] pooled_v1_1; // @[DMA.scala:593:43] wire [7:0] pooled_v1_2; // @[DMA.scala:593:43] wire [7:0] pooled_v1_3; // @[DMA.scala:593:43] wire [7:0] pooled_v1_4; // @[DMA.scala:593:43] wire [7:0] pooled_v1_5; // @[DMA.scala:593:43] wire [7:0] pooled_v1_6; // @[DMA.scala:593:43] wire [7:0] pooled_v1_7; // @[DMA.scala:593:43] wire [7:0] pooled_v1_8; // @[DMA.scala:593:43] wire [7:0] pooled_v1_9; // @[DMA.scala:593:43] wire [7:0] pooled_v1_10; // @[DMA.scala:593:43] wire [7:0] pooled_v1_11; // @[DMA.scala:593:43] wire [7:0] pooled_v1_12; // @[DMA.scala:593:43] wire [7:0] pooled_v1_13; // @[DMA.scala:593:43] wire [7:0] pooled_v1_14; // @[DMA.scala:593:43] wire [7:0] pooled_v1_15; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T = _pooled_v1_WIRE[7:0]; // @[DMA.scala:593:43] assign _pooled_v1_T_1 = _pooled_v1_T; // @[DMA.scala:593:43] assign pooled_v1_0 = _pooled_v1_T_1; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_2 = _pooled_v1_WIRE[15:8]; // @[DMA.scala:593:43] assign _pooled_v1_T_3 = _pooled_v1_T_2; // @[DMA.scala:593:43] assign pooled_v1_1 = _pooled_v1_T_3; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_4 = _pooled_v1_WIRE[23:16]; // @[DMA.scala:593:43] assign _pooled_v1_T_5 = _pooled_v1_T_4; // @[DMA.scala:593:43] assign pooled_v1_2 = _pooled_v1_T_5; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_6 = _pooled_v1_WIRE[31:24]; // @[DMA.scala:593:43] assign _pooled_v1_T_7 = _pooled_v1_T_6; // @[DMA.scala:593:43] assign pooled_v1_3 = _pooled_v1_T_7; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_8 = _pooled_v1_WIRE[39:32]; // @[DMA.scala:593:43] assign _pooled_v1_T_9 = _pooled_v1_T_8; // @[DMA.scala:593:43] assign pooled_v1_4 = _pooled_v1_T_9; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_10 = _pooled_v1_WIRE[47:40]; // @[DMA.scala:593:43] assign _pooled_v1_T_11 = _pooled_v1_T_10; // @[DMA.scala:593:43] assign pooled_v1_5 = _pooled_v1_T_11; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_12 = _pooled_v1_WIRE[55:48]; // @[DMA.scala:593:43] assign _pooled_v1_T_13 = _pooled_v1_T_12; // @[DMA.scala:593:43] assign pooled_v1_6 = _pooled_v1_T_13; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_14 = _pooled_v1_WIRE[63:56]; // @[DMA.scala:593:43] assign _pooled_v1_T_15 = _pooled_v1_T_14; // @[DMA.scala:593:43] assign pooled_v1_7 = _pooled_v1_T_15; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_16 = _pooled_v1_WIRE[71:64]; // @[DMA.scala:593:43] assign _pooled_v1_T_17 = _pooled_v1_T_16; // @[DMA.scala:593:43] assign pooled_v1_8 = _pooled_v1_T_17; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_18 = _pooled_v1_WIRE[79:72]; // @[DMA.scala:593:43] assign _pooled_v1_T_19 = _pooled_v1_T_18; // @[DMA.scala:593:43] assign pooled_v1_9 = _pooled_v1_T_19; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_20 = _pooled_v1_WIRE[87:80]; // @[DMA.scala:593:43] assign _pooled_v1_T_21 = _pooled_v1_T_20; // @[DMA.scala:593:43] assign pooled_v1_10 = _pooled_v1_T_21; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_22 = _pooled_v1_WIRE[95:88]; // @[DMA.scala:593:43] assign _pooled_v1_T_23 = _pooled_v1_T_22; // @[DMA.scala:593:43] assign pooled_v1_11 = _pooled_v1_T_23; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_24 = _pooled_v1_WIRE[103:96]; // @[DMA.scala:593:43] assign _pooled_v1_T_25 = _pooled_v1_T_24; // @[DMA.scala:593:43] assign pooled_v1_12 = _pooled_v1_T_25; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_26 = _pooled_v1_WIRE[111:104]; // @[DMA.scala:593:43] assign _pooled_v1_T_27 = _pooled_v1_T_26; // @[DMA.scala:593:43] assign pooled_v1_13 = _pooled_v1_T_27; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_28 = _pooled_v1_WIRE[119:112]; // @[DMA.scala:593:43] assign _pooled_v1_T_29 = _pooled_v1_T_28; // @[DMA.scala:593:43] assign pooled_v1_14 = _pooled_v1_T_29; // @[DMA.scala:593:43] wire [7:0] _pooled_v1_T_30 = _pooled_v1_WIRE[127:120]; // @[DMA.scala:593:43] assign _pooled_v1_T_31 = _pooled_v1_T_30; // @[DMA.scala:593:43] assign pooled_v1_15 = _pooled_v1_T_31; // @[DMA.scala:593:43] wire [7:0] _pooled_v2_T_1; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_3; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_5; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_7; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_9; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_11; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_13; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_15; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_17; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_19; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_21; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_23; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_25; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_27; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_29; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_31; // @[DMA.scala:594:44] wire [7:0] pooled_v2_0; // @[DMA.scala:594:44] wire [7:0] pooled_v2_1; // @[DMA.scala:594:44] wire [7:0] pooled_v2_2; // @[DMA.scala:594:44] wire [7:0] pooled_v2_3; // @[DMA.scala:594:44] wire [7:0] pooled_v2_4; // @[DMA.scala:594:44] wire [7:0] pooled_v2_5; // @[DMA.scala:594:44] wire [7:0] pooled_v2_6; // @[DMA.scala:594:44] wire [7:0] pooled_v2_7; // @[DMA.scala:594:44] wire [7:0] pooled_v2_8; // @[DMA.scala:594:44] wire [7:0] pooled_v2_9; // @[DMA.scala:594:44] wire [7:0] pooled_v2_10; // @[DMA.scala:594:44] wire [7:0] pooled_v2_11; // @[DMA.scala:594:44] wire [7:0] pooled_v2_12; // @[DMA.scala:594:44] wire [7:0] pooled_v2_13; // @[DMA.scala:594:44] wire [7:0] pooled_v2_14; // @[DMA.scala:594:44] wire [7:0] pooled_v2_15; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T = _pooled_v2_WIRE[7:0]; // @[DMA.scala:594:44] assign _pooled_v2_T_1 = _pooled_v2_T; // @[DMA.scala:594:44] assign pooled_v2_0 = _pooled_v2_T_1; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_2 = _pooled_v2_WIRE[15:8]; // @[DMA.scala:594:44] assign _pooled_v2_T_3 = _pooled_v2_T_2; // @[DMA.scala:594:44] assign pooled_v2_1 = _pooled_v2_T_3; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_4 = _pooled_v2_WIRE[23:16]; // @[DMA.scala:594:44] assign _pooled_v2_T_5 = _pooled_v2_T_4; // @[DMA.scala:594:44] assign pooled_v2_2 = _pooled_v2_T_5; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_6 = _pooled_v2_WIRE[31:24]; // @[DMA.scala:594:44] assign _pooled_v2_T_7 = _pooled_v2_T_6; // @[DMA.scala:594:44] assign pooled_v2_3 = _pooled_v2_T_7; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_8 = _pooled_v2_WIRE[39:32]; // @[DMA.scala:594:44] assign _pooled_v2_T_9 = _pooled_v2_T_8; // @[DMA.scala:594:44] assign pooled_v2_4 = _pooled_v2_T_9; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_10 = _pooled_v2_WIRE[47:40]; // @[DMA.scala:594:44] assign _pooled_v2_T_11 = _pooled_v2_T_10; // @[DMA.scala:594:44] assign pooled_v2_5 = _pooled_v2_T_11; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_12 = _pooled_v2_WIRE[55:48]; // @[DMA.scala:594:44] assign _pooled_v2_T_13 = _pooled_v2_T_12; // @[DMA.scala:594:44] assign pooled_v2_6 = _pooled_v2_T_13; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_14 = _pooled_v2_WIRE[63:56]; // @[DMA.scala:594:44] assign _pooled_v2_T_15 = _pooled_v2_T_14; // @[DMA.scala:594:44] assign pooled_v2_7 = _pooled_v2_T_15; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_16 = _pooled_v2_WIRE[71:64]; // @[DMA.scala:594:44] assign _pooled_v2_T_17 = _pooled_v2_T_16; // @[DMA.scala:594:44] assign pooled_v2_8 = _pooled_v2_T_17; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_18 = _pooled_v2_WIRE[79:72]; // @[DMA.scala:594:44] assign _pooled_v2_T_19 = _pooled_v2_T_18; // @[DMA.scala:594:44] assign pooled_v2_9 = _pooled_v2_T_19; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_20 = _pooled_v2_WIRE[87:80]; // @[DMA.scala:594:44] assign _pooled_v2_T_21 = _pooled_v2_T_20; // @[DMA.scala:594:44] assign pooled_v2_10 = _pooled_v2_T_21; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_22 = _pooled_v2_WIRE[95:88]; // @[DMA.scala:594:44] assign _pooled_v2_T_23 = _pooled_v2_T_22; // @[DMA.scala:594:44] assign pooled_v2_11 = _pooled_v2_T_23; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_24 = _pooled_v2_WIRE[103:96]; // @[DMA.scala:594:44] assign _pooled_v2_T_25 = _pooled_v2_T_24; // @[DMA.scala:594:44] assign pooled_v2_12 = _pooled_v2_T_25; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_26 = _pooled_v2_WIRE[111:104]; // @[DMA.scala:594:44] assign _pooled_v2_T_27 = _pooled_v2_T_26; // @[DMA.scala:594:44] assign pooled_v2_13 = _pooled_v2_T_27; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_28 = _pooled_v2_WIRE[119:112]; // @[DMA.scala:594:44] assign _pooled_v2_T_29 = _pooled_v2_T_28; // @[DMA.scala:594:44] assign pooled_v2_14 = _pooled_v2_T_29; // @[DMA.scala:594:44] wire [7:0] _pooled_v2_T_30 = _pooled_v2_WIRE[127:120]; // @[DMA.scala:594:44] assign _pooled_v2_T_31 = _pooled_v2_T_30; // @[DMA.scala:594:44] assign pooled_v2_15 = _pooled_v2_T_31; // @[DMA.scala:594:44] wire _pooled_T = $signed(pooled_v1_0) > $signed(pooled_v2_0); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_1 = _pooled_T ? pooled_v1_0 : pooled_v2_0; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_0 = _pooled_T_1; // @[Util.scala:105:8] wire _pooled_T_2 = $signed(pooled_v1_1) > $signed(pooled_v2_1); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_3 = _pooled_T_2 ? pooled_v1_1 : pooled_v2_1; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_1 = _pooled_T_3; // @[Util.scala:105:8] wire _pooled_T_4 = $signed(pooled_v1_2) > $signed(pooled_v2_2); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_5 = _pooled_T_4 ? pooled_v1_2 : pooled_v2_2; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_2 = _pooled_T_5; // @[Util.scala:105:8] wire _pooled_T_6 = $signed(pooled_v1_3) > $signed(pooled_v2_3); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_7 = _pooled_T_6 ? pooled_v1_3 : pooled_v2_3; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_3 = _pooled_T_7; // @[Util.scala:105:8] wire _pooled_T_8 = $signed(pooled_v1_4) > $signed(pooled_v2_4); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_9 = _pooled_T_8 ? pooled_v1_4 : pooled_v2_4; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_4 = _pooled_T_9; // @[Util.scala:105:8] wire _pooled_T_10 = $signed(pooled_v1_5) > $signed(pooled_v2_5); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_11 = _pooled_T_10 ? pooled_v1_5 : pooled_v2_5; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_5 = _pooled_T_11; // @[Util.scala:105:8] wire _pooled_T_12 = $signed(pooled_v1_6) > $signed(pooled_v2_6); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_13 = _pooled_T_12 ? pooled_v1_6 : pooled_v2_6; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_6 = _pooled_T_13; // @[Util.scala:105:8] wire _pooled_T_14 = $signed(pooled_v1_7) > $signed(pooled_v2_7); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_15 = _pooled_T_14 ? pooled_v1_7 : pooled_v2_7; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_7 = _pooled_T_15; // @[Util.scala:105:8] wire _pooled_T_16 = $signed(pooled_v1_8) > $signed(pooled_v2_8); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_17 = _pooled_T_16 ? pooled_v1_8 : pooled_v2_8; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_8 = _pooled_T_17; // @[Util.scala:105:8] wire _pooled_T_18 = $signed(pooled_v1_9) > $signed(pooled_v2_9); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_19 = _pooled_T_18 ? pooled_v1_9 : pooled_v2_9; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_9 = _pooled_T_19; // @[Util.scala:105:8] wire _pooled_T_20 = $signed(pooled_v1_10) > $signed(pooled_v2_10); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_21 = _pooled_T_20 ? pooled_v1_10 : pooled_v2_10; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_10 = _pooled_T_21; // @[Util.scala:105:8] wire _pooled_T_22 = $signed(pooled_v1_11) > $signed(pooled_v2_11); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_23 = _pooled_T_22 ? pooled_v1_11 : pooled_v2_11; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_11 = _pooled_T_23; // @[Util.scala:105:8] wire _pooled_T_24 = $signed(pooled_v1_12) > $signed(pooled_v2_12); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_25 = _pooled_T_24 ? pooled_v1_12 : pooled_v2_12; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_12 = _pooled_T_25; // @[Util.scala:105:8] wire _pooled_T_26 = $signed(pooled_v1_13) > $signed(pooled_v2_13); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_27 = _pooled_T_26 ? pooled_v1_13 : pooled_v2_13; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_13 = _pooled_T_27; // @[Util.scala:105:8] wire _pooled_T_28 = $signed(pooled_v1_14) > $signed(pooled_v2_14); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_29 = _pooled_T_28 ? pooled_v1_14 : pooled_v2_14; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_14 = _pooled_T_29; // @[Util.scala:105:8] wire _pooled_T_30 = $signed(pooled_v1_15) > $signed(pooled_v2_15); // @[DMA.scala:593:43, :594:44] wire [7:0] _pooled_T_31 = _pooled_T_30 ? pooled_v1_15 : pooled_v2_15; // @[Util.scala:105:8] wire [7:0] _pooled_WIRE_15 = _pooled_T_31; // @[Util.scala:105:8] wire [7:0] _pooled_T_32 = _pooled_WIRE_0; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_33 = _pooled_WIRE_1; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_34 = _pooled_WIRE_2; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_35 = _pooled_WIRE_3; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_36 = _pooled_WIRE_4; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_37 = _pooled_WIRE_5; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_38 = _pooled_WIRE_6; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_39 = _pooled_WIRE_7; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_40 = _pooled_WIRE_8; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_41 = _pooled_WIRE_9; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_42 = _pooled_WIRE_10; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_43 = _pooled_WIRE_11; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_44 = _pooled_WIRE_12; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_45 = _pooled_WIRE_13; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_46 = _pooled_WIRE_14; // @[DMA.scala:596:{16,97}] wire [7:0] _pooled_T_47 = _pooled_WIRE_15; // @[DMA.scala:596:{16,97}] wire [15:0] pooled_lo_lo_lo = {_pooled_T_33, _pooled_T_32}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_lo_hi = {_pooled_T_35, _pooled_T_34}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_lo = {pooled_lo_lo_hi, pooled_lo_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_lo = {_pooled_T_37, _pooled_T_36}; // @[DMA.scala:596:97] wire [15:0] pooled_lo_hi_hi = {_pooled_T_39, _pooled_T_38}; // @[DMA.scala:596:97] wire [31:0] pooled_lo_hi = {pooled_lo_hi_hi, pooled_lo_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_lo = {pooled_lo_hi, pooled_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_lo = {_pooled_T_41, _pooled_T_40}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_lo_hi = {_pooled_T_43, _pooled_T_42}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_lo = {pooled_hi_lo_hi, pooled_hi_lo_lo}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_lo = {_pooled_T_45, _pooled_T_44}; // @[DMA.scala:596:97] wire [15:0] pooled_hi_hi_hi = {_pooled_T_47, _pooled_T_46}; // @[DMA.scala:596:97] wire [31:0] pooled_hi_hi = {pooled_hi_hi_hi, pooled_hi_hi_lo}; // @[DMA.scala:596:97] wire [63:0] pooled_hi = {pooled_hi_hi, pooled_hi_lo}; // @[DMA.scala:596:97] wire [127:0] pooled = {pooled_hi, pooled_lo}; // @[DMA.scala:596:97] wire [12:0] _req_len_T = {1'h0, io_req_bits_block_0, 4'h0}; // @[DMA.scala:360:9, :600:36] wire [13:0] _req_len_T_1 = {1'h0, _req_len_T} + {7'h0, io_req_bits_len_0}; // @[DMA.scala:360:9, :600:{36,58}] wire [12:0] _req_len_T_2 = _req_len_T_1[12:0]; // @[DMA.scala:600:58] wire [127:0] _data_single_block_T = io_req_bits_pool_en_0 ? pooled : io_req_bits_data_0; // @[DMA.scala:360:9, :596:97, :602:31] wire [1:0] _state_T = {1'h0, io_req_bits_store_en_0}; // @[DMA.scala:360:9, :607:19]
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File LatencyInjectionQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ import freechips.rocketchip.util.DecoupledHelper class LatencyInjectionQueue[T <: Data](data: T, depth: Int) extends Module { val io = IO(new Bundle { val latency_cycles = Input(UInt(64.W)) val enq = Flipped(Decoupled(data)) val deq = Decoupled(data) }) val cur_cycle = RegInit(0.U(64.W)) cur_cycle := cur_cycle + 1.U val queue = Module(new Queue(data, depth)) val release_ready_cycle_q = Module(new Queue(UInt(64.W), depth)) release_ready_cycle_q.io.enq.bits := cur_cycle + io.latency_cycles queue.io.enq.bits := io.enq.bits io.deq.bits := queue.io.deq.bits val enq_fire = DecoupledHelper( queue.io.enq.ready, release_ready_cycle_q.io.enq.ready, io.enq.valid ) queue.io.enq.valid := enq_fire.fire(queue.io.enq.ready) release_ready_cycle_q.io.enq.valid := enq_fire.fire(release_ready_cycle_q.io.enq.ready) io.enq.ready := enq_fire.fire(io.enq.valid) val deq_fire = DecoupledHelper( queue.io.deq.valid, release_ready_cycle_q.io.deq.valid, release_ready_cycle_q.io.deq.bits <= cur_cycle, io.deq.ready ) queue.io.deq.ready := deq_fire.fire(queue.io.deq.valid) release_ready_cycle_q.io.deq.ready := deq_fire.fire(release_ready_cycle_q.io.deq.valid) io.deq.valid := deq_fire.fire(io.deq.ready) }
module LatencyInjectionQueue_32( // @[LatencyInjectionQueue.scala:9:7] input clock, // @[LatencyInjectionQueue.scala:9:7] input reset, // @[LatencyInjectionQueue.scala:9:7] input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14] output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14] input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14] input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14] input [31:0] io_enq_bits_address, // @[LatencyInjectionQueue.scala:10:14] input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14] output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14] output [2:0] io_deq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14] output [2:0] io_deq_bits_param, // @[LatencyInjectionQueue.scala:10:14] output [3:0] io_deq_bits_size, // @[LatencyInjectionQueue.scala:10:14] output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14] output [31:0] io_deq_bits_address, // @[LatencyInjectionQueue.scala:10:14] output [31:0] io_deq_bits_mask, // @[LatencyInjectionQueue.scala:10:14] output [255:0] io_deq_bits_data, // @[LatencyInjectionQueue.scala:10:14] output io_deq_bits_corrupt // @[LatencyInjectionQueue.scala:10:14] ); wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37] wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37] wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37] wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21] wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21] wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7] wire io_enq_bits_corrupt = 1'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire [255:0] io_enq_bits_data = 256'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire [31:0] io_enq_bits_mask = 32'hFFFFFFFF; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire [3:0] io_enq_bits_size = 4'h5; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire [2:0] io_enq_bits_param = 3'h0; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire [2:0] io_enq_bits_opcode = 3'h4; // @[LatencyInjectionQueue.scala:9:7, :10:14, :18:21] wire _io_enq_ready_T; // @[Misc.scala:26:53] wire _io_deq_valid_T_1; // @[Misc.scala:26:53] wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_opcode_0; // @[LatencyInjectionQueue.scala:9:7] wire [2:0] io_deq_bits_param_0; // @[LatencyInjectionQueue.scala:9:7] wire [3:0] io_deq_bits_size_0; // @[LatencyInjectionQueue.scala:9:7] wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_deq_bits_address_0; // @[LatencyInjectionQueue.scala:9:7] wire [31:0] io_deq_bits_mask_0; // @[LatencyInjectionQueue.scala:9:7] wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_bits_corrupt_0; // @[LatencyInjectionQueue.scala:9:7] wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26] wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:9:7, :10:14, :16:26, :17:26, :18:21] wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26] wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26] wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :10:14, :17:26, :18:21, :21:50] wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50] wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53] assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53] assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53] wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39] wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53] wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53] wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53] assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53] assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53] always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7] if (reset) // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26] else // @[LatencyInjectionQueue.scala:9:7] cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26] always @(posedge) Queue64_TLBundleA_a32d256s5k3z4u_12 queue ( // @[LatencyInjectionQueue.scala:18:21] .clock (clock), .reset (reset), .io_enq_ready (_queue_io_enq_ready), .io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7] .io_enq_bits_address (io_enq_bits_address_0), // @[LatencyInjectionQueue.scala:9:7] .io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_queue_io_deq_valid), .io_deq_bits_opcode (io_deq_bits_opcode_0), .io_deq_bits_param (io_deq_bits_param_0), .io_deq_bits_size (io_deq_bits_size_0), .io_deq_bits_source (io_deq_bits_source_0), .io_deq_bits_address (io_deq_bits_address_0), .io_deq_bits_mask (io_deq_bits_mask_0), .io_deq_bits_data (io_deq_bits_data_0), .io_deq_bits_corrupt (io_deq_bits_corrupt_0) ); // @[LatencyInjectionQueue.scala:18:21] Queue64_UInt64_24 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37] .clock (clock), .reset (reset), .io_enq_ready (_release_ready_cycle_q_io_enq_ready), .io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53] .io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50] .io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53] .io_deq_valid (_release_ready_cycle_q_io_deq_valid), .io_deq_bits (_release_ready_cycle_q_io_deq_bits) ); // @[LatencyInjectionQueue.scala:19:37] assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[LatencyInjectionQueue.scala:9:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } }
module BranchKillableQueue_10( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [33:0] io_enq_bits_addr, // @[util.scala:453:14] input [63:0] io_enq_bits_data, // @[util.scala:453:14] input io_enq_bits_is_hella, // @[util.scala:453:14] input io_enq_bits_tag_match, // @[util.scala:453:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14] input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14] input [1:0] io_enq_bits_way_en, // @[util.scala:453:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [33:0] io_deq_bits_addr, // @[util.scala:453:14] output [63:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_is_hella, // @[util.scala:453:14] output io_deq_bits_tag_match, // @[util.scala:453:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14] output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [3:0] out_uop_br_mask; // @[util.scala:506:17] wire [130:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7] wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7] wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire _valids_0_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_0_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_1_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_1_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_2_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_2_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_3_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_3_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_4_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_4_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_5_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_5_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_6_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_6_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_7_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_7_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_8_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_8_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_9_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_9_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_10_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_10_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_11_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_11_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_12_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_12_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_13_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_13_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_14_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_14_T_5 = 1'h1; // @[util.scala:481:72] wire _valids_15_T_2 = 1'h1; // @[util.scala:481:32] wire _valids_15_T_5 = 1'h1; // @[util.scala:481:72] wire _io_deq_valid_T_4 = 1'h1; // @[util.scala:509:68] wire _io_deq_valid_T_7 = 1'h1; // @[util.scala:509:111] wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_15_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [3:0] _io_deq_bits_uop_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:448:7, :453:14] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[util.scala:448:7, :453:14] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:448:7, :453:14] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:448:7, :453:14] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:448:7, :453:14] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_valid = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:448:7] wire io_brupdate_b2_taken = 1'h0; // @[util.scala:448:7] wire io_flush = 1'h0; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32] wire _valids_0_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_0_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_1_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_1_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_2_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_2_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_3_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_3_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_4_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_4_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_5_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_5_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_6_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_6_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_7_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_7_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_8_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_8_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_9_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_9_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_10_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_10_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_11_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_11_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_12_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_12_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_13_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_13_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_14_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_14_T_4 = 1'h0; // @[util.scala:481:83] wire _valids_15_T_1 = 1'h0; // @[util.scala:118:59] wire _valids_15_T_4 = 1'h0; // @[util.scala:481:83] wire _io_deq_valid_T_3 = 1'h0; // @[util.scala:118:59] wire _io_deq_valid_T_6 = 1'h0; // @[util.scala:509:122] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[util.scala:448:7, :453:14] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[util.scala:448:7, :453:14] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:448:7] wire [3:0] _valids_0_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_1_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_2_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_3_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_4_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_5_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_6_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_7_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_8_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_9_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_10_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_11_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_12_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_13_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_14_T = 4'h0; // @[util.scala:118:51] wire [3:0] _valids_15_T = 4'h0; // @[util.scala:118:51] wire _io_enq_ready_T; // @[util.scala:504:19] wire [3:0] _io_deq_valid_T_2 = 4'h0; // @[util.scala:118:51] wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:85:25, :448:7] wire _io_deq_valid_T_8; // @[util.scala:509:108] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [33:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [3:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [1:0] out_uop_br_tag; // @[util.scala:506:17] wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [5:0] out_uop_rob_idx; // @[util.scala:506:17] wire [3:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [3:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [6:0] out_uop_pdst; // @[util.scala:506:17] wire [6:0] out_uop_prs1; // @[util.scala:506:17] wire [6:0] out_uop_prs2; // @[util.scala:506:17] wire [6:0] out_uop_prs3; // @[util.scala:506:17] wire [3:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [33:0] out_addr; // @[util.scala:506:17] wire [63:0] out_data; // @[util.scala:506:17] wire out_is_hella; // @[util.scala:506:17] wire out_tag_match; // @[util.scala:506:17] wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17] wire [21:0] out_old_meta_tag; // @[util.scala:506:17] wire [1:0] out_way_en; // @[util.scala:506:17] wire [4:0] out_sdq_id; // @[util.scala:506:17] wire _io_empty_T_1; // @[util.scala:473:25] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] wire [33:0] io_deq_bits_addr_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_is_hella_0; // @[util.scala:448:7] wire io_deq_bits_tag_match_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [3:0] io_count; // @[util.scala:448:7] assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:464:20, :506:17] assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:464:20, :506:17] assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:464:20, :506:17] assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:464:20, :506:17] assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:464:20, :506:17] assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:464:20, :506:17] assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:464:20, :506:17] assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] wire _valids_0_T_3 = valids_0; // @[util.scala:465:24, :481:29] reg valids_1; // @[util.scala:465:24] wire _valids_1_T_3 = valids_1; // @[util.scala:465:24, :481:29] reg valids_2; // @[util.scala:465:24] wire _valids_2_T_3 = valids_2; // @[util.scala:465:24, :481:29] reg valids_3; // @[util.scala:465:24] wire _valids_3_T_3 = valids_3; // @[util.scala:465:24, :481:29] reg valids_4; // @[util.scala:465:24] wire _valids_4_T_3 = valids_4; // @[util.scala:465:24, :481:29] reg valids_5; // @[util.scala:465:24] wire _valids_5_T_3 = valids_5; // @[util.scala:465:24, :481:29] reg valids_6; // @[util.scala:465:24] wire _valids_6_T_3 = valids_6; // @[util.scala:465:24, :481:29] reg valids_7; // @[util.scala:465:24] wire _valids_7_T_3 = valids_7; // @[util.scala:465:24, :481:29] reg valids_8; // @[util.scala:465:24] wire _valids_8_T_3 = valids_8; // @[util.scala:465:24, :481:29] reg valids_9; // @[util.scala:465:24] wire _valids_9_T_3 = valids_9; // @[util.scala:465:24, :481:29] reg valids_10; // @[util.scala:465:24] wire _valids_10_T_3 = valids_10; // @[util.scala:465:24, :481:29] reg valids_11; // @[util.scala:465:24] wire _valids_11_T_3 = valids_11; // @[util.scala:465:24, :481:29] reg valids_12; // @[util.scala:465:24] wire _valids_12_T_3 = valids_12; // @[util.scala:465:24, :481:29] reg valids_13; // @[util.scala:465:24] wire _valids_13_T_3 = valids_13; // @[util.scala:465:24, :481:29] reg valids_14; // @[util.scala:465:24] wire _valids_14_T_3 = valids_14; // @[util.scala:465:24, :481:29] reg valids_15; // @[util.scala:465:24] wire _valids_15_T_3 = valids_15; // @[util.scala:465:24, :481:29] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [33:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [3:0] uops_0_br_mask; // @[util.scala:466:20] wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_0_br_tag; // @[util.scala:466:20] reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [5:0] uops_0_rob_idx; // @[util.scala:466:20] reg [3:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_0_pdst; // @[util.scala:466:20] reg [6:0] uops_0_prs1; // @[util.scala:466:20] reg [6:0] uops_0_prs2; // @[util.scala:466:20] reg [6:0] uops_0_prs3; // @[util.scala:466:20] reg [3:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [33:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [3:0] uops_1_br_mask; // @[util.scala:466:20] wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_1_br_tag; // @[util.scala:466:20] reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [5:0] uops_1_rob_idx; // @[util.scala:466:20] reg [3:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_1_pdst; // @[util.scala:466:20] reg [6:0] uops_1_prs1; // @[util.scala:466:20] reg [6:0] uops_1_prs2; // @[util.scala:466:20] reg [6:0] uops_1_prs3; // @[util.scala:466:20] reg [3:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [33:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [3:0] uops_2_br_mask; // @[util.scala:466:20] wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_2_br_tag; // @[util.scala:466:20] reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [5:0] uops_2_rob_idx; // @[util.scala:466:20] reg [3:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_2_pdst; // @[util.scala:466:20] reg [6:0] uops_2_prs1; // @[util.scala:466:20] reg [6:0] uops_2_prs2; // @[util.scala:466:20] reg [6:0] uops_2_prs3; // @[util.scala:466:20] reg [3:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_3_uopc; // @[util.scala:466:20] reg [31:0] uops_3_inst; // @[util.scala:466:20] reg [31:0] uops_3_debug_inst; // @[util.scala:466:20] reg uops_3_is_rvc; // @[util.scala:466:20] reg [33:0] uops_3_debug_pc; // @[util.scala:466:20] reg [2:0] uops_3_iq_type; // @[util.scala:466:20] reg [9:0] uops_3_fu_code; // @[util.scala:466:20] reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20] reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_3_ctrl_is_load; // @[util.scala:466:20] reg uops_3_ctrl_is_sta; // @[util.scala:466:20] reg uops_3_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_3_iw_state; // @[util.scala:466:20] reg uops_3_iw_p1_poisoned; // @[util.scala:466:20] reg uops_3_iw_p2_poisoned; // @[util.scala:466:20] reg uops_3_is_br; // @[util.scala:466:20] reg uops_3_is_jalr; // @[util.scala:466:20] reg uops_3_is_jal; // @[util.scala:466:20] reg uops_3_is_sfb; // @[util.scala:466:20] reg [3:0] uops_3_br_mask; // @[util.scala:466:20] wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_3_br_tag; // @[util.scala:466:20] reg [3:0] uops_3_ftq_idx; // @[util.scala:466:20] reg uops_3_edge_inst; // @[util.scala:466:20] reg [5:0] uops_3_pc_lob; // @[util.scala:466:20] reg uops_3_taken; // @[util.scala:466:20] reg [19:0] uops_3_imm_packed; // @[util.scala:466:20] reg [11:0] uops_3_csr_addr; // @[util.scala:466:20] reg [5:0] uops_3_rob_idx; // @[util.scala:466:20] reg [3:0] uops_3_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_3_stq_idx; // @[util.scala:466:20] reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_3_pdst; // @[util.scala:466:20] reg [6:0] uops_3_prs1; // @[util.scala:466:20] reg [6:0] uops_3_prs2; // @[util.scala:466:20] reg [6:0] uops_3_prs3; // @[util.scala:466:20] reg [3:0] uops_3_ppred; // @[util.scala:466:20] reg uops_3_prs1_busy; // @[util.scala:466:20] reg uops_3_prs2_busy; // @[util.scala:466:20] reg uops_3_prs3_busy; // @[util.scala:466:20] reg uops_3_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20] reg uops_3_exception; // @[util.scala:466:20] reg [63:0] uops_3_exc_cause; // @[util.scala:466:20] reg uops_3_bypassable; // @[util.scala:466:20] reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_3_mem_size; // @[util.scala:466:20] reg uops_3_mem_signed; // @[util.scala:466:20] reg uops_3_is_fence; // @[util.scala:466:20] reg uops_3_is_fencei; // @[util.scala:466:20] reg uops_3_is_amo; // @[util.scala:466:20] reg uops_3_uses_ldq; // @[util.scala:466:20] reg uops_3_uses_stq; // @[util.scala:466:20] reg uops_3_is_sys_pc2epc; // @[util.scala:466:20] reg uops_3_is_unique; // @[util.scala:466:20] reg uops_3_flush_on_commit; // @[util.scala:466:20] reg uops_3_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_3_ldst; // @[util.scala:466:20] reg [5:0] uops_3_lrs1; // @[util.scala:466:20] reg [5:0] uops_3_lrs2; // @[util.scala:466:20] reg [5:0] uops_3_lrs3; // @[util.scala:466:20] reg uops_3_ldst_val; // @[util.scala:466:20] reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20] reg uops_3_frs3_en; // @[util.scala:466:20] reg uops_3_fp_val; // @[util.scala:466:20] reg uops_3_fp_single; // @[util.scala:466:20] reg uops_3_xcpt_pf_if; // @[util.scala:466:20] reg uops_3_xcpt_ae_if; // @[util.scala:466:20] reg uops_3_xcpt_ma_if; // @[util.scala:466:20] reg uops_3_bp_debug_if; // @[util.scala:466:20] reg uops_3_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_4_uopc; // @[util.scala:466:20] reg [31:0] uops_4_inst; // @[util.scala:466:20] reg [31:0] uops_4_debug_inst; // @[util.scala:466:20] reg uops_4_is_rvc; // @[util.scala:466:20] reg [33:0] uops_4_debug_pc; // @[util.scala:466:20] reg [2:0] uops_4_iq_type; // @[util.scala:466:20] reg [9:0] uops_4_fu_code; // @[util.scala:466:20] reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20] reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_4_ctrl_is_load; // @[util.scala:466:20] reg uops_4_ctrl_is_sta; // @[util.scala:466:20] reg uops_4_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_4_iw_state; // @[util.scala:466:20] reg uops_4_iw_p1_poisoned; // @[util.scala:466:20] reg uops_4_iw_p2_poisoned; // @[util.scala:466:20] reg uops_4_is_br; // @[util.scala:466:20] reg uops_4_is_jalr; // @[util.scala:466:20] reg uops_4_is_jal; // @[util.scala:466:20] reg uops_4_is_sfb; // @[util.scala:466:20] reg [3:0] uops_4_br_mask; // @[util.scala:466:20] wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_4_br_tag; // @[util.scala:466:20] reg [3:0] uops_4_ftq_idx; // @[util.scala:466:20] reg uops_4_edge_inst; // @[util.scala:466:20] reg [5:0] uops_4_pc_lob; // @[util.scala:466:20] reg uops_4_taken; // @[util.scala:466:20] reg [19:0] uops_4_imm_packed; // @[util.scala:466:20] reg [11:0] uops_4_csr_addr; // @[util.scala:466:20] reg [5:0] uops_4_rob_idx; // @[util.scala:466:20] reg [3:0] uops_4_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_4_stq_idx; // @[util.scala:466:20] reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_4_pdst; // @[util.scala:466:20] reg [6:0] uops_4_prs1; // @[util.scala:466:20] reg [6:0] uops_4_prs2; // @[util.scala:466:20] reg [6:0] uops_4_prs3; // @[util.scala:466:20] reg [3:0] uops_4_ppred; // @[util.scala:466:20] reg uops_4_prs1_busy; // @[util.scala:466:20] reg uops_4_prs2_busy; // @[util.scala:466:20] reg uops_4_prs3_busy; // @[util.scala:466:20] reg uops_4_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20] reg uops_4_exception; // @[util.scala:466:20] reg [63:0] uops_4_exc_cause; // @[util.scala:466:20] reg uops_4_bypassable; // @[util.scala:466:20] reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_4_mem_size; // @[util.scala:466:20] reg uops_4_mem_signed; // @[util.scala:466:20] reg uops_4_is_fence; // @[util.scala:466:20] reg uops_4_is_fencei; // @[util.scala:466:20] reg uops_4_is_amo; // @[util.scala:466:20] reg uops_4_uses_ldq; // @[util.scala:466:20] reg uops_4_uses_stq; // @[util.scala:466:20] reg uops_4_is_sys_pc2epc; // @[util.scala:466:20] reg uops_4_is_unique; // @[util.scala:466:20] reg uops_4_flush_on_commit; // @[util.scala:466:20] reg uops_4_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_4_ldst; // @[util.scala:466:20] reg [5:0] uops_4_lrs1; // @[util.scala:466:20] reg [5:0] uops_4_lrs2; // @[util.scala:466:20] reg [5:0] uops_4_lrs3; // @[util.scala:466:20] reg uops_4_ldst_val; // @[util.scala:466:20] reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20] reg uops_4_frs3_en; // @[util.scala:466:20] reg uops_4_fp_val; // @[util.scala:466:20] reg uops_4_fp_single; // @[util.scala:466:20] reg uops_4_xcpt_pf_if; // @[util.scala:466:20] reg uops_4_xcpt_ae_if; // @[util.scala:466:20] reg uops_4_xcpt_ma_if; // @[util.scala:466:20] reg uops_4_bp_debug_if; // @[util.scala:466:20] reg uops_4_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_5_uopc; // @[util.scala:466:20] reg [31:0] uops_5_inst; // @[util.scala:466:20] reg [31:0] uops_5_debug_inst; // @[util.scala:466:20] reg uops_5_is_rvc; // @[util.scala:466:20] reg [33:0] uops_5_debug_pc; // @[util.scala:466:20] reg [2:0] uops_5_iq_type; // @[util.scala:466:20] reg [9:0] uops_5_fu_code; // @[util.scala:466:20] reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20] reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_5_ctrl_is_load; // @[util.scala:466:20] reg uops_5_ctrl_is_sta; // @[util.scala:466:20] reg uops_5_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_5_iw_state; // @[util.scala:466:20] reg uops_5_iw_p1_poisoned; // @[util.scala:466:20] reg uops_5_iw_p2_poisoned; // @[util.scala:466:20] reg uops_5_is_br; // @[util.scala:466:20] reg uops_5_is_jalr; // @[util.scala:466:20] reg uops_5_is_jal; // @[util.scala:466:20] reg uops_5_is_sfb; // @[util.scala:466:20] reg [3:0] uops_5_br_mask; // @[util.scala:466:20] wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_5_br_tag; // @[util.scala:466:20] reg [3:0] uops_5_ftq_idx; // @[util.scala:466:20] reg uops_5_edge_inst; // @[util.scala:466:20] reg [5:0] uops_5_pc_lob; // @[util.scala:466:20] reg uops_5_taken; // @[util.scala:466:20] reg [19:0] uops_5_imm_packed; // @[util.scala:466:20] reg [11:0] uops_5_csr_addr; // @[util.scala:466:20] reg [5:0] uops_5_rob_idx; // @[util.scala:466:20] reg [3:0] uops_5_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_5_stq_idx; // @[util.scala:466:20] reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_5_pdst; // @[util.scala:466:20] reg [6:0] uops_5_prs1; // @[util.scala:466:20] reg [6:0] uops_5_prs2; // @[util.scala:466:20] reg [6:0] uops_5_prs3; // @[util.scala:466:20] reg [3:0] uops_5_ppred; // @[util.scala:466:20] reg uops_5_prs1_busy; // @[util.scala:466:20] reg uops_5_prs2_busy; // @[util.scala:466:20] reg uops_5_prs3_busy; // @[util.scala:466:20] reg uops_5_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20] reg uops_5_exception; // @[util.scala:466:20] reg [63:0] uops_5_exc_cause; // @[util.scala:466:20] reg uops_5_bypassable; // @[util.scala:466:20] reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_5_mem_size; // @[util.scala:466:20] reg uops_5_mem_signed; // @[util.scala:466:20] reg uops_5_is_fence; // @[util.scala:466:20] reg uops_5_is_fencei; // @[util.scala:466:20] reg uops_5_is_amo; // @[util.scala:466:20] reg uops_5_uses_ldq; // @[util.scala:466:20] reg uops_5_uses_stq; // @[util.scala:466:20] reg uops_5_is_sys_pc2epc; // @[util.scala:466:20] reg uops_5_is_unique; // @[util.scala:466:20] reg uops_5_flush_on_commit; // @[util.scala:466:20] reg uops_5_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_5_ldst; // @[util.scala:466:20] reg [5:0] uops_5_lrs1; // @[util.scala:466:20] reg [5:0] uops_5_lrs2; // @[util.scala:466:20] reg [5:0] uops_5_lrs3; // @[util.scala:466:20] reg uops_5_ldst_val; // @[util.scala:466:20] reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20] reg uops_5_frs3_en; // @[util.scala:466:20] reg uops_5_fp_val; // @[util.scala:466:20] reg uops_5_fp_single; // @[util.scala:466:20] reg uops_5_xcpt_pf_if; // @[util.scala:466:20] reg uops_5_xcpt_ae_if; // @[util.scala:466:20] reg uops_5_xcpt_ma_if; // @[util.scala:466:20] reg uops_5_bp_debug_if; // @[util.scala:466:20] reg uops_5_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_6_uopc; // @[util.scala:466:20] reg [31:0] uops_6_inst; // @[util.scala:466:20] reg [31:0] uops_6_debug_inst; // @[util.scala:466:20] reg uops_6_is_rvc; // @[util.scala:466:20] reg [33:0] uops_6_debug_pc; // @[util.scala:466:20] reg [2:0] uops_6_iq_type; // @[util.scala:466:20] reg [9:0] uops_6_fu_code; // @[util.scala:466:20] reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20] reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_6_ctrl_is_load; // @[util.scala:466:20] reg uops_6_ctrl_is_sta; // @[util.scala:466:20] reg uops_6_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_6_iw_state; // @[util.scala:466:20] reg uops_6_iw_p1_poisoned; // @[util.scala:466:20] reg uops_6_iw_p2_poisoned; // @[util.scala:466:20] reg uops_6_is_br; // @[util.scala:466:20] reg uops_6_is_jalr; // @[util.scala:466:20] reg uops_6_is_jal; // @[util.scala:466:20] reg uops_6_is_sfb; // @[util.scala:466:20] reg [3:0] uops_6_br_mask; // @[util.scala:466:20] wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_6_br_tag; // @[util.scala:466:20] reg [3:0] uops_6_ftq_idx; // @[util.scala:466:20] reg uops_6_edge_inst; // @[util.scala:466:20] reg [5:0] uops_6_pc_lob; // @[util.scala:466:20] reg uops_6_taken; // @[util.scala:466:20] reg [19:0] uops_6_imm_packed; // @[util.scala:466:20] reg [11:0] uops_6_csr_addr; // @[util.scala:466:20] reg [5:0] uops_6_rob_idx; // @[util.scala:466:20] reg [3:0] uops_6_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_6_stq_idx; // @[util.scala:466:20] reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_6_pdst; // @[util.scala:466:20] reg [6:0] uops_6_prs1; // @[util.scala:466:20] reg [6:0] uops_6_prs2; // @[util.scala:466:20] reg [6:0] uops_6_prs3; // @[util.scala:466:20] reg [3:0] uops_6_ppred; // @[util.scala:466:20] reg uops_6_prs1_busy; // @[util.scala:466:20] reg uops_6_prs2_busy; // @[util.scala:466:20] reg uops_6_prs3_busy; // @[util.scala:466:20] reg uops_6_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20] reg uops_6_exception; // @[util.scala:466:20] reg [63:0] uops_6_exc_cause; // @[util.scala:466:20] reg uops_6_bypassable; // @[util.scala:466:20] reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_6_mem_size; // @[util.scala:466:20] reg uops_6_mem_signed; // @[util.scala:466:20] reg uops_6_is_fence; // @[util.scala:466:20] reg uops_6_is_fencei; // @[util.scala:466:20] reg uops_6_is_amo; // @[util.scala:466:20] reg uops_6_uses_ldq; // @[util.scala:466:20] reg uops_6_uses_stq; // @[util.scala:466:20] reg uops_6_is_sys_pc2epc; // @[util.scala:466:20] reg uops_6_is_unique; // @[util.scala:466:20] reg uops_6_flush_on_commit; // @[util.scala:466:20] reg uops_6_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_6_ldst; // @[util.scala:466:20] reg [5:0] uops_6_lrs1; // @[util.scala:466:20] reg [5:0] uops_6_lrs2; // @[util.scala:466:20] reg [5:0] uops_6_lrs3; // @[util.scala:466:20] reg uops_6_ldst_val; // @[util.scala:466:20] reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20] reg uops_6_frs3_en; // @[util.scala:466:20] reg uops_6_fp_val; // @[util.scala:466:20] reg uops_6_fp_single; // @[util.scala:466:20] reg uops_6_xcpt_pf_if; // @[util.scala:466:20] reg uops_6_xcpt_ae_if; // @[util.scala:466:20] reg uops_6_xcpt_ma_if; // @[util.scala:466:20] reg uops_6_bp_debug_if; // @[util.scala:466:20] reg uops_6_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_7_uopc; // @[util.scala:466:20] reg [31:0] uops_7_inst; // @[util.scala:466:20] reg [31:0] uops_7_debug_inst; // @[util.scala:466:20] reg uops_7_is_rvc; // @[util.scala:466:20] reg [33:0] uops_7_debug_pc; // @[util.scala:466:20] reg [2:0] uops_7_iq_type; // @[util.scala:466:20] reg [9:0] uops_7_fu_code; // @[util.scala:466:20] reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20] reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_7_ctrl_is_load; // @[util.scala:466:20] reg uops_7_ctrl_is_sta; // @[util.scala:466:20] reg uops_7_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_7_iw_state; // @[util.scala:466:20] reg uops_7_iw_p1_poisoned; // @[util.scala:466:20] reg uops_7_iw_p2_poisoned; // @[util.scala:466:20] reg uops_7_is_br; // @[util.scala:466:20] reg uops_7_is_jalr; // @[util.scala:466:20] reg uops_7_is_jal; // @[util.scala:466:20] reg uops_7_is_sfb; // @[util.scala:466:20] reg [3:0] uops_7_br_mask; // @[util.scala:466:20] wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_7_br_tag; // @[util.scala:466:20] reg [3:0] uops_7_ftq_idx; // @[util.scala:466:20] reg uops_7_edge_inst; // @[util.scala:466:20] reg [5:0] uops_7_pc_lob; // @[util.scala:466:20] reg uops_7_taken; // @[util.scala:466:20] reg [19:0] uops_7_imm_packed; // @[util.scala:466:20] reg [11:0] uops_7_csr_addr; // @[util.scala:466:20] reg [5:0] uops_7_rob_idx; // @[util.scala:466:20] reg [3:0] uops_7_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_7_stq_idx; // @[util.scala:466:20] reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_7_pdst; // @[util.scala:466:20] reg [6:0] uops_7_prs1; // @[util.scala:466:20] reg [6:0] uops_7_prs2; // @[util.scala:466:20] reg [6:0] uops_7_prs3; // @[util.scala:466:20] reg [3:0] uops_7_ppred; // @[util.scala:466:20] reg uops_7_prs1_busy; // @[util.scala:466:20] reg uops_7_prs2_busy; // @[util.scala:466:20] reg uops_7_prs3_busy; // @[util.scala:466:20] reg uops_7_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20] reg uops_7_exception; // @[util.scala:466:20] reg [63:0] uops_7_exc_cause; // @[util.scala:466:20] reg uops_7_bypassable; // @[util.scala:466:20] reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_7_mem_size; // @[util.scala:466:20] reg uops_7_mem_signed; // @[util.scala:466:20] reg uops_7_is_fence; // @[util.scala:466:20] reg uops_7_is_fencei; // @[util.scala:466:20] reg uops_7_is_amo; // @[util.scala:466:20] reg uops_7_uses_ldq; // @[util.scala:466:20] reg uops_7_uses_stq; // @[util.scala:466:20] reg uops_7_is_sys_pc2epc; // @[util.scala:466:20] reg uops_7_is_unique; // @[util.scala:466:20] reg uops_7_flush_on_commit; // @[util.scala:466:20] reg uops_7_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_7_ldst; // @[util.scala:466:20] reg [5:0] uops_7_lrs1; // @[util.scala:466:20] reg [5:0] uops_7_lrs2; // @[util.scala:466:20] reg [5:0] uops_7_lrs3; // @[util.scala:466:20] reg uops_7_ldst_val; // @[util.scala:466:20] reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20] reg uops_7_frs3_en; // @[util.scala:466:20] reg uops_7_fp_val; // @[util.scala:466:20] reg uops_7_fp_single; // @[util.scala:466:20] reg uops_7_xcpt_pf_if; // @[util.scala:466:20] reg uops_7_xcpt_ae_if; // @[util.scala:466:20] reg uops_7_xcpt_ma_if; // @[util.scala:466:20] reg uops_7_bp_debug_if; // @[util.scala:466:20] reg uops_7_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_8_uopc; // @[util.scala:466:20] reg [31:0] uops_8_inst; // @[util.scala:466:20] reg [31:0] uops_8_debug_inst; // @[util.scala:466:20] reg uops_8_is_rvc; // @[util.scala:466:20] reg [33:0] uops_8_debug_pc; // @[util.scala:466:20] reg [2:0] uops_8_iq_type; // @[util.scala:466:20] reg [9:0] uops_8_fu_code; // @[util.scala:466:20] reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20] reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_8_ctrl_is_load; // @[util.scala:466:20] reg uops_8_ctrl_is_sta; // @[util.scala:466:20] reg uops_8_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_8_iw_state; // @[util.scala:466:20] reg uops_8_iw_p1_poisoned; // @[util.scala:466:20] reg uops_8_iw_p2_poisoned; // @[util.scala:466:20] reg uops_8_is_br; // @[util.scala:466:20] reg uops_8_is_jalr; // @[util.scala:466:20] reg uops_8_is_jal; // @[util.scala:466:20] reg uops_8_is_sfb; // @[util.scala:466:20] reg [3:0] uops_8_br_mask; // @[util.scala:466:20] wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_8_br_tag; // @[util.scala:466:20] reg [3:0] uops_8_ftq_idx; // @[util.scala:466:20] reg uops_8_edge_inst; // @[util.scala:466:20] reg [5:0] uops_8_pc_lob; // @[util.scala:466:20] reg uops_8_taken; // @[util.scala:466:20] reg [19:0] uops_8_imm_packed; // @[util.scala:466:20] reg [11:0] uops_8_csr_addr; // @[util.scala:466:20] reg [5:0] uops_8_rob_idx; // @[util.scala:466:20] reg [3:0] uops_8_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_8_stq_idx; // @[util.scala:466:20] reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_8_pdst; // @[util.scala:466:20] reg [6:0] uops_8_prs1; // @[util.scala:466:20] reg [6:0] uops_8_prs2; // @[util.scala:466:20] reg [6:0] uops_8_prs3; // @[util.scala:466:20] reg [3:0] uops_8_ppred; // @[util.scala:466:20] reg uops_8_prs1_busy; // @[util.scala:466:20] reg uops_8_prs2_busy; // @[util.scala:466:20] reg uops_8_prs3_busy; // @[util.scala:466:20] reg uops_8_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20] reg uops_8_exception; // @[util.scala:466:20] reg [63:0] uops_8_exc_cause; // @[util.scala:466:20] reg uops_8_bypassable; // @[util.scala:466:20] reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_8_mem_size; // @[util.scala:466:20] reg uops_8_mem_signed; // @[util.scala:466:20] reg uops_8_is_fence; // @[util.scala:466:20] reg uops_8_is_fencei; // @[util.scala:466:20] reg uops_8_is_amo; // @[util.scala:466:20] reg uops_8_uses_ldq; // @[util.scala:466:20] reg uops_8_uses_stq; // @[util.scala:466:20] reg uops_8_is_sys_pc2epc; // @[util.scala:466:20] reg uops_8_is_unique; // @[util.scala:466:20] reg uops_8_flush_on_commit; // @[util.scala:466:20] reg uops_8_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_8_ldst; // @[util.scala:466:20] reg [5:0] uops_8_lrs1; // @[util.scala:466:20] reg [5:0] uops_8_lrs2; // @[util.scala:466:20] reg [5:0] uops_8_lrs3; // @[util.scala:466:20] reg uops_8_ldst_val; // @[util.scala:466:20] reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20] reg uops_8_frs3_en; // @[util.scala:466:20] reg uops_8_fp_val; // @[util.scala:466:20] reg uops_8_fp_single; // @[util.scala:466:20] reg uops_8_xcpt_pf_if; // @[util.scala:466:20] reg uops_8_xcpt_ae_if; // @[util.scala:466:20] reg uops_8_xcpt_ma_if; // @[util.scala:466:20] reg uops_8_bp_debug_if; // @[util.scala:466:20] reg uops_8_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_9_uopc; // @[util.scala:466:20] reg [31:0] uops_9_inst; // @[util.scala:466:20] reg [31:0] uops_9_debug_inst; // @[util.scala:466:20] reg uops_9_is_rvc; // @[util.scala:466:20] reg [33:0] uops_9_debug_pc; // @[util.scala:466:20] reg [2:0] uops_9_iq_type; // @[util.scala:466:20] reg [9:0] uops_9_fu_code; // @[util.scala:466:20] reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20] reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_9_ctrl_is_load; // @[util.scala:466:20] reg uops_9_ctrl_is_sta; // @[util.scala:466:20] reg uops_9_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_9_iw_state; // @[util.scala:466:20] reg uops_9_iw_p1_poisoned; // @[util.scala:466:20] reg uops_9_iw_p2_poisoned; // @[util.scala:466:20] reg uops_9_is_br; // @[util.scala:466:20] reg uops_9_is_jalr; // @[util.scala:466:20] reg uops_9_is_jal; // @[util.scala:466:20] reg uops_9_is_sfb; // @[util.scala:466:20] reg [3:0] uops_9_br_mask; // @[util.scala:466:20] wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_9_br_tag; // @[util.scala:466:20] reg [3:0] uops_9_ftq_idx; // @[util.scala:466:20] reg uops_9_edge_inst; // @[util.scala:466:20] reg [5:0] uops_9_pc_lob; // @[util.scala:466:20] reg uops_9_taken; // @[util.scala:466:20] reg [19:0] uops_9_imm_packed; // @[util.scala:466:20] reg [11:0] uops_9_csr_addr; // @[util.scala:466:20] reg [5:0] uops_9_rob_idx; // @[util.scala:466:20] reg [3:0] uops_9_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_9_stq_idx; // @[util.scala:466:20] reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_9_pdst; // @[util.scala:466:20] reg [6:0] uops_9_prs1; // @[util.scala:466:20] reg [6:0] uops_9_prs2; // @[util.scala:466:20] reg [6:0] uops_9_prs3; // @[util.scala:466:20] reg [3:0] uops_9_ppred; // @[util.scala:466:20] reg uops_9_prs1_busy; // @[util.scala:466:20] reg uops_9_prs2_busy; // @[util.scala:466:20] reg uops_9_prs3_busy; // @[util.scala:466:20] reg uops_9_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20] reg uops_9_exception; // @[util.scala:466:20] reg [63:0] uops_9_exc_cause; // @[util.scala:466:20] reg uops_9_bypassable; // @[util.scala:466:20] reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_9_mem_size; // @[util.scala:466:20] reg uops_9_mem_signed; // @[util.scala:466:20] reg uops_9_is_fence; // @[util.scala:466:20] reg uops_9_is_fencei; // @[util.scala:466:20] reg uops_9_is_amo; // @[util.scala:466:20] reg uops_9_uses_ldq; // @[util.scala:466:20] reg uops_9_uses_stq; // @[util.scala:466:20] reg uops_9_is_sys_pc2epc; // @[util.scala:466:20] reg uops_9_is_unique; // @[util.scala:466:20] reg uops_9_flush_on_commit; // @[util.scala:466:20] reg uops_9_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_9_ldst; // @[util.scala:466:20] reg [5:0] uops_9_lrs1; // @[util.scala:466:20] reg [5:0] uops_9_lrs2; // @[util.scala:466:20] reg [5:0] uops_9_lrs3; // @[util.scala:466:20] reg uops_9_ldst_val; // @[util.scala:466:20] reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20] reg uops_9_frs3_en; // @[util.scala:466:20] reg uops_9_fp_val; // @[util.scala:466:20] reg uops_9_fp_single; // @[util.scala:466:20] reg uops_9_xcpt_pf_if; // @[util.scala:466:20] reg uops_9_xcpt_ae_if; // @[util.scala:466:20] reg uops_9_xcpt_ma_if; // @[util.scala:466:20] reg uops_9_bp_debug_if; // @[util.scala:466:20] reg uops_9_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_10_uopc; // @[util.scala:466:20] reg [31:0] uops_10_inst; // @[util.scala:466:20] reg [31:0] uops_10_debug_inst; // @[util.scala:466:20] reg uops_10_is_rvc; // @[util.scala:466:20] reg [33:0] uops_10_debug_pc; // @[util.scala:466:20] reg [2:0] uops_10_iq_type; // @[util.scala:466:20] reg [9:0] uops_10_fu_code; // @[util.scala:466:20] reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20] reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_10_ctrl_is_load; // @[util.scala:466:20] reg uops_10_ctrl_is_sta; // @[util.scala:466:20] reg uops_10_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_10_iw_state; // @[util.scala:466:20] reg uops_10_iw_p1_poisoned; // @[util.scala:466:20] reg uops_10_iw_p2_poisoned; // @[util.scala:466:20] reg uops_10_is_br; // @[util.scala:466:20] reg uops_10_is_jalr; // @[util.scala:466:20] reg uops_10_is_jal; // @[util.scala:466:20] reg uops_10_is_sfb; // @[util.scala:466:20] reg [3:0] uops_10_br_mask; // @[util.scala:466:20] wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_10_br_tag; // @[util.scala:466:20] reg [3:0] uops_10_ftq_idx; // @[util.scala:466:20] reg uops_10_edge_inst; // @[util.scala:466:20] reg [5:0] uops_10_pc_lob; // @[util.scala:466:20] reg uops_10_taken; // @[util.scala:466:20] reg [19:0] uops_10_imm_packed; // @[util.scala:466:20] reg [11:0] uops_10_csr_addr; // @[util.scala:466:20] reg [5:0] uops_10_rob_idx; // @[util.scala:466:20] reg [3:0] uops_10_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_10_stq_idx; // @[util.scala:466:20] reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_10_pdst; // @[util.scala:466:20] reg [6:0] uops_10_prs1; // @[util.scala:466:20] reg [6:0] uops_10_prs2; // @[util.scala:466:20] reg [6:0] uops_10_prs3; // @[util.scala:466:20] reg [3:0] uops_10_ppred; // @[util.scala:466:20] reg uops_10_prs1_busy; // @[util.scala:466:20] reg uops_10_prs2_busy; // @[util.scala:466:20] reg uops_10_prs3_busy; // @[util.scala:466:20] reg uops_10_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20] reg uops_10_exception; // @[util.scala:466:20] reg [63:0] uops_10_exc_cause; // @[util.scala:466:20] reg uops_10_bypassable; // @[util.scala:466:20] reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_10_mem_size; // @[util.scala:466:20] reg uops_10_mem_signed; // @[util.scala:466:20] reg uops_10_is_fence; // @[util.scala:466:20] reg uops_10_is_fencei; // @[util.scala:466:20] reg uops_10_is_amo; // @[util.scala:466:20] reg uops_10_uses_ldq; // @[util.scala:466:20] reg uops_10_uses_stq; // @[util.scala:466:20] reg uops_10_is_sys_pc2epc; // @[util.scala:466:20] reg uops_10_is_unique; // @[util.scala:466:20] reg uops_10_flush_on_commit; // @[util.scala:466:20] reg uops_10_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_10_ldst; // @[util.scala:466:20] reg [5:0] uops_10_lrs1; // @[util.scala:466:20] reg [5:0] uops_10_lrs2; // @[util.scala:466:20] reg [5:0] uops_10_lrs3; // @[util.scala:466:20] reg uops_10_ldst_val; // @[util.scala:466:20] reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20] reg uops_10_frs3_en; // @[util.scala:466:20] reg uops_10_fp_val; // @[util.scala:466:20] reg uops_10_fp_single; // @[util.scala:466:20] reg uops_10_xcpt_pf_if; // @[util.scala:466:20] reg uops_10_xcpt_ae_if; // @[util.scala:466:20] reg uops_10_xcpt_ma_if; // @[util.scala:466:20] reg uops_10_bp_debug_if; // @[util.scala:466:20] reg uops_10_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_11_uopc; // @[util.scala:466:20] reg [31:0] uops_11_inst; // @[util.scala:466:20] reg [31:0] uops_11_debug_inst; // @[util.scala:466:20] reg uops_11_is_rvc; // @[util.scala:466:20] reg [33:0] uops_11_debug_pc; // @[util.scala:466:20] reg [2:0] uops_11_iq_type; // @[util.scala:466:20] reg [9:0] uops_11_fu_code; // @[util.scala:466:20] reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20] reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_11_ctrl_is_load; // @[util.scala:466:20] reg uops_11_ctrl_is_sta; // @[util.scala:466:20] reg uops_11_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_11_iw_state; // @[util.scala:466:20] reg uops_11_iw_p1_poisoned; // @[util.scala:466:20] reg uops_11_iw_p2_poisoned; // @[util.scala:466:20] reg uops_11_is_br; // @[util.scala:466:20] reg uops_11_is_jalr; // @[util.scala:466:20] reg uops_11_is_jal; // @[util.scala:466:20] reg uops_11_is_sfb; // @[util.scala:466:20] reg [3:0] uops_11_br_mask; // @[util.scala:466:20] wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_11_br_tag; // @[util.scala:466:20] reg [3:0] uops_11_ftq_idx; // @[util.scala:466:20] reg uops_11_edge_inst; // @[util.scala:466:20] reg [5:0] uops_11_pc_lob; // @[util.scala:466:20] reg uops_11_taken; // @[util.scala:466:20] reg [19:0] uops_11_imm_packed; // @[util.scala:466:20] reg [11:0] uops_11_csr_addr; // @[util.scala:466:20] reg [5:0] uops_11_rob_idx; // @[util.scala:466:20] reg [3:0] uops_11_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_11_stq_idx; // @[util.scala:466:20] reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_11_pdst; // @[util.scala:466:20] reg [6:0] uops_11_prs1; // @[util.scala:466:20] reg [6:0] uops_11_prs2; // @[util.scala:466:20] reg [6:0] uops_11_prs3; // @[util.scala:466:20] reg [3:0] uops_11_ppred; // @[util.scala:466:20] reg uops_11_prs1_busy; // @[util.scala:466:20] reg uops_11_prs2_busy; // @[util.scala:466:20] reg uops_11_prs3_busy; // @[util.scala:466:20] reg uops_11_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20] reg uops_11_exception; // @[util.scala:466:20] reg [63:0] uops_11_exc_cause; // @[util.scala:466:20] reg uops_11_bypassable; // @[util.scala:466:20] reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_11_mem_size; // @[util.scala:466:20] reg uops_11_mem_signed; // @[util.scala:466:20] reg uops_11_is_fence; // @[util.scala:466:20] reg uops_11_is_fencei; // @[util.scala:466:20] reg uops_11_is_amo; // @[util.scala:466:20] reg uops_11_uses_ldq; // @[util.scala:466:20] reg uops_11_uses_stq; // @[util.scala:466:20] reg uops_11_is_sys_pc2epc; // @[util.scala:466:20] reg uops_11_is_unique; // @[util.scala:466:20] reg uops_11_flush_on_commit; // @[util.scala:466:20] reg uops_11_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_11_ldst; // @[util.scala:466:20] reg [5:0] uops_11_lrs1; // @[util.scala:466:20] reg [5:0] uops_11_lrs2; // @[util.scala:466:20] reg [5:0] uops_11_lrs3; // @[util.scala:466:20] reg uops_11_ldst_val; // @[util.scala:466:20] reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20] reg uops_11_frs3_en; // @[util.scala:466:20] reg uops_11_fp_val; // @[util.scala:466:20] reg uops_11_fp_single; // @[util.scala:466:20] reg uops_11_xcpt_pf_if; // @[util.scala:466:20] reg uops_11_xcpt_ae_if; // @[util.scala:466:20] reg uops_11_xcpt_ma_if; // @[util.scala:466:20] reg uops_11_bp_debug_if; // @[util.scala:466:20] reg uops_11_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_12_uopc; // @[util.scala:466:20] reg [31:0] uops_12_inst; // @[util.scala:466:20] reg [31:0] uops_12_debug_inst; // @[util.scala:466:20] reg uops_12_is_rvc; // @[util.scala:466:20] reg [33:0] uops_12_debug_pc; // @[util.scala:466:20] reg [2:0] uops_12_iq_type; // @[util.scala:466:20] reg [9:0] uops_12_fu_code; // @[util.scala:466:20] reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20] reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_12_ctrl_is_load; // @[util.scala:466:20] reg uops_12_ctrl_is_sta; // @[util.scala:466:20] reg uops_12_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_12_iw_state; // @[util.scala:466:20] reg uops_12_iw_p1_poisoned; // @[util.scala:466:20] reg uops_12_iw_p2_poisoned; // @[util.scala:466:20] reg uops_12_is_br; // @[util.scala:466:20] reg uops_12_is_jalr; // @[util.scala:466:20] reg uops_12_is_jal; // @[util.scala:466:20] reg uops_12_is_sfb; // @[util.scala:466:20] reg [3:0] uops_12_br_mask; // @[util.scala:466:20] wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_12_br_tag; // @[util.scala:466:20] reg [3:0] uops_12_ftq_idx; // @[util.scala:466:20] reg uops_12_edge_inst; // @[util.scala:466:20] reg [5:0] uops_12_pc_lob; // @[util.scala:466:20] reg uops_12_taken; // @[util.scala:466:20] reg [19:0] uops_12_imm_packed; // @[util.scala:466:20] reg [11:0] uops_12_csr_addr; // @[util.scala:466:20] reg [5:0] uops_12_rob_idx; // @[util.scala:466:20] reg [3:0] uops_12_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_12_stq_idx; // @[util.scala:466:20] reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_12_pdst; // @[util.scala:466:20] reg [6:0] uops_12_prs1; // @[util.scala:466:20] reg [6:0] uops_12_prs2; // @[util.scala:466:20] reg [6:0] uops_12_prs3; // @[util.scala:466:20] reg [3:0] uops_12_ppred; // @[util.scala:466:20] reg uops_12_prs1_busy; // @[util.scala:466:20] reg uops_12_prs2_busy; // @[util.scala:466:20] reg uops_12_prs3_busy; // @[util.scala:466:20] reg uops_12_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20] reg uops_12_exception; // @[util.scala:466:20] reg [63:0] uops_12_exc_cause; // @[util.scala:466:20] reg uops_12_bypassable; // @[util.scala:466:20] reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_12_mem_size; // @[util.scala:466:20] reg uops_12_mem_signed; // @[util.scala:466:20] reg uops_12_is_fence; // @[util.scala:466:20] reg uops_12_is_fencei; // @[util.scala:466:20] reg uops_12_is_amo; // @[util.scala:466:20] reg uops_12_uses_ldq; // @[util.scala:466:20] reg uops_12_uses_stq; // @[util.scala:466:20] reg uops_12_is_sys_pc2epc; // @[util.scala:466:20] reg uops_12_is_unique; // @[util.scala:466:20] reg uops_12_flush_on_commit; // @[util.scala:466:20] reg uops_12_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_12_ldst; // @[util.scala:466:20] reg [5:0] uops_12_lrs1; // @[util.scala:466:20] reg [5:0] uops_12_lrs2; // @[util.scala:466:20] reg [5:0] uops_12_lrs3; // @[util.scala:466:20] reg uops_12_ldst_val; // @[util.scala:466:20] reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20] reg uops_12_frs3_en; // @[util.scala:466:20] reg uops_12_fp_val; // @[util.scala:466:20] reg uops_12_fp_single; // @[util.scala:466:20] reg uops_12_xcpt_pf_if; // @[util.scala:466:20] reg uops_12_xcpt_ae_if; // @[util.scala:466:20] reg uops_12_xcpt_ma_if; // @[util.scala:466:20] reg uops_12_bp_debug_if; // @[util.scala:466:20] reg uops_12_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_13_uopc; // @[util.scala:466:20] reg [31:0] uops_13_inst; // @[util.scala:466:20] reg [31:0] uops_13_debug_inst; // @[util.scala:466:20] reg uops_13_is_rvc; // @[util.scala:466:20] reg [33:0] uops_13_debug_pc; // @[util.scala:466:20] reg [2:0] uops_13_iq_type; // @[util.scala:466:20] reg [9:0] uops_13_fu_code; // @[util.scala:466:20] reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20] reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_13_ctrl_is_load; // @[util.scala:466:20] reg uops_13_ctrl_is_sta; // @[util.scala:466:20] reg uops_13_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_13_iw_state; // @[util.scala:466:20] reg uops_13_iw_p1_poisoned; // @[util.scala:466:20] reg uops_13_iw_p2_poisoned; // @[util.scala:466:20] reg uops_13_is_br; // @[util.scala:466:20] reg uops_13_is_jalr; // @[util.scala:466:20] reg uops_13_is_jal; // @[util.scala:466:20] reg uops_13_is_sfb; // @[util.scala:466:20] reg [3:0] uops_13_br_mask; // @[util.scala:466:20] wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_13_br_tag; // @[util.scala:466:20] reg [3:0] uops_13_ftq_idx; // @[util.scala:466:20] reg uops_13_edge_inst; // @[util.scala:466:20] reg [5:0] uops_13_pc_lob; // @[util.scala:466:20] reg uops_13_taken; // @[util.scala:466:20] reg [19:0] uops_13_imm_packed; // @[util.scala:466:20] reg [11:0] uops_13_csr_addr; // @[util.scala:466:20] reg [5:0] uops_13_rob_idx; // @[util.scala:466:20] reg [3:0] uops_13_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_13_stq_idx; // @[util.scala:466:20] reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_13_pdst; // @[util.scala:466:20] reg [6:0] uops_13_prs1; // @[util.scala:466:20] reg [6:0] uops_13_prs2; // @[util.scala:466:20] reg [6:0] uops_13_prs3; // @[util.scala:466:20] reg [3:0] uops_13_ppred; // @[util.scala:466:20] reg uops_13_prs1_busy; // @[util.scala:466:20] reg uops_13_prs2_busy; // @[util.scala:466:20] reg uops_13_prs3_busy; // @[util.scala:466:20] reg uops_13_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20] reg uops_13_exception; // @[util.scala:466:20] reg [63:0] uops_13_exc_cause; // @[util.scala:466:20] reg uops_13_bypassable; // @[util.scala:466:20] reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_13_mem_size; // @[util.scala:466:20] reg uops_13_mem_signed; // @[util.scala:466:20] reg uops_13_is_fence; // @[util.scala:466:20] reg uops_13_is_fencei; // @[util.scala:466:20] reg uops_13_is_amo; // @[util.scala:466:20] reg uops_13_uses_ldq; // @[util.scala:466:20] reg uops_13_uses_stq; // @[util.scala:466:20] reg uops_13_is_sys_pc2epc; // @[util.scala:466:20] reg uops_13_is_unique; // @[util.scala:466:20] reg uops_13_flush_on_commit; // @[util.scala:466:20] reg uops_13_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_13_ldst; // @[util.scala:466:20] reg [5:0] uops_13_lrs1; // @[util.scala:466:20] reg [5:0] uops_13_lrs2; // @[util.scala:466:20] reg [5:0] uops_13_lrs3; // @[util.scala:466:20] reg uops_13_ldst_val; // @[util.scala:466:20] reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20] reg uops_13_frs3_en; // @[util.scala:466:20] reg uops_13_fp_val; // @[util.scala:466:20] reg uops_13_fp_single; // @[util.scala:466:20] reg uops_13_xcpt_pf_if; // @[util.scala:466:20] reg uops_13_xcpt_ae_if; // @[util.scala:466:20] reg uops_13_xcpt_ma_if; // @[util.scala:466:20] reg uops_13_bp_debug_if; // @[util.scala:466:20] reg uops_13_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_14_uopc; // @[util.scala:466:20] reg [31:0] uops_14_inst; // @[util.scala:466:20] reg [31:0] uops_14_debug_inst; // @[util.scala:466:20] reg uops_14_is_rvc; // @[util.scala:466:20] reg [33:0] uops_14_debug_pc; // @[util.scala:466:20] reg [2:0] uops_14_iq_type; // @[util.scala:466:20] reg [9:0] uops_14_fu_code; // @[util.scala:466:20] reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20] reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_14_ctrl_is_load; // @[util.scala:466:20] reg uops_14_ctrl_is_sta; // @[util.scala:466:20] reg uops_14_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_14_iw_state; // @[util.scala:466:20] reg uops_14_iw_p1_poisoned; // @[util.scala:466:20] reg uops_14_iw_p2_poisoned; // @[util.scala:466:20] reg uops_14_is_br; // @[util.scala:466:20] reg uops_14_is_jalr; // @[util.scala:466:20] reg uops_14_is_jal; // @[util.scala:466:20] reg uops_14_is_sfb; // @[util.scala:466:20] reg [3:0] uops_14_br_mask; // @[util.scala:466:20] wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_14_br_tag; // @[util.scala:466:20] reg [3:0] uops_14_ftq_idx; // @[util.scala:466:20] reg uops_14_edge_inst; // @[util.scala:466:20] reg [5:0] uops_14_pc_lob; // @[util.scala:466:20] reg uops_14_taken; // @[util.scala:466:20] reg [19:0] uops_14_imm_packed; // @[util.scala:466:20] reg [11:0] uops_14_csr_addr; // @[util.scala:466:20] reg [5:0] uops_14_rob_idx; // @[util.scala:466:20] reg [3:0] uops_14_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_14_stq_idx; // @[util.scala:466:20] reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_14_pdst; // @[util.scala:466:20] reg [6:0] uops_14_prs1; // @[util.scala:466:20] reg [6:0] uops_14_prs2; // @[util.scala:466:20] reg [6:0] uops_14_prs3; // @[util.scala:466:20] reg [3:0] uops_14_ppred; // @[util.scala:466:20] reg uops_14_prs1_busy; // @[util.scala:466:20] reg uops_14_prs2_busy; // @[util.scala:466:20] reg uops_14_prs3_busy; // @[util.scala:466:20] reg uops_14_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20] reg uops_14_exception; // @[util.scala:466:20] reg [63:0] uops_14_exc_cause; // @[util.scala:466:20] reg uops_14_bypassable; // @[util.scala:466:20] reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_14_mem_size; // @[util.scala:466:20] reg uops_14_mem_signed; // @[util.scala:466:20] reg uops_14_is_fence; // @[util.scala:466:20] reg uops_14_is_fencei; // @[util.scala:466:20] reg uops_14_is_amo; // @[util.scala:466:20] reg uops_14_uses_ldq; // @[util.scala:466:20] reg uops_14_uses_stq; // @[util.scala:466:20] reg uops_14_is_sys_pc2epc; // @[util.scala:466:20] reg uops_14_is_unique; // @[util.scala:466:20] reg uops_14_flush_on_commit; // @[util.scala:466:20] reg uops_14_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_14_ldst; // @[util.scala:466:20] reg [5:0] uops_14_lrs1; // @[util.scala:466:20] reg [5:0] uops_14_lrs2; // @[util.scala:466:20] reg [5:0] uops_14_lrs3; // @[util.scala:466:20] reg uops_14_ldst_val; // @[util.scala:466:20] reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20] reg uops_14_frs3_en; // @[util.scala:466:20] reg uops_14_fp_val; // @[util.scala:466:20] reg uops_14_fp_single; // @[util.scala:466:20] reg uops_14_xcpt_pf_if; // @[util.scala:466:20] reg uops_14_xcpt_ae_if; // @[util.scala:466:20] reg uops_14_xcpt_ma_if; // @[util.scala:466:20] reg uops_14_bp_debug_if; // @[util.scala:466:20] reg uops_14_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_15_uopc; // @[util.scala:466:20] reg [31:0] uops_15_inst; // @[util.scala:466:20] reg [31:0] uops_15_debug_inst; // @[util.scala:466:20] reg uops_15_is_rvc; // @[util.scala:466:20] reg [33:0] uops_15_debug_pc; // @[util.scala:466:20] reg [2:0] uops_15_iq_type; // @[util.scala:466:20] reg [9:0] uops_15_fu_code; // @[util.scala:466:20] reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20] reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_15_ctrl_is_load; // @[util.scala:466:20] reg uops_15_ctrl_is_sta; // @[util.scala:466:20] reg uops_15_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_15_iw_state; // @[util.scala:466:20] reg uops_15_iw_p1_poisoned; // @[util.scala:466:20] reg uops_15_iw_p2_poisoned; // @[util.scala:466:20] reg uops_15_is_br; // @[util.scala:466:20] reg uops_15_is_jalr; // @[util.scala:466:20] reg uops_15_is_jal; // @[util.scala:466:20] reg uops_15_is_sfb; // @[util.scala:466:20] reg [3:0] uops_15_br_mask; // @[util.scala:466:20] wire [3:0] _uops_15_br_mask_T_1 = uops_15_br_mask; // @[util.scala:89:21, :466:20] reg [1:0] uops_15_br_tag; // @[util.scala:466:20] reg [3:0] uops_15_ftq_idx; // @[util.scala:466:20] reg uops_15_edge_inst; // @[util.scala:466:20] reg [5:0] uops_15_pc_lob; // @[util.scala:466:20] reg uops_15_taken; // @[util.scala:466:20] reg [19:0] uops_15_imm_packed; // @[util.scala:466:20] reg [11:0] uops_15_csr_addr; // @[util.scala:466:20] reg [5:0] uops_15_rob_idx; // @[util.scala:466:20] reg [3:0] uops_15_ldq_idx; // @[util.scala:466:20] reg [3:0] uops_15_stq_idx; // @[util.scala:466:20] reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_15_pdst; // @[util.scala:466:20] reg [6:0] uops_15_prs1; // @[util.scala:466:20] reg [6:0] uops_15_prs2; // @[util.scala:466:20] reg [6:0] uops_15_prs3; // @[util.scala:466:20] reg [3:0] uops_15_ppred; // @[util.scala:466:20] reg uops_15_prs1_busy; // @[util.scala:466:20] reg uops_15_prs2_busy; // @[util.scala:466:20] reg uops_15_prs3_busy; // @[util.scala:466:20] reg uops_15_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20] reg uops_15_exception; // @[util.scala:466:20] reg [63:0] uops_15_exc_cause; // @[util.scala:466:20] reg uops_15_bypassable; // @[util.scala:466:20] reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_15_mem_size; // @[util.scala:466:20] reg uops_15_mem_signed; // @[util.scala:466:20] reg uops_15_is_fence; // @[util.scala:466:20] reg uops_15_is_fencei; // @[util.scala:466:20] reg uops_15_is_amo; // @[util.scala:466:20] reg uops_15_uses_ldq; // @[util.scala:466:20] reg uops_15_uses_stq; // @[util.scala:466:20] reg uops_15_is_sys_pc2epc; // @[util.scala:466:20] reg uops_15_is_unique; // @[util.scala:466:20] reg uops_15_flush_on_commit; // @[util.scala:466:20] reg uops_15_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_15_ldst; // @[util.scala:466:20] reg [5:0] uops_15_lrs1; // @[util.scala:466:20] reg [5:0] uops_15_lrs2; // @[util.scala:466:20] reg [5:0] uops_15_lrs3; // @[util.scala:466:20] reg uops_15_ldst_val; // @[util.scala:466:20] reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20] reg uops_15_frs3_en; // @[util.scala:466:20] reg uops_15_fp_val; // @[util.scala:466:20] reg uops_15_fp_single; // @[util.scala:466:20] reg uops_15_xcpt_pf_if; // @[util.scala:466:20] reg uops_15_xcpt_ae_if; // @[util.scala:466:20] reg uops_15_xcpt_ma_if; // @[util.scala:466:20] reg uops_15_bp_debug_if; // @[util.scala:466:20] reg uops_15_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire full; // @[util.scala:474:24] assign full = _GEN; // @[util.scala:474:24] wire _io_count_T; // @[util.scala:526:32] assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35] wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}] wire _valids_0_T_6 = _valids_0_T_3; // @[util.scala:481:{29,69}] wire _valids_1_T_6 = _valids_1_T_3; // @[util.scala:481:{29,69}] wire _valids_2_T_6 = _valids_2_T_3; // @[util.scala:481:{29,69}] wire _valids_3_T_6 = _valids_3_T_3; // @[util.scala:481:{29,69}] wire _valids_4_T_6 = _valids_4_T_3; // @[util.scala:481:{29,69}] wire _valids_5_T_6 = _valids_5_T_3; // @[util.scala:481:{29,69}] wire _valids_6_T_6 = _valids_6_T_3; // @[util.scala:481:{29,69}] wire _valids_7_T_6 = _valids_7_T_3; // @[util.scala:481:{29,69}] wire _valids_8_T_6 = _valids_8_T_3; // @[util.scala:481:{29,69}] wire _valids_9_T_6 = _valids_9_T_3; // @[util.scala:481:{29,69}] wire _valids_10_T_6 = _valids_10_T_3; // @[util.scala:481:{29,69}] wire _valids_11_T_6 = _valids_11_T_3; // @[util.scala:481:{29,69}] wire _valids_12_T_6 = _valids_12_T_3; // @[util.scala:481:{29,69}] wire _valids_13_T_6 = _valids_13_T_3; // @[util.scala:481:{29,69}] wire _valids_14_T_6 = _valids_14_T_3; // @[util.scala:481:{29,69}] wire _valids_15_T_6 = _valids_15_T_3; // @[util.scala:481:{29,69}] wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17] assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask; // @[util.scala:85:25, :506:17] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17] wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][33:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}] wire _io_deq_valid_T_5 = _io_deq_valid_T_1; // @[util.scala:509:{40,65}] assign _io_deq_valid_T_8 = _io_deq_valid_T_5; // @[util.scala:509:{65,108}] assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108] assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7] wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40] wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}] assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}] wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40] wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] valids_3 <= 1'h0; // @[util.scala:465:24] valids_4 <= 1'h0; // @[util.scala:465:24] valids_5 <= 1'h0; // @[util.scala:465:24] valids_6 <= 1'h0; // @[util.scala:465:24] valids_7 <= 1'h0; // @[util.scala:465:24] valids_8 <= 1'h0; // @[util.scala:465:24] valids_9 <= 1'h0; // @[util.scala:465:24] valids_10 <= 1'h0; // @[util.scala:465:24] valids_11 <= 1'h0; // @[util.scala:465:24] valids_12 <= 1'h0; // @[util.scala:465:24] valids_13 <= 1'h0; // @[util.scala:465:24] valids_14 <= 1'h0; // @[util.scala:465:24] valids_15 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40] valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33] uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_3) // @[util.scala:465:24] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33] uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_4) // @[util.scala:465:24] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33] uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_5) // @[util.scala:465:24] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33] uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_6) // @[util.scala:465:24] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33] uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_7) // @[util.scala:465:24] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33] uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_8) // @[util.scala:465:24] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33] uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_9) // @[util.scala:465:24] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33] uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_10) // @[util.scala:465:24] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33] uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_11) // @[util.scala:465:24] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33] uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_12) // @[util.scala:465:24] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33] uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_13) // @[util.scala:465:24] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33] uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_14) // @[util.scala:465:24] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33] uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40] uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_15) // @[util.scala:465:24] uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_16x131 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_139( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_263( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_7 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_32( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_54 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31] wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31] wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_109 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1328 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1328; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1328; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1401 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1401; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1401; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1401; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1254 = _T_1328 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1254 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1254 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1254 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1254 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1254 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1300 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1300 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1269 = _T_1401 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1269 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1269 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1269 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1372 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1372 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1354 = _T_1401 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1354 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1354 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1354 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module MacUnit_35( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_76( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_120 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RouteComputer.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.{TruthTable, decoder} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.DecodeLogic import constellation.channel._ import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo} import constellation.noc.{HasNoCParams} class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams { val src_virt_id = UInt(virtualChannelBits.W) val flow = new FlowRoutingBundle } class RouteComputerResp( val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class RouteComputer( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) }) val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) }) }) (io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) => req.ready := true.B if (outParams.size == 0) { assert(!req.valid) resp.vc_sel := DontCare } else { def toUInt(t: (Int, FlowRoutingInfo)): UInt = { val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) | t._2.vNetId val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) | t._2.ingressNode val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) | t._2.ingressNodeId val l5 = ( l4 << req.bits.flow.egress_node .getWidth) | t._2.egressNode val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) | t._2.egressNodeId l6.U(req.bits.getWidth.W) } val flow = req.bits.flow val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI => allInParams(i).channelRoutingInfos.map { cI => var row: String = "b" (0 until nOutputs).foreach { o => (0 until outParams(o).nVirtualChannels).foreach { outVId => row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0") } } ((cI.vc, pI), row) } }.flatten val addr = req.bits.asUInt val width = outParams.map(_.nVirtualChannels).reduce(_+_) val decoded = if (table.size > 0) { val truthTable = TruthTable( table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) }, BitPat("b" + "?" * width) ) Reverse(decoder(addr, truthTable)) } else { 0.U(width.W) } var idx = 0 (0 until nAllOutputs).foreach { o => if (o < nOutputs) { (0 until outParams(o).nVirtualChannels).foreach { outVId => resp.vc_sel(o)(outVId) := decoded(idx) idx += 1 } } else { resp.vc_sel(o)(0) := false.B } } } } }
module RouteComputer_1( // @[RouteComputer.scala:29:7] input [3:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_8, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_9 // @[RouteComputer.scala:40:14] ); wire [20:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [18:0] _decoded_orMatrixOutputs_T_14 = {&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node_id[2], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node_id[2], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node_id[2], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] assign io_resp_0_vc_sel_0_0 = |{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[2], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_1 = |{&{decoded_invInputs[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_2 = |_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_0_3 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_4 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_5 = |{&{io_req_0_bits_flow_egress_node_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_6 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_7 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_8 = |{&{decoded_invInputs[0], decoded_invInputs[7], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_9 = |{&{decoded_invInputs[0], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[7], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel | (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens | chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) | 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_||_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_||_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }
module SwitchAllocator_8( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_3_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_3_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14] input io_req_3_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_3_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_2_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_3_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_5_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_3_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_3_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_3_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_3_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_3_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_3_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_in_3_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45] wire _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_3_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_3_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_3_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_3_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_0 | io_req_0_0_bits_vc_sel_0_1 | io_req_0_0_bits_vc_sel_0_2 | io_req_0_0_bits_vc_sel_0_3 | io_req_0_0_bits_vc_sel_0_4 | io_req_0_0_bits_vc_sel_0_5); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_0 | io_req_1_0_bits_vc_sel_0_1 | io_req_1_0_bits_vc_sel_0_2 | io_req_1_0_bits_vc_sel_0_3 | io_req_1_0_bits_vc_sel_0_4 | io_req_1_0_bits_vc_sel_0_5); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_3_valid = io_req_3_0_valid & (io_req_3_0_bits_vc_sel_0_0 | io_req_3_0_bits_vc_sel_0_1 | io_req_3_0_bits_vc_sel_0_2 | io_req_3_0_bits_vc_sel_0_3 | io_req_3_0_bits_vc_sel_0_4 | io_req_3_0_bits_vc_sel_0_5); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_3_valid = io_req_3_0_valid & io_req_3_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_3_valid = io_req_3_0_valid & io_req_3_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_3_io_in_3_valid = io_req_3_0_valid & io_req_3_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_3_0_alloc_0 = _arbs_3_io_out_0_valid & _arbs_3_io_out_0_bits_vc_sel_3_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_25 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_0_io_in_0_ready), .io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2), .io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3), .io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4), .io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_3_0 (io_req_1_0_bits_vc_sel_3_0), .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2), .io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_in_3_ready (_arbs_0_io_in_3_ready), .io_in_3_valid (arbs_0_io_in_3_valid), // @[SwitchAllocator.scala:95:37] .io_in_3_bits_vc_sel_3_0 (io_req_3_0_bits_vc_sel_3_0), .io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0), .io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0), .io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1), .io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2), .io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3), .io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4), .io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5), .io_in_3_bits_tail (io_req_3_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1), .io_out_0_bits_vc_sel_0_2 (_arbs_0_io_out_0_bits_vc_sel_0_2), .io_out_0_bits_vc_sel_0_3 (_arbs_0_io_out_0_bits_vc_sel_0_3), .io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4), .io_out_0_bits_vc_sel_0_5 (_arbs_0_io_out_0_bits_vc_sel_0_5), .io_out_0_bits_tail (/* unused */), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_25 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2), .io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3), .io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4), .io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_3_0 (io_req_1_0_bits_vc_sel_3_0), .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2), .io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_in_3_ready (_arbs_1_io_in_3_ready), .io_in_3_valid (arbs_1_io_in_3_valid), // @[SwitchAllocator.scala:95:37] .io_in_3_bits_vc_sel_3_0 (io_req_3_0_bits_vc_sel_3_0), .io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0), .io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0), .io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1), .io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2), .io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3), .io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4), .io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5), .io_in_3_bits_tail (io_req_3_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_1 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_25 arbs_2 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2), .io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3), .io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4), .io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_2_io_in_1_ready), .io_in_1_valid (arbs_2_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_3_0 (io_req_1_0_bits_vc_sel_3_0), .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2), .io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_in_3_ready (_arbs_2_io_in_3_ready), .io_in_3_valid (arbs_2_io_in_3_valid), // @[SwitchAllocator.scala:95:37] .io_in_3_bits_vc_sel_3_0 (io_req_3_0_bits_vc_sel_3_0), .io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0), .io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0), .io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1), .io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2), .io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3), .io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4), .io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5), .io_in_3_bits_tail (io_req_3_0_bits_tail), .io_out_0_valid (_arbs_2_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (/* unused */), .io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_1 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_2_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_25 arbs_3 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_3_io_in_0_ready), .io_in_0_valid (arbs_3_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_3_0 (io_req_0_0_bits_vc_sel_3_0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1), .io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2), .io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3), .io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4), .io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_3_io_in_1_ready), .io_in_1_valid (arbs_3_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_3_0 (io_req_1_0_bits_vc_sel_3_0), .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1), .io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2), .io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3), .io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4), .io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_in_3_ready (_arbs_3_io_in_3_ready), .io_in_3_valid (arbs_3_io_in_3_valid), // @[SwitchAllocator.scala:95:37] .io_in_3_bits_vc_sel_3_0 (io_req_3_0_bits_vc_sel_3_0), .io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0), .io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0), .io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1), .io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2), .io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3), .io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4), .io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5), .io_in_3_bits_tail (io_req_3_0_bits_tail), .io_out_0_valid (_arbs_3_io_out_0_valid), .io_out_0_bits_vc_sel_3_0 (_arbs_3_io_out_0_bits_vc_sel_3_0), .io_out_0_bits_vc_sel_2_0 (/* unused */), .io_out_0_bits_vc_sel_1_0 (/* unused */), .io_out_0_bits_vc_sel_0_1 (/* unused */), .io_out_0_bits_vc_sel_0_2 (/* unused */), .io_out_0_bits_vc_sel_0_3 (/* unused */), .io_out_0_bits_vc_sel_0_4 (/* unused */), .io_out_0_bits_vc_sel_0_5 (/* unused */), .io_out_0_bits_tail (_arbs_3_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_3_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_3_0_ready = _arbs_0_io_in_3_ready & arbs_0_io_in_3_valid | _arbs_1_io_in_3_ready & arbs_1_io_in_3_valid | _arbs_2_io_in_3_ready & arbs_2_io_in_3_valid | _arbs_3_io_in_3_ready & arbs_3_io_in_3_valid; // @[Decoupled.scala:51:35] assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid | _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid | _arbs_2_io_in_1_ready & arbs_2_io_in_1_valid | _arbs_3_io_in_1_ready & arbs_3_io_in_1_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid | _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid | _arbs_3_io_in_0_ready & arbs_3_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_3_0_alloc = io_credit_alloc_3_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_3_0_tail = io_credit_alloc_3_0_alloc_0 & _arbs_3_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_2_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_3_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_5_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_3_0_3_0 = arbs_3_io_in_3_valid & _arbs_3_io_chosen_oh_0[3] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_1_0 = arbs_3_io_in_1_valid & _arbs_3_io_chosen_oh_0[1] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_3_0_0_0 = arbs_3_io_in_0_valid & _arbs_3_io_chosen_oh_0[0] & _arbs_3_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_3_0 = arbs_2_io_in_3_valid & _arbs_2_io_chosen_oh_0[3] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_1_0 = arbs_2_io_in_1_valid & _arbs_2_io_chosen_oh_0[1] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_3_0 = arbs_1_io_in_3_valid & _arbs_1_io_chosen_oh_0[3] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_3_0 = arbs_0_io_in_3_valid & _arbs_0_io_chosen_oh_0[3] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }
module IssueSlot_39( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] next_uop_ppred = 5'h0; // @[issue-slot.scala:103:21] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire next_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_prs3_busy = 1'h0; // @[issue-slot.scala:103:21] wire next_uop_ppred_busy = 1'h0; // @[issue-slot.scala:103:21] wire _p3_T = 1'h1; // @[issue-slot.scala:171:11] wire _ppred_T = 1'h1; // @[issue-slot.scala:172:14] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = ~io_in_uop_valid_0 & p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = ~io_in_uop_valid_0 & p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :99:29, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File OutputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class OutputCreditAlloc extends Bundle { val alloc = Bool() val tail = Bool() } class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams { val occupied = Bool() def available = !occupied val flow = new FlowRoutingBundle } class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams { val alloc = Bool() val flow = new FlowRoutingBundle } class AbstractOutputUnitIO( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Bundle with HasRouterInputParams { val nodeId = cParam.srcId val nVirtualChannels = cParam.nVirtualChannels val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val credit_available = Output(Vec(nVirtualChannels, Bool())) val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus)) val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc)) val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc)) } abstract class AbstractOutputUnit( val inParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val cParam: BaseChannelParams )(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams { val nodeId = cParam.srcId def io: AbstractOutputUnitIO } class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = new Channel(cParam.asInstanceOf[ChannelParams]) } val io = IO(new OutputUnitIO) class OutputState(val bufferSize: Int) extends Bundle { val occupied = Bool() val c = UInt(log2Up(1+bufferSize).W) val flow = new FlowRoutingBundle } val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) })) (states zip io.channel_status).map { case (s,a) => a.occupied := s.occupied a.flow := s.flow } io.out.flit := io.in states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) { when (io.out.vc_free(i)) { assert(s.occupied) s.occupied := false.B } } } (states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) { when (a.alloc) { s.occupied := true.B s.flow := a.flow } } } (io.credit_available zip states).zipWithIndex.map { case ((c,s),i) => c := s.c =/= 0.U //|| (io.out.credit_return.valid && io.out.credit_return.bits === i.U) } states.zipWithIndex.map { case (s,i) => val free = io.out.credit_return(i) val alloc = io.credit_alloc(i).alloc if (cParam.virtualChannelParams(i).traversable) { s.c := s.c +& free - alloc } } when (reset.asBool) { states.foreach(_.occupied := false.B) states.foreach(s => s.c := s.bufferSize.U) } }
module OutputUnit_8( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [72:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_1, // @[OutputUnit.scala:58:14] output io_credit_available_2, // @[OutputUnit.scala:58:14] output io_credit_available_3, // @[OutputUnit.scala:58:14] output io_credit_available_4, // @[OutputUnit.scala:58:14] output io_credit_available_5, // @[OutputUnit.scala:58:14] output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_3_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_4_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_5_occupied, // @[OutputUnit.scala:58:14] input io_allocs_1_alloc, // @[OutputUnit.scala:58:14] input io_allocs_2_alloc, // @[OutputUnit.scala:58:14] input io_allocs_3_alloc, // @[OutputUnit.scala:58:14] input io_allocs_4_alloc, // @[OutputUnit.scala:58:14] input io_allocs_5_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_3_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_4_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_5_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [72:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [5:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [5:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_5_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_5_c; // @[OutputUnit.scala:66:19] reg states_4_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_4_c; // @[OutputUnit.scala:66:19] reg states_3_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_3_c; // @[OutputUnit.scala:66:19] reg states_2_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_2_c; // @[OutputUnit.scala:66:19] reg states_1_occupied; // @[OutputUnit.scala:66:19] reg [2:0] states_1_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_364( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_108 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_18( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_90( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46] wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46] wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_37( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLAToNoC_12( // @[TilelinkAdapters.scala:112:7] input clock, // @[TilelinkAdapters.scala:112:7] input reset, // @[TilelinkAdapters.scala:112:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [5:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}] wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}] wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}] wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31] wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31] wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31] wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31] assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}] wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7] if (reset) begin // @[TilelinkAdapters.scala:112:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7] end else begin // @[TilelinkAdapters.scala:112:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_4( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1326 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1326; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1326; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1394 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1394; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1394; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1394; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1259 = _T_1326 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1259 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1259 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1259 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1259 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1259 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1305 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1305 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1274 = _T_1394 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1274 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1274 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1274 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1370 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1370 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1352 = _T_1394 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1352 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1352 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1352 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module IntSyncSyncCrossingSink_n0x0_3(); // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w4_d3_i0_19( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_186 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_187 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_188 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_189 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_130( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_2_9, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_8, // @[InputUnit.scala:170:14] input io_out_credit_available_1_9, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_9; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_9; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, 8'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to the following Chisel files. File ResetCatchAndSync.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.{withClockAndReset, withReset} /** Reset: asynchronous assert, * synchronous de-assert * */ class ResetCatchAndSync (sync: Int = 3) extends Module { override def desiredName = s"ResetCatchAndSync_d${sync}" val io = IO(new Bundle { val sync_reset = Output(Bool()) val psd = Input(new PSDTestMode()) }) // Bypass both the resets to the flops themselves (to prevent DFT holes on // those flops) and on the output of the synchronizer circuit (to control // reset to any flops this circuit drives). val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool) withReset(post_psd_reset) { io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset, ~AsyncResetSynchronizerShiftReg(true.B, sync)) } } object ResetCatchAndSync { def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None, psd: Option[PSDTestMode] = None): Bool = { withClockAndReset(clk, rst) { val catcher = Module (new ResetCatchAndSync(sync)) if (name.isDefined) {catcher.suggestName(name.get)} catcher.io.psd <> psd.getOrElse(WireDefault(0.U.asTypeOf(new PSDTestMode()))) catcher.io.sync_reset } } def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name)) def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name)) def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool = apply(clk, rst, sync, Some(name), Some(psd)) def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool = apply(clk, rst, name = Some(name), psd = Some(psd)) } File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) }
module ResetCatchAndSync_d3_4( // @[ResetCatchAndSync.scala:13:7] input clock, // @[ResetCatchAndSync.scala:13:7] input reset, // @[ResetCatchAndSync.scala:13:7] output io_sync_reset // @[ResetCatchAndSync.scala:17:14] ); wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76] wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25] wire io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}] wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7] assign io_sync_reset_0 = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25] AsyncResetSynchronizerShiftReg_w1_d3_i0_205 io_sync_reset_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27] .io_q (_io_sync_reset_WIRE) ); // @[ShiftReg.scala:45:23] assign io_sync_reset = io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v3.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util._ import FUConstants._ /** * IO bundle to interact with Issue slot * * @param numWakeupPorts number of wakeup ports for the slot */ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val request_hp = Output(Bool()) val grant = Input(Bool()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted. val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz)))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W)))) val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue. val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued. val debug = { val result = new Bundle { val p1 = Bool() val p2 = Bool() val p3 = Bool() val ppred = Bool() val state = UInt(width=2.W) } Output(result) } } /** * Single issue slot. Holds a uop within the issue queue * * @param numWakeupPorts number of wakeup ports */ class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomModule with IssueUnitConstants { val io = IO(new IssueSlotIO(numWakeupPorts)) // slot invalid? // slot is valid, holding 1 uop // slot is valid, holds 2 uops (like a store) def is_invalid = state === s_invalid def is_valid = state =/= s_invalid val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot) val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot) val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot) val state = RegInit(s_invalid) val p1 = RegInit(false.B) val p2 = RegInit(false.B) val p3 = RegInit(false.B) val ppred = RegInit(false.B) // Poison if woken up by speculative load. // Poison lasts 1 cycle (as ldMiss will come on the next cycle). // SO if poisoned is true, set it to false! val p1_poisoned = RegInit(false.B) val p2_poisoned = RegInit(false.B) p1_poisoned := false.B p2_poisoned := false.B val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) val slot_uop = RegInit(NullMicroOp) val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop) //----------------------------------------------------------------------------- // next slot state computation // compute the next state for THIS entry slot (in a collasping queue, the // current uop may get moved elsewhere, and a new uop can enter when (io.kill) { state := s_invalid } .elsewhen (io.in_uop.valid) { state := io.in_uop.bits.iw_state } .elsewhen (io.clear) { state := s_invalid } .otherwise { state := next_state } //----------------------------------------------------------------------------- // "update" state // compute the next state for the micro-op in this slot. This micro-op may // be moved elsewhere, so the "next_state" travels with it. // defaults next_state := state next_uopc := slot_uop.uopc next_lrs1_rtype := slot_uop.lrs1_rtype next_lrs2_rtype := slot_uop.lrs2_rtype when (io.kill) { next_state := s_invalid } .elsewhen ((io.grant && (state === s_valid_1)) || (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) { // try to issue this uop. when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_invalid } } .elsewhen (io.grant && (state === s_valid_2)) { when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) { next_state := s_valid_1 when (p1) { slot_uop.uopc := uopSTD next_uopc := uopSTD slot_uop.lrs1_rtype := RT_X next_lrs1_rtype := RT_X } .otherwise { slot_uop.lrs2_rtype := RT_X next_lrs2_rtype := RT_X } } } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.") } // Wakeup Compare Logic // these signals are the "next_p*" for the current slot's micro-op. // they are important for shifting the current slot_uop up to an other entry. val next_p1 = WireInit(p1) val next_p2 = WireInit(p2) val next_p3 = WireInit(p3) val next_ppred = WireInit(ppred) when (io.in_uop.valid) { p1 := !(io.in_uop.bits.prs1_busy) p2 := !(io.in_uop.bits.prs2_busy) p3 := !(io.in_uop.bits.prs3_busy) ppred := !(io.in_uop.bits.ppred_busy) } when (io.ldspec_miss && next_p1_poisoned) { assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!") p1 := false.B } when (io.ldspec_miss && next_p2_poisoned) { assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!") p2 := false.B } for (i <- 0 until numWakeupPorts) { when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) { p1 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) { p2 := true.B } when (io.wakeup_ports(i).valid && (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) { p3 := true.B } } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) { ppred := true.B } for (w <- 0 until memWidth) { assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U), "Loads to x0 should never speculatively wakeup other instructions") } // TODO disable if FP IQ. for (w <- 0 until memWidth) { when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs1 && next_uop.lrs1_rtype === RT_FIX) { p1 := true.B p1_poisoned := true.B assert (!next_p1_poisoned) } when (io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === next_uop.prs2 && next_uop.lrs2_rtype === RT_FIX) { p2 := true.B p2_poisoned := true.B assert (!next_p2_poisoned) } } // Handle branch misspeculations val next_br_mask = GetNewBrMask(io.brupdate, slot_uop) // was this micro-op killed by a branch? if yes, we can't let it be valid if // we compact it into an other entry when (IsKilledByBranch(io.brupdate, slot_uop)) { next_state := s_invalid } when (!io.in_uop.valid) { slot_uop.br_mask := next_br_mask } //------------------------------------------------------------- // Request Logic io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr io.request_hp := io.request && high_priority when (state === s_valid_1) { io.request := p1 && p2 && p3 && ppred && !io.kill } .elsewhen (state === s_valid_2) { io.request := (p1 || p2) && ppred && !io.kill } .otherwise { io.request := false.B } //assign outputs io.valid := is_valid io.uop := slot_uop io.uop.iw_p1_poisoned := p1_poisoned io.uop.iw_p2_poisoned := p2_poisoned // micro-op will vacate due to grant. val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred) val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned) io.will_be_valid := is_valid && !(may_vacate && !squash_grant) io.out_uop := slot_uop io.out_uop.iw_state := next_state io.out_uop.uopc := next_uopc io.out_uop.lrs1_rtype := next_lrs1_rtype io.out_uop.lrs2_rtype := next_lrs2_rtype io.out_uop.br_mask := next_br_mask io.out_uop.prs1_busy := !p1 io.out_uop.prs2_busy := !p2 io.out_uop.prs3_busy := !p3 io.out_uop.ppred_busy := !ppred io.out_uop.iw_p1_poisoned := p1_poisoned io.out_uop.iw_p2_poisoned := p2_poisoned when (state === s_valid_2) { when (p1 && p2 && ppred) { ; // send out the entire instruction as one uop } .elsewhen (p1 && ppred) { io.uop.uopc := slot_uop.uopc io.uop.lrs2_rtype := RT_X } .elsewhen (p2 && ppred) { io.uop.uopc := uopSTD io.uop.lrs1_rtype := RT_X } } // debug outputs io.debug.p1 := p1 io.debug.p2 := p2 io.debug.p3 := p3 io.debug.ppred := ppred io.debug.state := state }
module IssueSlot_34( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File core.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISC-V Processor Core //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // BOOM has the following (conceptual) stages: // if0 - Instruction Fetch 0 (next-pc select) // if1 - Instruction Fetch 1 (I$ access) // if2 - Instruction Fetch 2 (instruction return) // if3 - Instruction Fetch 3 (enqueue to fetch buffer) // if4 - Instruction Fetch 4 (redirect from bpd) // dec - Decode // ren - Rename1 // dis - Rename2/Dispatch // iss - Issue // rrd - Register Read // exe - Execute // mem - Memory // sxt - Sign-extend // wb - Writeback // com - Commit package boom.v3.exu import java.nio.file.{Paths} import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.tile.{TraceBundle} import freechips.rocketchip.rocket.{Causes, PRV, TracedInstruction} import freechips.rocketchip.util.{Str, UIntIsOneOf, CoreMonitorBundle} import freechips.rocketchip.devices.tilelink.{PLICConsts, CLINTConsts} import boom.v3.common._ import boom.v3.ifu.{GlobalHistory, HasBoomFrontendParameters} import boom.v3.exu.FUConstants._ import boom.v3.util._ /** * Top level core object that connects the Frontend to the rest of the pipeline. */ class BoomCore()(implicit p: Parameters) extends BoomModule with HasBoomFrontendParameters // TODO: Don't add this trait { val io = IO(new Bundle { val hartid = Input(UInt(hartIdLen.W)) val interrupts = Input(new freechips.rocketchip.rocket.CoreInterrupts(false)) val ifu = new boom.v3.ifu.BoomFrontendIO val ptw = Flipped(new freechips.rocketchip.rocket.DatapathPTWIO()) val rocc = Flipped(new freechips.rocketchip.tile.RoCCCoreIO()) val lsu = Flipped(new boom.v3.lsu.LSUCoreIO) val ptw_tlb = new freechips.rocketchip.rocket.TLBPTWIO() val trace = Output(new TraceBundle) val fcsr_rm = UInt(freechips.rocketchip.tile.FPConstants.RM_SZ.W) }) io.ptw_tlb := DontCare io.ptw := DontCare io.ifu := DontCare //********************************** // construct all of the modules // Only holds integer-registerfile execution units. val exe_units = new boom.v3.exu.ExecutionUnits(fpu=false) val jmp_unit_idx = exe_units.jmp_unit_idx val jmp_unit = exe_units(jmp_unit_idx) // Meanwhile, the FP pipeline holds the FP issue window, FP regfile, and FP arithmetic units. var fp_pipeline: FpPipeline = null if (usingFPU) fp_pipeline = Module(new FpPipeline) // ******************************************************** // Clear fp_pipeline before use if (usingFPU) { fp_pipeline.io.ll_wports := DontCare fp_pipeline.io.wb_valids := DontCare fp_pipeline.io.wb_pdsts := DontCare } val numIrfWritePorts = exe_units.numIrfWritePorts + memWidth val numLlIrfWritePorts = exe_units.numLlIrfWritePorts val numIrfReadPorts = exe_units.numIrfReadPorts val numFastWakeupPorts = exe_units.count(_.bypassable) val numAlwaysBypassable = exe_units.count(_.alwaysBypassable) val numIntIssueWakeupPorts = numIrfWritePorts + numFastWakeupPorts - numAlwaysBypassable // + memWidth for ll_wb val numIntRenameWakeupPorts = numIntIssueWakeupPorts val numFpWakeupPorts = if (usingFPU) fp_pipeline.io.wakeups.length else 0 val decode_units = for (w <- 0 until decodeWidth) yield { val d = Module(new DecodeUnit); d } val dec_brmask_logic = Module(new BranchMaskGenerationLogic(coreWidth)) val rename_stage = Module(new RenameStage(coreWidth, numIntPhysRegs, numIntRenameWakeupPorts, false)) val fp_rename_stage = if (usingFPU) Module(new RenameStage(coreWidth, numFpPhysRegs, numFpWakeupPorts, true)) else null val pred_rename_stage = Module(new PredRenameStage(coreWidth, ftqSz, 1)) val rename_stages = if (usingFPU) Seq(rename_stage, fp_rename_stage, pred_rename_stage) else Seq(rename_stage, pred_rename_stage) val mem_iss_unit = Module(new IssueUnitCollapsing(memIssueParam, numIntIssueWakeupPorts)) mem_iss_unit.suggestName("mem_issue_unit") val int_iss_unit = Module(new IssueUnitCollapsing(intIssueParam, numIntIssueWakeupPorts)) int_iss_unit.suggestName("int_issue_unit") val issue_units = Seq(mem_iss_unit, int_iss_unit) val dispatcher = Module(new BasicDispatcher) val iregfile = Module(new RegisterFileSynthesizable( numIntPhysRegs, numIrfReadPorts, numIrfWritePorts, xLen, Seq.fill(memWidth) {true} ++ exe_units.bypassable_write_port_mask)) // bypassable ll_wb val pregfile = Module(new RegisterFileSynthesizable( ftqSz, exe_units.numIrfReaders, 1, 1, Seq(true))) // The jmp unit is always bypassable pregfile.io := DontCare // Only use the IO if enableSFBOpt // wb arbiter for the 0th ll writeback // TODO: should this be a multi-arb? val ll_wbarb = Module(new Arbiter(new ExeUnitResp(xLen), 1 + (if (usingFPU) 1 else 0) + (if (usingRoCC) 1 else 0))) val iregister_read = Module(new RegisterRead( issue_units.map(_.issueWidth).sum, exe_units.withFilter(_.readsIrf).map(_.supportedFuncUnits).toSeq, numIrfReadPorts, exe_units.withFilter(_.readsIrf).map(x => 2).toSeq, exe_units.numTotalBypassPorts, jmp_unit.numBypassStages, xLen)) val rob = Module(new Rob( numIrfWritePorts + numFpWakeupPorts, // +memWidth for ll writebacks numFpWakeupPorts)) // Used to wakeup registers in rename and issue. ROB needs to listen to something else. val int_iss_wakeups = Wire(Vec(numIntIssueWakeupPorts, Valid(new ExeUnitResp(xLen)))) val int_ren_wakeups = Wire(Vec(numIntRenameWakeupPorts, Valid(new ExeUnitResp(xLen)))) val pred_wakeup = Wire(Valid(new ExeUnitResp(1))) require (exe_units.length == issue_units.map(_.issueWidth).sum) //*********************************** // Pipeline State Registers and Wires // Decode/Rename1 Stage val dec_valids = Wire(Vec(coreWidth, Bool())) // are the decoded instruction valid? It may be held up though. val dec_uops = Wire(Vec(coreWidth, new MicroOp())) val dec_fire = Wire(Vec(coreWidth, Bool())) // can the instruction fire beyond decode? // (can still be stopped in ren or dis) val dec_ready = Wire(Bool()) val dec_xcpts = Wire(Vec(coreWidth, Bool())) val ren_stalls = Wire(Vec(coreWidth, Bool())) // Rename2/Dispatch stage val dis_valids = Wire(Vec(coreWidth, Bool())) val dis_uops = Wire(Vec(coreWidth, new MicroOp)) val dis_fire = Wire(Vec(coreWidth, Bool())) val dis_ready = Wire(Bool()) // Issue Stage/Register Read val iss_valids = Wire(Vec(exe_units.numIrfReaders, Bool())) val iss_uops = Wire(Vec(exe_units.numIrfReaders, new MicroOp())) val bypasses = Wire(Vec(exe_units.numTotalBypassPorts, Valid(new ExeUnitResp(xLen)))) val pred_bypasses = Wire(Vec(jmp_unit.numBypassStages, Valid(new ExeUnitResp(1)))) require(jmp_unit.bypassable) // -------------------------------------- // Dealing with branch resolutions // The individual branch resolutions from each ALU val brinfos = Reg(Vec(coreWidth, new BrResolutionInfo())) // "Merged" branch update info from all ALUs // brmask contains masks for rapidly clearing mispredicted instructions // brindices contains indices to reset pointers for allocated structures // brindices is delayed a cycle val brupdate = Wire(new BrUpdateInfo) val b1 = Wire(new BrUpdateMasks) val b2 = Reg(new BrResolutionInfo) brupdate.b1 := b1 brupdate.b2 := b2 for ((b, a) <- brinfos zip exe_units.alu_units) { b := a.io.brinfo b.valid := a.io.brinfo.valid && !rob.io.flush.valid } b1.resolve_mask := brinfos.map(x => x.valid << x.uop.br_tag).reduce(_|_) b1.mispredict_mask := brinfos.map(x => (x.valid && x.mispredict) << x.uop.br_tag).reduce(_|_) // Find the oldest mispredict and use it to update indices var mispredict_val = false.B var oldest_mispredict = brinfos(0) for (b <- brinfos) { val use_this_mispredict = !mispredict_val || b.valid && b.mispredict && IsOlder(b.uop.rob_idx, oldest_mispredict.uop.rob_idx, rob.io.rob_head_idx) mispredict_val = mispredict_val || (b.valid && b.mispredict) oldest_mispredict = Mux(use_this_mispredict, b, oldest_mispredict) } b2.mispredict := mispredict_val b2.cfi_type := oldest_mispredict.cfi_type b2.taken := oldest_mispredict.taken b2.pc_sel := oldest_mispredict.pc_sel b2.uop := UpdateBrMask(brupdate, oldest_mispredict.uop) b2.jalr_target := RegNext(jmp_unit.io.brinfo.jalr_target) b2.target_offset := oldest_mispredict.target_offset val oldest_mispredict_ftq_idx = oldest_mispredict.uop.ftq_idx assert (!((brupdate.b1.mispredict_mask =/= 0.U || brupdate.b2.mispredict) && rob.io.commit.rollback), "Can't have a mispredict during rollback.") io.ifu.brupdate := brupdate for (eu <- exe_units) { eu.io.brupdate := brupdate } if (usingFPU) { fp_pipeline.io.brupdate := brupdate } // Load/Store Unit & ExeUnits val mem_units = exe_units.memory_units val mem_resps = mem_units.map(_.io.ll_iresp) for (i <- 0 until memWidth) { mem_units(i).io.lsu_io <> io.lsu.exe(i) } //------------------------------------------------------------- // Uarch Hardware Performance Events (HPEs) val perfEvents = new freechips.rocketchip.rocket.EventSets(Seq( new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq( ("exception", () => rob.io.com_xcpt.valid), ("nop", () => false.B), ("nop", () => false.B), ("nop", () => false.B))), new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq( // ("I$ blocked", () => icache_blocked), ("nop", () => false.B), ("branch misprediction", () => b2.mispredict), ("control-flow target misprediction", () => b2.mispredict && b2.cfi_type === CFI_JALR), ("flush", () => rob.io.flush.valid), ("branch resolved", () => b2.valid) )), new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.ifu.perf.acquire), ("D$ miss", () => io.lsu.perf.acquire), ("D$ release", () => io.lsu.perf.release), ("ITLB miss", () => io.ifu.perf.tlbMiss), ("DTLB miss", () => io.lsu.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val csr = Module(new freechips.rocketchip.rocket.CSRFile(perfEvents, boomParams.customCSRs.decls)) csr.io.inst foreach { c => c := DontCare } csr.io.rocc_interrupt := io.rocc.interrupt csr.io.mhtinst_read_pseudo := false.B val custom_csrs = Wire(new BoomCustomCSRs) custom_csrs.csrs.foreach { c => c.stall := false.B; c.set := false.B; c.sdata := DontCare } (custom_csrs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } //val icache_blocked = !(io.ifu.fetchpacket.valid || RegNext(io.ifu.fetchpacket.valid)) val icache_blocked = false.B csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } //**************************************** // Time Stamp Counter & Retired Instruction Counter // (only used for printf and vcd dumps - the actual counters are in the CSRFile) val debug_tsc_reg = RegInit(0.U(xLen.W)) val debug_irt_reg = RegInit(0.U(xLen.W)) val debug_brs = Reg(Vec(4, UInt(xLen.W))) val debug_jals = Reg(Vec(4, UInt(xLen.W))) val debug_jalrs = Reg(Vec(4, UInt(xLen.W))) for (j <- 0 until 4) { debug_brs(j) := debug_brs(j) + PopCount(VecInit((0 until coreWidth) map {i => rob.io.commit.arch_valids(i) && (rob.io.commit.uops(i).debug_fsrc === j.U) && rob.io.commit.uops(i).is_br })) debug_jals(j) := debug_jals(j) + PopCount(VecInit((0 until coreWidth) map {i => rob.io.commit.arch_valids(i) && (rob.io.commit.uops(i).debug_fsrc === j.U) && rob.io.commit.uops(i).is_jal })) debug_jalrs(j) := debug_jalrs(j) + PopCount(VecInit((0 until coreWidth) map {i => rob.io.commit.arch_valids(i) && (rob.io.commit.uops(i).debug_fsrc === j.U) && rob.io.commit.uops(i).is_jalr })) } dontTouch(debug_brs) dontTouch(debug_jals) dontTouch(debug_jalrs) debug_tsc_reg := debug_tsc_reg + 1.U debug_irt_reg := debug_irt_reg + PopCount(rob.io.commit.arch_valids.asUInt) dontTouch(debug_tsc_reg) dontTouch(debug_irt_reg) //**************************************** // Print-out information about the machine val issStr = if (enableAgePriorityIssue) " (Age-based Priority)" else " (Unordered Priority)" // val btbStr = // if (enableBTB) ("" + boomParams.btb.nSets * boomParams.btb.nWays + " entries (" + boomParams.btb.nSets + " x " + boomParams.btb.nWays + " ways)") // else 0 val btbStr = "" val fpPipelineStr = if (usingFPU) fp_pipeline.toString else "" override def toString: String = (BoomCoreStringPrefix("====Overall Core Params====") + "\n" + exe_units.toString + "\n" + fpPipelineStr + "\n" + rob.toString + "\n" + BoomCoreStringPrefix( "===Other Core Params===", "Fetch Width : " + fetchWidth, "Decode Width : " + coreWidth, "Issue Width : " + issueParams.map(_.issueWidth).sum, "ROB Size : " + numRobEntries, "Issue Window Size : " + issueParams.map(_.numEntries) + issStr, "Load/Store Unit Size : " + numLdqEntries + "/" + numStqEntries, "Num Int Phys Registers: " + numIntPhysRegs, "Num FP Phys Registers: " + numFpPhysRegs, "Max Branch Count : " + maxBrCount) + iregfile.toString + "\n" + BoomCoreStringPrefix( "Num Slow Wakeup Ports : " + numIrfWritePorts, "Num Fast Wakeup Ports : " + exe_units.count(_.bypassable), "Num Bypass Ports : " + exe_units.numTotalBypassPorts) + "\n" + BoomCoreStringPrefix( "DCache Ways : " + dcacheParams.nWays, "DCache Sets : " + dcacheParams.nSets, "DCache nMSHRs : " + dcacheParams.nMSHRs, "ICache Ways : " + icacheParams.nWays, "ICache Sets : " + icacheParams.nSets, "D-TLB Ways : " + dcacheParams.nTLBWays, "I-TLB Ways : " + icacheParams.nTLBWays, "Paddr Bits : " + paddrBits, "Vaddr Bits : " + vaddrBits) + "\n" + BoomCoreStringPrefix( "Using FPU Unit? : " + usingFPU.toString, "Using FDivSqrt? : " + usingFDivSqrt.toString, "Using VM? : " + usingVM.toString) + "\n") //------------------------------------------------------------- //------------------------------------------------------------- // **** Fetch Stage/Frontend **** //------------------------------------------------------------- //------------------------------------------------------------- io.ifu.redirect_val := false.B io.ifu.redirect_flush := false.B // Breakpoint info io.ifu.status := csr.io.status io.ifu.bp := csr.io.bp io.ifu.mcontext := csr.io.mcontext io.ifu.scontext := csr.io.scontext io.ifu.flush_icache := (0 until coreWidth).map { i => (rob.io.commit.arch_valids(i) && rob.io.commit.uops(i).is_fencei) || (RegNext(dec_valids(i) && dec_uops(i).is_jalr && csr.io.status.debug)) }.reduce(_||_) // TODO FIX THIS HACK // The below code works because of two quirks with the flush mechanism // 1 ) All flush_on_commit instructions are also is_unique, // In the future, this constraint will be relaxed. // 2 ) We send out flush signals one cycle after the commit signal. We need to // mux between one/two cycle delay for the following cases: // ERETs are reported to the CSR two cycles before we send the flush // Exceptions are reported to the CSR on the cycle we send the flush // This discrepency should be resolved elsewhere. when (RegNext(rob.io.flush.valid)) { io.ifu.redirect_val := true.B io.ifu.redirect_flush := true.B val flush_typ = RegNext(rob.io.flush.bits.flush_typ) // Clear the global history when we flush the ROB (exceptions, AMOs, unique instructions, etc.) val new_ghist = WireInit((0.U).asTypeOf(new GlobalHistory)) new_ghist.current_saw_branch_not_taken := true.B new_ghist.ras_idx := io.ifu.get_pc(0).entry.ras_idx io.ifu.redirect_ghist := new_ghist when (FlushTypes.useCsrEvec(flush_typ)) { io.ifu.redirect_pc := Mux(flush_typ === FlushTypes.eret, RegNext(RegNext(csr.io.evec)), csr.io.evec) } .otherwise { val flush_pc = (AlignPCToBoundary(io.ifu.get_pc(0).pc, icBlockBytes) + RegNext(rob.io.flush.bits.pc_lob) - Mux(RegNext(rob.io.flush.bits.edge_inst), 2.U, 0.U)) val flush_pc_next = flush_pc + Mux(RegNext(rob.io.flush.bits.is_rvc), 2.U, 4.U) io.ifu.redirect_pc := Mux(FlushTypes.useSamePC(flush_typ), flush_pc, flush_pc_next) } io.ifu.redirect_ftq_idx := RegNext(rob.io.flush.bits.ftq_idx) } .elsewhen (brupdate.b2.mispredict && !RegNext(rob.io.flush.valid)) { val block_pc = AlignPCToBoundary(io.ifu.get_pc(1).pc, icBlockBytes) val uop_maybe_pc = block_pc | brupdate.b2.uop.pc_lob val npc = uop_maybe_pc + Mux(brupdate.b2.uop.is_rvc || brupdate.b2.uop.edge_inst, 2.U, 4.U) val jal_br_target = Wire(UInt(vaddrBitsExtended.W)) jal_br_target := (uop_maybe_pc.asSInt + brupdate.b2.target_offset + (Fill(vaddrBitsExtended-1, brupdate.b2.uop.edge_inst) << 1).asSInt).asUInt val bj_addr = Mux(brupdate.b2.cfi_type === CFI_JALR, brupdate.b2.jalr_target, jal_br_target) val mispredict_target = Mux(brupdate.b2.pc_sel === PC_PLUS4, npc, bj_addr) io.ifu.redirect_val := true.B io.ifu.redirect_pc := mispredict_target io.ifu.redirect_flush := true.B io.ifu.redirect_ftq_idx := brupdate.b2.uop.ftq_idx val use_same_ghist = (brupdate.b2.cfi_type === CFI_BR && !brupdate.b2.taken && bankAlign(block_pc) === bankAlign(npc)) val ftq_entry = io.ifu.get_pc(1).entry val cfi_idx = (brupdate.b2.uop.pc_lob ^ Mux(ftq_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1) val ftq_ghist = io.ifu.get_pc(1).ghist val next_ghist = ftq_ghist.update( ftq_entry.br_mask.asUInt, brupdate.b2.taken, brupdate.b2.cfi_type === CFI_BR, cfi_idx, true.B, io.ifu.get_pc(1).pc, ftq_entry.cfi_is_call && ftq_entry.cfi_idx.bits === cfi_idx, ftq_entry.cfi_is_ret && ftq_entry.cfi_idx.bits === cfi_idx) io.ifu.redirect_ghist := Mux( use_same_ghist, ftq_ghist, next_ghist) io.ifu.redirect_ghist.current_saw_branch_not_taken := use_same_ghist } .elsewhen (rob.io.flush_frontend || brupdate.b1.mispredict_mask =/= 0.U) { io.ifu.redirect_flush := true.B } // Tell the FTQ it can deallocate entries by passing youngest ftq_idx. val youngest_com_idx = (coreWidth-1).U - PriorityEncoder(rob.io.commit.valids.reverse) io.ifu.commit.valid := rob.io.commit.valids.reduce(_|_) || rob.io.com_xcpt.valid io.ifu.commit.bits := Mux(rob.io.com_xcpt.valid, rob.io.com_xcpt.bits.ftq_idx, rob.io.commit.uops(youngest_com_idx).ftq_idx) assert(!(rob.io.commit.valids.reduce(_|_) && rob.io.com_xcpt.valid), "ROB can't commit and except in same cycle!") for (i <- 0 until memWidth) { when (RegNext(io.lsu.exe(i).req.bits.sfence.valid)) { io.ifu.sfence := RegNext(io.lsu.exe(i).req.bits.sfence) } } //------------------------------------------------------------- //------------------------------------------------------------- // **** Branch Prediction **** //------------------------------------------------------------- //------------------------------------------------------------- //------------------------------------------------------------- //------------------------------------------------------------- // **** Decode Stage **** //------------------------------------------------------------- //------------------------------------------------------------- // track mask of finished instructions in the bundle // use this to mask out insts coming from FetchBuffer that have been finished // for example, back pressure may cause us to only issue some instructions from FetchBuffer // but on the next cycle, we only want to retry a subset val dec_finished_mask = RegInit(0.U(coreWidth.W)) //------------------------------------------------------------- // Pull out instructions and send to the Decoders io.ifu.fetchpacket.ready := dec_ready val dec_fbundle = io.ifu.fetchpacket.bits //------------------------------------------------------------- // Decoders for (w <- 0 until coreWidth) { dec_valids(w) := io.ifu.fetchpacket.valid && dec_fbundle.uops(w).valid && !dec_finished_mask(w) decode_units(w).io.enq.uop := dec_fbundle.uops(w).bits decode_units(w).io.status := csr.io.status decode_units(w).io.csr_decode <> csr.io.decode(w) decode_units(w).io.interrupt := csr.io.interrupt decode_units(w).io.interrupt_cause := csr.io.interrupt_cause dec_uops(w) := decode_units(w).io.deq.uop } //------------------------------------------------------------- // FTQ GetPC Port Arbitration val jmp_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W))) val xcpt_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W))) val flush_pc_req = Wire(Decoupled(UInt(log2Ceil(ftqSz).W))) val ftq_arb = Module(new Arbiter(UInt(log2Ceil(ftqSz).W), 3)) // Order by the oldest. Flushes come from the oldest instructions in pipe // Decoding exceptions come from youngest ftq_arb.io.in(0) <> flush_pc_req ftq_arb.io.in(1) <> jmp_pc_req ftq_arb.io.in(2) <> xcpt_pc_req // Hookup FTQ io.ifu.get_pc(0).ftq_idx := ftq_arb.io.out.bits ftq_arb.io.out.ready := true.B // Branch Unit Requests (for JALs) (Should delay issue of JALs if this not ready) jmp_pc_req.valid := RegNext(iss_valids(jmp_unit_idx) && iss_uops(jmp_unit_idx).fu_code === FU_JMP) jmp_pc_req.bits := RegNext(iss_uops(jmp_unit_idx).ftq_idx) jmp_unit.io.get_ftq_pc := DontCare jmp_unit.io.get_ftq_pc.pc := io.ifu.get_pc(0).pc jmp_unit.io.get_ftq_pc.entry := io.ifu.get_pc(0).entry jmp_unit.io.get_ftq_pc.next_val := io.ifu.get_pc(0).next_val jmp_unit.io.get_ftq_pc.next_pc := io.ifu.get_pc(0).next_pc // Frontend Exception Requests val xcpt_idx = PriorityEncoder(dec_xcpts) xcpt_pc_req.valid := dec_xcpts.reduce(_||_) xcpt_pc_req.bits := dec_uops(xcpt_idx).ftq_idx //rob.io.xcpt_fetch_pc := RegEnable(io.ifu.get_pc.fetch_pc, dis_ready) rob.io.xcpt_fetch_pc := io.ifu.get_pc(0).pc flush_pc_req.valid := rob.io.flush.valid flush_pc_req.bits := rob.io.flush.bits.ftq_idx // Mispredict requests (to get the correct target) io.ifu.get_pc(1).ftq_idx := oldest_mispredict_ftq_idx //------------------------------------------------------------- // Decode/Rename1 pipeline logic dec_xcpts := dec_uops zip dec_valids map {case (u,v) => u.exception && v} val dec_xcpt_stall = dec_xcpts.reduce(_||_) && !xcpt_pc_req.ready // stall fetch/dcode because we ran out of branch tags val branch_mask_full = Wire(Vec(coreWidth, Bool())) val dec_hazards = (0 until coreWidth).map(w => dec_valids(w) && ( !dis_ready || rob.io.commit.rollback || dec_xcpt_stall || branch_mask_full(w) || brupdate.b1.mispredict_mask =/= 0.U || brupdate.b2.mispredict || io.ifu.redirect_flush)) val dec_stalls = dec_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth) dec_fire := (0 until coreWidth).map(w => dec_valids(w) && !dec_stalls(w)) // all decoders are empty and ready for new instructions dec_ready := dec_fire.last when (dec_ready || io.ifu.redirect_flush) { dec_finished_mask := 0.U } .otherwise { dec_finished_mask := dec_fire.asUInt | dec_finished_mask } //------------------------------------------------------------- // Branch Mask Logic dec_brmask_logic.io.brupdate := brupdate dec_brmask_logic.io.flush_pipeline := RegNext(rob.io.flush.valid) for (w <- 0 until coreWidth) { dec_brmask_logic.io.is_branch(w) := !dec_finished_mask(w) && dec_uops(w).allocate_brtag dec_brmask_logic.io.will_fire(w) := dec_fire(w) && dec_uops(w).allocate_brtag // ren, dis can back pressure us dec_uops(w).br_tag := dec_brmask_logic.io.br_tag(w) dec_uops(w).br_mask := dec_brmask_logic.io.br_mask(w) } branch_mask_full := dec_brmask_logic.io.is_full //------------------------------------------------------------- //------------------------------------------------------------- // **** Register Rename Stage **** //------------------------------------------------------------- //------------------------------------------------------------- // Inputs for (rename <- rename_stages) { rename.io.kill := io.ifu.redirect_flush rename.io.brupdate := brupdate rename.io.debug_rob_empty := rob.io.empty rename.io.dec_fire := dec_fire rename.io.dec_uops := dec_uops rename.io.dis_fire := dis_fire rename.io.dis_ready := dis_ready rename.io.com_valids := rob.io.commit.valids rename.io.com_uops := rob.io.commit.uops rename.io.rbk_valids := rob.io.commit.rbk_valids rename.io.rollback := rob.io.commit.rollback } // Outputs dis_uops := rename_stage.io.ren2_uops dis_valids := rename_stage.io.ren2_mask ren_stalls := rename_stage.io.ren_stalls /** * TODO This is a bit nasty, but it's currently necessary to * split the INT/FP rename pipelines into separate instantiations. * Won't have to do this anymore with a properly decoupled FP pipeline. */ for (w <- 0 until coreWidth) { val i_uop = rename_stage.io.ren2_uops(w) val f_uop = if (usingFPU) fp_rename_stage.io.ren2_uops(w) else NullMicroOp val p_uop = if (enableSFBOpt) pred_rename_stage.io.ren2_uops(w) else NullMicroOp val f_stall = if (usingFPU) fp_rename_stage.io.ren_stalls(w) else false.B val p_stall = if (enableSFBOpt) pred_rename_stage.io.ren_stalls(w) else false.B // lrs1 can "pass through" to prs1. Used solely to index the csr file. dis_uops(w).prs1 := Mux(dis_uops(w).lrs1_rtype === RT_FLT, f_uop.prs1, Mux(dis_uops(w).lrs1_rtype === RT_FIX, i_uop.prs1, dis_uops(w).lrs1)) dis_uops(w).prs2 := Mux(dis_uops(w).lrs2_rtype === RT_FLT, f_uop.prs2, i_uop.prs2) dis_uops(w).prs3 := f_uop.prs3 dis_uops(w).ppred := p_uop.ppred dis_uops(w).pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.pdst, Mux(dis_uops(w).dst_rtype === RT_FIX, i_uop.pdst, p_uop.pdst)) dis_uops(w).stale_pdst := Mux(dis_uops(w).dst_rtype === RT_FLT, f_uop.stale_pdst, i_uop.stale_pdst) dis_uops(w).prs1_busy := i_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FIX) || f_uop.prs1_busy && (dis_uops(w).lrs1_rtype === RT_FLT) dis_uops(w).prs2_busy := i_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FIX) || f_uop.prs2_busy && (dis_uops(w).lrs2_rtype === RT_FLT) dis_uops(w).prs3_busy := f_uop.prs3_busy && dis_uops(w).frs3_en dis_uops(w).ppred_busy := p_uop.ppred_busy && dis_uops(w).is_sfb_shadow ren_stalls(w) := rename_stage.io.ren_stalls(w) || f_stall || p_stall } //------------------------------------------------------------- //------------------------------------------------------------- // **** Dispatch Stage **** //------------------------------------------------------------- //------------------------------------------------------------- //------------------------------------------------------------- // Rename2/Dispatch pipeline logic val dis_prior_slot_valid = dis_valids.scanLeft(false.B) ((s,v) => s || v) val dis_prior_slot_unique = (dis_uops zip dis_valids).scanLeft(false.B) {case (s,(u,v)) => s || v && u.is_unique} val wait_for_empty_pipeline = (0 until coreWidth).map(w => (dis_uops(w).is_unique || custom_csrs.disableOOO) && (!rob.io.empty || !io.lsu.fencei_rdy || dis_prior_slot_valid(w))) val rocc_shim_busy = if (usingRoCC) !exe_units.rocc_unit.io.rocc.rxq_empty else false.B val wait_for_rocc = (0 until coreWidth).map(w => (dis_uops(w).is_fence || dis_uops(w).is_fencei) && (io.rocc.busy || rocc_shim_busy)) val rxq_full = if (usingRoCC) exe_units.rocc_unit.io.rocc.rxq_full else false.B val block_rocc = (dis_uops zip dis_valids).map{case (u,v) => v && u.uopc === uopROCC}.scanLeft(rxq_full)(_||_) val dis_rocc_alloc_stall = (dis_uops.map(_.uopc === uopROCC) zip block_rocc) map {case (p,r) => if (usingRoCC) p && r else false.B} val dis_hazards = (0 until coreWidth).map(w => dis_valids(w) && ( !rob.io.ready || ren_stalls(w) || io.lsu.ldq_full(w) && dis_uops(w).uses_ldq || io.lsu.stq_full(w) && dis_uops(w).uses_stq || !dispatcher.io.ren_uops(w).ready || wait_for_empty_pipeline(w) || wait_for_rocc(w) || dis_prior_slot_unique(w) || dis_rocc_alloc_stall(w) || brupdate.b1.mispredict_mask =/= 0.U || brupdate.b2.mispredict || io.ifu.redirect_flush)) io.lsu.fence_dmem := (dis_valids zip wait_for_empty_pipeline).map {case (v,w) => v && w} .reduce(_||_) val dis_stalls = dis_hazards.scanLeft(false.B) ((s,h) => s || h).takeRight(coreWidth) dis_fire := dis_valids zip dis_stalls map {case (v,s) => v && !s} dis_ready := !dis_stalls.last //------------------------------------------------------------- // LDQ/STQ Allocation Logic for (w <- 0 until coreWidth) { // Dispatching instructions request load/store queue entries when they can proceed. dis_uops(w).ldq_idx := io.lsu.dis_ldq_idx(w) dis_uops(w).stq_idx := io.lsu.dis_stq_idx(w) } //------------------------------------------------------------- // Rob Allocation Logic rob.io.enq_valids := dis_fire rob.io.enq_uops := dis_uops rob.io.enq_partial_stall := dis_stalls.last // TODO come up with better ROB compacting scheme. rob.io.debug_tsc := debug_tsc_reg rob.io.csr_stall := csr.io.csr_stall // Minor hack: ecall and breaks need to increment the FTQ deq ptr earlier than commit, since // they write their PC into the CSR the cycle before they commit. // Since these are also unique, increment the FTQ ptr when they are dispatched when (RegNext(dis_fire.reduce(_||_) && dis_uops(PriorityEncoder(dis_fire)).is_sys_pc2epc)) { io.ifu.commit.valid := true.B io.ifu.commit.bits := RegNext(dis_uops(PriorityEncoder(dis_valids)).ftq_idx) } for (w <- 0 until coreWidth) { // note: this assumes uops haven't been shifted - there's a 1:1 match between PC's LSBs and "w" here // (thus the LSB of the rob_idx gives part of the PC) if (coreWidth == 1) { dis_uops(w).rob_idx := rob.io.rob_tail_idx } else { dis_uops(w).rob_idx := Cat(rob.io.rob_tail_idx >> log2Ceil(coreWidth).U, w.U(log2Ceil(coreWidth).W)) } } //------------------------------------------------------------- // RoCC allocation logic if (usingRoCC) { for (w <- 0 until coreWidth) { // We guarantee only decoding 1 RoCC instruction per cycle dis_uops(w).rxq_idx := exe_units.rocc_unit.io.rocc.rxq_idx(w) } } //------------------------------------------------------------- // Dispatch to issue queues // Get uops from rename2 for (w <- 0 until coreWidth) { dispatcher.io.ren_uops(w).valid := dis_fire(w) dispatcher.io.ren_uops(w).bits := dis_uops(w) } var iu_idx = 0 // Send dispatched uops to correct issue queues // Backpressure through dispatcher if necessary for (i <- 0 until issueParams.size) { if (issueParams(i).iqType == IQT_FP.litValue) { fp_pipeline.io.dis_uops <> dispatcher.io.dis_uops(i) } else { issue_units(iu_idx).io.dis_uops <> dispatcher.io.dis_uops(i) iu_idx += 1 } } //------------------------------------------------------------- //------------------------------------------------------------- // **** Issue Stage **** //------------------------------------------------------------- //------------------------------------------------------------- require (issue_units.map(_.issueWidth).sum == exe_units.length) var iss_wu_idx = 1 var ren_wu_idx = 1 // The 0th wakeup port goes to the ll_wbarb int_iss_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX int_iss_wakeups(0).bits := ll_wbarb.io.out.bits int_ren_wakeups(0).valid := ll_wbarb.io.out.fire && ll_wbarb.io.out.bits.uop.dst_rtype === RT_FIX int_ren_wakeups(0).bits := ll_wbarb.io.out.bits for (i <- 1 until memWidth) { int_iss_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX int_iss_wakeups(i).bits := mem_resps(i).bits int_ren_wakeups(i).valid := mem_resps(i).valid && mem_resps(i).bits.uop.dst_rtype === RT_FIX int_ren_wakeups(i).bits := mem_resps(i).bits iss_wu_idx += 1 ren_wu_idx += 1 } // loop through each issue-port (exe_units are statically connected to an issue-port) for (i <- 0 until exe_units.length) { if (exe_units(i).writesIrf) { val fast_wakeup = Wire(Valid(new ExeUnitResp(xLen))) val slow_wakeup = Wire(Valid(new ExeUnitResp(xLen))) fast_wakeup := DontCare slow_wakeup := DontCare val resp = exe_units(i).io.iresp assert(!(resp.valid && resp.bits.uop.rf_wen && resp.bits.uop.dst_rtype =/= RT_FIX)) // Fast Wakeup (uses just-issued uops that have known latencies) fast_wakeup.bits.uop := iss_uops(i) fast_wakeup.valid := iss_valids(i) && iss_uops(i).bypassable && iss_uops(i).dst_rtype === RT_FIX && iss_uops(i).ldst_val && !(io.lsu.ld_miss && (iss_uops(i).iw_p1_poisoned || iss_uops(i).iw_p2_poisoned)) // Slow Wakeup (uses write-port to register file) slow_wakeup.bits.uop := resp.bits.uop slow_wakeup.valid := resp.valid && resp.bits.uop.rf_wen && !resp.bits.uop.bypassable && resp.bits.uop.dst_rtype === RT_FIX if (exe_units(i).bypassable) { int_iss_wakeups(iss_wu_idx) := fast_wakeup iss_wu_idx += 1 } if (!exe_units(i).alwaysBypassable) { int_iss_wakeups(iss_wu_idx) := slow_wakeup iss_wu_idx += 1 } if (exe_units(i).bypassable) { int_ren_wakeups(ren_wu_idx) := fast_wakeup ren_wu_idx += 1 } if (!exe_units(i).alwaysBypassable) { int_ren_wakeups(ren_wu_idx) := slow_wakeup ren_wu_idx += 1 } } } require (iss_wu_idx == numIntIssueWakeupPorts) require (ren_wu_idx == numIntRenameWakeupPorts) require (iss_wu_idx == ren_wu_idx) // jmp unit performs fast wakeup of the predicate bits require (jmp_unit.bypassable) pred_wakeup.valid := (iss_valids(jmp_unit_idx) && iss_uops(jmp_unit_idx).is_sfb_br && !(io.lsu.ld_miss && (iss_uops(jmp_unit_idx).iw_p1_poisoned || iss_uops(jmp_unit_idx).iw_p2_poisoned)) ) pred_wakeup.bits.uop := iss_uops(jmp_unit_idx) pred_wakeup.bits.fflags := DontCare pred_wakeup.bits.data := DontCare pred_wakeup.bits.predicated := DontCare // Perform load-hit speculative wakeup through a special port (performs a poison wake-up). issue_units map { iu => iu.io.spec_ld_wakeup := io.lsu.spec_ld_wakeup } // Connect the predicate wakeup port issue_units map { iu => iu.io.pred_wakeup_port.valid := false.B iu.io.pred_wakeup_port.bits := DontCare } if (enableSFBOpt) { int_iss_unit.io.pred_wakeup_port.valid := pred_wakeup.valid int_iss_unit.io.pred_wakeup_port.bits := pred_wakeup.bits.uop.pdst } // ---------------------------------------------------------------- // Connect the wakeup ports to the busy tables in the rename stages for ((renport, intport) <- rename_stage.io.wakeups zip int_ren_wakeups) { renport <> intport } if (usingFPU) { for ((renport, fpport) <- fp_rename_stage.io.wakeups zip fp_pipeline.io.wakeups) { renport <> fpport } } if (enableSFBOpt) { pred_rename_stage.io.wakeups(0) := pred_wakeup } else { pred_rename_stage.io.wakeups := DontCare } // If we issue loads back-to-back endlessly (probably because we are executing some tight loop) // the store buffer will never drain, breaking the memory-model forward-progress guarantee // If we see a large number of loads saturate the LSU, pause for a cycle to let a store drain val loads_saturating = (mem_iss_unit.io.iss_valids(0) && mem_iss_unit.io.iss_uops(0).uses_ldq) val saturating_loads_counter = RegInit(0.U(5.W)) when (loads_saturating) { saturating_loads_counter := saturating_loads_counter + 1.U } .otherwise { saturating_loads_counter := 0.U } val pause_mem = RegNext(loads_saturating) && saturating_loads_counter === ~(0.U(5.W)) var iss_idx = 0 var int_iss_cnt = 0 var mem_iss_cnt = 0 for (w <- 0 until exe_units.length) { var fu_types = exe_units(w).io.fu_types val exe_unit = exe_units(w) if (exe_unit.readsIrf) { if (exe_unit.supportedFuncUnits.muld) { // Supress just-issued divides from issuing back-to-back, since it's an iterative divider. // But it takes a cycle to get to the Exe stage, so it can't tell us it is busy yet. val idiv_issued = iss_valids(iss_idx) && iss_uops(iss_idx).fu_code_is(FU_DIV) fu_types = fu_types & RegNext(~Mux(idiv_issued, FU_DIV, 0.U)) } if (exe_unit.hasMem) { iss_valids(iss_idx) := mem_iss_unit.io.iss_valids(mem_iss_cnt) iss_uops(iss_idx) := mem_iss_unit.io.iss_uops(mem_iss_cnt) mem_iss_unit.io.fu_types(mem_iss_cnt) := Mux(pause_mem, 0.U, fu_types) mem_iss_cnt += 1 } else { iss_valids(iss_idx) := int_iss_unit.io.iss_valids(int_iss_cnt) iss_uops(iss_idx) := int_iss_unit.io.iss_uops(int_iss_cnt) int_iss_unit.io.fu_types(int_iss_cnt) := fu_types int_iss_cnt += 1 } iss_idx += 1 } } require(iss_idx == exe_units.numIrfReaders) issue_units.map(_.io.tsc_reg := debug_tsc_reg) issue_units.map(_.io.brupdate := brupdate) issue_units.map(_.io.flush_pipeline := RegNext(rob.io.flush.valid)) // Load-hit Misspeculations require (mem_iss_unit.issueWidth <= 2) issue_units.map(_.io.ld_miss := io.lsu.ld_miss) mem_units.map(u => u.io.com_exception := RegNext(rob.io.flush.valid)) // Wakeup (Issue & Writeback) for { iu <- issue_units (issport, wakeup) <- iu.io.wakeup_ports zip int_iss_wakeups }{ issport.valid := wakeup.valid issport.bits.pdst := wakeup.bits.uop.pdst issport.bits.poisoned := wakeup.bits.uop.iw_p1_poisoned || wakeup.bits.uop.iw_p2_poisoned require (iu.io.wakeup_ports.length == int_iss_wakeups.length) } //------------------------------------------------------------- //------------------------------------------------------------- // **** Register Read Stage **** //------------------------------------------------------------- //------------------------------------------------------------- // Register Read <- Issue (rrd <- iss) iregister_read.io.rf_read_ports <> iregfile.io.read_ports iregister_read.io.prf_read_ports := DontCare if (enableSFBOpt) { iregister_read.io.prf_read_ports <> pregfile.io.read_ports } for (w <- 0 until exe_units.numIrfReaders) { iregister_read.io.iss_valids(w) := iss_valids(w) && !(io.lsu.ld_miss && (iss_uops(w).iw_p1_poisoned || iss_uops(w).iw_p2_poisoned)) } iregister_read.io.iss_uops := iss_uops iregister_read.io.iss_uops map { u => u.iw_p1_poisoned := false.B; u.iw_p2_poisoned := false.B } iregister_read.io.brupdate := brupdate iregister_read.io.kill := RegNext(rob.io.flush.valid) iregister_read.io.bypass := bypasses iregister_read.io.pred_bypass := pred_bypasses //------------------------------------------------------------- // Privileged Co-processor 0 Register File // Note: Normally this would be bad in that I'm writing state before // committing, so to get this to work I stall the entire pipeline for // CSR instructions so I never speculate these instructions. val csr_exe_unit = exe_units.csr_unit // for critical path reasons, we aren't zero'ing this out if resp is not valid val csr_rw_cmd = csr_exe_unit.io.iresp.bits.uop.ctrl.csr_cmd val wb_wdata = csr_exe_unit.io.iresp.bits.data csr.io.rw.addr := csr_exe_unit.io.iresp.bits.uop.csr_addr csr.io.rw.cmd := freechips.rocketchip.rocket.CSR.maskCmd(csr_exe_unit.io.iresp.valid, csr_rw_cmd) csr.io.rw.wdata := wb_wdata rob.io.csr_replay.valid := csr_exe_unit.io.iresp.valid && csr.io.rw_stall rob.io.csr_replay.bits.uop := csr_exe_unit.io.iresp.bits.uop rob.io.csr_replay.bits.cause := MINI_EXCEPTION_CSR_REPLAY rob.io.csr_replay.bits.badvaddr := DontCare // Extra I/O // Delay retire/exception 1 cycle csr.io.retire := RegNext(PopCount(rob.io.commit.arch_valids.asUInt)) csr.io.exception := RegNext(rob.io.com_xcpt.valid) // csr.io.pc used for setting EPC during exception or CSR.io.trace. csr.io.pc := (boom.v3.util.AlignPCToBoundary(io.ifu.get_pc(0).com_pc, icBlockBytes) + RegNext(rob.io.com_xcpt.bits.pc_lob) - Mux(RegNext(rob.io.com_xcpt.bits.edge_inst), 2.U, 0.U)) // Cause not valid for for CALL or BREAKPOINTs (CSRFile will override it). csr.io.cause := RegNext(rob.io.com_xcpt.bits.cause) csr.io.ungated_clock := clock val tval_valid = csr.io.exception && csr.io.cause.isOneOf( //Causes.illegal_instruction.U, we currently only write 0x0 for illegal instructions Causes.breakpoint.U, Causes.misaligned_load.U, Causes.misaligned_store.U, Causes.load_access.U, Causes.store_access.U, Causes.fetch_access.U, Causes.load_page_fault.U, Causes.store_page_fault.U, Causes.fetch_page_fault.U) csr.io.tval := Mux(tval_valid, RegNext(encodeVirtualAddress(rob.io.com_xcpt.bits.badvaddr, rob.io.com_xcpt.bits.badvaddr)), 0.U) // TODO move this function to some central location (since this is used elsewhere). def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } // reading requires serializing the entire pipeline csr.io.fcsr_flags.valid := rob.io.commit.fflags.valid csr.io.fcsr_flags.bits := rob.io.commit.fflags.bits csr.io.set_fs_dirty.get := rob.io.commit.fflags.valid exe_units.withFilter(_.hasFcsr).map(_.io.fcsr_rm := csr.io.fcsr_rm) io.fcsr_rm := csr.io.fcsr_rm if (usingFPU) { fp_pipeline.io.fcsr_rm := csr.io.fcsr_rm } csr.io.hartid := io.hartid csr.io.interrupts := io.interrupts // we do not support the H-extension csr.io.htval := DontCare csr.io.gva := DontCare // TODO can we add this back in, but handle reset properly and save us // the mux above on csr.io.rw.cmd? // assert (!(csr_rw_cmd =/= rocket.CSR.N && !exe_units(0).io.resp(0).valid), // "CSRFile is being written to spuriously.") //------------------------------------------------------------- //------------------------------------------------------------- // **** Execute Stage **** //------------------------------------------------------------- //------------------------------------------------------------- iss_idx = 0 var bypass_idx = 0 for (w <- 0 until exe_units.length) { val exe_unit = exe_units(w) if (exe_unit.readsIrf) { exe_unit.io.req <> iregister_read.io.exe_reqs(iss_idx) if (exe_unit.bypassable) { for (i <- 0 until exe_unit.numBypassStages) { bypasses(bypass_idx) := exe_unit.io.bypass(i) bypass_idx += 1 } } iss_idx += 1 } } require (bypass_idx == exe_units.numTotalBypassPorts) for (i <- 0 until jmp_unit.numBypassStages) { pred_bypasses(i) := jmp_unit.io.bypass(i) } //------------------------------------------------------------- //------------------------------------------------------------- // **** Load/Store Unit **** //------------------------------------------------------------- //------------------------------------------------------------- // enqueue basic load/store info in Decode for (w <- 0 until coreWidth) { io.lsu.dis_uops(w).valid := dis_fire(w) io.lsu.dis_uops(w).bits := dis_uops(w) } // tell LSU about committing loads and stores to clear entries io.lsu.commit := rob.io.commit // tell LSU that it should fire a load that waits for the rob to clear io.lsu.commit_load_at_rob_head := rob.io.com_load_is_at_rob_head //com_xcpt.valid comes too early, will fight against a branch that resolves same cycle as an exception io.lsu.exception := RegNext(rob.io.flush.valid) // Handle Branch Mispeculations io.lsu.brupdate := brupdate io.lsu.rob_head_idx := rob.io.rob_head_idx io.lsu.rob_pnr_idx := rob.io.rob_pnr_idx io.lsu.tsc_reg := debug_tsc_reg if (usingFPU) { io.lsu.fp_stdata <> fp_pipeline.io.to_sdq } //------------------------------------------------------------- //------------------------------------------------------------- // **** Writeback Stage **** //------------------------------------------------------------- //------------------------------------------------------------- var w_cnt = 1 iregfile.io.write_ports(0) := WritePort(ll_wbarb.io.out, ipregSz, xLen, RT_FIX) ll_wbarb.io.in(0) <> mem_resps(0) assert (ll_wbarb.io.in(0).ready) // never backpressure the memory unit. for (i <- 1 until memWidth) { iregfile.io.write_ports(w_cnt) := WritePort(mem_resps(i), ipregSz, xLen, RT_FIX) w_cnt += 1 } for (i <- 0 until exe_units.length) { if (exe_units(i).writesIrf) { val wbresp = exe_units(i).io.iresp val wbpdst = wbresp.bits.uop.pdst val wbdata = wbresp.bits.data def wbIsValid(rtype: UInt) = wbresp.valid && wbresp.bits.uop.rf_wen && wbresp.bits.uop.dst_rtype === rtype val wbReadsCSR = wbresp.bits.uop.ctrl.csr_cmd =/= freechips.rocketchip.rocket.CSR.N iregfile.io.write_ports(w_cnt).valid := wbIsValid(RT_FIX) iregfile.io.write_ports(w_cnt).bits.addr := wbpdst wbresp.ready := true.B if (exe_units(i).hasCSR) { iregfile.io.write_ports(w_cnt).bits.data := Mux(wbReadsCSR, csr.io.rw.rdata, wbdata) } else { iregfile.io.write_ports(w_cnt).bits.data := wbdata } assert (!wbIsValid(RT_FLT), "[fppipeline] An FP writeback is being attempted to the Int Regfile.") assert (!(wbresp.valid && !wbresp.bits.uop.rf_wen && wbresp.bits.uop.dst_rtype === RT_FIX), "[fppipeline] An Int writeback is being attempted with rf_wen disabled.") assert (!(wbresp.valid && wbresp.bits.uop.rf_wen && wbresp.bits.uop.dst_rtype =/= RT_FIX), "[fppipeline] writeback being attempted to Int RF with dst != Int type exe_units("+i+").iresp") w_cnt += 1 } } require(w_cnt == iregfile.io.write_ports.length) if (enableSFBOpt) { pregfile.io.write_ports(0).valid := jmp_unit.io.iresp.valid && jmp_unit.io.iresp.bits.uop.is_sfb_br pregfile.io.write_ports(0).bits.addr := jmp_unit.io.iresp.bits.uop.pdst pregfile.io.write_ports(0).bits.data := jmp_unit.io.iresp.bits.data } if (usingFPU) { // Connect IFPU fp_pipeline.io.from_int <> exe_units.ifpu_unit.io.ll_fresp // Connect FPIU ll_wbarb.io.in(1) <> fp_pipeline.io.to_int // Connect FLDs fp_pipeline.io.ll_wports <> exe_units.memory_units.map(_.io.ll_fresp).toSeq } if (usingRoCC) { require(usingFPU) ll_wbarb.io.in(2) <> exe_units.rocc_unit.io.ll_iresp } //------------------------------------------------------------- //------------------------------------------------------------- // **** Commit Stage **** //------------------------------------------------------------- //------------------------------------------------------------- // Writeback // --------- // First connect the ll_wport val ll_uop = ll_wbarb.io.out.bits.uop rob.io.wb_resps(0).valid := ll_wbarb.io.out.valid && !(ll_uop.uses_stq && !ll_uop.is_amo) rob.io.wb_resps(0).bits <> ll_wbarb.io.out.bits rob.io.debug_wb_valids(0) := ll_wbarb.io.out.valid && ll_uop.dst_rtype =/= RT_X rob.io.debug_wb_wdata(0) := ll_wbarb.io.out.bits.data var cnt = 1 for (i <- 1 until memWidth) { val mem_uop = mem_resps(i).bits.uop rob.io.wb_resps(cnt).valid := mem_resps(i).valid && !(mem_uop.uses_stq && !mem_uop.is_amo) rob.io.wb_resps(cnt).bits := mem_resps(i).bits rob.io.debug_wb_valids(cnt) := mem_resps(i).valid && mem_uop.dst_rtype =/= RT_X rob.io.debug_wb_wdata(cnt) := mem_resps(i).bits.data cnt += 1 } var f_cnt = 0 // rob fflags port index for (eu <- exe_units) { if (eu.writesIrf) { val resp = eu.io.iresp val wb_uop = resp.bits.uop val data = resp.bits.data rob.io.wb_resps(cnt).valid := resp.valid && !(wb_uop.uses_stq && !wb_uop.is_amo) rob.io.wb_resps(cnt).bits <> resp.bits rob.io.debug_wb_valids(cnt) := resp.valid && wb_uop.rf_wen && wb_uop.dst_rtype === RT_FIX if (eu.hasFFlags) { rob.io.fflags(f_cnt) <> resp.bits.fflags f_cnt += 1 } if (eu.hasCSR) { rob.io.debug_wb_wdata(cnt) := Mux(wb_uop.ctrl.csr_cmd =/= freechips.rocketchip.rocket.CSR.N, csr.io.rw.rdata, data) } else { rob.io.debug_wb_wdata(cnt) := data } cnt += 1 } } require(cnt == numIrfWritePorts) if (usingFPU) { for ((wdata, wakeup) <- fp_pipeline.io.debug_wb_wdata zip fp_pipeline.io.wakeups) { rob.io.wb_resps(cnt) <> wakeup rob.io.fflags(f_cnt) <> wakeup.bits.fflags rob.io.debug_wb_valids(cnt) := wakeup.valid rob.io.debug_wb_wdata(cnt) := wdata cnt += 1 f_cnt += 1 assert (!(wakeup.valid && wakeup.bits.uop.dst_rtype =/= RT_FLT), "[core] FP wakeup does not write back to a FP register.") assert (!(wakeup.valid && !wakeup.bits.uop.fp_val), "[core] FP wakeup does not involve an FP instruction.") } } require (cnt == rob.numWakeupPorts) require (f_cnt == rob.numFpuPorts) // branch resolution rob.io.brupdate <> brupdate exe_units.map(u => u.io.status := csr.io.status) if (usingFPU) fp_pipeline.io.status := csr.io.status // Connect breakpoint info to memaddrcalcunit for (i <- 0 until memWidth) { mem_units(i).io.status := csr.io.status mem_units(i).io.bp := csr.io.bp mem_units(i).io.mcontext := csr.io.mcontext mem_units(i).io.scontext := csr.io.scontext } // LSU <> ROB rob.io.lsu_clr_bsy := io.lsu.clr_bsy rob.io.lsu_clr_unsafe := io.lsu.clr_unsafe rob.io.lxcpt <> io.lsu.lxcpt assert (!(csr.io.singleStep), "[core] single-step is unsupported.") //------------------------------------------------------------- // **** Flush Pipeline **** //------------------------------------------------------------- // flush on exceptions, miniexeptions, and after some special instructions if (usingFPU) { fp_pipeline.io.flush_pipeline := RegNext(rob.io.flush.valid) } for (w <- 0 until exe_units.length) { exe_units(w).io.req.bits.kill := RegNext(rob.io.flush.valid) } assert (!(rob.io.com_xcpt.valid && !rob.io.flush.valid), "[core] exception occurred, but pipeline flush signal not set!") //------------------------------------------------------------- //------------------------------------------------------------- // **** Outputs to the External World **** //------------------------------------------------------------- //------------------------------------------------------------- // detect pipeline freezes and throw error val idle_cycles = freechips.rocketchip.util.WideCounter(32) when (rob.io.commit.valids.asUInt.orR || csr.io.csr_stall || io.rocc.busy || reset.asBool) { idle_cycles := 0.U } assert (!(idle_cycles.value(13)), "Pipeline has hung.") if (usingFPU) { fp_pipeline.io.debug_tsc_reg := debug_tsc_reg } //------------------------------------------------------------- //------------------------------------------------------------- // **** Handle Cycle-by-Cycle Printouts **** //------------------------------------------------------------- //------------------------------------------------------------- if (COMMIT_LOG_PRINTF) { var new_commit_cnt = 0.U for (w <- 0 until coreWidth) { val priv = RegNext(csr.io.status.prv) // erets change the privilege. Get the old one // To allow for diffs against spike :/ def printf_inst(uop: MicroOp) = { when (uop.is_rvc) { printf("(0x%x)", uop.debug_inst(15,0)) } .otherwise { printf("(0x%x)", uop.debug_inst) } } when (rob.io.commit.arch_valids(w)) { printf("%d 0x%x ", priv, Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen)) printf_inst(rob.io.commit.uops(w)) when (rob.io.commit.uops(w).dst_rtype === RT_FIX && rob.io.commit.uops(w).ldst =/= 0.U) { printf(" x%d 0x%x\n", rob.io.commit.uops(w).ldst, rob.io.commit.debug_wdata(w)) } .elsewhen (rob.io.commit.uops(w).dst_rtype === RT_FLT) { printf(" f%d 0x%x\n", rob.io.commit.uops(w).ldst, rob.io.commit.debug_wdata(w)) } .otherwise { printf("\n") } } } } else if (BRANCH_PRINTF) { val debug_ghist = RegInit(0.U(globalHistoryLength.W)) when (rob.io.flush.valid && FlushTypes.useCsrEvec(rob.io.flush.bits.flush_typ)) { debug_ghist := 0.U } var new_ghist = debug_ghist for (w <- 0 until coreWidth) { when (rob.io.commit.arch_valids(w) && (rob.io.commit.uops(w).is_br || rob.io.commit.uops(w).is_jal || rob.io.commit.uops(w).is_jalr)) { // for (i <- 0 until globalHistoryLength) { // printf("%x", new_ghist(globalHistoryLength-i-1)) // } // printf("\n") printf("%x %x %x %x %x %x\n", rob.io.commit.uops(w).debug_fsrc, rob.io.commit.uops(w).taken, rob.io.commit.uops(w).is_br, rob.io.commit.uops(w).is_jal, rob.io.commit.uops(w).is_jalr, Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen)) } new_ghist = Mux(rob.io.commit.arch_valids(w) && rob.io.commit.uops(w).is_br, Mux(rob.io.commit.uops(w).taken, new_ghist << 1 | 1.U(1.W), new_ghist << 1), new_ghist) } debug_ghist := new_ghist } // TODO: Does anyone want this debugging functionality? val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle := DontCare coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset //------------------------------------------------------------- //------------------------------------------------------------- // Page Table Walker io.ptw.ptbr := csr.io.ptbr io.ptw.status := csr.io.status io.ptw.pmp := csr.io.pmp io.ptw.sfence := io.ifu.sfence //------------------------------------------------------------- //------------------------------------------------------------- io.rocc := DontCare io.rocc.exception := csr.io.exception && csr.io.status.xs.orR io.rocc.csrs <> csr.io.roccCSRs if (usingRoCC) { exe_units.rocc_unit.io.rocc.rocc <> io.rocc exe_units.rocc_unit.io.rocc.dis_uops := dis_uops exe_units.rocc_unit.io.rocc.rob_head_idx := rob.io.rob_head_idx exe_units.rocc_unit.io.rocc.rob_pnr_idx := rob.io.rob_pnr_idx exe_units.rocc_unit.io.com_exception := rob.io.flush.valid exe_units.rocc_unit.io.status := csr.io.status for (w <- 0 until coreWidth) { exe_units.rocc_unit.io.rocc.dis_rocc_vals(w) := ( dis_fire(w) && dis_uops(w).uopc === uopROCC && !dis_uops(w).exception ) } } io.trace := DontCare io.trace.time := csr.io.time io.trace.insns map (t => t.valid := false.B) io.trace.custom.get.asInstanceOf[BoomTraceBundle].rob_empty := rob.io.empty if (trace) { for (w <- 0 until coreWidth) { // Delay the trace so we have a cycle to pull PCs out of the FTQ io.trace.insns(w).valid := RegNext(rob.io.commit.arch_valids(w)) // Recalculate the PC io.ifu.debug_ftq_idx(w) := rob.io.commit.uops(w).ftq_idx val iaddr = (AlignPCToBoundary(io.ifu.debug_fetch_pc(w), icBlockBytes) + RegNext(rob.io.commit.uops(w).pc_lob) - Mux(RegNext(rob.io.commit.uops(w).edge_inst), 2.U, 0.U))(vaddrBits-1,0) io.trace.insns(w).iaddr := Sext(iaddr, xLen) def getInst(uop: MicroOp, inst: UInt): UInt = { Mux(uop.is_rvc, Cat(0.U(16.W), inst(15,0)), inst) } def getWdata(uop: MicroOp, wdata: UInt): UInt = { Mux((uop.dst_rtype === RT_FIX && uop.ldst =/= 0.U) || (uop.dst_rtype === RT_FLT), wdata, 0.U(xLen.W)) } // use debug_insts instead of uop.debug_inst to use the rob's debug_inst_mem // note: rob.debug_insts comes 1 cycle later io.trace.insns(w).insn := getInst(RegNext(rob.io.commit.uops(w)), rob.io.commit.debug_insts(w)) io.trace.insns(w).wdata.map { _ := RegNext(getWdata(rob.io.commit.uops(w), rob.io.commit.debug_wdata(w))) } // Comment out this assert because it blows up FPGA synth-asserts // This tests correctedness of the debug_inst mem // when (RegNext(rob.io.commit.valids(w))) { // assert(rob.io.commit.debug_insts(w) === RegNext(rob.io.commit.uops(w).debug_inst)) // } // This tests correctedness of recovering pcs through ftq debug ports // when (RegNext(rob.io.commit.valids(w))) { // assert(Sext(io.trace.insns(w).iaddr, xLen) === // RegNext(Sext(rob.io.commit.uops(w).debug_pc(vaddrBits-1,0), xLen))) // } // These csr signals do not exactly match up with the ROB commit signals. io.trace.insns(w).priv := RegNext(Cat(RegNext(csr.io.status.debug), csr.io.status.prv)) // Can determine if it is an interrupt or not based on the MSB of the cause io.trace.insns(w).exception := RegNext(rob.io.com_xcpt.valid && !rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B io.trace.insns(w).interrupt := RegNext(rob.io.com_xcpt.valid && rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B io.trace.insns(w).cause := RegNext(rob.io.com_xcpt.bits.cause) io.trace.insns(w).tval := RegNext(csr.io.tval) } dontTouch(io.trace) } else { io.ifu.debug_ftq_idx := DontCare } } File Counters.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ // Produces 0-width value when counting to 1 class ZCounter(val n: Int) { val value = RegInit(0.U(log2Ceil(n).W)) def inc(): Bool = { if (n == 1) true.B else { val wrap = value === (n-1).U value := Mux(!isPow2(n).B && wrap, 0.U, value + 1.U) wrap } } } object ZCounter { def apply(n: Int) = new ZCounter(n) def apply(cond: Bool, n: Int): (UInt, Bool) = { val c = new ZCounter(n) var wrap: Bool = null when (cond) { wrap = c.inc() } (c.value, cond && wrap) } } object TwoWayCounter { def apply(up: Bool, down: Bool, max: Int): UInt = { val cnt = RegInit(0.U(log2Up(max + 1).W)) when (up && !down) { cnt := cnt + 1.U } when (down && !up) { cnt := cnt - 1.U } cnt } } // a counter that clock gates most of its MSBs using the LSB carry-out case class WideCounter(width: Int, inc: UInt = 1.U, reset: Boolean = true, inhibit: Bool = false.B) { private val isWide = width > (2 * inc.getWidth) private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val small = if (reset) RegInit(0.U(smallWidth.W)) else Reg(UInt(smallWidth.W)) private val nextSmall = small +& inc when (!inhibit) { small := nextSmall } private val large = if (isWide) { val r = if (reset) RegInit(0.U((width - smallWidth).W)) else Reg(UInt((width - smallWidth).W)) when (nextSmall(smallWidth) && !inhibit) { r := r + 1.U } r } else null val value = if (isWide) Cat(large, small) else small lazy val carryOut = { val lo = (small ^ nextSmall) >> 1 if (!isWide) lo else { val hi = Mux(nextSmall(smallWidth), large ^ (large +& 1.U), 0.U) >> 1 Cat(hi, lo) } } def := (x: UInt) = { small := x if (isWide) large := x >> smallWidth } } File util.scala: //****************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} /** * Object to XOR fold a input register of fullLength into a compressedLength. */ object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /** * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks */ object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /** * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. */ object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /** * Object to return a BR mask given a MicroOp mask and old BR mask. */ object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /** * Object to check if at least 1 bit matches in two masks */ object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /** * Object to clear one bit in a mask given an index */ object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /** * Object to shift a register over by one bit and concat a new one */ object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /** * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. */ object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /** * Object to increment an input value, wrapping it if * necessary. */ object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /** * Object to decrement an input value, wrapping it if * necessary. */ object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /** * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. */ object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc | (b-1).U) } } /** * Object to rotate a signal left by one */ object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /** * Object to sext a value to a particular length. */ object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /** * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. */ object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /** * Object to get the FP rounding mode out of a packed immediate. */ object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /** * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) */ object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /** * Object to see if an instruction is a JALR. */ object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /** * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). */ object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /** * Object to return the lowest bit position after the head. */ object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /** * Object to determine whether queue * index i0 is older than index i1. */ object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /** * Set all bits at or below the highest order '1'. */ object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_|_) } } /** * Set all bits at or above the lowest order '1'. */ object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_) } } /** * Transpose a matrix of Chisel Vecs. */ object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /** * N-wide one-hot priority encoder. */ object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /** * Connect the first k of n valid input interfaces to k output interfaces. */ class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_)) val out_valids = sels map (col => col.reduce(_||_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /** * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). */ class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /** * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" */ def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) */ def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) */ def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /** * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) */ def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /** * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) */ def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /** * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line */ def apply(strs: String*)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask | maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for issue queue types */ trait IQType { val IQT_SZ = 3 val IQT_INT = 1.U(IQT_SZ.W) val IQT_MEM = 2.U(IQT_SZ.W) val IQT_FP = 4.U(IQT_SZ.W) val IQT_MFP = 6.U(IQT_SZ.W) } /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 2 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val BR_N = 0.U(4.W) // Next val BR_NE = 1.U(4.W) // Branch on NotEqual val BR_EQ = 2.U(4.W) // Branch on Equal val BR_GE = 3.U(4.W) // Branch on Greater/Equal val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val BR_LT = 5.U(4.W) // Branch on Less Than val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned val BR_J = 7.U(4.W) // Jump val BR_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_X = BitPat("b???") // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc) val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.) // TODO rename RT_NAR // Micro-op opcodes // TODO change micro-op opcodes into using enum val UOPC_SZ = 7 val uopX = BitPat.dontCare(UOPC_SZ) val uopNOP = 0.U(UOPC_SZ.W) val uopLD = 1.U(UOPC_SZ.W) val uopSTA = 2.U(UOPC_SZ.W) // store address generation val uopSTD = 3.U(UOPC_SZ.W) // store data generation val uopLUI = 4.U(UOPC_SZ.W) val uopADDI = 5.U(UOPC_SZ.W) val uopANDI = 6.U(UOPC_SZ.W) val uopORI = 7.U(UOPC_SZ.W) val uopXORI = 8.U(UOPC_SZ.W) val uopSLTI = 9.U(UOPC_SZ.W) val uopSLTIU= 10.U(UOPC_SZ.W) val uopSLLI = 11.U(UOPC_SZ.W) val uopSRAI = 12.U(UOPC_SZ.W) val uopSRLI = 13.U(UOPC_SZ.W) val uopSLL = 14.U(UOPC_SZ.W) val uopADD = 15.U(UOPC_SZ.W) val uopSUB = 16.U(UOPC_SZ.W) val uopSLT = 17.U(UOPC_SZ.W) val uopSLTU = 18.U(UOPC_SZ.W) val uopAND = 19.U(UOPC_SZ.W) val uopOR = 20.U(UOPC_SZ.W) val uopXOR = 21.U(UOPC_SZ.W) val uopSRA = 22.U(UOPC_SZ.W) val uopSRL = 23.U(UOPC_SZ.W) val uopBEQ = 24.U(UOPC_SZ.W) val uopBNE = 25.U(UOPC_SZ.W) val uopBGE = 26.U(UOPC_SZ.W) val uopBGEU = 27.U(UOPC_SZ.W) val uopBLT = 28.U(UOPC_SZ.W) val uopBLTU = 29.U(UOPC_SZ.W) val uopCSRRW= 30.U(UOPC_SZ.W) val uopCSRRS= 31.U(UOPC_SZ.W) val uopCSRRC= 32.U(UOPC_SZ.W) val uopCSRRWI=33.U(UOPC_SZ.W) val uopCSRRSI=34.U(UOPC_SZ.W) val uopCSRRCI=35.U(UOPC_SZ.W) val uopJ = 36.U(UOPC_SZ.W) val uopJAL = 37.U(UOPC_SZ.W) val uopJALR = 38.U(UOPC_SZ.W) val uopAUIPC= 39.U(UOPC_SZ.W) //val uopSRET = 40.U(UOPC_SZ.W) val uopCFLSH= 41.U(UOPC_SZ.W) val uopFENCE= 42.U(UOPC_SZ.W) val uopADDIW= 43.U(UOPC_SZ.W) val uopADDW = 44.U(UOPC_SZ.W) val uopSUBW = 45.U(UOPC_SZ.W) val uopSLLIW= 46.U(UOPC_SZ.W) val uopSLLW = 47.U(UOPC_SZ.W) val uopSRAIW= 48.U(UOPC_SZ.W) val uopSRAW = 49.U(UOPC_SZ.W) val uopSRLIW= 50.U(UOPC_SZ.W) val uopSRLW = 51.U(UOPC_SZ.W) val uopMUL = 52.U(UOPC_SZ.W) val uopMULH = 53.U(UOPC_SZ.W) val uopMULHU= 54.U(UOPC_SZ.W) val uopMULHSU=55.U(UOPC_SZ.W) val uopMULW = 56.U(UOPC_SZ.W) val uopDIV = 57.U(UOPC_SZ.W) val uopDIVU = 58.U(UOPC_SZ.W) val uopREM = 59.U(UOPC_SZ.W) val uopREMU = 60.U(UOPC_SZ.W) val uopDIVW = 61.U(UOPC_SZ.W) val uopDIVUW= 62.U(UOPC_SZ.W) val uopREMW = 63.U(UOPC_SZ.W) val uopREMUW= 64.U(UOPC_SZ.W) val uopFENCEI = 65.U(UOPC_SZ.W) // = 66.U(UOPC_SZ.W) val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen) val uopFMV_W_X = 68.U(UOPC_SZ.W) val uopFMV_D_X = 69.U(UOPC_SZ.W) val uopFMV_X_W = 70.U(UOPC_SZ.W) val uopFMV_X_D = 71.U(UOPC_SZ.W) val uopFSGNJ_S = 72.U(UOPC_SZ.W) val uopFSGNJ_D = 73.U(UOPC_SZ.W) val uopFCVT_S_D = 74.U(UOPC_SZ.W) val uopFCVT_D_S = 75.U(UOPC_SZ.W) val uopFCVT_S_X = 76.U(UOPC_SZ.W) val uopFCVT_D_X = 77.U(UOPC_SZ.W) val uopFCVT_X_S = 78.U(UOPC_SZ.W) val uopFCVT_X_D = 79.U(UOPC_SZ.W) val uopCMPR_S = 80.U(UOPC_SZ.W) val uopCMPR_D = 81.U(UOPC_SZ.W) val uopFCLASS_S = 82.U(UOPC_SZ.W) val uopFCLASS_D = 83.U(UOPC_SZ.W) val uopFMINMAX_S = 84.U(UOPC_SZ.W) val uopFMINMAX_D = 85.U(UOPC_SZ.W) // = 86.U(UOPC_SZ.W) val uopFADD_S = 87.U(UOPC_SZ.W) val uopFSUB_S = 88.U(UOPC_SZ.W) val uopFMUL_S = 89.U(UOPC_SZ.W) val uopFADD_D = 90.U(UOPC_SZ.W) val uopFSUB_D = 91.U(UOPC_SZ.W) val uopFMUL_D = 92.U(UOPC_SZ.W) val uopFMADD_S = 93.U(UOPC_SZ.W) val uopFMSUB_S = 94.U(UOPC_SZ.W) val uopFNMADD_S = 95.U(UOPC_SZ.W) val uopFNMSUB_S = 96.U(UOPC_SZ.W) val uopFMADD_D = 97.U(UOPC_SZ.W) val uopFMSUB_D = 98.U(UOPC_SZ.W) val uopFNMADD_D = 99.U(UOPC_SZ.W) val uopFNMSUB_D = 100.U(UOPC_SZ.W) val uopFDIV_S = 101.U(UOPC_SZ.W) val uopFDIV_D = 102.U(UOPC_SZ.W) val uopFSQRT_S = 103.U(UOPC_SZ.W) val uopFSQRT_D = 104.U(UOPC_SZ.W) val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET val uopSFENCE = 107.U(UOPC_SZ.W) val uopROCC = 108.U(UOPC_SZ.W) val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2" // The Bubble Instruction (Machine generated NOP) // Insert (XOR x0,x0,x0) which is different from software compiler // generated NOPs which are (ADDI x0, x0, 0). // Reasoning for this is to let visualizers and stat-trackers differentiate // between software NOPs and machine-generated Bubbles in the pipeline. val BUBBLE = (0x4033).U(32.W) def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = { val uop = Wire(new boom.v3.common.MicroOp) uop := DontCare // Overridden in the following lines uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior uop.bypassable := false.B uop.fp_val := false.B uop.uses_stq := false.B uop.uses_ldq := false.B uop.pdst := 0.U uop.dst_rtype := RT_X val cs = Wire(new boom.v3.common.CtrlSignals()) cs := DontCare // Overridden in the following lines cs.br_type := BR_N cs.csr_cmd := freechips.rocketchip.rocket.CSR.N cs.is_load := false.B cs.is_sta := false.B cs.is_std := false.B uop.ctrl := cs uop } } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v3.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File frontend.scala: //****************************************************************************** // Copyright (c) 2017 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Frontend //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property._ import boom.v3.common._ import boom.v3.exu.{CommitExceptionSignals, BranchDecode, BrUpdateInfo, BranchDecodeSignals} import boom.v3.util._ class FrontendResp(implicit p: Parameters) extends BoomBundle()(p) { val pc = UInt(vaddrBitsExtended.W) // ID stage PC val data = UInt((fetchWidth * coreInstBits).W) val mask = UInt(fetchWidth.W) val xcpt = new FrontendExceptions val ghist = new GlobalHistory // fsrc provides the prediction FROM a branch in this packet // tsrc provides the prediction TO this packet val fsrc = UInt(BSRC_SZ.W) val tsrc = UInt(BSRC_SZ.W) } class GlobalHistory(implicit p: Parameters) extends BoomBundle()(p) with HasBoomFrontendParameters { // For the dual banked case, each bank ignores the contribution of the // last bank to the history. Thus we have to track the most recent update to the // history in that case val old_history = UInt(globalHistoryLength.W) val current_saw_branch_not_taken = Bool() val new_saw_branch_not_taken = Bool() val new_saw_branch_taken = Bool() val ras_idx = UInt(log2Ceil(nRasEntries).W) def histories(bank: Int) = { if (nBanks == 1) { old_history } else { require(nBanks == 2) if (bank == 0) { old_history } else { Mux(new_saw_branch_taken , old_history << 1 | 1.U, Mux(new_saw_branch_not_taken , old_history << 1, old_history)) } } } def ===(other: GlobalHistory): Bool = { ((old_history === other.old_history) && (new_saw_branch_not_taken === other.new_saw_branch_not_taken) && (new_saw_branch_taken === other.new_saw_branch_taken) ) } def =/=(other: GlobalHistory): Bool = !(this === other) def update(branches: UInt, cfi_taken: Bool, cfi_is_br: Bool, cfi_idx: UInt, cfi_valid: Bool, addr: UInt, cfi_is_call: Bool, cfi_is_ret: Bool): GlobalHistory = { val cfi_idx_fixed = cfi_idx(log2Ceil(fetchWidth)-1,0) val cfi_idx_oh = UIntToOH(cfi_idx_fixed) val new_history = Wire(new GlobalHistory) val not_taken_branches = branches & Mux(cfi_valid, MaskLower(cfi_idx_oh) & ~Mux(cfi_is_br && cfi_taken, cfi_idx_oh, 0.U(fetchWidth.W)), ~(0.U(fetchWidth.W))) if (nBanks == 1) { // In the single bank case every bank sees the history including the previous bank new_history := DontCare new_history.current_saw_branch_not_taken := false.B val saw_not_taken_branch = not_taken_branches =/= 0.U || current_saw_branch_not_taken new_history.old_history := Mux(cfi_is_br && cfi_taken && cfi_valid , histories(0) << 1 | 1.U, Mux(saw_not_taken_branch , histories(0) << 1, histories(0))) } else { // In the two bank case every bank ignore the history added by the previous bank val base = histories(1) val cfi_in_bank_0 = cfi_valid && cfi_taken && cfi_idx_fixed < bankWidth.U val ignore_second_bank = cfi_in_bank_0 || mayNotBeDualBanked(addr) val first_bank_saw_not_taken = not_taken_branches(bankWidth-1,0) =/= 0.U || current_saw_branch_not_taken new_history.current_saw_branch_not_taken := false.B when (ignore_second_bank) { new_history.old_history := histories(1) new_history.new_saw_branch_not_taken := first_bank_saw_not_taken new_history.new_saw_branch_taken := cfi_is_br && cfi_in_bank_0 } .otherwise { new_history.old_history := Mux(cfi_is_br && cfi_in_bank_0 , histories(1) << 1 | 1.U, Mux(first_bank_saw_not_taken , histories(1) << 1, histories(1))) new_history.new_saw_branch_not_taken := not_taken_branches(fetchWidth-1,bankWidth) =/= 0.U new_history.new_saw_branch_taken := cfi_valid && cfi_taken && cfi_is_br && !cfi_in_bank_0 } } new_history.ras_idx := Mux(cfi_valid && cfi_is_call, WrapInc(ras_idx, nRasEntries), Mux(cfi_valid && cfi_is_ret , WrapDec(ras_idx, nRasEntries), ras_idx)) new_history } } /** * Parameters to manage a L1 Banked ICache */ trait HasBoomFrontendParameters extends HasL1ICacheParameters { // How many banks does the ICache use? val nBanks = if (cacheParams.fetchBytes <= 8) 1 else 2 // How many bytes wide is a bank? val bankBytes = fetchBytes/nBanks val bankWidth = fetchWidth/nBanks require(nBanks == 1 || nBanks == 2) // How many "chunks"/interleavings make up a cache line? val numChunks = cacheParams.blockBytes / bankBytes // Which bank is the address pointing to? def bank(addr: UInt) = if (nBanks == 2) addr(log2Ceil(bankBytes)) else 0.U def isLastBankInBlock(addr: UInt) = { (nBanks == 2).B && addr(blockOffBits-1, log2Ceil(bankBytes)) === (numChunks-1).U } def mayNotBeDualBanked(addr: UInt) = { require(nBanks == 2) isLastBankInBlock(addr) } def blockAlign(addr: UInt) = ~(~addr | (cacheParams.blockBytes-1).U) def bankAlign(addr: UInt) = ~(~addr | (bankBytes-1).U) def fetchIdx(addr: UInt) = addr >> log2Ceil(fetchBytes) def nextBank(addr: UInt) = bankAlign(addr) + bankBytes.U def nextFetch(addr: UInt) = { if (nBanks == 1) { bankAlign(addr) + bankBytes.U } else { require(nBanks == 2) bankAlign(addr) + Mux(mayNotBeDualBanked(addr), bankBytes.U, fetchBytes.U) } } def fetchMask(addr: UInt) = { val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) if (nBanks == 1) { ((1 << fetchWidth)-1).U << idx } else { val shamt = idx.extract(log2Ceil(fetchWidth)-2, 0) val end_mask = Mux(mayNotBeDualBanked(addr), Fill(fetchWidth/2, 1.U), Fill(fetchWidth, 1.U)) ((1 << fetchWidth)-1).U << shamt & end_mask } } def bankMask(addr: UInt) = { val idx = addr.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) if (nBanks == 1) { 1.U(1.W) } else { Mux(mayNotBeDualBanked(addr), 1.U(2.W), 3.U(2.W)) } } } /** * Bundle passed into the FetchBuffer and used to combine multiple * relevant signals together. */ class FetchBundle(implicit p: Parameters) extends BoomBundle with HasBoomFrontendParameters { val pc = UInt(vaddrBitsExtended.W) val next_pc = UInt(vaddrBitsExtended.W) val edge_inst = Vec(nBanks, Bool()) // True if 1st instruction in this bundle is pc - 2 val insts = Vec(fetchWidth, Bits(32.W)) val exp_insts = Vec(fetchWidth, Bits(32.W)) // Information for sfb folding // NOTE: This IS NOT equivalent to uop.pc_lob, that gets calculated in the FB val sfbs = Vec(fetchWidth, Bool()) val sfb_masks = Vec(fetchWidth, UInt((2*fetchWidth).W)) val sfb_dests = Vec(fetchWidth, UInt((1+log2Ceil(fetchBytes)).W)) val shadowable_mask = Vec(fetchWidth, Bool()) val shadowed_mask = Vec(fetchWidth, Bool()) val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W)) val cfi_type = UInt(CFI_SZ.W) val cfi_is_call = Bool() val cfi_is_ret = Bool() val cfi_npc_plus4 = Bool() val ras_top = UInt(vaddrBitsExtended.W) val ftq_idx = UInt(log2Ceil(ftqSz).W) val mask = UInt(fetchWidth.W) // mark which words are valid instructions val br_mask = UInt(fetchWidth.W) val ghist = new GlobalHistory val lhist = Vec(nBanks, UInt(localHistoryLength.W)) val xcpt_pf_if = Bool() // I-TLB miss (instruction fetch fault). val xcpt_ae_if = Bool() // Access exception. val bp_debug_if_oh= Vec(fetchWidth, Bool()) val bp_xcpt_if_oh = Vec(fetchWidth, Bool()) val end_half = Valid(UInt(16.W)) val bpd_meta = Vec(nBanks, UInt()) // Source of the prediction from this bundle val fsrc = UInt(BSRC_SZ.W) // Source of the prediction to this bundle val tsrc = UInt(BSRC_SZ.W) } /** * IO for the BOOM Frontend to/from the CPU */ class BoomFrontendIO(implicit p: Parameters) extends BoomBundle { // Give the backend a packet of instructions. val fetchpacket = Flipped(new DecoupledIO(new FetchBufferResp)) // 1 for xcpt/jalr/auipc/flush val get_pc = Flipped(Vec(2, new GetPCFromFtqIO())) val debug_ftq_idx = Output(Vec(coreWidth, UInt(log2Ceil(ftqSz).W))) val debug_fetch_pc = Input(Vec(coreWidth, UInt(vaddrBitsExtended.W))) // Breakpoint info val status = Output(new MStatus) val bp = Output(Vec(nBreakpoints, new BP)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val sfence = Valid(new SFenceReq) val brupdate = Output(new BrUpdateInfo) // Redirects change the PC val redirect_flush = Output(Bool()) // Flush and hang the frontend? val redirect_val = Output(Bool()) // Redirect the frontend? val redirect_pc = Output(UInt()) // Where do we redirect to? val redirect_ftq_idx = Output(UInt()) // Which ftq entry should we reset to? val redirect_ghist = Output(new GlobalHistory) // What are we setting as the global history? val commit = Valid(UInt(ftqSz.W)) val flush_icache = Output(Bool()) val perf = Input(new FrontendPerfEvents) } /** * Top level Frontend class * * @param icacheParams parameters for the icache * @param hartid id for the hardware thread of the core */ class BoomFrontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new BoomFrontendModule(this) val icache = LazyModule(new boom.v3.ifu.ICache(icacheParams, staticIdForMetadataUseOnly)) val masterNode = icache.masterNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) } /** * Bundle wrapping the IO for the Frontend as a whole * * @param outer top level Frontend class */ class BoomFrontendBundle(val outer: BoomFrontend) extends CoreBundle()(outer.p) { val cpu = Flipped(new BoomFrontendIO()) val ptw = new TLBPTWIO() } /** * Main Frontend module that connects the icache, TLB, fetch controller, * and branch prediction pipeline together. * * @param outer top level Frontend class */ class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer) with HasBoomCoreParameters with HasBoomFrontendParameters { val io = IO(new BoomFrontendBundle(outer)) val io_reset_vector = outer.resetVectorSinkNode.bundle implicit val edge = outer.masterNode.edges.out(0) require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) val bpd = Module(new BranchPredictor) bpd.io.f3_fire := false.B val ras = Module(new BoomRAS) val icache = outer.icache.module icache.io.invalidate := io.cpu.flush_icache val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays))) io.ptw <> tlb.io.ptw io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.acquire := icache.io.perf.acquire // -------------------------------------------------------- // **** NextPC Select (F0) **** // Send request to ICache // -------------------------------------------------------- val s0_vpc = WireInit(0.U(vaddrBitsExtended.W)) val s0_ghist = WireInit((0.U).asTypeOf(new GlobalHistory)) val s0_tsrc = WireInit(0.U(BSRC_SZ.W)) val s0_valid = WireInit(false.B) val s0_is_replay = WireInit(false.B) val s0_is_sfence = WireInit(false.B) val s0_replay_resp = Wire(new TLBResp(log2Ceil(fetchBytes))) val s0_replay_bpd_resp = Wire(new BranchPredictionBundle) val s0_replay_ppc = Wire(UInt()) val s0_s1_use_f3_bpd_resp = WireInit(false.B) when (RegNext(reset.asBool) && !reset.asBool) { s0_valid := true.B s0_vpc := io_reset_vector s0_ghist := (0.U).asTypeOf(new GlobalHistory) s0_tsrc := BSRC_C } icache.io.req.valid := s0_valid icache.io.req.bits.addr := s0_vpc bpd.io.f0_req.valid := s0_valid bpd.io.f0_req.bits.pc := s0_vpc bpd.io.f0_req.bits.ghist := s0_ghist // -------------------------------------------------------- // **** ICache Access (F1) **** // Translate VPC // -------------------------------------------------------- val s1_vpc = RegNext(s0_vpc) val s1_valid = RegNext(s0_valid, false.B) val s1_ghist = RegNext(s0_ghist) val s1_is_replay = RegNext(s0_is_replay) val s1_is_sfence = RegNext(s0_is_sfence) val f1_clear = WireInit(false.B) val s1_tsrc = RegNext(s0_tsrc) tlb.io.req.valid := (s1_valid && !s1_is_replay && !f1_clear) || s1_is_sfence tlb.io.req.bits.cmd := DontCare tlb.io.req.bits.vaddr := s1_vpc tlb.io.req.bits.passthrough := false.B tlb.io.req.bits.size := log2Ceil(coreInstBytes * fetchWidth).U tlb.io.req.bits.v := io.ptw.status.v tlb.io.req.bits.prv := io.ptw.status.prv tlb.io.sfence := RegNext(io.cpu.sfence) tlb.io.kill := false.B val s1_tlb_miss = !s1_is_replay && tlb.io.resp.miss val s1_tlb_resp = Mux(s1_is_replay, RegNext(s0_replay_resp), tlb.io.resp) val s1_ppc = Mux(s1_is_replay, RegNext(s0_replay_ppc), tlb.io.resp.paddr) val s1_bpd_resp = bpd.io.resp.f1 icache.io.s1_paddr := s1_ppc icache.io.s1_kill := tlb.io.resp.miss || f1_clear val f1_mask = fetchMask(s1_vpc) val f1_redirects = (0 until fetchWidth) map { i => s1_valid && f1_mask(i) && s1_bpd_resp.preds(i).predicted_pc.valid && (s1_bpd_resp.preds(i).is_jal || (s1_bpd_resp.preds(i).is_br && s1_bpd_resp.preds(i).taken)) } val f1_redirect_idx = PriorityEncoder(f1_redirects) val f1_do_redirect = f1_redirects.reduce(_||_) && useBPD.B val f1_targs = s1_bpd_resp.preds.map(_.predicted_pc.bits) val f1_predicted_target = Mux(f1_do_redirect, f1_targs(f1_redirect_idx), nextFetch(s1_vpc)) val f1_predicted_ghist = s1_ghist.update( s1_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f1_mask, s1_bpd_resp.preds(f1_redirect_idx).taken && f1_do_redirect, s1_bpd_resp.preds(f1_redirect_idx).is_br, f1_redirect_idx, f1_do_redirect, s1_vpc, false.B, false.B) when (s1_valid && !s1_tlb_miss) { // Stop fetching on fault s0_valid := !(s1_tlb_resp.ae.inst || s1_tlb_resp.pf.inst) s0_tsrc := BSRC_1 s0_vpc := f1_predicted_target s0_ghist := f1_predicted_ghist s0_is_replay := false.B } // -------------------------------------------------------- // **** ICache Response (F2) **** // -------------------------------------------------------- val s2_valid = RegNext(s1_valid && !f1_clear, false.B) val s2_vpc = RegNext(s1_vpc) val s2_ghist = Reg(new GlobalHistory) s2_ghist := s1_ghist val s2_ppc = RegNext(s1_ppc) val s2_tsrc = RegNext(s1_tsrc) // tsrc provides the predictor component which provided the prediction TO this instruction val s2_fsrc = WireInit(BSRC_1) // fsrc provides the predictor component which provided the prediction FROM this instruction val f2_clear = WireInit(false.B) val s2_tlb_resp = RegNext(s1_tlb_resp) val s2_tlb_miss = RegNext(s1_tlb_miss) val s2_is_replay = RegNext(s1_is_replay) && s2_valid val s2_xcpt = s2_valid && (s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay val f3_ready = Wire(Bool()) icache.io.s2_kill := s2_xcpt val f2_bpd_resp = bpd.io.resp.f2 val f2_mask = fetchMask(s2_vpc) val f2_redirects = (0 until fetchWidth) map { i => s2_valid && f2_mask(i) && f2_bpd_resp.preds(i).predicted_pc.valid && (f2_bpd_resp.preds(i).is_jal || (f2_bpd_resp.preds(i).is_br && f2_bpd_resp.preds(i).taken)) } val f2_redirect_idx = PriorityEncoder(f2_redirects) val f2_targs = f2_bpd_resp.preds.map(_.predicted_pc.bits) val f2_do_redirect = f2_redirects.reduce(_||_) && useBPD.B val f2_predicted_target = Mux(f2_do_redirect, f2_targs(f2_redirect_idx), nextFetch(s2_vpc)) val f2_predicted_ghist = s2_ghist.update( f2_bpd_resp.preds.map(p => p.is_br && p.predicted_pc.valid).asUInt & f2_mask, f2_bpd_resp.preds(f2_redirect_idx).taken && f2_do_redirect, f2_bpd_resp.preds(f2_redirect_idx).is_br, f2_redirect_idx, f2_do_redirect, s2_vpc, false.B, false.B) val f2_correct_f1_ghist = s1_ghist =/= f2_predicted_ghist && enableGHistStallRepair.B when ((s2_valid && !icache.io.resp.valid) || (s2_valid && icache.io.resp.valid && !f3_ready)) { s0_valid := (!s2_tlb_resp.ae.inst && !s2_tlb_resp.pf.inst) || s2_is_replay || s2_tlb_miss s0_vpc := s2_vpc s0_is_replay := s2_valid && icache.io.resp.valid // When this is not a replay (it queried the BPDs, we should use f3 resp in the replaying s1) s0_s1_use_f3_bpd_resp := !s2_is_replay s0_ghist := s2_ghist s0_tsrc := s2_tsrc f1_clear := true.B } .elsewhen (s2_valid && f3_ready) { when (s1_valid && s1_vpc === f2_predicted_target && !f2_correct_f1_ghist) { // We trust our prediction of what the global history for the next branch should be s2_ghist := f2_predicted_ghist } when ((s1_valid && (s1_vpc =/= f2_predicted_target || f2_correct_f1_ghist)) || !s1_valid) { f1_clear := true.B s0_valid := !((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_is_replay) s0_vpc := f2_predicted_target s0_is_replay := false.B s0_ghist := f2_predicted_ghist s2_fsrc := BSRC_2 s0_tsrc := BSRC_2 } } s0_replay_bpd_resp := f2_bpd_resp s0_replay_resp := s2_tlb_resp s0_replay_ppc := s2_ppc // -------------------------------------------------------- // **** F3 **** // -------------------------------------------------------- val f3_clear = WireInit(false.B) val f3 = withReset(reset.asBool || f3_clear) { Module(new Queue(new FrontendResp, 1, pipe=true, flow=false)) } // Queue up the bpd resp as well, incase f4 backpressures f3 // This is "flow" because the response (enq) arrives in f3, not f2 val f3_bpd_resp = withReset(reset.asBool || f3_clear) { Module(new Queue(new BranchPredictionBundle, 1, pipe=true, flow=true)) } val f4_ready = Wire(Bool()) f3_ready := f3.io.enq.ready f3.io.enq.valid := (s2_valid && !f2_clear && (icache.io.resp.valid || ((s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst) && !s2_tlb_miss)) ) f3.io.enq.bits.pc := s2_vpc f3.io.enq.bits.data := Mux(s2_xcpt, 0.U, icache.io.resp.bits.data) f3.io.enq.bits.ghist := s2_ghist f3.io.enq.bits.mask := fetchMask(s2_vpc) f3.io.enq.bits.xcpt := s2_tlb_resp f3.io.enq.bits.fsrc := s2_fsrc f3.io.enq.bits.tsrc := s2_tsrc // RAS takes a cycle to read val ras_read_idx = RegInit(0.U(log2Ceil(nRasEntries).W)) ras.io.read_idx := ras_read_idx when (f3.io.enq.fire) { ras_read_idx := f3.io.enq.bits.ghist.ras_idx ras.io.read_idx := f3.io.enq.bits.ghist.ras_idx } // The BPD resp comes in f3 f3_bpd_resp.io.enq.valid := f3.io.deq.valid && RegNext(f3.io.enq.ready) f3_bpd_resp.io.enq.bits := bpd.io.resp.f3 when (f3_bpd_resp.io.enq.fire) { bpd.io.f3_fire := true.B } f3.io.deq.ready := f4_ready f3_bpd_resp.io.deq.ready := f4_ready val f3_imemresp = f3.io.deq.bits val f3_bank_mask = bankMask(f3_imemresp.pc) val f3_data = f3_imemresp.data val f3_aligned_pc = bankAlign(f3_imemresp.pc) val f3_is_last_bank_in_block = isLastBankInBlock(f3_aligned_pc) val f3_is_rvc = Wire(Vec(fetchWidth, Bool())) val f3_redirects = Wire(Vec(fetchWidth, Bool())) val f3_targs = Wire(Vec(fetchWidth, UInt(vaddrBitsExtended.W))) val f3_cfi_types = Wire(Vec(fetchWidth, UInt(CFI_SZ.W))) val f3_shadowed_mask = Wire(Vec(fetchWidth, Bool())) val f3_fetch_bundle = Wire(new FetchBundle) val f3_mask = Wire(Vec(fetchWidth, Bool())) val f3_br_mask = Wire(Vec(fetchWidth, Bool())) val f3_call_mask = Wire(Vec(fetchWidth, Bool())) val f3_ret_mask = Wire(Vec(fetchWidth, Bool())) val f3_npc_plus4_mask = Wire(Vec(fetchWidth, Bool())) val f3_btb_mispredicts = Wire(Vec(fetchWidth, Bool())) f3_fetch_bundle.mask := f3_mask.asUInt f3_fetch_bundle.br_mask := f3_br_mask.asUInt f3_fetch_bundle.pc := f3_imemresp.pc f3_fetch_bundle.ftq_idx := 0.U // This gets assigned later f3_fetch_bundle.xcpt_pf_if := f3_imemresp.xcpt.pf.inst f3_fetch_bundle.xcpt_ae_if := f3_imemresp.xcpt.ae.inst f3_fetch_bundle.fsrc := f3_imemresp.fsrc f3_fetch_bundle.tsrc := f3_imemresp.tsrc f3_fetch_bundle.shadowed_mask := f3_shadowed_mask // Tracks trailing 16b of previous fetch packet val f3_prev_half = Reg(UInt(16.W)) // Tracks if last fetchpacket contained a half-inst val f3_prev_is_half = RegInit(false.B) require(fetchWidth >= 4) // Logic gets kind of annoying with fetchWidth = 2 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) var redirect_found = false.B var bank_prev_is_half = f3_prev_is_half var bank_prev_half = f3_prev_half var last_inst = 0.U(16.W) for (b <- 0 until nBanks) { val bank_data = f3_data((b+1)*bankWidth*16-1, b*bankWidth*16) val bank_mask = Wire(Vec(bankWidth, Bool())) val bank_insts = Wire(Vec(bankWidth, UInt(32.W))) for (w <- 0 until bankWidth) { val i = (b * bankWidth) + w val valid = Wire(Bool()) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := io.cpu.status bpu.io.bp := io.cpu.bp bpu.io.ea := DontCare bpu.io.mcontext := io.cpu.mcontext bpu.io.scontext := io.cpu.scontext val brsigs = Wire(new BranchDecodeSignals) if (w == 0) { val inst0 = Cat(bank_data(15,0), f3_prev_half) val inst1 = bank_data(31,0) val exp_inst0 = ExpandRVC(inst0) val exp_inst1 = ExpandRVC(inst1) val pc0 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U - 2.U) val pc1 = (f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U) val bpd_decoder0 = Module(new BranchDecode) bpd_decoder0.io.inst := exp_inst0 bpd_decoder0.io.pc := pc0 val bpd_decoder1 = Module(new BranchDecode) bpd_decoder1.io.inst := exp_inst1 bpd_decoder1.io.pc := pc1 when (bank_prev_is_half) { bank_insts(w) := inst0 f3_fetch_bundle.insts(i) := inst0 f3_fetch_bundle.exp_insts(i) := exp_inst0 bpu.io.pc := pc0 brsigs := bpd_decoder0.io.out f3_fetch_bundle.edge_inst(b) := true.B if (b > 0) { val inst0b = Cat(bank_data(15,0), last_inst) val exp_inst0b = ExpandRVC(inst0b) val bpd_decoder0b = Module(new BranchDecode) bpd_decoder0b.io.inst := exp_inst0b bpd_decoder0b.io.pc := pc0 when (f3_bank_mask(b-1)) { bank_insts(w) := inst0b f3_fetch_bundle.insts(i) := inst0b f3_fetch_bundle.exp_insts(i) := exp_inst0b brsigs := bpd_decoder0b.io.out } } } .otherwise { bank_insts(w) := inst1 f3_fetch_bundle.insts(i) := inst1 f3_fetch_bundle.exp_insts(i) := exp_inst1 bpu.io.pc := pc1 brsigs := bpd_decoder1.io.out f3_fetch_bundle.edge_inst(b) := false.B } valid := true.B } else { val inst = Wire(UInt(32.W)) val exp_inst = ExpandRVC(inst) val pc = f3_aligned_pc + (i << log2Ceil(coreInstBytes)).U val bpd_decoder = Module(new BranchDecode) bpd_decoder.io.inst := exp_inst bpd_decoder.io.pc := pc bank_insts(w) := inst f3_fetch_bundle.insts(i) := inst f3_fetch_bundle.exp_insts(i) := exp_inst bpu.io.pc := pc brsigs := bpd_decoder.io.out if (w == 1) { // Need special case since 0th instruction may carry over the wrap around inst := bank_data(47,16) valid := bank_prev_is_half || !(bank_mask(0) && !isRVC(bank_insts(0))) } else if (w == bankWidth - 1) { inst := Cat(0.U(16.W), bank_data(bankWidth*16-1,(bankWidth-1)*16)) valid := !((bank_mask(w-1) && !isRVC(bank_insts(w-1))) || !isRVC(inst)) } else { inst := bank_data(w*16+32-1,w*16) valid := !(bank_mask(w-1) && !isRVC(bank_insts(w-1))) } } f3_is_rvc(i) := isRVC(bank_insts(w)) bank_mask(w) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found f3_mask (i) := f3.io.deq.valid && f3_imemresp.mask(i) && valid && !redirect_found f3_targs (i) := Mux(brsigs.cfi_type === CFI_JALR, f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits, brsigs.target) // Flush BTB entries for JALs if we mispredict the target f3_btb_mispredicts(i) := (brsigs.cfi_type === CFI_JAL && valid && f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.valid && (f3_bpd_resp.io.deq.bits.preds(i).predicted_pc.bits =/= brsigs.target) ) f3_npc_plus4_mask(i) := (if (w == 0) { !f3_is_rvc(i) && !bank_prev_is_half } else { !f3_is_rvc(i) }) val offset_from_aligned_pc = ( (i << 1).U((log2Ceil(icBlockBytes)+1).W) + brsigs.sfb_offset.bits - Mux(bank_prev_is_half && (w == 0).B, 2.U, 0.U) ) val lower_mask = Wire(UInt((2*fetchWidth).W)) val upper_mask = Wire(UInt((2*fetchWidth).W)) lower_mask := UIntToOH(i.U) upper_mask := UIntToOH(offset_from_aligned_pc(log2Ceil(fetchBytes)+1,1)) << Mux(f3_is_last_bank_in_block, bankWidth.U, 0.U) f3_fetch_bundle.sfbs(i) := ( f3_mask(i) && brsigs.sfb_offset.valid && (offset_from_aligned_pc <= Mux(f3_is_last_bank_in_block, (fetchBytes+bankBytes).U,(2*fetchBytes).U)) ) f3_fetch_bundle.sfb_masks(i) := ~MaskLower(lower_mask) & ~MaskUpper(upper_mask) f3_fetch_bundle.shadowable_mask(i) := (!(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if || bpu.io.debug_if || bpu.io.xcpt_if) && f3_bank_mask(b) && (brsigs.shadowable || !f3_mask(i))) f3_fetch_bundle.sfb_dests(i) := offset_from_aligned_pc // Redirect if // 1) its a JAL/JALR (unconditional) // 2) the BPD believes this is a branch and says we should take it f3_redirects(i) := f3_mask(i) && ( brsigs.cfi_type === CFI_JAL || brsigs.cfi_type === CFI_JALR || (brsigs.cfi_type === CFI_BR && f3_bpd_resp.io.deq.bits.preds(i).taken && useBPD.B) ) f3_br_mask(i) := f3_mask(i) && brsigs.cfi_type === CFI_BR f3_cfi_types(i) := brsigs.cfi_type f3_call_mask(i) := brsigs.is_call f3_ret_mask(i) := brsigs.is_ret f3_fetch_bundle.bp_debug_if_oh(i) := bpu.io.debug_if f3_fetch_bundle.bp_xcpt_if_oh (i) := bpu.io.xcpt_if redirect_found = redirect_found || f3_redirects(i) } last_inst = bank_insts(bankWidth-1)(15,0) bank_prev_is_half = Mux(f3_bank_mask(b), (!(bank_mask(bankWidth-2) && !isRVC(bank_insts(bankWidth-2))) && !isRVC(last_inst)), bank_prev_is_half) bank_prev_half = Mux(f3_bank_mask(b), last_inst(15,0), bank_prev_half) } f3_fetch_bundle.cfi_type := f3_cfi_types(f3_fetch_bundle.cfi_idx.bits) f3_fetch_bundle.cfi_is_call := f3_call_mask(f3_fetch_bundle.cfi_idx.bits) f3_fetch_bundle.cfi_is_ret := f3_ret_mask (f3_fetch_bundle.cfi_idx.bits) f3_fetch_bundle.cfi_npc_plus4 := f3_npc_plus4_mask(f3_fetch_bundle.cfi_idx.bits) f3_fetch_bundle.ghist := f3.io.deq.bits.ghist f3_fetch_bundle.lhist := f3_bpd_resp.io.deq.bits.lhist f3_fetch_bundle.bpd_meta := f3_bpd_resp.io.deq.bits.meta f3_fetch_bundle.end_half.valid := bank_prev_is_half f3_fetch_bundle.end_half.bits := bank_prev_half when (f3.io.deq.fire) { f3_prev_is_half := bank_prev_is_half f3_prev_half := bank_prev_half assert(f3_bpd_resp.io.deq.bits.pc === f3_fetch_bundle.pc) } when (f3_clear) { f3_prev_is_half := false.B } f3_fetch_bundle.cfi_idx.valid := f3_redirects.reduce(_||_) f3_fetch_bundle.cfi_idx.bits := PriorityEncoder(f3_redirects) f3_fetch_bundle.ras_top := ras.io.read_addr // Redirect earlier stages only if the later stage // can consume this packet val f3_predicted_target = Mux(f3_redirects.reduce(_||_), Mux(f3_fetch_bundle.cfi_is_ret && useBPD.B && useRAS.B, ras.io.read_addr, f3_targs(PriorityEncoder(f3_redirects)) ), nextFetch(f3_fetch_bundle.pc) ) f3_fetch_bundle.next_pc := f3_predicted_target val f3_predicted_ghist = f3_fetch_bundle.ghist.update( f3_fetch_bundle.br_mask, f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.br_mask(f3_fetch_bundle.cfi_idx.bits), f3_fetch_bundle.cfi_idx.bits, f3_fetch_bundle.cfi_idx.valid, f3_fetch_bundle.pc, f3_fetch_bundle.cfi_is_call, f3_fetch_bundle.cfi_is_ret ) ras.io.write_valid := false.B ras.io.write_addr := f3_aligned_pc + (f3_fetch_bundle.cfi_idx.bits << 1) + Mux( f3_fetch_bundle.cfi_npc_plus4, 4.U, 2.U) ras.io.write_idx := WrapInc(f3_fetch_bundle.ghist.ras_idx, nRasEntries) val f3_correct_f1_ghist = s1_ghist =/= f3_predicted_ghist && enableGHistStallRepair.B val f3_correct_f2_ghist = s2_ghist =/= f3_predicted_ghist && enableGHistStallRepair.B when (f3.io.deq.valid && f4_ready) { when (f3_fetch_bundle.cfi_is_call && f3_fetch_bundle.cfi_idx.valid) { ras.io.write_valid := true.B } when (f3_redirects.reduce(_||_)) { f3_prev_is_half := false.B } when (s2_valid && s2_vpc === f3_predicted_target && !f3_correct_f2_ghist) { f3.io.enq.bits.ghist := f3_predicted_ghist } .elsewhen (!s2_valid && s1_valid && s1_vpc === f3_predicted_target && !f3_correct_f1_ghist) { s2_ghist := f3_predicted_ghist } .elsewhen (( s2_valid && (s2_vpc =/= f3_predicted_target || f3_correct_f2_ghist)) || (!s2_valid && s1_valid && (s1_vpc =/= f3_predicted_target || f3_correct_f1_ghist)) || (!s2_valid && !s1_valid)) { f2_clear := true.B f1_clear := true.B s0_valid := !(f3_fetch_bundle.xcpt_pf_if || f3_fetch_bundle.xcpt_ae_if) s0_vpc := f3_predicted_target s0_is_replay := false.B s0_ghist := f3_predicted_ghist s0_tsrc := BSRC_3 f3_fetch_bundle.fsrc := BSRC_3 } } // When f3 finds a btb mispredict, queue up a bpd correction update val f4_btb_corrections = Module(new Queue(new BranchPredictionUpdate, 2)) f4_btb_corrections.io.enq.valid := f3.io.deq.fire && f3_btb_mispredicts.reduce(_||_) && enableBTBFastRepair.B f4_btb_corrections.io.enq.bits := DontCare f4_btb_corrections.io.enq.bits.is_mispredict_update := false.B f4_btb_corrections.io.enq.bits.is_repair_update := false.B f4_btb_corrections.io.enq.bits.btb_mispredicts := f3_btb_mispredicts.asUInt f4_btb_corrections.io.enq.bits.pc := f3_fetch_bundle.pc f4_btb_corrections.io.enq.bits.ghist := f3_fetch_bundle.ghist f4_btb_corrections.io.enq.bits.lhist := f3_fetch_bundle.lhist f4_btb_corrections.io.enq.bits.meta := f3_fetch_bundle.bpd_meta // ------------------------------------------------------- // **** F4 **** // ------------------------------------------------------- val f4_clear = WireInit(false.B) val f4 = withReset(reset.asBool || f4_clear) { Module(new Queue(new FetchBundle, 1, pipe=true, flow=false))} val fb = Module(new FetchBuffer) val ftq = Module(new FetchTargetQueue) // When we mispredict, we need to repair // Deal with sfbs val f4_shadowable_masks = VecInit((0 until fetchWidth) map { i => f4.io.deq.bits.shadowable_mask.asUInt | ~f4.io.deq.bits.sfb_masks(i)(fetchWidth-1,0) }) val f3_shadowable_masks = VecInit((0 until fetchWidth) map { i => Mux(f4.io.enq.valid, f4.io.enq.bits.shadowable_mask.asUInt, 0.U) | ~f4.io.deq.bits.sfb_masks(i)(2*fetchWidth-1,fetchWidth) }) val f4_sfbs = VecInit((0 until fetchWidth) map { i => enableSFBOpt.B && ((~f4_shadowable_masks(i) === 0.U) && (~f3_shadowable_masks(i) === 0.U) && f4.io.deq.bits.sfbs(i) && !(f4.io.deq.bits.cfi_idx.valid && f4.io.deq.bits.cfi_idx.bits === i.U) && Mux(f4.io.deq.bits.sfb_dests(i) === 0.U, !bank_prev_is_half, Mux(f4.io.deq.bits.sfb_dests(i) === fetchBytes.U, !f4.io.deq.bits.end_half.valid, true.B) ) ) }) val f4_sfb_valid = f4_sfbs.reduce(_||_) && f4.io.deq.valid val f4_sfb_idx = PriorityEncoder(f4_sfbs) val f4_sfb_mask = f4.io.deq.bits.sfb_masks(f4_sfb_idx) // If we have a SFB, wait for next fetch to be available in f3 val f4_delay = ( f4.io.deq.bits.sfbs.reduce(_||_) && !f4.io.deq.bits.cfi_idx.valid && !f4.io.enq.valid && !f4.io.deq.bits.xcpt_pf_if && !f4.io.deq.bits.xcpt_ae_if ) when (f4_sfb_valid) { f3_shadowed_mask := f4_sfb_mask(2*fetchWidth-1,fetchWidth).asBools } .otherwise { f3_shadowed_mask := VecInit(0.U(fetchWidth.W).asBools) } f4_ready := f4.io.enq.ready f4.io.enq.valid := f3.io.deq.valid && !f3_clear f4.io.enq.bits := f3_fetch_bundle f4.io.deq.ready := fb.io.enq.ready && ftq.io.enq.ready && !f4_delay fb.io.enq.valid := f4.io.deq.valid && ftq.io.enq.ready && !f4_delay fb.io.enq.bits := f4.io.deq.bits fb.io.enq.bits.ftq_idx := ftq.io.enq_idx fb.io.enq.bits.sfbs := Mux(f4_sfb_valid, UIntToOH(f4_sfb_idx), 0.U(fetchWidth.W)).asBools fb.io.enq.bits.shadowed_mask := ( Mux(f4_sfb_valid, f4_sfb_mask(fetchWidth-1,0), 0.U(fetchWidth.W)) | f4.io.deq.bits.shadowed_mask.asUInt ).asBools ftq.io.enq.valid := f4.io.deq.valid && fb.io.enq.ready && !f4_delay ftq.io.enq.bits := f4.io.deq.bits val bpd_update_arbiter = Module(new Arbiter(new BranchPredictionUpdate, 2)) bpd_update_arbiter.io.in(0).valid := ftq.io.bpdupdate.valid bpd_update_arbiter.io.in(0).bits := ftq.io.bpdupdate.bits assert(bpd_update_arbiter.io.in(0).ready) bpd_update_arbiter.io.in(1) <> f4_btb_corrections.io.deq bpd.io.update := bpd_update_arbiter.io.out bpd_update_arbiter.io.out.ready := true.B when (ftq.io.ras_update && enableRasTopRepair.B) { ras.io.write_valid := true.B ras.io.write_idx := ftq.io.ras_update_idx ras.io.write_addr := ftq.io.ras_update_pc } // ------------------------------------------------------- // **** To Core (F5) **** // ------------------------------------------------------- io.cpu.fetchpacket <> fb.io.deq io.cpu.get_pc <> ftq.io.get_ftq_pc ftq.io.deq := io.cpu.commit ftq.io.brupdate := io.cpu.brupdate ftq.io.redirect.valid := io.cpu.redirect_val ftq.io.redirect.bits := io.cpu.redirect_ftq_idx fb.io.clear := false.B when (io.cpu.sfence.valid) { fb.io.clear := true.B f4_clear := true.B f3_clear := true.B f2_clear := true.B f1_clear := true.B s0_valid := false.B s0_vpc := io.cpu.sfence.bits.addr s0_is_replay := false.B s0_is_sfence := true.B }.elsewhen (io.cpu.redirect_flush) { fb.io.clear := true.B f4_clear := true.B f3_clear := true.B f2_clear := true.B f1_clear := true.B f3_prev_is_half := false.B s0_valid := io.cpu.redirect_val s0_vpc := io.cpu.redirect_pc s0_ghist := io.cpu.redirect_ghist s0_tsrc := BSRC_C s0_is_replay := false.B ftq.io.redirect.valid := io.cpu.redirect_val ftq.io.redirect.bits := io.cpu.redirect_ftq_idx } ftq.io.debug_ftq_idx := io.cpu.debug_ftq_idx io.cpu.debug_fetch_pc := ftq.io.debug_fetch_pc override def toString: String = (BoomCoreStringPrefix("====Overall Frontend Params====") + "\n" + icache.toString + bpd.toString) } File regfile.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Register File (Abstract class and Synthesizable RegFile) //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import scala.collection.mutable.ArrayBuffer import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} /** * IO bundle for a register read port * * @param addrWidth size of register address in bits * @param dataWidth size of register in bits */ class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle { val addr = Input(UInt(addrWidth.W)) val data = Output(UInt(dataWidth.W)) } /** * IO bundle for the register write port * * @param addrWidth size of register address in bits * @param dataWidth size of register in bits */ class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle { val addr = UInt(addrWidth.W) val data = UInt(dataWidth.W) } /** * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os. */ object WritePort { def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt) (implicit p: Parameters): Valid[RegisterFileWritePort] = { val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth))) wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype wport.bits.addr := enq.bits.uop.pdst wport.bits.data := enq.bits.data enq.ready := true.B wport } } /** * Register file abstract class * * @param numRegisters number of registers * @param numReadPorts number of read ports * @param numWritePorts number of write ports * @param registerWidth size of registers in bits * @param bypassableArray list of write ports from func units to the read port of the regfile */ abstract class RegisterFile( numRegisters: Int, numReadPorts: Int, numWritePorts: Int, registerWidth: Int, bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports? (implicit p: Parameters) extends BoomModule { val io = IO(new BoomBundle { val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth)) val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth)))) }) private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts) private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer" override def toString: String = BoomCoreStringPrefix( "==" + type_str + " Regfile==", "Num RF Read Ports : " + numReadPorts, "Num RF Write Ports : " + numWritePorts, "RF Cost (R+W)*(R+2W) : " + rf_cost, "Bypassable Units : " + bypassableArray) } /** * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts. * * @param numRegisters number of registers * @param numReadPorts number of read ports * @param numWritePorts number of write ports * @param registerWidth size of registers in bits * @param bypassableArray list of write ports from func units to the read port of the regfile */ class RegisterFileSynthesizable( numRegisters: Int, numReadPorts: Int, numWritePorts: Int, registerWidth: Int, bypassableArray: Seq[Boolean]) (implicit p: Parameters) extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray) { // -------------------------------------------------------------- val regfile = Mem(numRegisters, UInt(registerWidth.W)) // -------------------------------------------------------------- // Read ports. val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W))) // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired). val read_addrs = io.read_ports.map(p => RegNext(p.addr)) for (i <- 0 until numReadPorts) { read_data(i) := regfile(read_addrs(i)) } // -------------------------------------------------------------- // Bypass out of the ALU's write ports. // We are assuming we cannot bypass a writer to a reader within the regfile memory // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1. // But since these bypasses are expensive, and not all write ports need to bypass their data, // only perform the w->r bypass on a select number of write ports. require (bypassableArray.length == io.write_ports.length) if (bypassableArray.reduce(_||_)) { val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]() io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} } for (i <- 0 until numReadPorts) { val bypass_ens = bypassable_wports.map(x => x.valid && x.bits.addr === read_addrs(i)) val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq)) io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i)) } } else { for (i <- 0 until numReadPorts) { io.read_ports(i).data := read_data(i) } } // -------------------------------------------------------------- // Write ports. for (wport <- io.write_ports) { when (wport.valid) { regfile(wport.bits.addr) := wport.bits.data } } // ensure there is only 1 writer per register (unless to preg0) if (numWritePorts > 1) { for (i <- 0 until (numWritePorts - 1)) { for (j <- (i + 1) until numWritePorts) { assert(!io.write_ports(i).valid || !io.write_ports(j).valid || (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) || (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here "[regfile] too many writers a register") } } } } File execution-units.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISC-V Constructing the Execution Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import scala.collection.mutable.{ArrayBuffer} import chisel3._ import org.chipsalliance.cde.config.{Parameters} import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} /** * Top level class to wrap all execution units together into a "collection" * * @param fpu using a FPU? */ class ExecutionUnits(val fpu: Boolean)(implicit val p: Parameters) extends HasBoomCoreParameters { val totalIssueWidth = issueParams.map(_.issueWidth).sum //******************************* // Instantiate the ExecutionUnits private val exe_units = ArrayBuffer[ExecutionUnit]() //******************************* // Act like a collection def length = exe_units.length def apply(n: Int) = exe_units(n) def map[T](f: ExecutionUnit => T) = { exe_units.map(f) } def withFilter(f: ExecutionUnit => Boolean) = { exe_units.withFilter(f) } def foreach[U](f: ExecutionUnit => U) = { exe_units.foreach(f) } def zipWithIndex = { exe_units.zipWithIndex } def indexWhere(f: ExecutionUnit => Boolean) = { exe_units.indexWhere(f) } def count(f: ExecutionUnit => Boolean) = { exe_units.count(f) } lazy val memory_units = { exe_units.filter(_.hasMem) } lazy val alu_units = { exe_units.filter(_.hasAlu) } lazy val csr_unit = { require (exe_units.count(_.hasCSR) == 1) exe_units.find(_.hasCSR).get } lazy val ifpu_unit = { require (usingFPU) require (exe_units.count(_.hasIfpu) == 1) exe_units.find(_.hasIfpu).get } lazy val fpiu_unit = { require (usingFPU) require (exe_units.count(_.hasFpiu) == 1) exe_units.find(_.hasFpiu).get } lazy val jmp_unit_idx = { exe_units.indexWhere(_.hasJmpUnit) } lazy val rocc_unit = { require (usingRoCC) require (exe_units.count(_.hasRocc) == 1) exe_units.find(_.hasRocc).get } if (!fpu) { val int_width = issueParams.find(_.iqType == IQT_INT.litValue).get.issueWidth for (w <- 0 until memWidth) { val memExeUnit = Module(new ALUExeUnit( hasAlu = false, hasMem = true)) memExeUnit.io.ll_iresp.ready := DontCare exe_units += memExeUnit } for (w <- 0 until int_width) { def is_nth(n: Int): Boolean = w == ((n) % int_width) val alu_exe_unit = Module(new ALUExeUnit( hasJmpUnit = is_nth(0), hasCSR = is_nth(1), hasRocc = is_nth(1) && usingRoCC, hasMul = is_nth(2), hasDiv = is_nth(3), hasIfpu = is_nth(4) && usingFPU)) exe_units += alu_exe_unit } } else { val fp_width = issueParams.find(_.iqType == IQT_FP.litValue).get.issueWidth for (w <- 0 until fp_width) { val fpu_exe_unit = Module(new FPUExeUnit(hasFpu = true, hasFdiv = usingFDivSqrt && (w==0), hasFpiu = (w==0))) exe_units += fpu_exe_unit } } val exeUnitsStr = new StringBuilder for (exe_unit <- exe_units) { exeUnitsStr.append(exe_unit.toString) } override def toString: String = (BoomCoreStringPrefix("===ExecutionUnits===") + "\n" + (if (!fpu) { BoomCoreStringPrefix( "==" + coreWidth + "-wide Machine==", "==" + totalIssueWidth + " Issue==") } else { "" }) + "\n" + exeUnitsStr.toString) require (exe_units.length != 0) if (!fpu) { // if this is for FPU units, we don't need a memory unit (or other integer units). require (exe_units.map(_.hasMem).reduce(_|_), "Datapath is missing a memory unit.") require (exe_units.map(_.hasMul).reduce(_|_), "Datapath is missing a multiplier.") require (exe_units.map(_.hasDiv).reduce(_|_), "Datapath is missing a divider.") } else { require (exe_units.map(_.hasFpu).reduce(_|_), "Datapath is missing a fpu (or has an fpu and shouldnt).") } val numIrfReaders = exe_units.count(_.readsIrf) val numIrfReadPorts = exe_units.count(_.readsIrf) * 2 val numIrfWritePorts = exe_units.count(_.writesIrf) val numLlIrfWritePorts = exe_units.count(_.writesLlIrf) val numTotalBypassPorts = exe_units.withFilter(_.bypassable).map(_.numBypassStages).foldLeft(0)(_+_) val numFrfReaders = exe_units.count(_.readsFrf) val numFrfReadPorts = exe_units.count(_.readsFrf) * 3 val numFrfWritePorts = exe_units.count(_.writesFrf) val numLlFrfWritePorts = exe_units.count(_.writesLlFrf) // The mem-unit will also bypass writes to readers in the RRD stage. // NOTE: This does NOT include the ll_wport val bypassable_write_port_mask = exe_units.withFilter(x => x.writesIrf).map(u => u.bypassable) } File micro-op.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // MicroOp //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.common import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.exu.FUConstants /** * Extension to BoomBundle to add a MicroOp */ abstract trait HasBoomUOP extends BoomBundle { val uop = new MicroOp() } /** * MicroOp passing through the pipeline */ class MicroOp(implicit p: Parameters) extends BoomBundle with freechips.rocketchip.rocket.constants.MemoryOpConstants with freechips.rocketchip.rocket.constants.ScalarOpConstants { val uopc = UInt(UOPC_SZ.W) // micro-op code val inst = UInt(32.W) val debug_inst = UInt(32.W) val is_rvc = Bool() val debug_pc = UInt(coreMaxAddrBits.W) val iq_type = UInt(IQT_SZ.W) // which issue unit do we use? val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use? val ctrl = new CtrlSignals // What is the next state of this uop in the issue window? useful // for the compacting queue. val iw_state = UInt(2.W) // Has operand 1 or 2 been waken speculatively by a load? // Only integer operands are speculaively woken up, // so we can ignore p3. val iw_p1_poisoned = Bool() val iw_p2_poisoned = Bool() val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst? val is_jalr = Bool() // is this a jump? (jal or jalr) val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit val is_sfb = Bool() // is this a sfb or in the shadow of a sfb val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under? val br_tag = UInt(brTagSz.W) // Index into FTQ to figure out our fetch PC. val ftq_idx = UInt(log2Ceil(ftqSz).W) // This inst straddles two fetch packets val edge_inst = Bool() // Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC. // Aligned to a cache-line size, as that is the greater fetch granularity. // TODO: Shouldn't this be aligned to fetch-width size? val pc_lob = UInt(log2Ceil(icBlockBytes).W) // Was this a branch that was predicted taken? val taken = Bool() val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode... // then translate and sign-extend in execute val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe val rob_idx = UInt(robAddrSz.W) val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) val pdst = UInt(maxPregSz.W) val prs1 = UInt(maxPregSz.W) val prs2 = UInt(maxPregSz.W) val prs3 = UInt(maxPregSz.W) val ppred = UInt(log2Ceil(ftqSz).W) val prs1_busy = Bool() val prs2_busy = Bool() val prs3_busy = Bool() val ppred_busy = Bool() val stale_pdst = UInt(maxPregSz.W) val exception = Bool() val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...) val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes val mem_size = UInt(2.W) val mem_signed = Bool() val is_fence = Bool() val is_fencei = Bool() val is_amo = Bool() val uses_ldq = Bool() val uses_stq = Bool() val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC. val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to // drain, clear fetcha fter it (tell ROB to un-ready until empty) val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them // Preditation def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst, // else copy rs2 to dst // logical specifiers (only used in Decode->Rename), except rollback (ldst) val ldst = UInt(lregSz.W) val lrs1 = UInt(lregSz.W) val lrs2 = UInt(lregSz.W) val lrs3 = UInt(lregSz.W) val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc. val dst_rtype = UInt(2.W) val lrs1_rtype = UInt(2.W) val lrs2_rtype = UInt(2.W) val frs3_en = Bool() // floating point information val fp_val = Bool() // is a floating-point instruction (F- or D-extension)? // If it's non-ld/st it will write back exception bits to the fcsr. val fp_single = Bool() // single-precision floating point instruction (F-extension) // frontend exception information val xcpt_pf_if = Bool() // I-TLB page fault. val xcpt_ae_if = Bool() // I$ access exception. val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr). val bp_debug_if = Bool() // Breakpoint val bp_xcpt_if = Bool() // Breakpoint // What prediction structure provides the prediction FROM this op val debug_fsrc = UInt(BSRC_SZ.W) // What prediction structure provides the prediction TO this op val debug_tsrc = UInt(BSRC_SZ.W) // Do we allocate a branch tag for this? // SFB branches don't get a mask, they get a predicate bit def allocate_brtag = (is_br && !is_sfb) || is_jalr // Does this register write-back def rf_wen = dst_rtype =/= RT_X // Is it possible for this uop to misspeculate, preventing the commit of subsequent uops? def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U } /** * Control signals within a MicroOp * * TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution */ class CtrlSignals extends Bundle() { val br_type = UInt(BR_N.getWidth.W) val op1_sel = UInt(OP1_X.getWidth.W) val op2_sel = UInt(OP2_X.getWidth.W) val imm_sel = UInt(IS_X.getWidth.W) val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W) val fcn_dw = Bool() val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W) val is_load = Bool() // will invoke TLB address lookup val is_sta = Bool() // will invoke TLB address lookup val is_std = Bool() } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill when (!vill || ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill || useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt | supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts | (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) | io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined || usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U | (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu) val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) && (!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) && (!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) || usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal || !csr_exists || ((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) || is_counter && !allow_counter || decodeFast(debug_csrs.keys.toList) && !reg_debug || decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal || io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr | (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv || is_wfi && !allow_wfi || is_ret && !allow_sret || is_ret && addr(10) && addr(7) && !reg_debug || (is_sfence || is_hfence_gvma) && !allow_sfence_vma || is_hfence_vvma && !allow_hfence_vvma || is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U || is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) || CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) || addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma || is_hfence_gvma || is_hlsv || is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) || is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) || is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt || trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call || insn_break || insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call || insn_break || io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) || exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep || io.retire <= 1.U) assert(!reg_singleStepped || io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe | (if (usingCompressed && !coreParams.misaWritable) 0 else 1) | (if (usingUser) 0x100 else 0) | (if (usingSupervisor) 0x200 else 0) | (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi || io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags | io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */ val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U } when (mode_ok || !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain) bp.control.dmode := dMode when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) | (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) | (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U || t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }
module BoomCore( // @[core.scala:51:7] input clock, // @[core.scala:51:7] input reset, // @[core.scala:51:7] input [1:0] io_hartid, // @[core.scala:54:14] input io_interrupts_debug, // @[core.scala:54:14] input io_interrupts_mtip, // @[core.scala:54:14] input io_interrupts_msip, // @[core.scala:54:14] input io_interrupts_meip, // @[core.scala:54:14] input io_interrupts_seip, // @[core.scala:54:14] output io_ifu_fetchpacket_ready, // @[core.scala:54:14] input io_ifu_fetchpacket_valid, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_valid, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_is_rvc, // @[core.scala:54:14] input [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_is_sfb, // @[core.scala:54:14] input [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_edge_inst, // @[core.scala:54:14] input [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_taken, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_valid, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_is_rvc, // @[core.scala:54:14] input [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_is_sfb, // @[core.scala:54:14] input [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_edge_inst, // @[core.scala:54:14] input [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_taken, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_valid, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_2_bits_inst, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_inst, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_is_rvc, // @[core.scala:54:14] input [39:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_pc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_is_sfb, // @[core.scala:54:14] input [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_edge_inst, // @[core.scala:54:14] input [5:0] io_ifu_fetchpacket_bits_uops_2_bits_pc_lob, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_taken, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc, // @[core.scala:54:14] output [4:0] io_ifu_get_pc_0_ftq_idx, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_idx_valid, // @[core.scala:54:14] input [2:0] io_ifu_get_pc_0_entry_cfi_idx_bits, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_taken, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_mispredicted, // @[core.scala:54:14] input [2:0] io_ifu_get_pc_0_entry_cfi_type, // @[core.scala:54:14] input [7:0] io_ifu_get_pc_0_entry_br_mask, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_is_call, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_is_ret, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_npc_plus4, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_0_entry_ras_top, // @[core.scala:54:14] input [4:0] io_ifu_get_pc_0_entry_ras_idx, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_start_bank, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_0_pc, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_0_com_pc, // @[core.scala:54:14] input io_ifu_get_pc_0_next_val, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_0_next_pc, // @[core.scala:54:14] output [4:0] io_ifu_get_pc_1_ftq_idx, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_idx_valid, // @[core.scala:54:14] input [2:0] io_ifu_get_pc_1_entry_cfi_idx_bits, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_taken, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_mispredicted, // @[core.scala:54:14] input [2:0] io_ifu_get_pc_1_entry_cfi_type, // @[core.scala:54:14] input [7:0] io_ifu_get_pc_1_entry_br_mask, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_is_call, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_is_ret, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_npc_plus4, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_1_entry_ras_top, // @[core.scala:54:14] input [4:0] io_ifu_get_pc_1_entry_ras_idx, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_start_bank, // @[core.scala:54:14] input [63:0] io_ifu_get_pc_1_ghist_old_history, // @[core.scala:54:14] input io_ifu_get_pc_1_ghist_current_saw_branch_not_taken, // @[core.scala:54:14] input io_ifu_get_pc_1_ghist_new_saw_branch_not_taken, // @[core.scala:54:14] input io_ifu_get_pc_1_ghist_new_saw_branch_taken, // @[core.scala:54:14] input [4:0] io_ifu_get_pc_1_ghist_ras_idx, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_1_pc, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_1_com_pc, // @[core.scala:54:14] input io_ifu_get_pc_1_next_val, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_1_next_pc, // @[core.scala:54:14] input [39:0] io_ifu_debug_fetch_pc_0, // @[core.scala:54:14] input [39:0] io_ifu_debug_fetch_pc_1, // @[core.scala:54:14] input [39:0] io_ifu_debug_fetch_pc_2, // @[core.scala:54:14] output io_ifu_status_debug, // @[core.scala:54:14] output io_ifu_status_cease, // @[core.scala:54:14] output io_ifu_status_wfi, // @[core.scala:54:14] output [1:0] io_ifu_status_dprv, // @[core.scala:54:14] output io_ifu_status_dv, // @[core.scala:54:14] output [1:0] io_ifu_status_prv, // @[core.scala:54:14] output io_ifu_status_v, // @[core.scala:54:14] output io_ifu_status_sd, // @[core.scala:54:14] output io_ifu_status_mpv, // @[core.scala:54:14] output io_ifu_status_gva, // @[core.scala:54:14] output io_ifu_status_tsr, // @[core.scala:54:14] output io_ifu_status_tw, // @[core.scala:54:14] output io_ifu_status_tvm, // @[core.scala:54:14] output io_ifu_status_mxr, // @[core.scala:54:14] output io_ifu_status_sum, // @[core.scala:54:14] output io_ifu_status_mprv, // @[core.scala:54:14] output [1:0] io_ifu_status_fs, // @[core.scala:54:14] output [1:0] io_ifu_status_mpp, // @[core.scala:54:14] output io_ifu_status_spp, // @[core.scala:54:14] output io_ifu_status_mpie, // @[core.scala:54:14] output io_ifu_status_spie, // @[core.scala:54:14] output io_ifu_status_mie, // @[core.scala:54:14] output io_ifu_status_sie, // @[core.scala:54:14] output io_ifu_sfence_valid, // @[core.scala:54:14] output io_ifu_sfence_bits_rs1, // @[core.scala:54:14] output io_ifu_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_ifu_sfence_bits_addr, // @[core.scala:54:14] output io_ifu_sfence_bits_asid, // @[core.scala:54:14] output [15:0] io_ifu_brupdate_b1_resolve_mask, // @[core.scala:54:14] output [15:0] io_ifu_brupdate_b1_mispredict_mask, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_uopc, // @[core.scala:54:14] output [31:0] io_ifu_brupdate_b2_uop_inst, // @[core.scala:54:14] output [31:0] io_ifu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_ifu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_iq_type, // @[core.scala:54:14] output [9:0] io_ifu_brupdate_b2_uop_fu_code, // @[core.scala:54:14] output [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ctrl_is_load, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ctrl_is_sta, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_iw_state, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_br, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_jalr, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_jal, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_ifu_brupdate_b2_uop_br_mask, // @[core.scala:54:14] output [3:0] io_ifu_brupdate_b2_uop_br_tag, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_taken, // @[core.scala:54:14] output [19:0] io_ifu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_ifu_brupdate_b2_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_pdst, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs1, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs2, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs3, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ppred, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_exception, // @[core.scala:54:14] output [63:0] io_ifu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_bypassable, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_mem_size, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_fence, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_amo, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_unique, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_ldst, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs1, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs2, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs3, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_val, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_single, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14] output io_ifu_brupdate_b2_valid, // @[core.scala:54:14] output io_ifu_brupdate_b2_mispredict, // @[core.scala:54:14] output io_ifu_brupdate_b2_taken, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_cfi_type, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_pc_sel, // @[core.scala:54:14] output [39:0] io_ifu_brupdate_b2_jalr_target, // @[core.scala:54:14] output [20:0] io_ifu_brupdate_b2_target_offset, // @[core.scala:54:14] output io_ifu_redirect_flush, // @[core.scala:54:14] output io_ifu_redirect_val, // @[core.scala:54:14] output [39:0] io_ifu_redirect_pc, // @[core.scala:54:14] output [4:0] io_ifu_redirect_ftq_idx, // @[core.scala:54:14] output [63:0] io_ifu_redirect_ghist_old_history, // @[core.scala:54:14] output io_ifu_redirect_ghist_current_saw_branch_not_taken, // @[core.scala:54:14] output io_ifu_redirect_ghist_new_saw_branch_not_taken, // @[core.scala:54:14] output io_ifu_redirect_ghist_new_saw_branch_taken, // @[core.scala:54:14] output [4:0] io_ifu_redirect_ghist_ras_idx, // @[core.scala:54:14] output io_ifu_commit_valid, // @[core.scala:54:14] output [31:0] io_ifu_commit_bits, // @[core.scala:54:14] output io_ifu_flush_icache, // @[core.scala:54:14] input io_ifu_perf_acquire, // @[core.scala:54:14] input io_ifu_perf_tlbMiss, // @[core.scala:54:14] output [3:0] io_ptw_ptbr_mode, // @[core.scala:54:14] output [43:0] io_ptw_ptbr_ppn, // @[core.scala:54:14] output io_ptw_sfence_valid, // @[core.scala:54:14] output io_ptw_sfence_bits_rs1, // @[core.scala:54:14] output io_ptw_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_ptw_sfence_bits_addr, // @[core.scala:54:14] output io_ptw_sfence_bits_asid, // @[core.scala:54:14] output io_ptw_status_debug, // @[core.scala:54:14] output io_ptw_status_cease, // @[core.scala:54:14] output io_ptw_status_wfi, // @[core.scala:54:14] output [1:0] io_ptw_status_dprv, // @[core.scala:54:14] output io_ptw_status_dv, // @[core.scala:54:14] output [1:0] io_ptw_status_prv, // @[core.scala:54:14] output io_ptw_status_v, // @[core.scala:54:14] output io_ptw_status_sd, // @[core.scala:54:14] output io_ptw_status_mpv, // @[core.scala:54:14] output io_ptw_status_gva, // @[core.scala:54:14] output io_ptw_status_tsr, // @[core.scala:54:14] output io_ptw_status_tw, // @[core.scala:54:14] output io_ptw_status_tvm, // @[core.scala:54:14] output io_ptw_status_mxr, // @[core.scala:54:14] output io_ptw_status_sum, // @[core.scala:54:14] output io_ptw_status_mprv, // @[core.scala:54:14] output [1:0] io_ptw_status_fs, // @[core.scala:54:14] output [1:0] io_ptw_status_mpp, // @[core.scala:54:14] output io_ptw_status_spp, // @[core.scala:54:14] output io_ptw_status_mpie, // @[core.scala:54:14] output io_ptw_status_spie, // @[core.scala:54:14] output io_ptw_status_mie, // @[core.scala:54:14] output io_ptw_status_sie, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_0_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_0_mask, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_1_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_1_mask, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_2_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_2_mask, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_3_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_3_mask, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_4_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_4_mask, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_5_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_5_mask, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_6_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_6_mask, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_7_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_7_mask, // @[core.scala:54:14] input io_ptw_perf_l2miss, // @[core.scala:54:14] input io_ptw_perf_l2hit, // @[core.scala:54:14] input io_ptw_perf_pte_miss, // @[core.scala:54:14] input io_ptw_perf_pte_hit, // @[core.scala:54:14] input io_ptw_clock_enabled, // @[core.scala:54:14] output io_lsu_exe_0_req_valid, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_uopc, // @[core.scala:54:14] output [31:0] io_lsu_exe_0_req_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_exe_0_req_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_exe_0_req_bits_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_exe_0_req_bits_uop_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_exe_0_req_bits_uop_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_load, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_iw_state, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_br, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_jalr, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_jal, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_exe_0_req_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_exe_0_req_bits_uop_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_taken, // @[core.scala:54:14] output [19:0] io_lsu_exe_0_req_bits_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_exe_0_req_bits_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_exe_0_req_bits_uop_exc_cause, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_flush_on_commit, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_lrs3, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_fp_val, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_fp_single, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc, // @[core.scala:54:14] output [63:0] io_lsu_exe_0_req_bits_data, // @[core.scala:54:14] output [39:0] io_lsu_exe_0_req_bits_addr, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_mxcpt_valid, // @[core.scala:54:14] output [24:0] io_lsu_exe_0_req_bits_mxcpt_bits, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_sfence_valid, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_sfence_bits_rs1, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_sfence_bits_asid, // @[core.scala:54:14] input io_lsu_exe_0_iresp_valid, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_uopc, // @[core.scala:54:14] input [31:0] io_lsu_exe_0_iresp_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type, // @[core.scala:54:14] input [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code, // @[core.scala:54:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_load, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_std, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_br, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_jalr, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_jal, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_sfb, // @[core.scala:54:14] input [15:0] io_lsu_exe_0_iresp_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_br_tag, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_taken, // @[core.scala:54:14] input [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed, // @[core.scala:54:14] input [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_rob_idx, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_bypassable, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_flush_on_commit, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ldst_val, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_fp_val, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_fp_single, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc, // @[core.scala:54:14] input [63:0] io_lsu_exe_0_iresp_bits_data, // @[core.scala:54:14] input io_lsu_exe_0_fresp_valid, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_uopc, // @[core.scala:54:14] input [31:0] io_lsu_exe_0_fresp_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type, // @[core.scala:54:14] input [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code, // @[core.scala:54:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_load, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_std, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_br, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_jalr, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_jal, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_sfb, // @[core.scala:54:14] input [15:0] io_lsu_exe_0_fresp_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_br_tag, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_taken, // @[core.scala:54:14] input [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed, // @[core.scala:54:14] input [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_rob_idx, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_bypassable, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_flush_on_commit, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ldst_val, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_fp_val, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_fp_single, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc, // @[core.scala:54:14] input [64:0] io_lsu_exe_0_fresp_bits_data, // @[core.scala:54:14] output io_lsu_dis_uops_0_valid, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_uopc, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_0_bits_inst, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_0_bits_debug_inst, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dis_uops_0_bits_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_dis_uops_0_bits_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ctrl_is_load, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_iw_state, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_br, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_jalr, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_jal, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_dis_uops_0_bits_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_0_bits_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_ftq_idx, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_pc_lob, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_taken, // @[core.scala:54:14] output [19:0] io_lsu_dis_uops_0_bits_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_dis_uops_0_bits_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs3, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs1_busy, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs2_busy, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs3_busy, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_stale_pdst, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_exception, // @[core.scala:54:14] output [63:0] io_lsu_dis_uops_0_bits_exc_cause, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_mem_size, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_mem_signed, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_fence, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_fencei, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_amo, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_uses_ldq, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_uses_stq, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_unique, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_flush_on_commit, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs3, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_frs3_en, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_val, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_single, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_bp_debug_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_debug_tsrc, // @[core.scala:54:14] output io_lsu_dis_uops_1_valid, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_uopc, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_1_bits_inst, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_1_bits_debug_inst, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dis_uops_1_bits_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_dis_uops_1_bits_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_1_bits_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ctrl_is_load, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_iw_state, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_br, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_jalr, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_jal, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_dis_uops_1_bits_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_1_bits_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_ftq_idx, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_pc_lob, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_taken, // @[core.scala:54:14] output [19:0] io_lsu_dis_uops_1_bits_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_dis_uops_1_bits_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs3, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs1_busy, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs2_busy, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs3_busy, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_stale_pdst, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_exception, // @[core.scala:54:14] output [63:0] io_lsu_dis_uops_1_bits_exc_cause, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_mem_size, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_mem_signed, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_fence, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_fencei, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_amo, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_uses_ldq, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_uses_stq, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_unique, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_flush_on_commit, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs3, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_frs3_en, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_val, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_single, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_bp_debug_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_debug_tsrc, // @[core.scala:54:14] output io_lsu_dis_uops_2_valid, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_uopc, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_2_bits_inst, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_2_bits_debug_inst, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dis_uops_2_bits_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_2_bits_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_dis_uops_2_bits_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_2_bits_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_2_bits_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_2_bits_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_2_bits_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ctrl_is_load, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_iw_state, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_br, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_jalr, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_jal, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_dis_uops_2_bits_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_2_bits_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_ftq_idx, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_pc_lob, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_taken, // @[core.scala:54:14] output [19:0] io_lsu_dis_uops_2_bits_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_dis_uops_2_bits_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_prs3, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_prs1_busy, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_prs2_busy, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_prs3_busy, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_stale_pdst, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_exception, // @[core.scala:54:14] output [63:0] io_lsu_dis_uops_2_bits_exc_cause, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_mem_size, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_mem_signed, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_fence, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_fencei, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_amo, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_uses_ldq, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_uses_stq, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_unique, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_flush_on_commit, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_lrs3, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_frs3_en, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_fp_val, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_fp_single, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_bp_debug_if, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_debug_tsrc, // @[core.scala:54:14] input [4:0] io_lsu_dis_ldq_idx_0, // @[core.scala:54:14] input [4:0] io_lsu_dis_ldq_idx_1, // @[core.scala:54:14] input [4:0] io_lsu_dis_ldq_idx_2, // @[core.scala:54:14] input [4:0] io_lsu_dis_stq_idx_0, // @[core.scala:54:14] input [4:0] io_lsu_dis_stq_idx_1, // @[core.scala:54:14] input [4:0] io_lsu_dis_stq_idx_2, // @[core.scala:54:14] input io_lsu_ldq_full_0, // @[core.scala:54:14] input io_lsu_ldq_full_1, // @[core.scala:54:14] input io_lsu_ldq_full_2, // @[core.scala:54:14] input io_lsu_stq_full_0, // @[core.scala:54:14] input io_lsu_stq_full_1, // @[core.scala:54:14] input io_lsu_stq_full_2, // @[core.scala:54:14] input io_lsu_fp_stdata_ready, // @[core.scala:54:14] output io_lsu_fp_stdata_valid, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_uopc, // @[core.scala:54:14] output [31:0] io_lsu_fp_stdata_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_fp_stdata_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_fp_stdata_bits_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_uop_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_fp_stdata_bits_uop_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ctrl_is_load, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_iw_state, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_br, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_jalr, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_jal, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_fp_stdata_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_fp_stdata_bits_uop_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_taken, // @[core.scala:54:14] output [19:0] io_lsu_fp_stdata_bits_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_fp_stdata_bits_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_fp_stdata_bits_uop_exc_cause, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_flush_on_commit, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_lrs3, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_fp_val, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_fp_single, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc, // @[core.scala:54:14] output [63:0] io_lsu_fp_stdata_bits_data, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_predicated, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_valid, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc, // @[core.scala:54:14] output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_br, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_taken, // @[core.scala:54:14] output [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags, // @[core.scala:54:14] output io_lsu_commit_valids_0, // @[core.scala:54:14] output io_lsu_commit_valids_1, // @[core.scala:54:14] output io_lsu_commit_valids_2, // @[core.scala:54:14] output io_lsu_commit_arch_valids_0, // @[core.scala:54:14] output io_lsu_commit_arch_valids_1, // @[core.scala:54:14] output io_lsu_commit_arch_valids_2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_uopc, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_0_inst, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_0_debug_inst, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_commit_uops_0_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_commit_uops_0_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_0_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_commit_uops_0_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_commit_uops_0_ctrl_is_load, // @[core.scala:54:14] output io_lsu_commit_uops_0_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_commit_uops_0_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_iw_state, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_br, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_jalr, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_jal, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_commit_uops_0_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_0_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ftq_idx, // @[core.scala:54:14] output io_lsu_commit_uops_0_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_pc_lob, // @[core.scala:54:14] output io_lsu_commit_uops_0_taken, // @[core.scala:54:14] output [19:0] io_lsu_commit_uops_0_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_commit_uops_0_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_pdst, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs1, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs3, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ppred, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs1_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs2_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs3_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_stale_pdst, // @[core.scala:54:14] output io_lsu_commit_uops_0_exception, // @[core.scala:54:14] output [63:0] io_lsu_commit_uops_0_exc_cause, // @[core.scala:54:14] output io_lsu_commit_uops_0_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_mem_size, // @[core.scala:54:14] output io_lsu_commit_uops_0_mem_signed, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_fence, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_fencei, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_amo, // @[core.scala:54:14] output io_lsu_commit_uops_0_uses_ldq, // @[core.scala:54:14] output io_lsu_commit_uops_0_uses_stq, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_unique, // @[core.scala:54:14] output io_lsu_commit_uops_0_flush_on_commit, // @[core.scala:54:14] output io_lsu_commit_uops_0_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_ldst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs3, // @[core.scala:54:14] output io_lsu_commit_uops_0_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[core.scala:54:14] output io_lsu_commit_uops_0_frs3_en, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_val, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_single, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_bp_debug_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_debug_tsrc, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_uopc, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_1_inst, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_1_debug_inst, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_commit_uops_1_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_commit_uops_1_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_1_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_commit_uops_1_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_commit_uops_1_ctrl_is_load, // @[core.scala:54:14] output io_lsu_commit_uops_1_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_commit_uops_1_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_iw_state, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_br, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_jalr, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_jal, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_commit_uops_1_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_1_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ftq_idx, // @[core.scala:54:14] output io_lsu_commit_uops_1_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_pc_lob, // @[core.scala:54:14] output io_lsu_commit_uops_1_taken, // @[core.scala:54:14] output [19:0] io_lsu_commit_uops_1_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_commit_uops_1_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_pdst, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs1, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs3, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ppred, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs1_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs2_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs3_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_stale_pdst, // @[core.scala:54:14] output io_lsu_commit_uops_1_exception, // @[core.scala:54:14] output [63:0] io_lsu_commit_uops_1_exc_cause, // @[core.scala:54:14] output io_lsu_commit_uops_1_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_mem_size, // @[core.scala:54:14] output io_lsu_commit_uops_1_mem_signed, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_fence, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_fencei, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_amo, // @[core.scala:54:14] output io_lsu_commit_uops_1_uses_ldq, // @[core.scala:54:14] output io_lsu_commit_uops_1_uses_stq, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_unique, // @[core.scala:54:14] output io_lsu_commit_uops_1_flush_on_commit, // @[core.scala:54:14] output io_lsu_commit_uops_1_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_ldst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs3, // @[core.scala:54:14] output io_lsu_commit_uops_1_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_lrs2_rtype, // @[core.scala:54:14] output io_lsu_commit_uops_1_frs3_en, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_val, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_single, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_bp_debug_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_debug_tsrc, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_uopc, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_2_inst, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_2_debug_inst, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_commit_uops_2_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_2_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_commit_uops_2_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_2_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_2_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_2_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_commit_uops_2_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_2_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_commit_uops_2_ctrl_is_load, // @[core.scala:54:14] output io_lsu_commit_uops_2_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_commit_uops_2_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_iw_state, // @[core.scala:54:14] output io_lsu_commit_uops_2_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_2_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_br, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_jalr, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_jal, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_commit_uops_2_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_2_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_ftq_idx, // @[core.scala:54:14] output io_lsu_commit_uops_2_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_pc_lob, // @[core.scala:54:14] output io_lsu_commit_uops_2_taken, // @[core.scala:54:14] output [19:0] io_lsu_commit_uops_2_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_commit_uops_2_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_pdst, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_prs1, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_prs2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_prs3, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_ppred, // @[core.scala:54:14] output io_lsu_commit_uops_2_prs1_busy, // @[core.scala:54:14] output io_lsu_commit_uops_2_prs2_busy, // @[core.scala:54:14] output io_lsu_commit_uops_2_prs3_busy, // @[core.scala:54:14] output io_lsu_commit_uops_2_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_stale_pdst, // @[core.scala:54:14] output io_lsu_commit_uops_2_exception, // @[core.scala:54:14] output [63:0] io_lsu_commit_uops_2_exc_cause, // @[core.scala:54:14] output io_lsu_commit_uops_2_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_mem_size, // @[core.scala:54:14] output io_lsu_commit_uops_2_mem_signed, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_fence, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_fencei, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_amo, // @[core.scala:54:14] output io_lsu_commit_uops_2_uses_ldq, // @[core.scala:54:14] output io_lsu_commit_uops_2_uses_stq, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_unique, // @[core.scala:54:14] output io_lsu_commit_uops_2_flush_on_commit, // @[core.scala:54:14] output io_lsu_commit_uops_2_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_ldst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_lrs3, // @[core.scala:54:14] output io_lsu_commit_uops_2_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_lrs2_rtype, // @[core.scala:54:14] output io_lsu_commit_uops_2_frs3_en, // @[core.scala:54:14] output io_lsu_commit_uops_2_fp_val, // @[core.scala:54:14] output io_lsu_commit_uops_2_fp_single, // @[core.scala:54:14] output io_lsu_commit_uops_2_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_commit_uops_2_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_commit_uops_2_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_commit_uops_2_bp_debug_if, // @[core.scala:54:14] output io_lsu_commit_uops_2_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_debug_tsrc, // @[core.scala:54:14] output io_lsu_commit_fflags_valid, // @[core.scala:54:14] output [4:0] io_lsu_commit_fflags_bits, // @[core.scala:54:14] output [31:0] io_lsu_commit_debug_insts_0, // @[core.scala:54:14] output [31:0] io_lsu_commit_debug_insts_1, // @[core.scala:54:14] output [31:0] io_lsu_commit_debug_insts_2, // @[core.scala:54:14] output io_lsu_commit_rbk_valids_0, // @[core.scala:54:14] output io_lsu_commit_rbk_valids_1, // @[core.scala:54:14] output io_lsu_commit_rbk_valids_2, // @[core.scala:54:14] output io_lsu_commit_rollback, // @[core.scala:54:14] output [63:0] io_lsu_commit_debug_wdata_0, // @[core.scala:54:14] output [63:0] io_lsu_commit_debug_wdata_1, // @[core.scala:54:14] output [63:0] io_lsu_commit_debug_wdata_2, // @[core.scala:54:14] output io_lsu_commit_load_at_rob_head, // @[core.scala:54:14] input io_lsu_clr_bsy_0_valid, // @[core.scala:54:14] input [6:0] io_lsu_clr_bsy_0_bits, // @[core.scala:54:14] input io_lsu_clr_bsy_1_valid, // @[core.scala:54:14] input [6:0] io_lsu_clr_bsy_1_bits, // @[core.scala:54:14] input [6:0] io_lsu_clr_unsafe_0_bits, // @[core.scala:54:14] output io_lsu_fence_dmem, // @[core.scala:54:14] input io_lsu_spec_ld_wakeup_0_valid, // @[core.scala:54:14] input [6:0] io_lsu_spec_ld_wakeup_0_bits, // @[core.scala:54:14] input io_lsu_ld_miss, // @[core.scala:54:14] output [15:0] io_lsu_brupdate_b1_resolve_mask, // @[core.scala:54:14] output [15:0] io_lsu_brupdate_b1_mispredict_mask, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_uopc, // @[core.scala:54:14] output [31:0] io_lsu_brupdate_b2_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_brupdate_b2_uop_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ctrl_is_load, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_iw_state, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_br, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_jalr, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_jal, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_brupdate_b2_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_brupdate_b2_uop_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_taken, // @[core.scala:54:14] output [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_brupdate_b2_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ppred, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_fence, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_amo, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_unique, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_val, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_single, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14] output io_lsu_brupdate_b2_valid, // @[core.scala:54:14] output io_lsu_brupdate_b2_mispredict, // @[core.scala:54:14] output io_lsu_brupdate_b2_taken, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_cfi_type, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_pc_sel, // @[core.scala:54:14] output [39:0] io_lsu_brupdate_b2_jalr_target, // @[core.scala:54:14] output [20:0] io_lsu_brupdate_b2_target_offset, // @[core.scala:54:14] output [6:0] io_lsu_rob_pnr_idx, // @[core.scala:54:14] output [6:0] io_lsu_rob_head_idx, // @[core.scala:54:14] output io_lsu_exception, // @[core.scala:54:14] input io_lsu_fencei_rdy, // @[core.scala:54:14] input io_lsu_lxcpt_valid, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_uopc, // @[core.scala:54:14] input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_iq_type, // @[core.scala:54:14] input [9:0] io_lsu_lxcpt_bits_uop_fu_code, // @[core.scala:54:14] input [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ctrl_is_load, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ctrl_is_sta, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ctrl_is_std, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_iw_state, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_br, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_jalr, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_jal, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_sfb, // @[core.scala:54:14] input [15:0] io_lsu_lxcpt_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_lxcpt_bits_uop_br_tag, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_taken, // @[core.scala:54:14] input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[core.scala:54:14] input [11:0] io_lsu_lxcpt_bits_uop_csr_addr, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_bypassable, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ldst_val, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_val, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_single, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_cause, // @[core.scala:54:14] input [39:0] io_lsu_lxcpt_bits_badvaddr, // @[core.scala:54:14] output [63:0] io_lsu_tsc_reg, // @[core.scala:54:14] input io_lsu_perf_acquire, // @[core.scala:54:14] input io_lsu_perf_release, // @[core.scala:54:14] input io_lsu_perf_tlbMiss, // @[core.scala:54:14] input io_ptw_tlb_req_ready, // @[core.scala:54:14] input io_ptw_tlb_resp_valid, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_ae_ptw, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_ae_final, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pf, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gf, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hr, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hw, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hx, // @[core.scala:54:14] input [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future, // @[core.scala:54:14] input [43:0] io_ptw_tlb_resp_bits_pte_ppn, // @[core.scala:54:14] input [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_d, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_a, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_g, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_u, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_x, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_w, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_r, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_v, // @[core.scala:54:14] input [1:0] io_ptw_tlb_resp_bits_level, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_homogeneous, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gpa_valid, // @[core.scala:54:14] input [38:0] io_ptw_tlb_resp_bits_gpa_bits, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gpa_is_pte, // @[core.scala:54:14] input [3:0] io_ptw_tlb_ptbr_mode, // @[core.scala:54:14] input [43:0] io_ptw_tlb_ptbr_ppn, // @[core.scala:54:14] input io_ptw_tlb_status_debug, // @[core.scala:54:14] input io_ptw_tlb_status_cease, // @[core.scala:54:14] input io_ptw_tlb_status_wfi, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_dprv, // @[core.scala:54:14] input io_ptw_tlb_status_dv, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_prv, // @[core.scala:54:14] input io_ptw_tlb_status_v, // @[core.scala:54:14] input io_ptw_tlb_status_sd, // @[core.scala:54:14] input io_ptw_tlb_status_mpv, // @[core.scala:54:14] input io_ptw_tlb_status_gva, // @[core.scala:54:14] input io_ptw_tlb_status_tsr, // @[core.scala:54:14] input io_ptw_tlb_status_tw, // @[core.scala:54:14] input io_ptw_tlb_status_tvm, // @[core.scala:54:14] input io_ptw_tlb_status_mxr, // @[core.scala:54:14] input io_ptw_tlb_status_sum, // @[core.scala:54:14] input io_ptw_tlb_status_mprv, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_fs, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_mpp, // @[core.scala:54:14] input io_ptw_tlb_status_spp, // @[core.scala:54:14] input io_ptw_tlb_status_mpie, // @[core.scala:54:14] input io_ptw_tlb_status_spie, // @[core.scala:54:14] input io_ptw_tlb_status_mie, // @[core.scala:54:14] input io_ptw_tlb_status_sie, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_0_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_0_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_0_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_1_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_1_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_1_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_2_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_2_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_2_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_3_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_3_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_3_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_4_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_4_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_4_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_5_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_5_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_5_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_6_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_6_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_6_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_7_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_7_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_7_mask, // @[core.scala:54:14] output [63:0] io_trace_time, // @[core.scala:54:14] output io_trace_custom_rob_empty // @[core.scala:54:14] ); wire [1:0] iss_uops_3_debug_tsrc; // @[core.scala:173:24] wire [1:0] iss_uops_3_debug_fsrc; // @[core.scala:173:24] wire iss_uops_3_bp_xcpt_if; // @[core.scala:173:24] wire iss_uops_3_bp_debug_if; // @[core.scala:173:24] wire iss_uops_3_xcpt_ma_if; // @[core.scala:173:24] wire iss_uops_3_xcpt_ae_if; // @[core.scala:173:24] wire iss_uops_3_xcpt_pf_if; // @[core.scala:173:24] wire iss_uops_3_fp_single; // @[core.scala:173:24] wire iss_uops_3_fp_val; // @[core.scala:173:24] wire iss_uops_3_frs3_en; // @[core.scala:173:24] wire [1:0] iss_uops_3_lrs2_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_3_lrs1_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_3_dst_rtype; // @[core.scala:173:24] wire iss_uops_3_ldst_val; // @[core.scala:173:24] wire [5:0] iss_uops_3_lrs3; // @[core.scala:173:24] wire [5:0] iss_uops_3_lrs2; // @[core.scala:173:24] wire [5:0] iss_uops_3_lrs1; // @[core.scala:173:24] wire [5:0] iss_uops_3_ldst; // @[core.scala:173:24] wire iss_uops_3_ldst_is_rs1; // @[core.scala:173:24] wire iss_uops_3_flush_on_commit; // @[core.scala:173:24] wire iss_uops_3_is_unique; // @[core.scala:173:24] wire iss_uops_3_is_sys_pc2epc; // @[core.scala:173:24] wire iss_uops_3_uses_stq; // @[core.scala:173:24] wire iss_uops_3_uses_ldq; // @[core.scala:173:24] wire iss_uops_3_is_amo; // @[core.scala:173:24] wire iss_uops_3_is_fencei; // @[core.scala:173:24] wire iss_uops_3_is_fence; // @[core.scala:173:24] wire iss_uops_3_mem_signed; // @[core.scala:173:24] wire [1:0] iss_uops_3_mem_size; // @[core.scala:173:24] wire [4:0] iss_uops_3_mem_cmd; // @[core.scala:173:24] wire iss_uops_3_bypassable; // @[core.scala:173:24] wire [63:0] iss_uops_3_exc_cause; // @[core.scala:173:24] wire iss_uops_3_exception; // @[core.scala:173:24] wire [6:0] iss_uops_3_stale_pdst; // @[core.scala:173:24] wire iss_uops_3_ppred_busy; // @[core.scala:173:24] wire iss_uops_3_prs3_busy; // @[core.scala:173:24] wire iss_uops_3_prs2_busy; // @[core.scala:173:24] wire iss_uops_3_prs1_busy; // @[core.scala:173:24] wire [4:0] iss_uops_3_ppred; // @[core.scala:173:24] wire [6:0] iss_uops_3_prs3; // @[core.scala:173:24] wire [6:0] iss_uops_3_prs2; // @[core.scala:173:24] wire [6:0] iss_uops_3_prs1; // @[core.scala:173:24] wire [6:0] iss_uops_3_pdst; // @[core.scala:173:24] wire [1:0] iss_uops_3_rxq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_3_stq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_3_ldq_idx; // @[core.scala:173:24] wire [6:0] iss_uops_3_rob_idx; // @[core.scala:173:24] wire [11:0] iss_uops_3_csr_addr; // @[core.scala:173:24] wire [19:0] iss_uops_3_imm_packed; // @[core.scala:173:24] wire iss_uops_3_taken; // @[core.scala:173:24] wire [5:0] iss_uops_3_pc_lob; // @[core.scala:173:24] wire iss_uops_3_edge_inst; // @[core.scala:173:24] wire [4:0] iss_uops_3_ftq_idx; // @[core.scala:173:24] wire [3:0] iss_uops_3_br_tag; // @[core.scala:173:24] wire [15:0] iss_uops_3_br_mask; // @[core.scala:173:24] wire iss_uops_3_is_sfb; // @[core.scala:173:24] wire iss_uops_3_is_jal; // @[core.scala:173:24] wire iss_uops_3_is_jalr; // @[core.scala:173:24] wire iss_uops_3_is_br; // @[core.scala:173:24] wire iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24] wire iss_uops_3_iw_p1_poisoned; // @[core.scala:173:24] wire [1:0] iss_uops_3_iw_state; // @[core.scala:173:24] wire [9:0] iss_uops_3_fu_code; // @[core.scala:173:24] wire [2:0] iss_uops_3_iq_type; // @[core.scala:173:24] wire [39:0] iss_uops_3_debug_pc; // @[core.scala:173:24] wire iss_uops_3_is_rvc; // @[core.scala:173:24] wire [31:0] iss_uops_3_debug_inst; // @[core.scala:173:24] wire [31:0] iss_uops_3_inst; // @[core.scala:173:24] wire [6:0] iss_uops_3_uopc; // @[core.scala:173:24] wire iss_uops_3_ctrl_is_std; // @[core.scala:173:24] wire iss_uops_3_ctrl_is_sta; // @[core.scala:173:24] wire iss_uops_3_ctrl_is_load; // @[core.scala:173:24] wire [2:0] iss_uops_3_ctrl_csr_cmd; // @[core.scala:173:24] wire iss_uops_3_ctrl_fcn_dw; // @[core.scala:173:24] wire [4:0] iss_uops_3_ctrl_op_fcn; // @[core.scala:173:24] wire [2:0] iss_uops_3_ctrl_imm_sel; // @[core.scala:173:24] wire [2:0] iss_uops_3_ctrl_op2_sel; // @[core.scala:173:24] wire [1:0] iss_uops_3_ctrl_op1_sel; // @[core.scala:173:24] wire [3:0] iss_uops_3_ctrl_br_type; // @[core.scala:173:24] wire [1:0] iss_uops_2_debug_tsrc; // @[core.scala:173:24] wire [1:0] iss_uops_2_debug_fsrc; // @[core.scala:173:24] wire iss_uops_2_bp_xcpt_if; // @[core.scala:173:24] wire iss_uops_2_bp_debug_if; // @[core.scala:173:24] wire iss_uops_2_xcpt_ma_if; // @[core.scala:173:24] wire iss_uops_2_xcpt_ae_if; // @[core.scala:173:24] wire iss_uops_2_xcpt_pf_if; // @[core.scala:173:24] wire iss_uops_2_fp_single; // @[core.scala:173:24] wire iss_uops_2_fp_val; // @[core.scala:173:24] wire iss_uops_2_frs3_en; // @[core.scala:173:24] wire [1:0] iss_uops_2_lrs2_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_2_lrs1_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_2_dst_rtype; // @[core.scala:173:24] wire iss_uops_2_ldst_val; // @[core.scala:173:24] wire [5:0] iss_uops_2_lrs3; // @[core.scala:173:24] wire [5:0] iss_uops_2_lrs2; // @[core.scala:173:24] wire [5:0] iss_uops_2_lrs1; // @[core.scala:173:24] wire [5:0] iss_uops_2_ldst; // @[core.scala:173:24] wire iss_uops_2_ldst_is_rs1; // @[core.scala:173:24] wire iss_uops_2_flush_on_commit; // @[core.scala:173:24] wire iss_uops_2_is_unique; // @[core.scala:173:24] wire iss_uops_2_is_sys_pc2epc; // @[core.scala:173:24] wire iss_uops_2_uses_stq; // @[core.scala:173:24] wire iss_uops_2_uses_ldq; // @[core.scala:173:24] wire iss_uops_2_is_amo; // @[core.scala:173:24] wire iss_uops_2_is_fencei; // @[core.scala:173:24] wire iss_uops_2_is_fence; // @[core.scala:173:24] wire iss_uops_2_mem_signed; // @[core.scala:173:24] wire [1:0] iss_uops_2_mem_size; // @[core.scala:173:24] wire [4:0] iss_uops_2_mem_cmd; // @[core.scala:173:24] wire iss_uops_2_bypassable; // @[core.scala:173:24] wire [63:0] iss_uops_2_exc_cause; // @[core.scala:173:24] wire iss_uops_2_exception; // @[core.scala:173:24] wire [6:0] iss_uops_2_stale_pdst; // @[core.scala:173:24] wire iss_uops_2_ppred_busy; // @[core.scala:173:24] wire iss_uops_2_prs3_busy; // @[core.scala:173:24] wire iss_uops_2_prs2_busy; // @[core.scala:173:24] wire iss_uops_2_prs1_busy; // @[core.scala:173:24] wire [4:0] iss_uops_2_ppred; // @[core.scala:173:24] wire [6:0] iss_uops_2_prs3; // @[core.scala:173:24] wire [6:0] iss_uops_2_prs2; // @[core.scala:173:24] wire [6:0] iss_uops_2_prs1; // @[core.scala:173:24] wire [6:0] iss_uops_2_pdst; // @[core.scala:173:24] wire [1:0] iss_uops_2_rxq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_2_stq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_2_ldq_idx; // @[core.scala:173:24] wire [6:0] iss_uops_2_rob_idx; // @[core.scala:173:24] wire [11:0] iss_uops_2_csr_addr; // @[core.scala:173:24] wire [19:0] iss_uops_2_imm_packed; // @[core.scala:173:24] wire iss_uops_2_taken; // @[core.scala:173:24] wire [5:0] iss_uops_2_pc_lob; // @[core.scala:173:24] wire iss_uops_2_edge_inst; // @[core.scala:173:24] wire [4:0] iss_uops_2_ftq_idx; // @[core.scala:173:24] wire [3:0] iss_uops_2_br_tag; // @[core.scala:173:24] wire [15:0] iss_uops_2_br_mask; // @[core.scala:173:24] wire iss_uops_2_is_sfb; // @[core.scala:173:24] wire iss_uops_2_is_jal; // @[core.scala:173:24] wire iss_uops_2_is_jalr; // @[core.scala:173:24] wire iss_uops_2_is_br; // @[core.scala:173:24] wire iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24] wire iss_uops_2_iw_p1_poisoned; // @[core.scala:173:24] wire [1:0] iss_uops_2_iw_state; // @[core.scala:173:24] wire [9:0] iss_uops_2_fu_code; // @[core.scala:173:24] wire [2:0] iss_uops_2_iq_type; // @[core.scala:173:24] wire [39:0] iss_uops_2_debug_pc; // @[core.scala:173:24] wire iss_uops_2_is_rvc; // @[core.scala:173:24] wire [31:0] iss_uops_2_debug_inst; // @[core.scala:173:24] wire [31:0] iss_uops_2_inst; // @[core.scala:173:24] wire [6:0] iss_uops_2_uopc; // @[core.scala:173:24] wire iss_uops_2_ctrl_is_std; // @[core.scala:173:24] wire iss_uops_2_ctrl_is_sta; // @[core.scala:173:24] wire iss_uops_2_ctrl_is_load; // @[core.scala:173:24] wire [2:0] iss_uops_2_ctrl_csr_cmd; // @[core.scala:173:24] wire iss_uops_2_ctrl_fcn_dw; // @[core.scala:173:24] wire [4:0] iss_uops_2_ctrl_op_fcn; // @[core.scala:173:24] wire [2:0] iss_uops_2_ctrl_imm_sel; // @[core.scala:173:24] wire [2:0] iss_uops_2_ctrl_op2_sel; // @[core.scala:173:24] wire [1:0] iss_uops_2_ctrl_op1_sel; // @[core.scala:173:24] wire [3:0] iss_uops_2_ctrl_br_type; // @[core.scala:173:24] wire dis_valids_0; // @[core.scala:166:24] wire io_ifu_sfence_bits_asid_0; // @[core.scala:51:7] wire [38:0] io_ifu_sfence_bits_addr_0; // @[core.scala:51:7] wire io_ifu_sfence_bits_rs2_0; // @[core.scala:51:7] wire io_ifu_sfence_bits_rs1_0; // @[core.scala:51:7] wire io_ifu_sfence_valid_0; // @[core.scala:51:7] wire [63:0] _csr_io_rw_rdata; // @[core.scala:271:19] wire _csr_io_decode_0_fp_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_fp_csr; // @[core.scala:271:19] wire _csr_io_decode_0_read_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_write_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_write_flush; // @[core.scala:271:19] wire _csr_io_decode_0_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_virtual_access_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_virtual_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_fp_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_fp_csr; // @[core.scala:271:19] wire _csr_io_decode_1_read_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_write_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_write_flush; // @[core.scala:271:19] wire _csr_io_decode_1_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_virtual_access_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_virtual_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_fp_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_fp_csr; // @[core.scala:271:19] wire _csr_io_decode_2_read_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_write_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_write_flush; // @[core.scala:271:19] wire _csr_io_decode_2_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_virtual_access_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_virtual_system_illegal; // @[core.scala:271:19] wire _csr_io_csr_stall; // @[core.scala:271:19] wire _csr_io_singleStep; // @[core.scala:271:19] wire _csr_io_status_debug; // @[core.scala:271:19] wire _csr_io_status_cease; // @[core.scala:271:19] wire _csr_io_status_wfi; // @[core.scala:271:19] wire [1:0] _csr_io_status_dprv; // @[core.scala:271:19] wire _csr_io_status_dv; // @[core.scala:271:19] wire [1:0] _csr_io_status_prv; // @[core.scala:271:19] wire _csr_io_status_v; // @[core.scala:271:19] wire _csr_io_status_sd; // @[core.scala:271:19] wire _csr_io_status_mpv; // @[core.scala:271:19] wire _csr_io_status_gva; // @[core.scala:271:19] wire _csr_io_status_tsr; // @[core.scala:271:19] wire _csr_io_status_tw; // @[core.scala:271:19] wire _csr_io_status_tvm; // @[core.scala:271:19] wire _csr_io_status_mxr; // @[core.scala:271:19] wire _csr_io_status_sum; // @[core.scala:271:19] wire _csr_io_status_mprv; // @[core.scala:271:19] wire [1:0] _csr_io_status_fs; // @[core.scala:271:19] wire [1:0] _csr_io_status_mpp; // @[core.scala:271:19] wire _csr_io_status_spp; // @[core.scala:271:19] wire _csr_io_status_mpie; // @[core.scala:271:19] wire _csr_io_status_spie; // @[core.scala:271:19] wire _csr_io_status_mie; // @[core.scala:271:19] wire _csr_io_status_sie; // @[core.scala:271:19] wire [39:0] _csr_io_evec; // @[core.scala:271:19] wire [2:0] _csr_io_fcsr_rm; // @[core.scala:271:19] wire _csr_io_interrupt; // @[core.scala:271:19] wire [63:0] _csr_io_interrupt_cause; // @[core.scala:271:19] wire [6:0] _rob_io_rob_tail_idx; // @[core.scala:143:32] wire [6:0] _rob_io_rob_head_idx; // @[core.scala:143:32] wire _rob_io_commit_valids_0; // @[core.scala:143:32] wire _rob_io_commit_valids_1; // @[core.scala:143:32] wire _rob_io_commit_valids_2; // @[core.scala:143:32] wire _rob_io_commit_arch_valids_0; // @[core.scala:143:32] wire _rob_io_commit_arch_valids_1; // @[core.scala:143:32] wire _rob_io_commit_arch_valids_2; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_uopc; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_0_inst; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_0_debug_inst; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_rvc; // @[core.scala:143:32] wire [39:0] _rob_io_commit_uops_0_debug_pc; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_0_iq_type; // @[core.scala:143:32] wire [9:0] _rob_io_commit_uops_0_fu_code; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_0_ctrl_br_type; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_ctrl_op1_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_0_ctrl_op2_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_0_ctrl_imm_sel; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_ctrl_op_fcn; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ctrl_fcn_dw; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_0_ctrl_csr_cmd; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ctrl_is_load; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ctrl_is_sta; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ctrl_is_std; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_iw_state; // @[core.scala:143:32] wire _rob_io_commit_uops_0_iw_p1_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_0_iw_p2_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_br; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_sfb; // @[core.scala:143:32] wire [15:0] _rob_io_commit_uops_0_br_mask; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_0_br_tag; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_ftq_idx; // @[core.scala:143:32] wire _rob_io_commit_uops_0_edge_inst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_pc_lob; // @[core.scala:143:32] wire _rob_io_commit_uops_0_taken; // @[core.scala:143:32] wire [19:0] _rob_io_commit_uops_0_imm_packed; // @[core.scala:143:32] wire [11:0] _rob_io_commit_uops_0_csr_addr; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_rob_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_ldq_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_stq_idx; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_rxq_idx; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_pdst; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_prs1; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_prs2; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_prs3; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_ppred; // @[core.scala:143:32] wire _rob_io_commit_uops_0_prs1_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_0_prs2_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_0_prs3_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ppred_busy; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_stale_pdst; // @[core.scala:143:32] wire _rob_io_commit_uops_0_exception; // @[core.scala:143:32] wire [63:0] _rob_io_commit_uops_0_exc_cause; // @[core.scala:143:32] wire _rob_io_commit_uops_0_bypassable; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_mem_cmd; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_mem_size; // @[core.scala:143:32] wire _rob_io_commit_uops_0_mem_signed; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_fence; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_fencei; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_amo; // @[core.scala:143:32] wire _rob_io_commit_uops_0_uses_ldq; // @[core.scala:143:32] wire _rob_io_commit_uops_0_uses_stq; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_sys_pc2epc; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_unique; // @[core.scala:143:32] wire _rob_io_commit_uops_0_flush_on_commit; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ldst_is_rs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_ldst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_lrs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_lrs2; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_lrs3; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ldst_val; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_dst_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_lrs1_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_lrs2_rtype; // @[core.scala:143:32] wire _rob_io_commit_uops_0_frs3_en; // @[core.scala:143:32] wire _rob_io_commit_uops_0_fp_val; // @[core.scala:143:32] wire _rob_io_commit_uops_0_fp_single; // @[core.scala:143:32] wire _rob_io_commit_uops_0_xcpt_pf_if; // @[core.scala:143:32] wire _rob_io_commit_uops_0_xcpt_ae_if; // @[core.scala:143:32] wire _rob_io_commit_uops_0_xcpt_ma_if; // @[core.scala:143:32] wire _rob_io_commit_uops_0_bp_debug_if; // @[core.scala:143:32] wire _rob_io_commit_uops_0_bp_xcpt_if; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_debug_tsrc; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_uopc; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_1_inst; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_1_debug_inst; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_rvc; // @[core.scala:143:32] wire [39:0] _rob_io_commit_uops_1_debug_pc; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_1_iq_type; // @[core.scala:143:32] wire [9:0] _rob_io_commit_uops_1_fu_code; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_1_ctrl_br_type; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_ctrl_op1_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_1_ctrl_op2_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_1_ctrl_imm_sel; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_ctrl_op_fcn; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ctrl_fcn_dw; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_1_ctrl_csr_cmd; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ctrl_is_load; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ctrl_is_sta; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ctrl_is_std; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_iw_state; // @[core.scala:143:32] wire _rob_io_commit_uops_1_iw_p1_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_1_iw_p2_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_br; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_sfb; // @[core.scala:143:32] wire [15:0] _rob_io_commit_uops_1_br_mask; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_1_br_tag; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_ftq_idx; // @[core.scala:143:32] wire _rob_io_commit_uops_1_edge_inst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_pc_lob; // @[core.scala:143:32] wire _rob_io_commit_uops_1_taken; // @[core.scala:143:32] wire [19:0] _rob_io_commit_uops_1_imm_packed; // @[core.scala:143:32] wire [11:0] _rob_io_commit_uops_1_csr_addr; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_rob_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_ldq_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_stq_idx; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_rxq_idx; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_pdst; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_prs1; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_prs2; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_prs3; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_ppred; // @[core.scala:143:32] wire _rob_io_commit_uops_1_prs1_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_1_prs2_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_1_prs3_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ppred_busy; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_stale_pdst; // @[core.scala:143:32] wire _rob_io_commit_uops_1_exception; // @[core.scala:143:32] wire [63:0] _rob_io_commit_uops_1_exc_cause; // @[core.scala:143:32] wire _rob_io_commit_uops_1_bypassable; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_mem_cmd; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_mem_size; // @[core.scala:143:32] wire _rob_io_commit_uops_1_mem_signed; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_fence; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_fencei; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_amo; // @[core.scala:143:32] wire _rob_io_commit_uops_1_uses_ldq; // @[core.scala:143:32] wire _rob_io_commit_uops_1_uses_stq; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_sys_pc2epc; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_unique; // @[core.scala:143:32] wire _rob_io_commit_uops_1_flush_on_commit; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ldst_is_rs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_ldst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_lrs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_lrs2; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_lrs3; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ldst_val; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_dst_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_lrs1_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_lrs2_rtype; // @[core.scala:143:32] wire _rob_io_commit_uops_1_frs3_en; // @[core.scala:143:32] wire _rob_io_commit_uops_1_fp_val; // @[core.scala:143:32] wire _rob_io_commit_uops_1_fp_single; // @[core.scala:143:32] wire _rob_io_commit_uops_1_xcpt_pf_if; // @[core.scala:143:32] wire _rob_io_commit_uops_1_xcpt_ae_if; // @[core.scala:143:32] wire _rob_io_commit_uops_1_xcpt_ma_if; // @[core.scala:143:32] wire _rob_io_commit_uops_1_bp_debug_if; // @[core.scala:143:32] wire _rob_io_commit_uops_1_bp_xcpt_if; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_debug_tsrc; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_uopc; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_2_inst; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_2_debug_inst; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_rvc; // @[core.scala:143:32] wire [39:0] _rob_io_commit_uops_2_debug_pc; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_2_iq_type; // @[core.scala:143:32] wire [9:0] _rob_io_commit_uops_2_fu_code; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_2_ctrl_br_type; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_ctrl_op1_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_2_ctrl_op2_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_2_ctrl_imm_sel; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_ctrl_op_fcn; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ctrl_fcn_dw; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_2_ctrl_csr_cmd; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ctrl_is_load; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ctrl_is_sta; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ctrl_is_std; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_iw_state; // @[core.scala:143:32] wire _rob_io_commit_uops_2_iw_p1_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_2_iw_p2_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_br; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_sfb; // @[core.scala:143:32] wire [15:0] _rob_io_commit_uops_2_br_mask; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_2_br_tag; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_ftq_idx; // @[core.scala:143:32] wire _rob_io_commit_uops_2_edge_inst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_pc_lob; // @[core.scala:143:32] wire _rob_io_commit_uops_2_taken; // @[core.scala:143:32] wire [19:0] _rob_io_commit_uops_2_imm_packed; // @[core.scala:143:32] wire [11:0] _rob_io_commit_uops_2_csr_addr; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_rob_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_ldq_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_stq_idx; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_rxq_idx; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_pdst; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_prs1; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_prs2; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_prs3; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_ppred; // @[core.scala:143:32] wire _rob_io_commit_uops_2_prs1_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_2_prs2_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_2_prs3_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ppred_busy; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_stale_pdst; // @[core.scala:143:32] wire _rob_io_commit_uops_2_exception; // @[core.scala:143:32] wire [63:0] _rob_io_commit_uops_2_exc_cause; // @[core.scala:143:32] wire _rob_io_commit_uops_2_bypassable; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_mem_cmd; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_mem_size; // @[core.scala:143:32] wire _rob_io_commit_uops_2_mem_signed; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_fence; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_fencei; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_amo; // @[core.scala:143:32] wire _rob_io_commit_uops_2_uses_ldq; // @[core.scala:143:32] wire _rob_io_commit_uops_2_uses_stq; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_sys_pc2epc; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_unique; // @[core.scala:143:32] wire _rob_io_commit_uops_2_flush_on_commit; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ldst_is_rs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_ldst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_lrs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_lrs2; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_lrs3; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ldst_val; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_dst_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_lrs1_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_lrs2_rtype; // @[core.scala:143:32] wire _rob_io_commit_uops_2_frs3_en; // @[core.scala:143:32] wire _rob_io_commit_uops_2_fp_val; // @[core.scala:143:32] wire _rob_io_commit_uops_2_fp_single; // @[core.scala:143:32] wire _rob_io_commit_uops_2_xcpt_pf_if; // @[core.scala:143:32] wire _rob_io_commit_uops_2_xcpt_ae_if; // @[core.scala:143:32] wire _rob_io_commit_uops_2_xcpt_ma_if; // @[core.scala:143:32] wire _rob_io_commit_uops_2_bp_debug_if; // @[core.scala:143:32] wire _rob_io_commit_uops_2_bp_xcpt_if; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_debug_tsrc; // @[core.scala:143:32] wire _rob_io_commit_fflags_valid; // @[core.scala:143:32] wire [4:0] _rob_io_commit_fflags_bits; // @[core.scala:143:32] wire _rob_io_commit_rbk_valids_0; // @[core.scala:143:32] wire _rob_io_commit_rbk_valids_1; // @[core.scala:143:32] wire _rob_io_commit_rbk_valids_2; // @[core.scala:143:32] wire _rob_io_commit_rollback; // @[core.scala:143:32] wire _rob_io_com_xcpt_valid; // @[core.scala:143:32] wire [4:0] _rob_io_com_xcpt_bits_ftq_idx; // @[core.scala:143:32] wire _rob_io_com_xcpt_bits_edge_inst; // @[core.scala:143:32] wire [5:0] _rob_io_com_xcpt_bits_pc_lob; // @[core.scala:143:32] wire [63:0] _rob_io_com_xcpt_bits_cause; // @[core.scala:143:32] wire [63:0] _rob_io_com_xcpt_bits_badvaddr; // @[core.scala:143:32] wire _rob_io_flush_valid; // @[core.scala:143:32] wire [4:0] _rob_io_flush_bits_ftq_idx; // @[core.scala:143:32] wire _rob_io_flush_bits_edge_inst; // @[core.scala:143:32] wire _rob_io_flush_bits_is_rvc; // @[core.scala:143:32] wire [5:0] _rob_io_flush_bits_pc_lob; // @[core.scala:143:32] wire [2:0] _rob_io_flush_bits_flush_typ; // @[core.scala:143:32] wire _rob_io_empty; // @[core.scala:143:32] wire _rob_io_ready; // @[core.scala:143:32] wire _rob_io_flush_frontend; // @[core.scala:143:32] wire [6:0] _iregister_read_io_rf_read_ports_0_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_1_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_2_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_3_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_4_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_5_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_6_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_7_addr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_valid; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_uopc; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_inst; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_inst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_rvc; // @[core.scala:135:32] wire [39:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_pc; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_iq_type; // @[core.scala:135:32] wire [9:0] _iregister_read_io_exe_reqs_0_bits_uop_fu_code; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_br_type; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op1_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op2_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_imm_sel; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op_fcn; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_load; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_sta; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_std; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_iw_state; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p1_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p2_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_br; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_jalr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_jal; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_sfb; // @[core.scala:135:32] wire [15:0] _iregister_read_io_exe_reqs_0_bits_uop_br_mask; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_br_tag; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ftq_idx; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_edge_inst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_pc_lob; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_taken; // @[core.scala:135:32] wire [19:0] _iregister_read_io_exe_reqs_0_bits_uop_imm_packed; // @[core.scala:135:32] wire [11:0] _iregister_read_io_exe_reqs_0_bits_uop_csr_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_rob_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ldq_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_stq_idx; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_rxq_idx; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_pdst; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs1; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs2; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs3; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ppred; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_prs1_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_prs2_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_prs3_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ppred_busy; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_stale_pdst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_exception; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_0_bits_uop_exc_cause; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_bypassable; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_cmd; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_size; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_mem_signed; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_fence; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_fencei; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_amo; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_uses_ldq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_uses_stq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_sys_pc2epc; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_unique; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_flush_on_commit; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_is_rs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_ldst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs3; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_val; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_dst_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2_rtype; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_frs3_en; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_fp_val; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_fp_single; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_pf_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ae_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ma_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_bp_debug_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_bp_xcpt_if; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_fsrc; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_tsrc; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs1_data; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs2_data; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_valid; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_uopc; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_inst; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_inst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_rvc; // @[core.scala:135:32] wire [39:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_pc; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_iq_type; // @[core.scala:135:32] wire [9:0] _iregister_read_io_exe_reqs_1_bits_uop_fu_code; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_br_type; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op1_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op2_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_imm_sel; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op_fcn; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_load; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_sta; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_std; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_iw_state; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p1_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p2_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_br; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_jalr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_jal; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_sfb; // @[core.scala:135:32] wire [15:0] _iregister_read_io_exe_reqs_1_bits_uop_br_mask; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_br_tag; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ftq_idx; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_edge_inst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_pc_lob; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_taken; // @[core.scala:135:32] wire [19:0] _iregister_read_io_exe_reqs_1_bits_uop_imm_packed; // @[core.scala:135:32] wire [11:0] _iregister_read_io_exe_reqs_1_bits_uop_csr_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_rob_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ldq_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_stq_idx; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_rxq_idx; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_pdst; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs1; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs2; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs3; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ppred; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_prs1_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_prs2_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_prs3_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ppred_busy; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_stale_pdst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_exception; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_1_bits_uop_exc_cause; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_bypassable; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_cmd; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_size; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_mem_signed; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_fence; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_fencei; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_amo; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_uses_ldq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_uses_stq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_sys_pc2epc; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_unique; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_flush_on_commit; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_is_rs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_ldst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs3; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_val; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_dst_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2_rtype; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_frs3_en; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_fp_val; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_fp_single; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_pf_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ae_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ma_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_bp_debug_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_bp_xcpt_if; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_fsrc; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_tsrc; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs1_data; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs2_data; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_valid; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_uopc; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_2_bits_uop_inst; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_inst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_rvc; // @[core.scala:135:32] wire [39:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_pc; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_iq_type; // @[core.scala:135:32] wire [9:0] _iregister_read_io_exe_reqs_2_bits_uop_fu_code; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_br_type; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op1_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op2_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_imm_sel; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op_fcn; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_load; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_sta; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_std; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_iw_state; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_iw_p1_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_iw_p2_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_br; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_jalr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_jal; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_sfb; // @[core.scala:135:32] wire [15:0] _iregister_read_io_exe_reqs_2_bits_uop_br_mask; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_2_bits_uop_br_tag; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ftq_idx; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_edge_inst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_pc_lob; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_taken; // @[core.scala:135:32] wire [19:0] _iregister_read_io_exe_reqs_2_bits_uop_imm_packed; // @[core.scala:135:32] wire [11:0] _iregister_read_io_exe_reqs_2_bits_uop_csr_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_rob_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ldq_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_stq_idx; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_rxq_idx; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_pdst; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs1; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs2; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs3; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ppred; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_prs1_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_prs2_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_prs3_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ppred_busy; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_stale_pdst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_exception; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_2_bits_uop_exc_cause; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_bypassable; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_mem_cmd; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_mem_size; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_mem_signed; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_fence; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_fencei; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_amo; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_uses_ldq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_uses_stq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_sys_pc2epc; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_unique; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_flush_on_commit; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ldst_is_rs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_ldst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs2; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs3; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ldst_val; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_dst_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs1_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs2_rtype; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_frs3_en; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_fp_val; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_fp_single; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_pf_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_ae_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_ma_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_bp_debug_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_bp_xcpt_if; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_fsrc; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_tsrc; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_2_bits_rs1_data; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_2_bits_rs2_data; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_valid; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_uopc; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_3_bits_uop_inst; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_inst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_rvc; // @[core.scala:135:32] wire [39:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_pc; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_iq_type; // @[core.scala:135:32] wire [9:0] _iregister_read_io_exe_reqs_3_bits_uop_fu_code; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_br_type; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op1_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op2_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_imm_sel; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op_fcn; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_load; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_sta; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_std; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_iw_state; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_iw_p1_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_iw_p2_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_br; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_jalr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_jal; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_sfb; // @[core.scala:135:32] wire [15:0] _iregister_read_io_exe_reqs_3_bits_uop_br_mask; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_3_bits_uop_br_tag; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ftq_idx; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_edge_inst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_pc_lob; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_taken; // @[core.scala:135:32] wire [19:0] _iregister_read_io_exe_reqs_3_bits_uop_imm_packed; // @[core.scala:135:32] wire [11:0] _iregister_read_io_exe_reqs_3_bits_uop_csr_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_rob_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ldq_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_stq_idx; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_rxq_idx; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_pdst; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs1; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs2; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs3; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ppred; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_prs1_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_prs2_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_prs3_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ppred_busy; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_stale_pdst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_exception; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_3_bits_uop_exc_cause; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_bypassable; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_mem_cmd; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_mem_size; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_mem_signed; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_fence; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_fencei; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_amo; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_uses_ldq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_uses_stq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_sys_pc2epc; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_unique; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_flush_on_commit; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ldst_is_rs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_ldst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs2; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs3; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ldst_val; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_dst_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs1_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs2_rtype; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_frs3_en; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_fp_val; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_fp_single; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_pf_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_ae_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_ma_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_bp_debug_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_bp_xcpt_if; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_fsrc; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_tsrc; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_3_bits_rs1_data; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_3_bits_rs2_data; // @[core.scala:135:32] wire _ll_wbarb_io_in_1_ready; // @[core.scala:132:32] wire _ll_wbarb_io_out_valid; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_uopc; // @[core.scala:132:32] wire [31:0] _ll_wbarb_io_out_bits_uop_inst; // @[core.scala:132:32] wire [31:0] _ll_wbarb_io_out_bits_uop_debug_inst; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_rvc; // @[core.scala:132:32] wire [39:0] _ll_wbarb_io_out_bits_uop_debug_pc; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_uop_iq_type; // @[core.scala:132:32] wire [9:0] _ll_wbarb_io_out_bits_uop_fu_code; // @[core.scala:132:32] wire [3:0] _ll_wbarb_io_out_bits_uop_ctrl_br_type; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_ctrl_op1_sel; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_op2_sel; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_imm_sel; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_ctrl_op_fcn; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ctrl_fcn_dw; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_csr_cmd; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ctrl_is_load; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ctrl_is_sta; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ctrl_is_std; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_iw_state; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_iw_p1_poisoned; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_iw_p2_poisoned; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_br; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_jalr; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_jal; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_sfb; // @[core.scala:132:32] wire [15:0] _ll_wbarb_io_out_bits_uop_br_mask; // @[core.scala:132:32] wire [3:0] _ll_wbarb_io_out_bits_uop_br_tag; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_ftq_idx; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_edge_inst; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_pc_lob; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_taken; // @[core.scala:132:32] wire [19:0] _ll_wbarb_io_out_bits_uop_imm_packed; // @[core.scala:132:32] wire [11:0] _ll_wbarb_io_out_bits_uop_csr_addr; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_rob_idx; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_ldq_idx; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_stq_idx; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_rxq_idx; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_pdst; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_prs1; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_prs2; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_prs3; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_ppred; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_prs1_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_prs2_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_prs3_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ppred_busy; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_stale_pdst; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_exception; // @[core.scala:132:32] wire [63:0] _ll_wbarb_io_out_bits_uop_exc_cause; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_bypassable; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_mem_cmd; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_mem_size; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_mem_signed; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_fence; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_fencei; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_amo; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_uses_ldq; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_uses_stq; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_sys_pc2epc; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_unique; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_flush_on_commit; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ldst_is_rs1; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_ldst; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_lrs1; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_lrs2; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_lrs3; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ldst_val; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_dst_rtype; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_lrs1_rtype; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_lrs2_rtype; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_frs3_en; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_fp_val; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_fp_single; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_xcpt_pf_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_xcpt_ae_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_xcpt_ma_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_bp_debug_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_bp_xcpt_if; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_debug_fsrc; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_debug_tsrc; // @[core.scala:132:32] wire [63:0] _ll_wbarb_io_out_bits_data; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_predicated; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_valid; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_uopc; // @[core.scala:132:32] wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_inst; // @[core.scala:132:32] wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_inst; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_rvc; // @[core.scala:132:32] wire [39:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_pc; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iq_type; // @[core.scala:132:32] wire [9:0] _ll_wbarb_io_out_bits_fflags_bits_uop_fu_code; // @[core.scala:132:32] wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iw_state; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_br; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jalr; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jal; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sfb; // @[core.scala:132:32] wire [15:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_mask; // @[core.scala:132:32] wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_tag; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ftq_idx; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_edge_inst; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pc_lob; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_taken; // @[core.scala:132:32] wire [19:0] _ll_wbarb_io_out_bits_fflags_bits_uop_imm_packed; // @[core.scala:132:32] wire [11:0] _ll_wbarb_io_out_bits_fflags_bits_uop_csr_addr; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rob_idx; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldq_idx; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stq_idx; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rxq_idx; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pdst; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs1; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs2; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs3; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ppred; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs1_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs2_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs3_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ppred_busy; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stale_pdst; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_exception; // @[core.scala:132:32] wire [63:0] _ll_wbarb_io_out_bits_fflags_bits_uop_exc_cause; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_bypassable; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_cmd; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_size; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_mem_signed; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fence; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fencei; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_amo; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_ldq; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_stq; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_unique; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldst; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs3; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_val; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_dst_rtype; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_frs3_en; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_val; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_single; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_flags; // @[core.scala:132:32] wire [63:0] _iregfile_io_read_ports_0_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_1_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_2_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_3_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_4_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_5_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_6_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_7_data; // @[core.scala:116:32] wire _dispatcher_io_ren_uops_0_ready; // @[core.scala:114:32] wire _dispatcher_io_ren_uops_1_ready; // @[core.scala:114:32] wire _dispatcher_io_ren_uops_2_ready; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_0_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_0_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_2_0_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_2_0_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_2_0_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_0_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_2_0_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_2_0_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_2_0_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_1_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_1_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_2_1_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_2_1_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_2_1_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_1_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_2_1_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_2_1_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_2_1_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_2_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_2_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_2_2_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_2_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_2_2_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_2_2_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_2_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_2_2_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_2_2_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_2_2_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_0_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_0_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_1_0_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_1_0_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_1_0_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_0_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_1_0_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_1_0_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_1_0_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_1_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_1_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_1_1_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_1_1_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_1_1_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_1_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_1_1_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_1_1_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_1_1_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_2_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_2_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_1_2_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_2_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_1_2_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_1_2_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_2_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_1_2_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_1_2_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_1_2_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_0_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_0_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_0_0_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_0_0_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_0_0_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_0_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_0_0_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_0_0_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_0_0_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_1_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_1_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_0_1_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_0_1_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_0_1_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_1_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_0_1_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_0_1_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_0_1_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_2_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_2_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_0_2_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_2_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_0_2_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_0_2_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_2_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_0_2_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_0_2_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_0_2_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_debug_tsrc; // @[core.scala:114:32] wire _int_issue_unit_io_dis_uops_0_ready; // @[core.scala:110:32] wire _int_issue_unit_io_dis_uops_1_ready; // @[core.scala:110:32] wire _int_issue_unit_io_dis_uops_2_ready; // @[core.scala:110:32] wire _mem_issue_unit_io_dis_uops_0_ready; // @[core.scala:108:32] wire _mem_issue_unit_io_dis_uops_1_ready; // @[core.scala:108:32] wire _mem_issue_unit_io_dis_uops_2_ready; // @[core.scala:108:32] wire _mem_issue_unit_io_iss_valids_0; // @[core.scala:108:32] wire _mem_issue_unit_io_iss_uops_0_uses_ldq; // @[core.scala:108:32] wire _fp_rename_stage_io_ren_stalls_0; // @[core.scala:104:46] wire _fp_rename_stage_io_ren_stalls_1; // @[core.scala:104:46] wire _fp_rename_stage_io_ren_stalls_2; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_0_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs1; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs2; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_0_prs3_busy; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_1_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs1; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs2; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_1_prs1_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_1_prs2_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_1_prs3_busy; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_2_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_2_prs1; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_2_prs2; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_2_prs1_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_2_prs2_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_2_prs3_busy; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:104:46] wire _rename_stage_io_ren_stalls_0; // @[core.scala:103:32] wire _rename_stage_io_ren_stalls_1; // @[core.scala:103:32] wire _rename_stage_io_ren_stalls_2; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_0_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_0_prs1; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_1_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_1_prs1; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_1_prs2; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_1_prs1_busy; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_1_prs2_busy; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_2_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_2_prs1; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_2_prs2; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_2_prs1_busy; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_2_prs2_busy; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:103:32] wire [31:0] _decode_units_2_io_csr_decode_inst; // @[core.scala:101:79] wire [31:0] _decode_units_1_io_csr_decode_inst; // @[core.scala:101:79] wire [31:0] _decode_units_0_io_csr_decode_inst; // @[core.scala:101:79] wire _FpPipeline_io_dis_uops_0_ready; // @[core.scala:80:37] wire _FpPipeline_io_dis_uops_1_ready; // @[core.scala:80:37] wire _FpPipeline_io_dis_uops_2_ready; // @[core.scala:80:37] wire _FpPipeline_io_from_int_ready; // @[core.scala:80:37] wire _FpPipeline_io_to_int_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_to_int_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_to_int_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_to_int_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_to_int_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_to_int_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_to_int_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_to_int_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_to_int_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_to_int_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_to_int_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_to_int_bits_data; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_predicated; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_flags; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_wakeups_0_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_wakeups_0_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_wakeups_0_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_wakeups_0_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_wakeups_0_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_wakeups_0_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [64:0] _FpPipeline_io_wakeups_0_bits_data; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_predicated; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_flags; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_wakeups_1_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_wakeups_1_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_wakeups_1_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_wakeups_1_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_wakeups_1_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_wakeups_1_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [64:0] _FpPipeline_io_wakeups_1_bits_data; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_flags; // @[core.scala:80:37] wire [64:0] _FpPipeline_io_debug_wb_wdata_0; // @[core.scala:80:37] wire [64:0] _FpPipeline_io_debug_wb_wdata_1; // @[core.scala:80:37] wire _alu_exe_unit_2_io_iresp_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_2_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_2_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_2_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_2_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_2_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_2_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_2_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_2_io_iresp_bits_data; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_2_io_bypass_0_bits_data; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_2_io_bypass_1_bits_data; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_2_io_bypass_2_bits_data; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_2_io_brinfo_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_2_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_2_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_2_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_2_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_2_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_2_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_2_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_2_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_valid; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_mispredict; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_taken; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_cfi_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_pc_sel; // @[execution-units.scala:119:32] wire [20:0] _alu_exe_unit_2_io_brinfo_target_offset; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_fu_types; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_1_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_1_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_1_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_1_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_1_io_ll_fresp_bits_data; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_predicated; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_flags; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_1_io_bypass_0_bits_data; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_brinfo_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_1_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_1_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_1_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_1_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_1_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_valid; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_mispredict; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_taken; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_cfi_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_pc_sel; // @[execution-units.scala:119:32] wire [20:0] _alu_exe_unit_1_io_brinfo_target_offset; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_io_fu_types; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_io_iresp_bits_data; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_io_bypass_0_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_io_bypass_0_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_io_bypass_0_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_io_bypass_0_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_io_bypass_0_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_io_bypass_0_bits_data; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_brinfo_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_valid; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_mispredict; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_taken; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_cfi_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_pc_sel; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_io_brinfo_jalr_target; // @[execution-units.scala:119:32] wire [20:0] _alu_exe_unit_io_brinfo_target_offset; // @[execution-units.scala:119:32] wire _memExeUnit_io_ll_iresp_valid; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_uopc; // @[execution-units.scala:108:30] wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_inst; // @[execution-units.scala:108:30] wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_debug_inst; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_rvc; // @[execution-units.scala:108:30] wire [39:0] _memExeUnit_io_ll_iresp_bits_uop_debug_pc; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_iq_type; // @[execution-units.scala:108:30] wire [9:0] _memExeUnit_io_ll_iresp_bits_uop_fu_code; // @[execution-units.scala:108:30] wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_iw_state; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_br; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_jalr; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_jal; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_sfb; // @[execution-units.scala:108:30] wire [15:0] _memExeUnit_io_ll_iresp_bits_uop_br_mask; // @[execution-units.scala:108:30] wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_br_tag; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ftq_idx; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_edge_inst; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_pc_lob; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_taken; // @[execution-units.scala:108:30] wire [19:0] _memExeUnit_io_ll_iresp_bits_uop_imm_packed; // @[execution-units.scala:108:30] wire [11:0] _memExeUnit_io_ll_iresp_bits_uop_csr_addr; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_rob_idx; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ldq_idx; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_stq_idx; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_rxq_idx; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_pdst; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs1; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs2; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs3; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ppred; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_prs1_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_prs2_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_prs3_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ppred_busy; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_stale_pdst; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_exception; // @[execution-units.scala:108:30] wire [63:0] _memExeUnit_io_ll_iresp_bits_uop_exc_cause; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_bypassable; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_mem_cmd; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_mem_size; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_mem_signed; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_fence; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_fencei; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_amo; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_uses_ldq; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_uses_stq; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_unique; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_ldst; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs3; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ldst_val; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_dst_rtype; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_frs3_en; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_fp_val; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_fp_single; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:108:30] wire [64:0] _memExeUnit_io_ll_iresp_bits_data; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_valid; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_uopc; // @[execution-units.scala:108:30] wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_inst; // @[execution-units.scala:108:30] wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_debug_inst; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_rvc; // @[execution-units.scala:108:30] wire [39:0] _memExeUnit_io_ll_fresp_bits_uop_debug_pc; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_iq_type; // @[execution-units.scala:108:30] wire [9:0] _memExeUnit_io_ll_fresp_bits_uop_fu_code; // @[execution-units.scala:108:30] wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_br_type; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_load; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_std; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_iw_state; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_br; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_jalr; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_jal; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_sfb; // @[execution-units.scala:108:30] wire [15:0] _memExeUnit_io_ll_fresp_bits_uop_br_mask; // @[execution-units.scala:108:30] wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_br_tag; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ftq_idx; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_edge_inst; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_pc_lob; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_taken; // @[execution-units.scala:108:30] wire [19:0] _memExeUnit_io_ll_fresp_bits_uop_imm_packed; // @[execution-units.scala:108:30] wire [11:0] _memExeUnit_io_ll_fresp_bits_uop_csr_addr; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_rob_idx; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ldq_idx; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_stq_idx; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_rxq_idx; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_pdst; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs1; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs2; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs3; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ppred; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_prs1_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_prs2_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_prs3_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ppred_busy; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_stale_pdst; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_exception; // @[execution-units.scala:108:30] wire [63:0] _memExeUnit_io_ll_fresp_bits_uop_exc_cause; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_bypassable; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_mem_cmd; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_mem_size; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_mem_signed; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_fence; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_fencei; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_amo; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_uses_ldq; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_uses_stq; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_unique; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_flush_on_commit; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_ldst; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs3; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ldst_val; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_dst_rtype; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1_rtype; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2_rtype; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_frs3_en; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_fp_val; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_fp_single; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_bp_debug_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_fsrc; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_tsrc; // @[execution-units.scala:108:30] wire [64:0] _memExeUnit_io_ll_fresp_bits_data; // @[execution-units.scala:108:30] wire [1:0] io_hartid_0 = io_hartid; // @[core.scala:51:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[core.scala:51:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[core.scala:51:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[core.scala:51:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[core.scala:51:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[core.scala:51:7] wire io_ifu_fetchpacket_valid_0 = io_ifu_fetchpacket_valid; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_valid_0 = io_ifu_fetchpacket_bits_uops_0_valid; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_inst; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_inst; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_rvc; // @[core.scala:51:7] wire [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_pc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_sfb; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_edge_inst; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_0_bits_pc_lob; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_taken_0 = io_ifu_fetchpacket_bits_uops_0_bits_taken; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_valid_0 = io_ifu_fetchpacket_bits_uops_1_valid; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_inst; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_inst; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_rvc; // @[core.scala:51:7] wire [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_pc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_sfb; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_edge_inst; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_1_bits_pc_lob; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_taken_0 = io_ifu_fetchpacket_bits_uops_1_bits_taken; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_valid_0 = io_ifu_fetchpacket_bits_uops_2_valid; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_2_bits_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_inst; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_inst; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_2_bits_is_rvc; // @[core.scala:51:7] wire [39:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_pc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_2_bits_is_sfb; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_edge_inst; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_2_bits_pc_lob; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_taken_0 = io_ifu_fetchpacket_bits_uops_2_bits_taken; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_idx_valid_0 = io_ifu_get_pc_0_entry_cfi_idx_valid; // @[core.scala:51:7] wire [2:0] io_ifu_get_pc_0_entry_cfi_idx_bits_0 = io_ifu_get_pc_0_entry_cfi_idx_bits; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_taken_0 = io_ifu_get_pc_0_entry_cfi_taken; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_mispredicted_0 = io_ifu_get_pc_0_entry_cfi_mispredicted; // @[core.scala:51:7] wire [2:0] io_ifu_get_pc_0_entry_cfi_type_0 = io_ifu_get_pc_0_entry_cfi_type; // @[core.scala:51:7] wire [7:0] io_ifu_get_pc_0_entry_br_mask_0 = io_ifu_get_pc_0_entry_br_mask; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_is_call_0 = io_ifu_get_pc_0_entry_cfi_is_call; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_is_ret_0 = io_ifu_get_pc_0_entry_cfi_is_ret; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_npc_plus4_0 = io_ifu_get_pc_0_entry_cfi_npc_plus4; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_0_entry_ras_top_0 = io_ifu_get_pc_0_entry_ras_top; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_0_entry_ras_idx_0 = io_ifu_get_pc_0_entry_ras_idx; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_start_bank_0 = io_ifu_get_pc_0_entry_start_bank; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_0_pc_0 = io_ifu_get_pc_0_pc; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_0_com_pc_0 = io_ifu_get_pc_0_com_pc; // @[core.scala:51:7] wire io_ifu_get_pc_0_next_val_0 = io_ifu_get_pc_0_next_val; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_0_next_pc_0 = io_ifu_get_pc_0_next_pc; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_idx_valid_0 = io_ifu_get_pc_1_entry_cfi_idx_valid; // @[core.scala:51:7] wire [2:0] io_ifu_get_pc_1_entry_cfi_idx_bits_0 = io_ifu_get_pc_1_entry_cfi_idx_bits; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_taken_0 = io_ifu_get_pc_1_entry_cfi_taken; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_mispredicted_0 = io_ifu_get_pc_1_entry_cfi_mispredicted; // @[core.scala:51:7] wire [2:0] io_ifu_get_pc_1_entry_cfi_type_0 = io_ifu_get_pc_1_entry_cfi_type; // @[core.scala:51:7] wire [7:0] io_ifu_get_pc_1_entry_br_mask_0 = io_ifu_get_pc_1_entry_br_mask; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_is_call_0 = io_ifu_get_pc_1_entry_cfi_is_call; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_is_ret_0 = io_ifu_get_pc_1_entry_cfi_is_ret; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_npc_plus4_0 = io_ifu_get_pc_1_entry_cfi_npc_plus4; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_1_entry_ras_top_0 = io_ifu_get_pc_1_entry_ras_top; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_1_entry_ras_idx_0 = io_ifu_get_pc_1_entry_ras_idx; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_start_bank_0 = io_ifu_get_pc_1_entry_start_bank; // @[core.scala:51:7] wire [63:0] io_ifu_get_pc_1_ghist_old_history_0 = io_ifu_get_pc_1_ghist_old_history; // @[core.scala:51:7] wire io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_current_saw_branch_not_taken; // @[core.scala:51:7] wire io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken; // @[core.scala:51:7] wire io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_taken; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_1_ghist_ras_idx_0 = io_ifu_get_pc_1_ghist_ras_idx; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_1_pc_0 = io_ifu_get_pc_1_pc; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_1_com_pc_0 = io_ifu_get_pc_1_com_pc; // @[core.scala:51:7] wire io_ifu_get_pc_1_next_val_0 = io_ifu_get_pc_1_next_val; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_1_next_pc_0 = io_ifu_get_pc_1_next_pc; // @[core.scala:51:7] wire [39:0] io_ifu_debug_fetch_pc_0_0 = io_ifu_debug_fetch_pc_0; // @[core.scala:51:7] wire [39:0] io_ifu_debug_fetch_pc_1_0 = io_ifu_debug_fetch_pc_1; // @[core.scala:51:7] wire [39:0] io_ifu_debug_fetch_pc_2_0 = io_ifu_debug_fetch_pc_2; // @[core.scala:51:7] wire io_ifu_perf_acquire_0 = io_ifu_perf_acquire; // @[core.scala:51:7] wire io_ifu_perf_tlbMiss_0 = io_ifu_perf_tlbMiss; // @[core.scala:51:7] wire io_ptw_perf_l2miss_0 = io_ptw_perf_l2miss; // @[core.scala:51:7] wire io_ptw_perf_l2hit_0 = io_ptw_perf_l2hit; // @[core.scala:51:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[core.scala:51:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[core.scala:51:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_valid_0 = io_lsu_exe_0_iresp_valid; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_uopc_0 = io_lsu_exe_0_iresp_bits_uop_uopc; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_iresp_bits_uop_inst_0 = io_lsu_exe_0_iresp_bits_uop_inst; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst_0 = io_lsu_exe_0_iresp_bits_uop_debug_inst; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_rvc_0 = io_lsu_exe_0_iresp_bits_uop_is_rvc; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc_0 = io_lsu_exe_0_iresp_bits_uop_debug_pc; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type_0 = io_lsu_exe_0_iresp_bits_uop_iq_type; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code_0 = io_lsu_exe_0_iresp_bits_uop_fu_code; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_br_type; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_load; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_std; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state_0 = io_lsu_exe_0_iresp_bits_uop_iw_state; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_br_0 = io_lsu_exe_0_iresp_bits_uop_is_br; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_jalr_0 = io_lsu_exe_0_iresp_bits_uop_is_jalr; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_jal_0 = io_lsu_exe_0_iresp_bits_uop_is_jal; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_sfb_0 = io_lsu_exe_0_iresp_bits_uop_is_sfb; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_iresp_bits_uop_br_mask_0 = io_lsu_exe_0_iresp_bits_uop_br_mask; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_br_tag_0 = io_lsu_exe_0_iresp_bits_uop_br_tag; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ftq_idx; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_edge_inst_0 = io_lsu_exe_0_iresp_bits_uop_edge_inst; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob_0 = io_lsu_exe_0_iresp_bits_uop_pc_lob; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_taken_0 = io_lsu_exe_0_iresp_bits_uop_taken; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed_0 = io_lsu_exe_0_iresp_bits_uop_imm_packed; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr_0 = io_lsu_exe_0_iresp_bits_uop_csr_addr; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_rob_idx_0 = io_lsu_exe_0_iresp_bits_uop_rob_idx; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ldq_idx; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_stq_idx_0 = io_lsu_exe_0_iresp_bits_uop_stq_idx; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_iresp_bits_uop_rxq_idx; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_pdst_0 = io_lsu_exe_0_iresp_bits_uop_pdst; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs1_0 = io_lsu_exe_0_iresp_bits_uop_prs1; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs2_0 = io_lsu_exe_0_iresp_bits_uop_prs2; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs3_0 = io_lsu_exe_0_iresp_bits_uop_prs3; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ppred_0 = io_lsu_exe_0_iresp_bits_uop_ppred; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs1_busy; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs2_busy; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs3_busy; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_iresp_bits_uop_ppred_busy; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_iresp_bits_uop_stale_pdst; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_exception_0 = io_lsu_exe_0_iresp_bits_uop_exception; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause_0 = io_lsu_exe_0_iresp_bits_uop_exc_cause; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_bypassable_0 = io_lsu_exe_0_iresp_bits_uop_bypassable; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_iresp_bits_uop_mem_cmd; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_mem_signed_0 = io_lsu_exe_0_iresp_bits_uop_mem_signed; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_fence_0 = io_lsu_exe_0_iresp_bits_uop_is_fence; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_fencei_0 = io_lsu_exe_0_iresp_bits_uop_is_fencei; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_amo_0 = io_lsu_exe_0_iresp_bits_uop_is_amo; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_iresp_bits_uop_uses_ldq; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_uses_stq_0 = io_lsu_exe_0_iresp_bits_uop_uses_stq; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_unique_0 = io_lsu_exe_0_iresp_bits_uop_is_unique; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_iresp_bits_uop_flush_on_commit; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_ldst_0 = io_lsu_exe_0_iresp_bits_uop_ldst; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1_0 = io_lsu_exe_0_iresp_bits_uop_lrs1; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2_0 = io_lsu_exe_0_iresp_bits_uop_lrs2; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3_0 = io_lsu_exe_0_iresp_bits_uop_lrs3; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ldst_val_0 = io_lsu_exe_0_iresp_bits_uop_ldst_val; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_iresp_bits_uop_dst_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs1_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs2_rtype; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_frs3_en_0 = io_lsu_exe_0_iresp_bits_uop_frs3_en; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_fp_val_0 = io_lsu_exe_0_iresp_bits_uop_fp_val; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_fp_single_0 = io_lsu_exe_0_iresp_bits_uop_fp_single; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_debug_if; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_fsrc; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_tsrc; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_iresp_bits_data_0 = io_lsu_exe_0_iresp_bits_data; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_valid_0 = io_lsu_exe_0_fresp_valid; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_uopc_0 = io_lsu_exe_0_fresp_bits_uop_uopc; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_fresp_bits_uop_inst_0 = io_lsu_exe_0_fresp_bits_uop_inst; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst_0 = io_lsu_exe_0_fresp_bits_uop_debug_inst; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_rvc_0 = io_lsu_exe_0_fresp_bits_uop_is_rvc; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc_0 = io_lsu_exe_0_fresp_bits_uop_debug_pc; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type_0 = io_lsu_exe_0_fresp_bits_uop_iq_type; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code_0 = io_lsu_exe_0_fresp_bits_uop_fu_code; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_br_type; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_load; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_std; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state_0 = io_lsu_exe_0_fresp_bits_uop_iw_state; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_br_0 = io_lsu_exe_0_fresp_bits_uop_is_br; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_jalr_0 = io_lsu_exe_0_fresp_bits_uop_is_jalr; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_jal_0 = io_lsu_exe_0_fresp_bits_uop_is_jal; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_sfb_0 = io_lsu_exe_0_fresp_bits_uop_is_sfb; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_fresp_bits_uop_br_mask_0 = io_lsu_exe_0_fresp_bits_uop_br_mask; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_br_tag_0 = io_lsu_exe_0_fresp_bits_uop_br_tag; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ftq_idx; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_edge_inst_0 = io_lsu_exe_0_fresp_bits_uop_edge_inst; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob_0 = io_lsu_exe_0_fresp_bits_uop_pc_lob; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_taken_0 = io_lsu_exe_0_fresp_bits_uop_taken; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed_0 = io_lsu_exe_0_fresp_bits_uop_imm_packed; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr_0 = io_lsu_exe_0_fresp_bits_uop_csr_addr; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_rob_idx_0 = io_lsu_exe_0_fresp_bits_uop_rob_idx; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ldq_idx; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_stq_idx_0 = io_lsu_exe_0_fresp_bits_uop_stq_idx; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_fresp_bits_uop_rxq_idx; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_pdst_0 = io_lsu_exe_0_fresp_bits_uop_pdst; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs1_0 = io_lsu_exe_0_fresp_bits_uop_prs1; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs2_0 = io_lsu_exe_0_fresp_bits_uop_prs2; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs3_0 = io_lsu_exe_0_fresp_bits_uop_prs3; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ppred_0 = io_lsu_exe_0_fresp_bits_uop_ppred; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs1_busy; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs2_busy; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs3_busy; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_fresp_bits_uop_ppred_busy; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_fresp_bits_uop_stale_pdst; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_exception_0 = io_lsu_exe_0_fresp_bits_uop_exception; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause_0 = io_lsu_exe_0_fresp_bits_uop_exc_cause; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_bypassable_0 = io_lsu_exe_0_fresp_bits_uop_bypassable; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_fresp_bits_uop_mem_cmd; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size_0 = io_lsu_exe_0_fresp_bits_uop_mem_size; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_mem_signed_0 = io_lsu_exe_0_fresp_bits_uop_mem_signed; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_fence_0 = io_lsu_exe_0_fresp_bits_uop_is_fence; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_fencei_0 = io_lsu_exe_0_fresp_bits_uop_is_fencei; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_amo_0 = io_lsu_exe_0_fresp_bits_uop_is_amo; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_fresp_bits_uop_uses_ldq; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_uses_stq_0 = io_lsu_exe_0_fresp_bits_uop_uses_stq; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_unique_0 = io_lsu_exe_0_fresp_bits_uop_is_unique; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_fresp_bits_uop_flush_on_commit; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_ldst_0 = io_lsu_exe_0_fresp_bits_uop_ldst; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1_0 = io_lsu_exe_0_fresp_bits_uop_lrs1; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2_0 = io_lsu_exe_0_fresp_bits_uop_lrs2; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3_0 = io_lsu_exe_0_fresp_bits_uop_lrs3; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ldst_val_0 = io_lsu_exe_0_fresp_bits_uop_ldst_val; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_fresp_bits_uop_dst_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs1_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs2_rtype; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_frs3_en_0 = io_lsu_exe_0_fresp_bits_uop_frs3_en; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_fp_val_0 = io_lsu_exe_0_fresp_bits_uop_fp_val; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_fp_single_0 = io_lsu_exe_0_fresp_bits_uop_fp_single; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_debug_if; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_fsrc; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_tsrc; // @[core.scala:51:7] wire [64:0] io_lsu_exe_0_fresp_bits_data_0 = io_lsu_exe_0_fresp_bits_data; // @[core.scala:51:7] wire [4:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_ldq_idx_1_0 = io_lsu_dis_ldq_idx_1; // @[core.scala:51:7] wire [4:0] io_lsu_dis_ldq_idx_2_0 = io_lsu_dis_ldq_idx_2; // @[core.scala:51:7] wire [4:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_stq_idx_1_0 = io_lsu_dis_stq_idx_1; // @[core.scala:51:7] wire [4:0] io_lsu_dis_stq_idx_2_0 = io_lsu_dis_stq_idx_2; // @[core.scala:51:7] wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[core.scala:51:7] wire io_lsu_ldq_full_1_0 = io_lsu_ldq_full_1; // @[core.scala:51:7] wire io_lsu_ldq_full_2_0 = io_lsu_ldq_full_2; // @[core.scala:51:7] wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[core.scala:51:7] wire io_lsu_stq_full_1_0 = io_lsu_stq_full_1; // @[core.scala:51:7] wire io_lsu_stq_full_2_0 = io_lsu_stq_full_2; // @[core.scala:51:7] wire io_lsu_fp_stdata_ready_0 = io_lsu_fp_stdata_ready; // @[core.scala:51:7] wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[core.scala:51:7] wire [6:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[core.scala:51:7] wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[core.scala:51:7] wire [6:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[core.scala:51:7] wire [6:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[core.scala:51:7] wire io_lsu_spec_ld_wakeup_0_valid_0 = io_lsu_spec_ld_wakeup_0_valid; // @[core.scala:51:7] wire [6:0] io_lsu_spec_ld_wakeup_0_bits_0 = io_lsu_spec_ld_wakeup_0_bits; // @[core.scala:51:7] wire io_lsu_ld_miss_0 = io_lsu_ld_miss; // @[core.scala:51:7] wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[core.scala:51:7] wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_uopc_0 = io_lsu_lxcpt_bits_uop_uopc; // @[core.scala:51:7] wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[core.scala:51:7] wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[core.scala:51:7] wire [39:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[core.scala:51:7] wire [2:0] io_lsu_lxcpt_bits_uop_iq_type_0 = io_lsu_lxcpt_bits_uop_iq_type; // @[core.scala:51:7] wire [9:0] io_lsu_lxcpt_bits_uop_fu_code_0 = io_lsu_lxcpt_bits_uop_fu_code; // @[core.scala:51:7] wire [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type_0 = io_lsu_lxcpt_bits_uop_ctrl_br_type; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op1_sel; // @[core.scala:51:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op2_sel; // @[core.scala:51:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_imm_sel; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lsu_lxcpt_bits_uop_ctrl_op_fcn; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lsu_lxcpt_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lsu_lxcpt_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_load_0 = io_lsu_lxcpt_bits_uop_ctrl_is_load; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_sta_0 = io_lsu_lxcpt_bits_uop_ctrl_is_sta; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_std_0 = io_lsu_lxcpt_bits_uop_ctrl_is_std; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_iw_state_0 = io_lsu_lxcpt_bits_uop_iw_state; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p1_poisoned; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p2_poisoned; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_br_0 = io_lsu_lxcpt_bits_uop_is_br; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_jalr_0 = io_lsu_lxcpt_bits_uop_is_jalr; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_jal_0 = io_lsu_lxcpt_bits_uop_is_jal; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[core.scala:51:7] wire [15:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[core.scala:51:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[core.scala:51:7] wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[core.scala:51:7] wire [11:0] io_lsu_lxcpt_bits_uop_csr_addr_0 = io_lsu_lxcpt_bits_uop_csr_addr; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[core.scala:51:7] wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_bypassable_0 = io_lsu_lxcpt_bits_uop_bypassable; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ldst_val_0 = io_lsu_lxcpt_bits_uop_ldst_val; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_fp_single_0 = io_lsu_lxcpt_bits_uop_fp_single; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[core.scala:51:7] wire [39:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[core.scala:51:7] wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[core.scala:51:7] wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[core.scala:51:7] wire io_lsu_perf_tlbMiss_0 = io_lsu_perf_tlbMiss; // @[core.scala:51:7] wire io_ptw_tlb_req_ready_0 = io_ptw_tlb_req_ready; // @[core.scala:51:7] wire io_ptw_tlb_resp_valid_0 = io_ptw_tlb_resp_valid; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_ae_ptw_0 = io_ptw_tlb_resp_bits_ae_ptw; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_ae_final_0 = io_ptw_tlb_resp_bits_ae_final; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pf_0 = io_ptw_tlb_resp_bits_pf; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_gf_0 = io_ptw_tlb_resp_bits_gf; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_hr_0 = io_ptw_tlb_resp_bits_hr; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_hw_0 = io_ptw_tlb_resp_bits_hw; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_hx_0 = io_ptw_tlb_resp_bits_hx; // @[core.scala:51:7] wire [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future_0 = io_ptw_tlb_resp_bits_pte_reserved_for_future; // @[core.scala:51:7] wire [43:0] io_ptw_tlb_resp_bits_pte_ppn_0 = io_ptw_tlb_resp_bits_pte_ppn; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software_0 = io_ptw_tlb_resp_bits_pte_reserved_for_software; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_d_0 = io_ptw_tlb_resp_bits_pte_d; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_a_0 = io_ptw_tlb_resp_bits_pte_a; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_g_0 = io_ptw_tlb_resp_bits_pte_g; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_u_0 = io_ptw_tlb_resp_bits_pte_u; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_x_0 = io_ptw_tlb_resp_bits_pte_x; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_w_0 = io_ptw_tlb_resp_bits_pte_w; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_r_0 = io_ptw_tlb_resp_bits_pte_r; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_v_0 = io_ptw_tlb_resp_bits_pte_v; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_resp_bits_level_0 = io_ptw_tlb_resp_bits_level; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_homogeneous_0 = io_ptw_tlb_resp_bits_homogeneous; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_gpa_valid_0 = io_ptw_tlb_resp_bits_gpa_valid; // @[core.scala:51:7] wire [38:0] io_ptw_tlb_resp_bits_gpa_bits_0 = io_ptw_tlb_resp_bits_gpa_bits; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_gpa_is_pte_0 = io_ptw_tlb_resp_bits_gpa_is_pte; // @[core.scala:51:7] wire [3:0] io_ptw_tlb_ptbr_mode_0 = io_ptw_tlb_ptbr_mode; // @[core.scala:51:7] wire [43:0] io_ptw_tlb_ptbr_ppn_0 = io_ptw_tlb_ptbr_ppn; // @[core.scala:51:7] wire io_ptw_tlb_status_debug_0 = io_ptw_tlb_status_debug; // @[core.scala:51:7] wire io_ptw_tlb_status_cease_0 = io_ptw_tlb_status_cease; // @[core.scala:51:7] wire io_ptw_tlb_status_wfi_0 = io_ptw_tlb_status_wfi; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_dprv_0 = io_ptw_tlb_status_dprv; // @[core.scala:51:7] wire io_ptw_tlb_status_dv_0 = io_ptw_tlb_status_dv; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_prv_0 = io_ptw_tlb_status_prv; // @[core.scala:51:7] wire io_ptw_tlb_status_v_0 = io_ptw_tlb_status_v; // @[core.scala:51:7] wire io_ptw_tlb_status_sd_0 = io_ptw_tlb_status_sd; // @[core.scala:51:7] wire io_ptw_tlb_status_mpv_0 = io_ptw_tlb_status_mpv; // @[core.scala:51:7] wire io_ptw_tlb_status_gva_0 = io_ptw_tlb_status_gva; // @[core.scala:51:7] wire io_ptw_tlb_status_tsr_0 = io_ptw_tlb_status_tsr; // @[core.scala:51:7] wire io_ptw_tlb_status_tw_0 = io_ptw_tlb_status_tw; // @[core.scala:51:7] wire io_ptw_tlb_status_tvm_0 = io_ptw_tlb_status_tvm; // @[core.scala:51:7] wire io_ptw_tlb_status_mxr_0 = io_ptw_tlb_status_mxr; // @[core.scala:51:7] wire io_ptw_tlb_status_sum_0 = io_ptw_tlb_status_sum; // @[core.scala:51:7] wire io_ptw_tlb_status_mprv_0 = io_ptw_tlb_status_mprv; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_fs_0 = io_ptw_tlb_status_fs; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_mpp_0 = io_ptw_tlb_status_mpp; // @[core.scala:51:7] wire io_ptw_tlb_status_spp_0 = io_ptw_tlb_status_spp; // @[core.scala:51:7] wire io_ptw_tlb_status_mpie_0 = io_ptw_tlb_status_mpie; // @[core.scala:51:7] wire io_ptw_tlb_status_spie_0 = io_ptw_tlb_status_spie; // @[core.scala:51:7] wire io_ptw_tlb_status_mie_0 = io_ptw_tlb_status_mie; // @[core.scala:51:7] wire io_ptw_tlb_status_sie_0 = io_ptw_tlb_status_sie; // @[core.scala:51:7] wire io_ptw_tlb_pmp_0_cfg_l_0 = io_ptw_tlb_pmp_0_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_0_cfg_a_0 = io_ptw_tlb_pmp_0_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_0_cfg_x_0 = io_ptw_tlb_pmp_0_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_0_cfg_w_0 = io_ptw_tlb_pmp_0_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_0_cfg_r_0 = io_ptw_tlb_pmp_0_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_0_addr_0 = io_ptw_tlb_pmp_0_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_0_mask_0 = io_ptw_tlb_pmp_0_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_1_cfg_l_0 = io_ptw_tlb_pmp_1_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_1_cfg_a_0 = io_ptw_tlb_pmp_1_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_1_cfg_x_0 = io_ptw_tlb_pmp_1_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_1_cfg_w_0 = io_ptw_tlb_pmp_1_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_1_cfg_r_0 = io_ptw_tlb_pmp_1_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_1_addr_0 = io_ptw_tlb_pmp_1_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_1_mask_0 = io_ptw_tlb_pmp_1_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_2_cfg_l_0 = io_ptw_tlb_pmp_2_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_2_cfg_a_0 = io_ptw_tlb_pmp_2_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_2_cfg_x_0 = io_ptw_tlb_pmp_2_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_2_cfg_w_0 = io_ptw_tlb_pmp_2_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_2_cfg_r_0 = io_ptw_tlb_pmp_2_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_2_addr_0 = io_ptw_tlb_pmp_2_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_2_mask_0 = io_ptw_tlb_pmp_2_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_3_cfg_l_0 = io_ptw_tlb_pmp_3_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_3_cfg_a_0 = io_ptw_tlb_pmp_3_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_3_cfg_x_0 = io_ptw_tlb_pmp_3_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_3_cfg_w_0 = io_ptw_tlb_pmp_3_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_3_cfg_r_0 = io_ptw_tlb_pmp_3_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_3_addr_0 = io_ptw_tlb_pmp_3_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_3_mask_0 = io_ptw_tlb_pmp_3_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_4_cfg_l_0 = io_ptw_tlb_pmp_4_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_4_cfg_a_0 = io_ptw_tlb_pmp_4_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_4_cfg_x_0 = io_ptw_tlb_pmp_4_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_4_cfg_w_0 = io_ptw_tlb_pmp_4_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_4_cfg_r_0 = io_ptw_tlb_pmp_4_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_4_addr_0 = io_ptw_tlb_pmp_4_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_4_mask_0 = io_ptw_tlb_pmp_4_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_5_cfg_l_0 = io_ptw_tlb_pmp_5_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_5_cfg_a_0 = io_ptw_tlb_pmp_5_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_5_cfg_x_0 = io_ptw_tlb_pmp_5_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_5_cfg_w_0 = io_ptw_tlb_pmp_5_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_5_cfg_r_0 = io_ptw_tlb_pmp_5_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_5_addr_0 = io_ptw_tlb_pmp_5_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_5_mask_0 = io_ptw_tlb_pmp_5_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_6_cfg_l_0 = io_ptw_tlb_pmp_6_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_6_cfg_a_0 = io_ptw_tlb_pmp_6_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_6_cfg_x_0 = io_ptw_tlb_pmp_6_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_6_cfg_w_0 = io_ptw_tlb_pmp_6_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_6_cfg_r_0 = io_ptw_tlb_pmp_6_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_6_addr_0 = io_ptw_tlb_pmp_6_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_6_mask_0 = io_ptw_tlb_pmp_6_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_7_cfg_l_0 = io_ptw_tlb_pmp_7_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_7_cfg_a_0 = io_ptw_tlb_pmp_7_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_7_cfg_x_0 = io_ptw_tlb_pmp_7_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_7_cfg_w_0 = io_ptw_tlb_pmp_7_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_7_cfg_r_0 = io_ptw_tlb_pmp_7_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_7_addr_0 = io_ptw_tlb_pmp_7_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_7_mask_0 = io_ptw_tlb_pmp_7_mask; // @[core.scala:51:7] wire coreMonitorBundle_clock = clock; // @[core.scala:1405:31] wire coreMonitorBundle_reset = reset; // @[core.scala:1405:31] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_rocc_cmd_bits_inst_funct = 7'h0; // @[core.scala:51:7] wire [6:0] io_rocc_cmd_bits_inst_opcode = 7'h0; // @[core.scala:51:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[core.scala:51:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] pred_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:149:26] wire [6:0] dec_uops_0_rob_idx = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_prs1 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_prs2 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_prs3 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_stale_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_rob_idx = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_prs1 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_prs2 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_prs3 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_stale_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_rob_idx = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_prs1 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_prs2 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_prs3 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_stale_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:175:27] wire [6:0] p_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] fast_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_trace_insns_0_priv = 3'h0; // @[core.scala:51:7] wire [2:0] io_trace_insns_1_priv = 3'h0; // @[core.scala:51:7] wire [2:0] io_trace_insns_2_priv = 3'h0; // @[core.scala:51:7] wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] pred_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:149:26] wire [2:0] dec_uops_0_ctrl_op2_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_0_ctrl_imm_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_0_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_1_ctrl_op2_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_1_ctrl_imm_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_1_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_2_ctrl_op2_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_2_ctrl_imm_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_2_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24] wire [2:0] bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:175:27] wire [2:0] p_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_1_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_1_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_1_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_1_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_cs_1_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_1_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_1_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_2_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_2_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_2_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_2_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_cs_2_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_2_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_2_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] fast_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29] wire [2:0] slow_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29] wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29] wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29] wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29] wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29] wire [2:0] coreMonitorBundle_priv_mode = 3'h0; // @[core.scala:1405:31] wire [9:0] io_ifu_fetchpacket_bits_uops_0_bits_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_ifu_fetchpacket_bits_uops_1_bits_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_ifu_fetchpacket_bits_uops_2_bits_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] int_iss_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_ren_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] pred_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:149:26] wire [9:0] bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] bypasses_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] bypasses_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] bypasses_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] bypasses_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] pred_bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:175:27] wire [9:0] p_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] p_uop_1_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] p_uop_2_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] fast_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29] wire [9:0] slow_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29] wire [9:0] fast_wakeup_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29] wire [9:0] slow_wakeup_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29] wire [9:0] fast_wakeup_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29] wire [9:0] slow_wakeup_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29] wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_2_bits_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[core.scala:51:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_ptw_tlb_hgatp_mode = 4'h0; // @[core.scala:51:7] wire [3:0] io_ptw_tlb_vsatp_mode = 4'h0; // @[core.scala:51:7] wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] pred_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:149:26] wire [3:0] pred_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:149:26] wire [3:0] dec_uops_0_ctrl_br_type = 4'h0; // @[core.scala:158:24] wire [3:0] dec_uops_1_ctrl_br_type = 4'h0; // @[core.scala:158:24] wire [3:0] dec_uops_2_ctrl_br_type = 4'h0; // @[core.scala:158:24] wire [3:0] bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:175:27] wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:175:27] wire [3:0] p_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] p_uop_1_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_1_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_cs_1_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] p_uop_2_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_2_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_cs_2_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] fast_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29] wire [3:0] fast_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29] wire [3:0] slow_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29] wire [3:0] slow_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29] wire [3:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29] wire [3:0] fast_wakeup_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29] wire [3:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29] wire [3:0] slow_wakeup_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29] wire [3:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29] wire [3:0] fast_wakeup_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29] wire [3:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29] wire [3:0] slow_wakeup_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_status_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_status_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_prv = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_fs = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_mpp = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_hstatus_vsxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_hstatus_zero3 = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_hstatus_zero2 = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_prv = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_sxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_uxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_fs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_mpp = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_0_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_1_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_2_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_3_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_4_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_5_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_6_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_7_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:149:26] wire [1:0] dec_uops_0_ctrl_op1_sel = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_0_iw_state = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_0_rxq_idx = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_0_debug_tsrc = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_1_ctrl_op1_sel = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_1_iw_state = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_1_rxq_idx = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_1_debug_tsrc = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_2_ctrl_op1_sel = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_2_iw_state = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_2_rxq_idx = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_2_debug_tsrc = 2'h0; // @[core.scala:158:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:175:27] wire [1:0] p_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] p_uop_1_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_cs_1_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] p_uop_2_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_cs_2_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_0_ghist_ras_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_debug_ftq_idx_0 = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_debug_ftq_idx_1 = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_debug_ftq_idx_2 = 5'h0; // @[core.scala:51:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_cmd_bits_inst_rs2 = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_cmd_bits_inst_rs1 = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_cmd_bits_inst_rd = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_ptw_tlb_hstatus_zero1 = 5'h0; // @[core.scala:51:7] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:149:26] wire [4:0] dec_uops_0_ctrl_op_fcn = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_0_ldq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_0_stq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_0_ppred = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_1_ctrl_op_fcn = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_1_ldq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_1_stq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_1_ppred = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_2_ctrl_op_fcn = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_2_ldq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_2_stq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_2_ppred = 5'h0; // @[core.scala:158:24] wire [4:0] dis_uops_0_ppred = 5'h0; // @[core.scala:167:24] wire [4:0] dis_uops_1_ppred = 5'h0; // @[core.scala:167:24] wire [4:0] dis_uops_2_ppred = 5'h0; // @[core.scala:167:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_flags = 5'h0; // @[core.scala:175:27] wire [4:0] _new_ghist_WIRE_ras_idx = 5'h0; // @[core.scala:406:44] wire [4:0] p_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] p_uop_1_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_cs_1_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] p_uop_2_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_cs_2_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29] wire [4:0] coreMonitorBundle_wrdst = 5'h0; // @[core.scala:1405:31] wire [4:0] coreMonitorBundle_rd0src = 5'h0; // @[core.scala:1405:31] wire [4:0] coreMonitorBundle_rd1src = 5'h0; // @[core.scala:1405:31] wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_br = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_jalr = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_jal = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_exception = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_bypassable = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_single = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_br = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_jalr = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_jal = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_exception = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_bypassable = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_mem_signed = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_fence = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_fencei = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_amo = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_uses_stq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_unique = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_frs3_en = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_single = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_br = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_jalr = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_jal = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_exception = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_bypassable = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_mem_signed = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_fence = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_fencei = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_amo = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_uses_stq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_unique = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ldst_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_frs3_en = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_fp_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_fp_single = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_ifu_get_pc_0_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:51:7] wire io_ifu_get_pc_0_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:51:7] wire io_ifu_get_pc_0_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:51:7] wire io_ifu_status_mbe = 1'h0; // @[core.scala:51:7] wire io_ifu_status_sbe = 1'h0; // @[core.scala:51:7] wire io_ifu_status_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ifu_status_ube = 1'h0; // @[core.scala:51:7] wire io_ifu_status_upie = 1'h0; // @[core.scala:51:7] wire io_ifu_status_hie = 1'h0; // @[core.scala:51:7] wire io_ifu_status_uie = 1'h0; // @[core.scala:51:7] wire io_ifu_sfence_bits_hv = 1'h0; // @[core.scala:51:7] wire io_ifu_sfence_bits_hg = 1'h0; // @[core.scala:51:7] wire io_ptw_sfence_bits_hv = 1'h0; // @[core.scala:51:7] wire io_ptw_sfence_bits_hg = 1'h0; // @[core.scala:51:7] wire io_ptw_status_mbe = 1'h0; // @[core.scala:51:7] wire io_ptw_status_sbe = 1'h0; // @[core.scala:51:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ptw_status_ube = 1'h0; // @[core.scala:51:7] wire io_ptw_status_upie = 1'h0; // @[core.scala:51:7] wire io_ptw_status_hie = 1'h0; // @[core.scala:51:7] wire io_ptw_status_uie = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_vtw = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_hu = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_spvp = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_spv = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_gva = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_debug = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_cease = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_wfi = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_dv = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_v = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sd = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mpv = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_gva = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mbe = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sbe = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_tsr = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_tw = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_tvm = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mxr = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sum = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mprv = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_spp = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mpie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_ube = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_spie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_upie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_hie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_uie = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_ready = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_valid = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_inst_xd = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_inst_xs1 = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_inst_xs2 = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_debug = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_cease = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_wfi = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_dv = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_v = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sd = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mpv = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_gva = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_tsr = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_tw = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_tvm = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mxr = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sum = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mprv = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_spp = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mpie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_spie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[core.scala:51:7] wire io_rocc_resp_ready = 1'h0; // @[core.scala:51:7] wire io_rocc_resp_valid = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_ready = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_valid = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s1_kill = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_nack = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_kill = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_valid = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_replay_next = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_ordered = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_store_pending = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_release = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_grant = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[core.scala:51:7] wire io_rocc_busy = 1'h0; // @[core.scala:51:7] wire io_rocc_interrupt = 1'h0; // @[core.scala:51:7] wire io_rocc_exception = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_predicated = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_valid = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_predicated = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_valid = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_predicated = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_valid = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_valid = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_bits_valid = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_bits_bits_need_gpa = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_bits_bits_vstage1 = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_bits_bits_stage2 = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_fragmented_superpage = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_mbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_sbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_ube = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_upie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_hie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_uie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_vtsr = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_vtw = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_vtvm = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_hu = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_spvp = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_spv = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_gva = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_vsbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_debug = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_cease = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_wfi = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_dv = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_v = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sd = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mpv = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_gva = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_tsr = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_tw = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_tvm = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mxr = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sum = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mprv = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_spp = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mpie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_ube = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_spie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_upie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_hie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_uie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_0_set = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_1_set = 1'h0; // @[core.scala:51:7] wire io_trace_insns_0_valid = 1'h0; // @[core.scala:51:7] wire io_trace_insns_0_exception = 1'h0; // @[core.scala:51:7] wire io_trace_insns_0_interrupt = 1'h0; // @[core.scala:51:7] wire io_trace_insns_1_valid = 1'h0; // @[core.scala:51:7] wire io_trace_insns_1_exception = 1'h0; // @[core.scala:51:7] wire io_trace_insns_1_interrupt = 1'h0; // @[core.scala:51:7] wire io_trace_insns_2_valid = 1'h0; // @[core.scala:51:7] wire io_trace_insns_2_exception = 1'h0; // @[core.scala:51:7] wire io_trace_insns_2_interrupt = 1'h0; // @[core.scala:51:7] wire int_iss_wakeups_1_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_ren_wakeups_1_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire pred_wakeup_valid = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_data = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_predicated = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:149:26] wire dec_uops_0_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ctrl_is_load = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ctrl_is_sta = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ctrl_is_std = 1'h0; // @[core.scala:158:24] wire dec_uops_0_iw_p1_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_0_iw_p2_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_0_prs1_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_0_prs2_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_0_prs3_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ppred_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ldst_is_rs1 = 1'h0; // @[core.scala:158:24] wire dec_uops_0_xcpt_ma_if = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ctrl_is_load = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ctrl_is_sta = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ctrl_is_std = 1'h0; // @[core.scala:158:24] wire dec_uops_1_iw_p1_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_1_iw_p2_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_1_prs1_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_1_prs2_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_1_prs3_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ppred_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ldst_is_rs1 = 1'h0; // @[core.scala:158:24] wire dec_uops_1_xcpt_ma_if = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ctrl_is_load = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ctrl_is_sta = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ctrl_is_std = 1'h0; // @[core.scala:158:24] wire dec_uops_2_iw_p1_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_2_iw_p2_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_2_prs1_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_2_prs2_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_2_prs3_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ppred_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ldst_is_rs1 = 1'h0; // @[core.scala:158:24] wire dec_uops_2_xcpt_ma_if = 1'h0; // @[core.scala:158:24] wire dis_uops_0_ppred_busy = 1'h0; // @[core.scala:167:24] wire dis_uops_1_ppred_busy = 1'h0; // @[core.scala:167:24] wire dis_uops_2_ppred_busy = 1'h0; // @[core.scala:167:24] wire bypasses_0_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire pred_bypasses_0_bits_predicated = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_valid = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:175:27] wire brupdate_b2_valid = 1'h0; // @[core.scala:188:23] wire _use_this_mispredict_T_2 = 1'h0; // @[util.scala:363:52] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire custom_csrs_csrs_0_stall = 1'h0; // @[core.scala:276:25] wire custom_csrs_csrs_0_set = 1'h0; // @[core.scala:276:25] wire custom_csrs_csrs_1_stall = 1'h0; // @[core.scala:276:25] wire custom_csrs_csrs_1_set = 1'h0; // @[core.scala:276:25] wire _new_ghist_WIRE_current_saw_branch_not_taken = 1'h0; // @[core.scala:406:44] wire _new_ghist_WIRE_new_saw_branch_not_taken = 1'h0; // @[core.scala:406:44] wire _new_ghist_WIRE_new_saw_branch_taken = 1'h0; // @[core.scala:406:44] wire new_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:406:29] wire new_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:406:29] wire next_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire p_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire p_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire p_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire p_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire p_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire p_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_is_br = 1'h0; // @[consts.scala:269:19] wire p_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire p_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire p_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire p_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire p_uop_taken = 1'h0; // @[consts.scala:269:19] wire p_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_exception = 1'h0; // @[consts.scala:269:19] wire p_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire p_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire p_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire p_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire p_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire p_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire p_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire p_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire p_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire p_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire p_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire p_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire p_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire p_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire p_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire p_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire p_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire p_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire p_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire p_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire p_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _dis_uops_0_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43] wire _dis_uops_0_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48] wire p_uop_1_is_rvc = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire p_uop_1_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_1_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_br = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_jalr = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_jal = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_sfb = 1'h0; // @[consts.scala:269:19] wire p_uop_1_edge_inst = 1'h0; // @[consts.scala:269:19] wire p_uop_1_taken = 1'h0; // @[consts.scala:269:19] wire p_uop_1_prs1_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_1_prs2_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_1_prs3_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ppred_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_1_exception = 1'h0; // @[consts.scala:269:19] wire p_uop_1_bypassable = 1'h0; // @[consts.scala:269:19] wire p_uop_1_mem_signed = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_fence = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_fencei = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_amo = 1'h0; // @[consts.scala:269:19] wire p_uop_1_uses_ldq = 1'h0; // @[consts.scala:269:19] wire p_uop_1_uses_stq = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_unique = 1'h0; // @[consts.scala:269:19] wire p_uop_1_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ldst_val = 1'h0; // @[consts.scala:269:19] wire p_uop_1_frs3_en = 1'h0; // @[consts.scala:269:19] wire p_uop_1_fp_val = 1'h0; // @[consts.scala:269:19] wire p_uop_1_fp_single = 1'h0; // @[consts.scala:269:19] wire p_uop_1_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire p_uop_1_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire p_uop_1_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire p_uop_1_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire p_uop_1_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire p_uop_cs_1_fcn_dw = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_1_is_load = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_1_is_sta = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_1_is_std = 1'h0; // @[consts.scala:279:18] wire _dis_uops_1_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43] wire _dis_uops_1_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48] wire p_uop_2_is_rvc = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire p_uop_2_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_2_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_br = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_jalr = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_jal = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_sfb = 1'h0; // @[consts.scala:269:19] wire p_uop_2_edge_inst = 1'h0; // @[consts.scala:269:19] wire p_uop_2_taken = 1'h0; // @[consts.scala:269:19] wire p_uop_2_prs1_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_2_prs2_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_2_prs3_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ppred_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_2_exception = 1'h0; // @[consts.scala:269:19] wire p_uop_2_bypassable = 1'h0; // @[consts.scala:269:19] wire p_uop_2_mem_signed = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_fence = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_fencei = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_amo = 1'h0; // @[consts.scala:269:19] wire p_uop_2_uses_ldq = 1'h0; // @[consts.scala:269:19] wire p_uop_2_uses_stq = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_unique = 1'h0; // @[consts.scala:269:19] wire p_uop_2_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ldst_val = 1'h0; // @[consts.scala:269:19] wire p_uop_2_frs3_en = 1'h0; // @[consts.scala:269:19] wire p_uop_2_fp_val = 1'h0; // @[consts.scala:269:19] wire p_uop_2_fp_single = 1'h0; // @[consts.scala:269:19] wire p_uop_2_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire p_uop_2_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire p_uop_2_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire p_uop_2_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire p_uop_2_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire p_uop_cs_2_fcn_dw = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_2_is_load = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_2_is_sta = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_2_is_std = 1'h0; // @[consts.scala:279:18] wire _dis_uops_2_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43] wire _dis_uops_2_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48] wire _wait_for_rocc_T_1 = 1'h0; // @[core.scala:689:90] wire wait_for_rocc_0 = 1'h0; // @[core.scala:689:73] wire _wait_for_rocc_T_3 = 1'h0; // @[core.scala:689:90] wire wait_for_rocc_1 = 1'h0; // @[core.scala:689:73] wire _wait_for_rocc_T_5 = 1'h0; // @[core.scala:689:90] wire wait_for_rocc_2 = 1'h0; // @[core.scala:689:73] wire fast_wakeup_bits_predicated = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29] wire slow_wakeup_bits_predicated = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29] wire fast_wakeup_1_bits_predicated = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_valid = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29] wire slow_wakeup_1_bits_predicated = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_valid = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29] wire fast_wakeup_2_bits_predicated = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_valid = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29] wire slow_wakeup_2_bits_predicated = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_valid = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29] wire _pred_wakeup_valid_T_1 = 1'h0; // @[micro-op.scala:109:42] wire _pred_wakeup_valid_T_2 = 1'h0; // @[core.scala:862:50] wire _pred_wakeup_valid_T_6 = 1'h0; // @[core.scala:863:58] wire _rob_io_csr_replay_valid_T = 1'h0; // @[core.scala:1008:58] wire _large_T_3 = 1'h0; // @[Counters.scala:68:28] wire coreMonitorBundle_excpt = 1'h0; // @[core.scala:1405:31] wire coreMonitorBundle_valid = 1'h0; // @[core.scala:1405:31] wire coreMonitorBundle_wrenx = 1'h0; // @[core.scala:1405:31] wire coreMonitorBundle_wrenf = 1'h0; // @[core.scala:1405:31] wire _io_rocc_exception_T = 1'h0; // @[core.scala:1424:61] wire _io_rocc_exception_T_1 = 1'h0; // @[core.scala:1424:41] wire [15:0] io_ifu_fetchpacket_bits_uops_0_bits_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_ifu_fetchpacket_bits_uops_1_bits_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_ifu_fetchpacket_bits_uops_2_bits_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_tlb_ptbr_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_tlb_hgatp_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_tlb_vsatp_asid = 16'h0; // @[core.scala:51:7] wire [15:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] pred_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:149:26] wire [15:0] bypasses_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] bypasses_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] bypasses_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] bypasses_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] bypasses_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] pred_bypasses_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:175:27] wire [15:0] p_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] p_uop_1_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] p_uop_2_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] fast_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29] wire [15:0] slow_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29] wire [15:0] fast_wakeup_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29] wire [15:0] slow_wakeup_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29] wire [15:0] fast_wakeup_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29] wire [15:0] slow_wakeup_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29] wire [19:0] io_ifu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_ifu_fetchpacket_bits_uops_1_bits_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_ifu_fetchpacket_bits_uops_2_bits_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] int_iss_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_ren_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] pred_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:149:26] wire [19:0] bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] bypasses_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] bypasses_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] bypasses_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] bypasses_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] pred_bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:175:27] wire [19:0] p_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] p_uop_1_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] p_uop_2_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] fast_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29] wire [19:0] slow_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29] wire [19:0] fast_wakeup_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29] wire [19:0] slow_wakeup_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29] wire [19:0] fast_wakeup_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29] wire [19:0] slow_wakeup_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29] wire [11:0] io_ifu_fetchpacket_bits_uops_0_bits_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_ifu_fetchpacket_bits_uops_1_bits_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_ifu_fetchpacket_bits_uops_2_bits_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] int_iss_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_ren_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] pred_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:149:26] wire [11:0] dec_uops_0_csr_addr = 12'h0; // @[core.scala:158:24] wire [11:0] dec_uops_1_csr_addr = 12'h0; // @[core.scala:158:24] wire [11:0] dec_uops_2_csr_addr = 12'h0; // @[core.scala:158:24] wire [11:0] bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] bypasses_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] bypasses_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] bypasses_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] bypasses_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] pred_bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:175:27] wire [11:0] p_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] p_uop_1_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] p_uop_2_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] fast_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29] wire [11:0] slow_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29] wire [11:0] fast_wakeup_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29] wire [11:0] slow_wakeup_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29] wire [11:0] fast_wakeup_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29] wire [11:0] slow_wakeup_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29] wire [63:0] io_ifu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_ifu_fetchpacket_bits_uops_1_bits_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_ifu_fetchpacket_bits_uops_2_bits_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_ifu_get_pc_0_ghist_old_history = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_cmd_bits_rs1 = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_cmd_bits_rs2 = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_value = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_value = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_trace_insns_0_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_trace_insns_1_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_trace_insns_2_cause = 64'h0; // @[core.scala:51:7] wire [63:0] int_iss_wakeups_1_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_2_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_3_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_4_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_5_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_6_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_ren_wakeups_1_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_2_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_3_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_4_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_5_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_6_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] pred_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:149:26] wire [63:0] bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] bypasses_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] bypasses_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] bypasses_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] bypasses_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] pred_bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:175:27] wire [63:0] custom_csrs_csrs_0_sdata = 64'h0; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_1_sdata = 64'h0; // @[core.scala:276:25] wire [63:0] _new_ghist_WIRE_old_history = 64'h0; // @[core.scala:406:44] wire [63:0] new_ghist_old_history = 64'h0; // @[core.scala:406:29] wire [63:0] p_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] p_uop_1_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] p_uop_2_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] fast_wakeup_bits_data = 64'h0; // @[core.scala:814:29] wire [63:0] fast_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29] wire [63:0] slow_wakeup_bits_data = 64'h0; // @[core.scala:815:29] wire [63:0] slow_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29] wire [63:0] fast_wakeup_1_bits_data = 64'h0; // @[core.scala:814:29] wire [63:0] fast_wakeup_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29] wire [63:0] slow_wakeup_1_bits_data = 64'h0; // @[core.scala:815:29] wire [63:0] slow_wakeup_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29] wire [63:0] fast_wakeup_2_bits_data = 64'h0; // @[core.scala:814:29] wire [63:0] fast_wakeup_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29] wire [63:0] slow_wakeup_2_bits_data = 64'h0; // @[core.scala:815:29] wire [63:0] slow_wakeup_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29] wire [63:0] coreMonitorBundle_hartid = 64'h0; // @[core.scala:1405:31] wire [63:0] coreMonitorBundle_pc = 64'h0; // @[core.scala:1405:31] wire [63:0] coreMonitorBundle_wrdata = 64'h0; // @[core.scala:1405:31] wire [63:0] coreMonitorBundle_rd0val = 64'h0; // @[core.scala:1405:31] wire [63:0] coreMonitorBundle_rd1val = 64'h0; // @[core.scala:1405:31] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ptw_tlb_hstatus_vgein = 6'h0; // @[core.scala:51:7] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] pred_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:149:26] wire [5:0] bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:175:27] wire [5:0] p_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] fast_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29] wire [31:0] io_ifu_status_isa = 32'h14112D; // @[core.scala:51:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_status_isa = 32'h14112D; // @[core.scala:51:7] wire [22:0] io_ifu_status_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_ptw_tlb_status_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_ptw_tlb_gstatus_zero2 = 23'h0; // @[core.scala:51:7] wire [7:0] io_ifu_status_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[core.scala:51:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[core.scala:51:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[core.scala:51:7] wire [7:0] io_ptw_tlb_status_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_ptw_tlb_gstatus_zero1 = 8'h0; // @[core.scala:51:7] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[core.scala:51:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[core.scala:51:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_0_iaddr = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_0_tval = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_1_iaddr = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_1_tval = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_2_iaddr = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_2_tval = 40'h0; // @[core.scala:51:7] wire [39:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] pred_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:149:26] wire [39:0] bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] bypasses_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] bypasses_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] bypasses_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] bypasses_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] pred_bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:175:27] wire [39:0] p_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] p_uop_1_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] p_uop_2_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] fast_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29] wire [39:0] slow_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29] wire [39:0] fast_wakeup_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29] wire [39:0] slow_wakeup_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29] wire [39:0] fast_wakeup_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29] wire [39:0] slow_wakeup_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29] wire [1:0] io_ifu_status_sxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ifu_status_uxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_sxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_uxl = 2'h2; // @[core.scala:51:7] wire [1:0] p_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] p_uop_1_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] p_uop_2_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[core.scala:51:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[core.scala:51:7] wire [43:0] io_ptw_tlb_hgatp_ppn = 44'h0; // @[core.scala:51:7] wire [43:0] io_ptw_tlb_vsatp_ppn = 44'h0; // @[core.scala:51:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_hstatus_zero6 = 30'h0; // @[core.scala:51:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[core.scala:51:7] wire [8:0] io_ptw_tlb_hstatus_zero5 = 9'h0; // @[core.scala:51:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[core.scala:51:7] wire [31:0] io_rocc_cmd_bits_status_isa = 32'h0; // @[core.scala:51:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_gstatus_isa = 32'h0; // @[core.scala:51:7] wire [31:0] io_trace_insns_0_insn = 32'h0; // @[core.scala:51:7] wire [31:0] io_trace_insns_1_insn = 32'h0; // @[core.scala:51:7] wire [31:0] io_trace_insns_2_insn = 32'h0; // @[core.scala:51:7] wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_5_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_6_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_5_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_6_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] pred_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:149:26] wire [31:0] pred_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:149:26] wire [31:0] bypasses_0_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:175:27] wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:175:27] wire [31:0] p_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_1_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_1_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_2_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_2_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] fast_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29] wire [31:0] fast_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29] wire [31:0] slow_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29] wire [31:0] slow_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29] wire [31:0] fast_wakeup_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29] wire [31:0] fast_wakeup_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29] wire [31:0] slow_wakeup_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29] wire [31:0] slow_wakeup_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29] wire [31:0] fast_wakeup_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29] wire [31:0] fast_wakeup_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29] wire [31:0] slow_wakeup_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29] wire [31:0] slow_wakeup_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29] wire [31:0] coreMonitorBundle_timer = 32'h0; // @[core.scala:1405:31] wire [31:0] coreMonitorBundle_inst = 32'h0; // @[core.scala:1405:31] wire io_lsu_exe_0_iresp_ready = 1'h1; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_ready = 1'h1; // @[core.scala:51:7] wire _use_this_mispredict_T = 1'h1; // @[core.scala:206:31] wire use_this_mispredict = 1'h1; // @[core.scala:206:47] wire new_ghist_current_saw_branch_not_taken = 1'h1; // @[core.scala:406:29] wire flush_pc_req_ready = 1'h1; // @[core.scala:524:26] wire _large_T_1 = 1'h1; // @[Counters.scala:51:36] wire [26:0] io_ptw_tlb_req_bits_bits_addr = 27'h0; // @[core.scala:51:7] wire [4:0] _pause_mem_T = 5'h1F; // @[core.scala:912:77] wire [3:0] _cfi_idx_T_1 = 4'h8; // @[core.scala:442:45] wire [7:0] _next_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45] wire dec_ready; // @[core.scala:161:24] wire [4:0] new_ghist_ras_idx = io_ifu_get_pc_0_entry_ras_idx_0; // @[core.scala:51:7, :406:29] wire _cfi_idx_T = io_ifu_get_pc_1_entry_start_bank_0; // @[core.scala:51:7, :442:32] wire io_ptw_sfence_valid_0 = io_ifu_sfence_valid_0; // @[core.scala:51:7] wire io_ptw_sfence_bits_rs1_0 = io_ifu_sfence_bits_rs1_0; // @[core.scala:51:7] wire io_ptw_sfence_bits_rs2_0 = io_ifu_sfence_bits_rs2_0; // @[core.scala:51:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_ifu_sfence_bits_addr_0; // @[core.scala:51:7] wire io_ptw_sfence_bits_asid_0 = io_ifu_sfence_bits_asid_0; // @[core.scala:51:7] wire [15:0] brupdate_b1_resolve_mask; // @[core.scala:188:23] wire [15:0] brupdate_b1_mispredict_mask; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_uopc; // @[core.scala:188:23] wire [31:0] brupdate_b2_uop_inst; // @[core.scala:188:23] wire [31:0] brupdate_b2_uop_debug_inst; // @[core.scala:188:23] wire brupdate_b2_uop_is_rvc; // @[core.scala:188:23] wire [39:0] brupdate_b2_uop_debug_pc; // @[core.scala:188:23] wire [2:0] brupdate_b2_uop_iq_type; // @[core.scala:188:23] wire [9:0] brupdate_b2_uop_fu_code; // @[core.scala:188:23] wire [3:0] brupdate_b2_uop_ctrl_br_type; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:188:23] wire [2:0] brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:188:23] wire [2:0] brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:188:23] wire brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:188:23] wire [2:0] brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:188:23] wire brupdate_b2_uop_ctrl_is_load; // @[core.scala:188:23] wire brupdate_b2_uop_ctrl_is_sta; // @[core.scala:188:23] wire brupdate_b2_uop_ctrl_is_std; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_iw_state; // @[core.scala:188:23] wire brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:188:23] wire brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:188:23] wire brupdate_b2_uop_is_br; // @[core.scala:188:23] wire brupdate_b2_uop_is_jalr; // @[core.scala:188:23] wire brupdate_b2_uop_is_jal; // @[core.scala:188:23] wire brupdate_b2_uop_is_sfb; // @[core.scala:188:23] wire [15:0] brupdate_b2_uop_br_mask; // @[core.scala:188:23] wire [3:0] brupdate_b2_uop_br_tag; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_ftq_idx; // @[core.scala:188:23] wire brupdate_b2_uop_edge_inst; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_pc_lob; // @[core.scala:188:23] wire brupdate_b2_uop_taken; // @[core.scala:188:23] wire [19:0] brupdate_b2_uop_imm_packed; // @[core.scala:188:23] wire [11:0] brupdate_b2_uop_csr_addr; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_rob_idx; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_ldq_idx; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_stq_idx; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_rxq_idx; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_pdst; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_prs1; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_prs2; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_prs3; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_ppred; // @[core.scala:188:23] wire brupdate_b2_uop_prs1_busy; // @[core.scala:188:23] wire brupdate_b2_uop_prs2_busy; // @[core.scala:188:23] wire brupdate_b2_uop_prs3_busy; // @[core.scala:188:23] wire brupdate_b2_uop_ppred_busy; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_stale_pdst; // @[core.scala:188:23] wire brupdate_b2_uop_exception; // @[core.scala:188:23] wire [63:0] brupdate_b2_uop_exc_cause; // @[core.scala:188:23] wire brupdate_b2_uop_bypassable; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_mem_cmd; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_mem_size; // @[core.scala:188:23] wire brupdate_b2_uop_mem_signed; // @[core.scala:188:23] wire brupdate_b2_uop_is_fence; // @[core.scala:188:23] wire brupdate_b2_uop_is_fencei; // @[core.scala:188:23] wire brupdate_b2_uop_is_amo; // @[core.scala:188:23] wire brupdate_b2_uop_uses_ldq; // @[core.scala:188:23] wire brupdate_b2_uop_uses_stq; // @[core.scala:188:23] wire brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:188:23] wire brupdate_b2_uop_is_unique; // @[core.scala:188:23] wire brupdate_b2_uop_flush_on_commit; // @[core.scala:188:23] wire brupdate_b2_uop_ldst_is_rs1; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_ldst; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_lrs1; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_lrs2; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_lrs3; // @[core.scala:188:23] wire brupdate_b2_uop_ldst_val; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_dst_rtype; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_lrs1_rtype; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_lrs2_rtype; // @[core.scala:188:23] wire brupdate_b2_uop_frs3_en; // @[core.scala:188:23] wire brupdate_b2_uop_fp_val; // @[core.scala:188:23] wire brupdate_b2_uop_fp_single; // @[core.scala:188:23] wire brupdate_b2_uop_xcpt_pf_if; // @[core.scala:188:23] wire brupdate_b2_uop_xcpt_ae_if; // @[core.scala:188:23] wire brupdate_b2_uop_xcpt_ma_if; // @[core.scala:188:23] wire brupdate_b2_uop_bp_debug_if; // @[core.scala:188:23] wire brupdate_b2_uop_bp_xcpt_if; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_debug_fsrc; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_debug_tsrc; // @[core.scala:188:23] wire brupdate_b2_mispredict; // @[core.scala:188:23] wire brupdate_b2_taken; // @[core.scala:188:23] wire [2:0] brupdate_b2_cfi_type; // @[core.scala:188:23] wire [1:0] brupdate_b2_pc_sel; // @[core.scala:188:23] wire [39:0] brupdate_b2_jalr_target; // @[core.scala:188:23] wire [20:0] brupdate_b2_target_offset; // @[core.scala:188:23] wire _io_ifu_flush_icache_T_13; // @[core.scala:390:13] wire dis_fire_0; // @[core.scala:168:24] wire [6:0] dis_uops_0_uopc; // @[core.scala:167:24] wire [31:0] dis_uops_0_inst; // @[core.scala:167:24] wire [31:0] dis_uops_0_debug_inst; // @[core.scala:167:24] wire dis_uops_0_is_rvc; // @[core.scala:167:24] wire [39:0] dis_uops_0_debug_pc; // @[core.scala:167:24] wire [2:0] dis_uops_0_iq_type; // @[core.scala:167:24] wire [9:0] dis_uops_0_fu_code; // @[core.scala:167:24] wire [3:0] dis_uops_0_ctrl_br_type; // @[core.scala:167:24] wire [1:0] dis_uops_0_ctrl_op1_sel; // @[core.scala:167:24] wire [2:0] dis_uops_0_ctrl_op2_sel; // @[core.scala:167:24] wire [2:0] dis_uops_0_ctrl_imm_sel; // @[core.scala:167:24] wire [4:0] dis_uops_0_ctrl_op_fcn; // @[core.scala:167:24] wire dis_uops_0_ctrl_fcn_dw; // @[core.scala:167:24] wire [2:0] dis_uops_0_ctrl_csr_cmd; // @[core.scala:167:24] wire dis_uops_0_ctrl_is_load; // @[core.scala:167:24] wire dis_uops_0_ctrl_is_sta; // @[core.scala:167:24] wire dis_uops_0_ctrl_is_std; // @[core.scala:167:24] wire [1:0] dis_uops_0_iw_state; // @[core.scala:167:24] wire dis_uops_0_iw_p1_poisoned; // @[core.scala:167:24] wire dis_uops_0_iw_p2_poisoned; // @[core.scala:167:24] wire dis_uops_0_is_br; // @[core.scala:167:24] wire dis_uops_0_is_jalr; // @[core.scala:167:24] wire dis_uops_0_is_jal; // @[core.scala:167:24] wire dis_uops_0_is_sfb; // @[core.scala:167:24] wire [15:0] dis_uops_0_br_mask; // @[core.scala:167:24] wire [3:0] dis_uops_0_br_tag; // @[core.scala:167:24] wire [4:0] dis_uops_0_ftq_idx; // @[core.scala:167:24] wire dis_uops_0_edge_inst; // @[core.scala:167:24] wire [5:0] dis_uops_0_pc_lob; // @[core.scala:167:24] wire dis_uops_0_taken; // @[core.scala:167:24] wire [19:0] dis_uops_0_imm_packed; // @[core.scala:167:24] wire [11:0] dis_uops_0_csr_addr; // @[core.scala:167:24] wire [6:0] dis_uops_0_rob_idx; // @[core.scala:167:24] wire [4:0] dis_uops_0_ldq_idx; // @[core.scala:167:24] wire [4:0] dis_uops_0_stq_idx; // @[core.scala:167:24] wire [1:0] dis_uops_0_rxq_idx; // @[core.scala:167:24] wire [6:0] dis_uops_0_pdst; // @[core.scala:167:24] wire [6:0] dis_uops_0_prs1; // @[core.scala:167:24] wire [6:0] dis_uops_0_prs2; // @[core.scala:167:24] wire [6:0] dis_uops_0_prs3; // @[core.scala:167:24] wire dis_uops_0_prs1_busy; // @[core.scala:167:24] wire dis_uops_0_prs2_busy; // @[core.scala:167:24] wire dis_uops_0_prs3_busy; // @[core.scala:167:24] wire [6:0] dis_uops_0_stale_pdst; // @[core.scala:167:24] wire dis_uops_0_exception; // @[core.scala:167:24] wire [63:0] dis_uops_0_exc_cause; // @[core.scala:167:24] wire dis_uops_0_bypassable; // @[core.scala:167:24] wire [4:0] dis_uops_0_mem_cmd; // @[core.scala:167:24] wire [1:0] dis_uops_0_mem_size; // @[core.scala:167:24] wire dis_uops_0_mem_signed; // @[core.scala:167:24] wire dis_uops_0_is_fence; // @[core.scala:167:24] wire dis_uops_0_is_fencei; // @[core.scala:167:24] wire dis_uops_0_is_amo; // @[core.scala:167:24] wire dis_uops_0_uses_ldq; // @[core.scala:167:24] wire dis_uops_0_uses_stq; // @[core.scala:167:24] wire dis_uops_0_is_sys_pc2epc; // @[core.scala:167:24] wire dis_uops_0_is_unique; // @[core.scala:167:24] wire dis_uops_0_flush_on_commit; // @[core.scala:167:24] wire dis_uops_0_ldst_is_rs1; // @[core.scala:167:24] wire [5:0] dis_uops_0_ldst; // @[core.scala:167:24] wire [5:0] dis_uops_0_lrs1; // @[core.scala:167:24] wire [5:0] dis_uops_0_lrs2; // @[core.scala:167:24] wire [5:0] dis_uops_0_lrs3; // @[core.scala:167:24] wire dis_uops_0_ldst_val; // @[core.scala:167:24] wire [1:0] dis_uops_0_dst_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_0_lrs1_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_0_lrs2_rtype; // @[core.scala:167:24] wire dis_uops_0_frs3_en; // @[core.scala:167:24] wire dis_uops_0_fp_val; // @[core.scala:167:24] wire dis_uops_0_fp_single; // @[core.scala:167:24] wire dis_uops_0_xcpt_pf_if; // @[core.scala:167:24] wire dis_uops_0_xcpt_ae_if; // @[core.scala:167:24] wire dis_uops_0_xcpt_ma_if; // @[core.scala:167:24] wire dis_uops_0_bp_debug_if; // @[core.scala:167:24] wire dis_uops_0_bp_xcpt_if; // @[core.scala:167:24] wire [1:0] dis_uops_0_debug_fsrc; // @[core.scala:167:24] wire [1:0] dis_uops_0_debug_tsrc; // @[core.scala:167:24] wire dis_fire_1; // @[core.scala:168:24] wire [6:0] dis_uops_1_uopc; // @[core.scala:167:24] wire [31:0] dis_uops_1_inst; // @[core.scala:167:24] wire [31:0] dis_uops_1_debug_inst; // @[core.scala:167:24] wire dis_uops_1_is_rvc; // @[core.scala:167:24] wire [39:0] dis_uops_1_debug_pc; // @[core.scala:167:24] wire [2:0] dis_uops_1_iq_type; // @[core.scala:167:24] wire [9:0] dis_uops_1_fu_code; // @[core.scala:167:24] wire [3:0] dis_uops_1_ctrl_br_type; // @[core.scala:167:24] wire [1:0] dis_uops_1_ctrl_op1_sel; // @[core.scala:167:24] wire [2:0] dis_uops_1_ctrl_op2_sel; // @[core.scala:167:24] wire [2:0] dis_uops_1_ctrl_imm_sel; // @[core.scala:167:24] wire [4:0] dis_uops_1_ctrl_op_fcn; // @[core.scala:167:24] wire dis_uops_1_ctrl_fcn_dw; // @[core.scala:167:24] wire [2:0] dis_uops_1_ctrl_csr_cmd; // @[core.scala:167:24] wire dis_uops_1_ctrl_is_load; // @[core.scala:167:24] wire dis_uops_1_ctrl_is_sta; // @[core.scala:167:24] wire dis_uops_1_ctrl_is_std; // @[core.scala:167:24] wire [1:0] dis_uops_1_iw_state; // @[core.scala:167:24] wire dis_uops_1_iw_p1_poisoned; // @[core.scala:167:24] wire dis_uops_1_iw_p2_poisoned; // @[core.scala:167:24] wire dis_uops_1_is_br; // @[core.scala:167:24] wire dis_uops_1_is_jalr; // @[core.scala:167:24] wire dis_uops_1_is_jal; // @[core.scala:167:24] wire dis_uops_1_is_sfb; // @[core.scala:167:24] wire [15:0] dis_uops_1_br_mask; // @[core.scala:167:24] wire [3:0] dis_uops_1_br_tag; // @[core.scala:167:24] wire [4:0] dis_uops_1_ftq_idx; // @[core.scala:167:24] wire dis_uops_1_edge_inst; // @[core.scala:167:24] wire [5:0] dis_uops_1_pc_lob; // @[core.scala:167:24] wire dis_uops_1_taken; // @[core.scala:167:24] wire [19:0] dis_uops_1_imm_packed; // @[core.scala:167:24] wire [11:0] dis_uops_1_csr_addr; // @[core.scala:167:24] wire [6:0] dis_uops_1_rob_idx; // @[core.scala:167:24] wire [4:0] dis_uops_1_ldq_idx; // @[core.scala:167:24] wire [4:0] dis_uops_1_stq_idx; // @[core.scala:167:24] wire [1:0] dis_uops_1_rxq_idx; // @[core.scala:167:24] wire [6:0] dis_uops_1_pdst; // @[core.scala:167:24] wire [6:0] dis_uops_1_prs1; // @[core.scala:167:24] wire [6:0] dis_uops_1_prs2; // @[core.scala:167:24] wire [6:0] dis_uops_1_prs3; // @[core.scala:167:24] wire dis_uops_1_prs1_busy; // @[core.scala:167:24] wire dis_uops_1_prs2_busy; // @[core.scala:167:24] wire dis_uops_1_prs3_busy; // @[core.scala:167:24] wire [6:0] dis_uops_1_stale_pdst; // @[core.scala:167:24] wire dis_uops_1_exception; // @[core.scala:167:24] wire [63:0] dis_uops_1_exc_cause; // @[core.scala:167:24] wire dis_uops_1_bypassable; // @[core.scala:167:24] wire [4:0] dis_uops_1_mem_cmd; // @[core.scala:167:24] wire [1:0] dis_uops_1_mem_size; // @[core.scala:167:24] wire dis_uops_1_mem_signed; // @[core.scala:167:24] wire dis_uops_1_is_fence; // @[core.scala:167:24] wire dis_uops_1_is_fencei; // @[core.scala:167:24] wire dis_uops_1_is_amo; // @[core.scala:167:24] wire dis_uops_1_uses_ldq; // @[core.scala:167:24] wire dis_uops_1_uses_stq; // @[core.scala:167:24] wire dis_uops_1_is_sys_pc2epc; // @[core.scala:167:24] wire dis_uops_1_is_unique; // @[core.scala:167:24] wire dis_uops_1_flush_on_commit; // @[core.scala:167:24] wire dis_uops_1_ldst_is_rs1; // @[core.scala:167:24] wire [5:0] dis_uops_1_ldst; // @[core.scala:167:24] wire [5:0] dis_uops_1_lrs1; // @[core.scala:167:24] wire [5:0] dis_uops_1_lrs2; // @[core.scala:167:24] wire [5:0] dis_uops_1_lrs3; // @[core.scala:167:24] wire dis_uops_1_ldst_val; // @[core.scala:167:24] wire [1:0] dis_uops_1_dst_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_1_lrs1_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_1_lrs2_rtype; // @[core.scala:167:24] wire dis_uops_1_frs3_en; // @[core.scala:167:24] wire dis_uops_1_fp_val; // @[core.scala:167:24] wire dis_uops_1_fp_single; // @[core.scala:167:24] wire dis_uops_1_xcpt_pf_if; // @[core.scala:167:24] wire dis_uops_1_xcpt_ae_if; // @[core.scala:167:24] wire dis_uops_1_xcpt_ma_if; // @[core.scala:167:24] wire dis_uops_1_bp_debug_if; // @[core.scala:167:24] wire dis_uops_1_bp_xcpt_if; // @[core.scala:167:24] wire [1:0] dis_uops_1_debug_fsrc; // @[core.scala:167:24] wire [1:0] dis_uops_1_debug_tsrc; // @[core.scala:167:24] wire dis_fire_2; // @[core.scala:168:24] wire [6:0] dis_uops_2_uopc; // @[core.scala:167:24] wire [31:0] dis_uops_2_inst; // @[core.scala:167:24] wire [31:0] dis_uops_2_debug_inst; // @[core.scala:167:24] wire dis_uops_2_is_rvc; // @[core.scala:167:24] wire [39:0] dis_uops_2_debug_pc; // @[core.scala:167:24] wire [2:0] dis_uops_2_iq_type; // @[core.scala:167:24] wire [9:0] dis_uops_2_fu_code; // @[core.scala:167:24] wire [3:0] dis_uops_2_ctrl_br_type; // @[core.scala:167:24] wire [1:0] dis_uops_2_ctrl_op1_sel; // @[core.scala:167:24] wire [2:0] dis_uops_2_ctrl_op2_sel; // @[core.scala:167:24] wire [2:0] dis_uops_2_ctrl_imm_sel; // @[core.scala:167:24] wire [4:0] dis_uops_2_ctrl_op_fcn; // @[core.scala:167:24] wire dis_uops_2_ctrl_fcn_dw; // @[core.scala:167:24] wire [2:0] dis_uops_2_ctrl_csr_cmd; // @[core.scala:167:24] wire dis_uops_2_ctrl_is_load; // @[core.scala:167:24] wire dis_uops_2_ctrl_is_sta; // @[core.scala:167:24] wire dis_uops_2_ctrl_is_std; // @[core.scala:167:24] wire [1:0] dis_uops_2_iw_state; // @[core.scala:167:24] wire dis_uops_2_iw_p1_poisoned; // @[core.scala:167:24] wire dis_uops_2_iw_p2_poisoned; // @[core.scala:167:24] wire dis_uops_2_is_br; // @[core.scala:167:24] wire dis_uops_2_is_jalr; // @[core.scala:167:24] wire dis_uops_2_is_jal; // @[core.scala:167:24] wire dis_uops_2_is_sfb; // @[core.scala:167:24] wire [15:0] dis_uops_2_br_mask; // @[core.scala:167:24] wire [3:0] dis_uops_2_br_tag; // @[core.scala:167:24] wire [4:0] dis_uops_2_ftq_idx; // @[core.scala:167:24] wire dis_uops_2_edge_inst; // @[core.scala:167:24] wire [5:0] dis_uops_2_pc_lob; // @[core.scala:167:24] wire dis_uops_2_taken; // @[core.scala:167:24] wire [19:0] dis_uops_2_imm_packed; // @[core.scala:167:24] wire [11:0] dis_uops_2_csr_addr; // @[core.scala:167:24] wire [6:0] dis_uops_2_rob_idx; // @[core.scala:167:24] wire [4:0] dis_uops_2_ldq_idx; // @[core.scala:167:24] wire [4:0] dis_uops_2_stq_idx; // @[core.scala:167:24] wire [1:0] dis_uops_2_rxq_idx; // @[core.scala:167:24] wire [6:0] dis_uops_2_pdst; // @[core.scala:167:24] wire [6:0] dis_uops_2_prs1; // @[core.scala:167:24] wire [6:0] dis_uops_2_prs2; // @[core.scala:167:24] wire [6:0] dis_uops_2_prs3; // @[core.scala:167:24] wire dis_uops_2_prs1_busy; // @[core.scala:167:24] wire dis_uops_2_prs2_busy; // @[core.scala:167:24] wire dis_uops_2_prs3_busy; // @[core.scala:167:24] wire [6:0] dis_uops_2_stale_pdst; // @[core.scala:167:24] wire dis_uops_2_exception; // @[core.scala:167:24] wire [63:0] dis_uops_2_exc_cause; // @[core.scala:167:24] wire dis_uops_2_bypassable; // @[core.scala:167:24] wire [4:0] dis_uops_2_mem_cmd; // @[core.scala:167:24] wire [1:0] dis_uops_2_mem_size; // @[core.scala:167:24] wire dis_uops_2_mem_signed; // @[core.scala:167:24] wire dis_uops_2_is_fence; // @[core.scala:167:24] wire dis_uops_2_is_fencei; // @[core.scala:167:24] wire dis_uops_2_is_amo; // @[core.scala:167:24] wire dis_uops_2_uses_ldq; // @[core.scala:167:24] wire dis_uops_2_uses_stq; // @[core.scala:167:24] wire dis_uops_2_is_sys_pc2epc; // @[core.scala:167:24] wire dis_uops_2_is_unique; // @[core.scala:167:24] wire dis_uops_2_flush_on_commit; // @[core.scala:167:24] wire dis_uops_2_ldst_is_rs1; // @[core.scala:167:24] wire [5:0] dis_uops_2_ldst; // @[core.scala:167:24] wire [5:0] dis_uops_2_lrs1; // @[core.scala:167:24] wire [5:0] dis_uops_2_lrs2; // @[core.scala:167:24] wire [5:0] dis_uops_2_lrs3; // @[core.scala:167:24] wire dis_uops_2_ldst_val; // @[core.scala:167:24] wire [1:0] dis_uops_2_dst_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_2_lrs1_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_2_lrs2_rtype; // @[core.scala:167:24] wire dis_uops_2_frs3_en; // @[core.scala:167:24] wire dis_uops_2_fp_val; // @[core.scala:167:24] wire dis_uops_2_fp_single; // @[core.scala:167:24] wire dis_uops_2_xcpt_pf_if; // @[core.scala:167:24] wire dis_uops_2_xcpt_ae_if; // @[core.scala:167:24] wire dis_uops_2_xcpt_ma_if; // @[core.scala:167:24] wire dis_uops_2_bp_debug_if; // @[core.scala:167:24] wire dis_uops_2_bp_xcpt_if; // @[core.scala:167:24] wire [1:0] dis_uops_2_debug_fsrc; // @[core.scala:167:24] wire [1:0] dis_uops_2_debug_tsrc; // @[core.scala:167:24] assign dis_uops_0_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[core.scala:51:7, :167:24] assign dis_uops_1_ldq_idx = io_lsu_dis_ldq_idx_1_0; // @[core.scala:51:7, :167:24] assign dis_uops_2_ldq_idx = io_lsu_dis_ldq_idx_2_0; // @[core.scala:51:7, :167:24] assign dis_uops_0_stq_idx = io_lsu_dis_stq_idx_0_0; // @[core.scala:51:7, :167:24] assign dis_uops_1_stq_idx = io_lsu_dis_stq_idx_1_0; // @[core.scala:51:7, :167:24] assign dis_uops_2_stq_idx = io_lsu_dis_stq_idx_2_0; // @[core.scala:51:7, :167:24] wire _io_lsu_fence_dmem_T_4; // @[core.scala:711:101] wire io_ifu_fetchpacket_ready_0; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_0_ftq_idx_0; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_1_ftq_idx_0; // @[core.scala:51:7] wire io_ifu_status_debug_0; // @[core.scala:51:7] wire io_ifu_status_cease_0; // @[core.scala:51:7] wire io_ifu_status_wfi_0; // @[core.scala:51:7] wire [1:0] io_ifu_status_dprv_0; // @[core.scala:51:7] wire io_ifu_status_dv_0; // @[core.scala:51:7] wire [1:0] io_ifu_status_prv_0; // @[core.scala:51:7] wire io_ifu_status_v_0; // @[core.scala:51:7] wire io_ifu_status_sd_0; // @[core.scala:51:7] wire io_ifu_status_mpv_0; // @[core.scala:51:7] wire io_ifu_status_gva_0; // @[core.scala:51:7] wire io_ifu_status_tsr_0; // @[core.scala:51:7] wire io_ifu_status_tw_0; // @[core.scala:51:7] wire io_ifu_status_tvm_0; // @[core.scala:51:7] wire io_ifu_status_mxr_0; // @[core.scala:51:7] wire io_ifu_status_sum_0; // @[core.scala:51:7] wire io_ifu_status_mprv_0; // @[core.scala:51:7] wire [1:0] io_ifu_status_fs_0; // @[core.scala:51:7] wire [1:0] io_ifu_status_mpp_0; // @[core.scala:51:7] wire io_ifu_status_spp_0; // @[core.scala:51:7] wire io_ifu_status_mpie_0; // @[core.scala:51:7] wire io_ifu_status_spie_0; // @[core.scala:51:7] wire io_ifu_status_mie_0; // @[core.scala:51:7] wire io_ifu_status_sie_0; // @[core.scala:51:7] wire [15:0] io_ifu_brupdate_b1_resolve_mask_0; // @[core.scala:51:7] wire [15:0] io_ifu_brupdate_b1_mispredict_mask_0; // @[core.scala:51:7] wire [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_ifu_brupdate_b2_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_ifu_brupdate_b2_uop_debug_inst_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_ifu_brupdate_b2_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_ifu_brupdate_b2_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_iw_state_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_br_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_jalr_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_jal_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_ifu_brupdate_b2_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_ifu_brupdate_b2_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_pc_lob_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_ifu_brupdate_b2_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_ifu_brupdate_b2_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_ppred_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_ifu_brupdate_b2_uop_exc_cause_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_mem_size_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_mem_signed_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_fence_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_fencei_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_amo_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_uses_stq_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_unique_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs3_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_frs3_en_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_fp_val_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_fp_single_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_valid_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_mispredict_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_taken_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_cfi_type_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_pc_sel_0; // @[core.scala:51:7] wire [39:0] io_ifu_brupdate_b2_jalr_target_0; // @[core.scala:51:7] wire [20:0] io_ifu_brupdate_b2_target_offset_0; // @[core.scala:51:7] wire [63:0] io_ifu_redirect_ghist_old_history_0; // @[core.scala:51:7] wire io_ifu_redirect_ghist_current_saw_branch_not_taken_0; // @[core.scala:51:7] wire io_ifu_redirect_ghist_new_saw_branch_not_taken_0; // @[core.scala:51:7] wire io_ifu_redirect_ghist_new_saw_branch_taken_0; // @[core.scala:51:7] wire [4:0] io_ifu_redirect_ghist_ras_idx_0; // @[core.scala:51:7] wire io_ifu_commit_valid_0; // @[core.scala:51:7] wire [31:0] io_ifu_commit_bits_0; // @[core.scala:51:7] wire io_ifu_redirect_flush_0; // @[core.scala:51:7] wire io_ifu_redirect_val_0; // @[core.scala:51:7] wire [39:0] io_ifu_redirect_pc_0; // @[core.scala:51:7] wire [4:0] io_ifu_redirect_ftq_idx_0; // @[core.scala:51:7] wire io_ifu_flush_icache_0; // @[core.scala:51:7] wire [3:0] io_ptw_ptbr_mode_0; // @[core.scala:51:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[core.scala:51:7] wire io_ptw_status_debug_0; // @[core.scala:51:7] wire io_ptw_status_cease_0; // @[core.scala:51:7] wire io_ptw_status_wfi_0; // @[core.scala:51:7] wire [1:0] io_ptw_status_dprv_0; // @[core.scala:51:7] wire io_ptw_status_dv_0; // @[core.scala:51:7] wire [1:0] io_ptw_status_prv_0; // @[core.scala:51:7] wire io_ptw_status_v_0; // @[core.scala:51:7] wire io_ptw_status_sd_0; // @[core.scala:51:7] wire io_ptw_status_mpv_0; // @[core.scala:51:7] wire io_ptw_status_gva_0; // @[core.scala:51:7] wire io_ptw_status_tsr_0; // @[core.scala:51:7] wire io_ptw_status_tw_0; // @[core.scala:51:7] wire io_ptw_status_tvm_0; // @[core.scala:51:7] wire io_ptw_status_mxr_0; // @[core.scala:51:7] wire io_ptw_status_sum_0; // @[core.scala:51:7] wire io_ptw_status_mprv_0; // @[core.scala:51:7] wire [1:0] io_ptw_status_fs_0; // @[core.scala:51:7] wire [1:0] io_ptw_status_mpp_0; // @[core.scala:51:7] wire io_ptw_status_spp_0; // @[core.scala:51:7] wire io_ptw_status_mpie_0; // @[core.scala:51:7] wire io_ptw_status_spie_0; // @[core.scala:51:7] wire io_ptw_status_mie_0; // @[core.scala:51:7] wire io_ptw_status_sie_0; // @[core.scala:51:7] wire io_ptw_pmp_0_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_0_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_0_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_0_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_1_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_1_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_1_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_1_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_2_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_2_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_2_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_2_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_3_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_3_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_3_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_3_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_4_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_4_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_4_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_4_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_5_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_5_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_5_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_5_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_6_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_6_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_6_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_6_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_7_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_7_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_7_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_7_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_req_bits_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_req_bits_uop_debug_inst_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_req_bits_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_req_bits_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_iw_state_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_br_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_jalr_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_jal_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_req_bits_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_req_bits_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_pc_lob_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_req_bits_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_req_bits_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_ppred_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_req_bits_uop_exc_cause_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_mem_size_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_mem_signed_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_fence_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_fencei_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_amo_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_uses_stq_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_unique_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs3_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_frs3_en_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_fp_val_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_fp_single_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_mxcpt_valid_0; // @[core.scala:51:7] wire [24:0] io_lsu_exe_0_req_bits_mxcpt_bits_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_rs1_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_rs2_0; // @[core.scala:51:7] wire [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_asid_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_valid_0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_req_bits_data_0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_req_bits_addr_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_valid_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_0_bits_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_dis_uops_0_bits_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_0_bits_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_dis_uops_0_bits_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_iw_state_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_br_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_jalr_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_jal_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_dis_uops_0_bits_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_0_bits_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_pc_lob_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_dis_uops_0_bits_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_dis_uops_0_bits_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_prs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_prs3_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_dis_uops_0_bits_exc_cause_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_mem_size_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_mem_signed_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_fence_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_fencei_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_amo_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_unique_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_frs3_en_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_fp_val_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_fp_single_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_valid_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_1_bits_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_1_bits_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_1_bits_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_1_bits_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_1_bits_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_1_bits_debug_inst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_dis_uops_1_bits_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_1_bits_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_dis_uops_1_bits_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_iw_state_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_br_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_jalr_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_jal_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_dis_uops_1_bits_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_1_bits_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_pc_lob_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_dis_uops_1_bits_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_dis_uops_1_bits_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_prs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_prs3_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_dis_uops_1_bits_exc_cause_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_mem_size_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_mem_signed_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_fence_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_fencei_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_amo_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_uses_stq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_unique_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_frs3_en_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_fp_val_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_fp_single_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_valid_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_2_bits_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_2_bits_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_2_bits_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_2_bits_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_2_bits_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_2_bits_debug_inst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_dis_uops_2_bits_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_2_bits_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_dis_uops_2_bits_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_iw_state_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_br_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_jalr_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_jal_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_dis_uops_2_bits_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_2_bits_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_pc_lob_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_dis_uops_2_bits_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_dis_uops_2_bits_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_prs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_prs3_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_dis_uops_2_bits_exc_cause_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_mem_size_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_mem_signed_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_fence_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_fencei_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_amo_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_uses_stq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_unique_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_lrs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_frs3_en_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_fp_val_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_fp_single_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_valid_0; // @[core.scala:51:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_fp_stdata_bits_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_fp_stdata_bits_uop_debug_inst_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_fp_stdata_bits_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_fp_stdata_bits_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_iw_state_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_br_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_jalr_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_jal_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_fp_stdata_bits_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_fp_stdata_bits_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_pc_lob_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_fp_stdata_bits_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_fp_stdata_bits_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ppred_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_fp_stdata_bits_uop_exc_cause_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_mem_size_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_mem_signed_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_fence_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_fencei_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_amo_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_uses_stq_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_unique_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs3_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_frs3_en_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_fp_val_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_fp_single_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc_0; // @[core.scala:51:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_br_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_valid_0; // @[core.scala:51:7] wire [63:0] io_lsu_fp_stdata_bits_data_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_predicated_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_valid_0; // @[core.scala:51:7] wire io_lsu_commit_valids_0_0; // @[core.scala:51:7] wire io_lsu_commit_valids_1_0; // @[core.scala:51:7] wire io_lsu_commit_valids_2_0; // @[core.scala:51:7] wire io_lsu_commit_arch_valids_0_0; // @[core.scala:51:7] wire io_lsu_commit_arch_valids_1_0; // @[core.scala:51:7] wire io_lsu_commit_arch_valids_2_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_0_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_0_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_0_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_0_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_0_debug_inst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_commit_uops_0_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_0_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_commit_uops_0_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_iw_state_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_br_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_jalr_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_jal_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_commit_uops_0_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_0_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_pc_lob_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_commit_uops_0_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_commit_uops_0_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_ppred_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_uops_0_exc_cause_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_mem_size_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_mem_signed_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_fence_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_fencei_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_amo_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_uses_stq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_unique_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_lrs3_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_frs3_en_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_fp_val_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_fp_single_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_debug_tsrc_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_1_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_1_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_1_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_1_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_1_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_1_debug_inst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_commit_uops_1_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_1_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_commit_uops_1_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_iw_state_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_br_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_jalr_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_jal_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_commit_uops_1_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_1_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_pc_lob_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_commit_uops_1_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_commit_uops_1_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_ppred_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_uops_1_exc_cause_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_mem_size_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_mem_signed_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_fence_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_fencei_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_amo_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_uses_stq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_unique_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_lrs3_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_frs3_en_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_fp_val_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_fp_single_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_debug_tsrc_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_2_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_2_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_2_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_2_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_2_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_2_debug_inst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_commit_uops_2_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_2_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_commit_uops_2_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_iw_state_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_br_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_jalr_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_jal_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_commit_uops_2_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_2_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_pc_lob_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_commit_uops_2_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_commit_uops_2_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_ppred_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_uops_2_exc_cause_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_mem_size_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_mem_signed_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_fence_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_fencei_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_amo_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_uses_stq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_unique_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_lrs3_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_frs3_en_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_fp_val_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_fp_single_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_commit_fflags_valid_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_fflags_bits_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_debug_insts_0_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_debug_insts_1_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_debug_insts_2_0; // @[core.scala:51:7] wire io_lsu_commit_rbk_valids_0_0; // @[core.scala:51:7] wire io_lsu_commit_rbk_valids_1_0; // @[core.scala:51:7] wire io_lsu_commit_rbk_valids_2_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_debug_wdata_0_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_debug_wdata_1_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_debug_wdata_2_0; // @[core.scala:51:7] wire io_lsu_commit_rollback_0; // @[core.scala:51:7] wire [15:0] io_lsu_brupdate_b1_resolve_mask_0; // @[core.scala:51:7] wire [15:0] io_lsu_brupdate_b1_mispredict_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_brupdate_b2_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_brupdate_b2_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_iw_state_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_br_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_jalr_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_jal_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_brupdate_b2_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_brupdate_b2_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_brupdate_b2_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_ppred_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_mem_signed_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_fence_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_fencei_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_amo_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_uses_stq_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_unique_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_frs3_en_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_fp_val_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_fp_single_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_valid_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_mispredict_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_taken_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_cfi_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_pc_sel_0; // @[core.scala:51:7] wire [39:0] io_lsu_brupdate_b2_jalr_target_0; // @[core.scala:51:7] wire [20:0] io_lsu_brupdate_b2_target_offset_0; // @[core.scala:51:7] wire io_lsu_commit_load_at_rob_head_0; // @[core.scala:51:7] wire io_lsu_fence_dmem_0; // @[core.scala:51:7] wire [6:0] io_lsu_rob_pnr_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_rob_head_idx_0; // @[core.scala:51:7] wire io_lsu_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_tsc_reg_0; // @[core.scala:51:7] wire io_trace_custom_rob_empty_0; // @[core.scala:51:7] wire [63:0] io_trace_time_0; // @[core.scala:51:7] wire [2:0] io_fcsr_rm; // @[core.scala:51:7] wire _int_iss_wakeups_0_valid_T_2; // @[core.scala:795:52] wire fast_wakeup_valid; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_uopc; // @[core.scala:814:29] wire [31:0] fast_wakeup_bits_uop_inst; // @[core.scala:814:29] wire [31:0] fast_wakeup_bits_uop_debug_inst; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_rvc; // @[core.scala:814:29] wire [39:0] fast_wakeup_bits_uop_debug_pc; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_uop_iq_type; // @[core.scala:814:29] wire [9:0] fast_wakeup_bits_uop_fu_code; // @[core.scala:814:29] wire [3:0] fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_iw_state; // @[core.scala:814:29] wire fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:814:29] wire fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_br; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_jalr; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_jal; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_sfb; // @[core.scala:814:29] wire [15:0] fast_wakeup_bits_uop_br_mask; // @[core.scala:814:29] wire [3:0] fast_wakeup_bits_uop_br_tag; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_ftq_idx; // @[core.scala:814:29] wire fast_wakeup_bits_uop_edge_inst; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_pc_lob; // @[core.scala:814:29] wire fast_wakeup_bits_uop_taken; // @[core.scala:814:29] wire [19:0] fast_wakeup_bits_uop_imm_packed; // @[core.scala:814:29] wire [11:0] fast_wakeup_bits_uop_csr_addr; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_rob_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_ldq_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_stq_idx; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_rxq_idx; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_pdst; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_prs1; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_prs2; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_prs3; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_ppred; // @[core.scala:814:29] wire fast_wakeup_bits_uop_prs1_busy; // @[core.scala:814:29] wire fast_wakeup_bits_uop_prs2_busy; // @[core.scala:814:29] wire fast_wakeup_bits_uop_prs3_busy; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ppred_busy; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_stale_pdst; // @[core.scala:814:29] wire fast_wakeup_bits_uop_exception; // @[core.scala:814:29] wire [63:0] fast_wakeup_bits_uop_exc_cause; // @[core.scala:814:29] wire fast_wakeup_bits_uop_bypassable; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_mem_cmd; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_mem_size; // @[core.scala:814:29] wire fast_wakeup_bits_uop_mem_signed; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_fence; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_fencei; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_amo; // @[core.scala:814:29] wire fast_wakeup_bits_uop_uses_ldq; // @[core.scala:814:29] wire fast_wakeup_bits_uop_uses_stq; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_unique; // @[core.scala:814:29] wire fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_ldst; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_lrs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_lrs2; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_lrs3; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ldst_val; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_dst_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:814:29] wire fast_wakeup_bits_uop_frs3_en; // @[core.scala:814:29] wire fast_wakeup_bits_uop_fp_val; // @[core.scala:814:29] wire fast_wakeup_bits_uop_fp_single; // @[core.scala:814:29] wire fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:814:29] wire fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:814:29] wire fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:814:29] wire fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:814:29] wire fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:814:29] wire slow_wakeup_valid; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_uopc; // @[core.scala:815:29] wire [31:0] slow_wakeup_bits_uop_inst; // @[core.scala:815:29] wire [31:0] slow_wakeup_bits_uop_debug_inst; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_rvc; // @[core.scala:815:29] wire [39:0] slow_wakeup_bits_uop_debug_pc; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_uop_iq_type; // @[core.scala:815:29] wire [9:0] slow_wakeup_bits_uop_fu_code; // @[core.scala:815:29] wire [3:0] slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_iw_state; // @[core.scala:815:29] wire slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:815:29] wire slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_br; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_jalr; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_jal; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_sfb; // @[core.scala:815:29] wire [15:0] slow_wakeup_bits_uop_br_mask; // @[core.scala:815:29] wire [3:0] slow_wakeup_bits_uop_br_tag; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_ftq_idx; // @[core.scala:815:29] wire slow_wakeup_bits_uop_edge_inst; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_pc_lob; // @[core.scala:815:29] wire slow_wakeup_bits_uop_taken; // @[core.scala:815:29] wire [19:0] slow_wakeup_bits_uop_imm_packed; // @[core.scala:815:29] wire [11:0] slow_wakeup_bits_uop_csr_addr; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_rob_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_ldq_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_stq_idx; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_rxq_idx; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_pdst; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_prs1; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_prs2; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_prs3; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_ppred; // @[core.scala:815:29] wire slow_wakeup_bits_uop_prs1_busy; // @[core.scala:815:29] wire slow_wakeup_bits_uop_prs2_busy; // @[core.scala:815:29] wire slow_wakeup_bits_uop_prs3_busy; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ppred_busy; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_stale_pdst; // @[core.scala:815:29] wire slow_wakeup_bits_uop_exception; // @[core.scala:815:29] wire [63:0] slow_wakeup_bits_uop_exc_cause; // @[core.scala:815:29] wire slow_wakeup_bits_uop_bypassable; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_mem_cmd; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_mem_size; // @[core.scala:815:29] wire slow_wakeup_bits_uop_mem_signed; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_fence; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_fencei; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_amo; // @[core.scala:815:29] wire slow_wakeup_bits_uop_uses_ldq; // @[core.scala:815:29] wire slow_wakeup_bits_uop_uses_stq; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_unique; // @[core.scala:815:29] wire slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_ldst; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_lrs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_lrs2; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_lrs3; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ldst_val; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_dst_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:815:29] wire slow_wakeup_bits_uop_frs3_en; // @[core.scala:815:29] wire slow_wakeup_bits_uop_fp_val; // @[core.scala:815:29] wire slow_wakeup_bits_uop_fp_single; // @[core.scala:815:29] wire slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:815:29] wire slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:815:29] wire slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:815:29] wire slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:815:29] wire slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:815:29] wire fast_wakeup_1_valid; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_uopc; // @[core.scala:814:29] wire [31:0] fast_wakeup_1_bits_uop_inst; // @[core.scala:814:29] wire [31:0] fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:814:29] wire [39:0] fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_uop_iq_type; // @[core.scala:814:29] wire [9:0] fast_wakeup_1_bits_uop_fu_code; // @[core.scala:814:29] wire [3:0] fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_iw_state; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_br; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_jal; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:814:29] wire [15:0] fast_wakeup_1_bits_uop_br_mask; // @[core.scala:814:29] wire [3:0] fast_wakeup_1_bits_uop_br_tag; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_taken; // @[core.scala:814:29] wire [19:0] fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:814:29] wire [11:0] fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_pdst; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_prs1; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_prs2; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_prs3; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_ppred; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_exception; // @[core.scala:814:29] wire [63:0] fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_bypassable; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_mem_size; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_fence; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_amo; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_unique; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_ldst; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_lrs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_lrs2; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_lrs3; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_fp_val; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_fp_single; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:814:29] wire slow_wakeup_1_valid; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_uopc; // @[core.scala:815:29] wire [31:0] slow_wakeup_1_bits_uop_inst; // @[core.scala:815:29] wire [31:0] slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:815:29] wire [39:0] slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_uop_iq_type; // @[core.scala:815:29] wire [9:0] slow_wakeup_1_bits_uop_fu_code; // @[core.scala:815:29] wire [3:0] slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_iw_state; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_br; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_jal; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:815:29] wire [15:0] slow_wakeup_1_bits_uop_br_mask; // @[core.scala:815:29] wire [3:0] slow_wakeup_1_bits_uop_br_tag; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_taken; // @[core.scala:815:29] wire [19:0] slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:815:29] wire [11:0] slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_pdst; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_prs1; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_prs2; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_prs3; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_ppred; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_exception; // @[core.scala:815:29] wire [63:0] slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_bypassable; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_mem_size; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_fence; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_amo; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_unique; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_ldst; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_lrs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_lrs2; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_lrs3; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_fp_val; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_fp_single; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:815:29] wire fast_wakeup_2_valid; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_uopc; // @[core.scala:814:29] wire [31:0] fast_wakeup_2_bits_uop_inst; // @[core.scala:814:29] wire [31:0] fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:814:29] wire [39:0] fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_uop_iq_type; // @[core.scala:814:29] wire [9:0] fast_wakeup_2_bits_uop_fu_code; // @[core.scala:814:29] wire [3:0] fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_iw_state; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_br; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_jal; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:814:29] wire [15:0] fast_wakeup_2_bits_uop_br_mask; // @[core.scala:814:29] wire [3:0] fast_wakeup_2_bits_uop_br_tag; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_taken; // @[core.scala:814:29] wire [19:0] fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:814:29] wire [11:0] fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_pdst; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_prs1; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_prs2; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_prs3; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_ppred; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_exception; // @[core.scala:814:29] wire [63:0] fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_bypassable; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_mem_size; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_fence; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_amo; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_unique; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_ldst; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_lrs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_lrs2; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_lrs3; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_fp_val; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_fp_single; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:814:29] wire slow_wakeup_2_valid; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_uopc; // @[core.scala:815:29] wire [31:0] slow_wakeup_2_bits_uop_inst; // @[core.scala:815:29] wire [31:0] slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:815:29] wire [39:0] slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_uop_iq_type; // @[core.scala:815:29] wire [9:0] slow_wakeup_2_bits_uop_fu_code; // @[core.scala:815:29] wire [3:0] slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_iw_state; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_br; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_jal; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:815:29] wire [15:0] slow_wakeup_2_bits_uop_br_mask; // @[core.scala:815:29] wire [3:0] slow_wakeup_2_bits_uop_br_tag; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_taken; // @[core.scala:815:29] wire [19:0] slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:815:29] wire [11:0] slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_pdst; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_prs1; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_prs2; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_prs3; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_ppred; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_exception; // @[core.scala:815:29] wire [63:0] slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_bypassable; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_mem_size; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_fence; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_amo; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_unique; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_ldst; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_lrs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_lrs2; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_lrs3; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_fp_val; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_fp_single; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:815:29] wire [3:0] int_iss_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_0_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_0_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_0_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_0_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_0_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_0_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_0_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_0_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_0_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_flags; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_valid; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_0_bits_data; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_predicated; // @[core.scala:147:30] wire int_iss_wakeups_0_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_1_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_1_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_1_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_1_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_1_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_1_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_1_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_1_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_1_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_1_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_2_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_2_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_2_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_2_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_2_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_2_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_2_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_2_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_2_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_2_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_2_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_3_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_3_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_3_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_3_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_3_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_3_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_3_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_3_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_3_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_3_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_3_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_4_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_4_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_4_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_4_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_4_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_4_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_4_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_4_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_4_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_4_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_4_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_5_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_5_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_5_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_5_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_5_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_5_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_5_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_5_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_5_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_5_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_5_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_6_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_6_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_6_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_6_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_6_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_6_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_6_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_6_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_6_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_6_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_6_valid; // @[core.scala:147:30] wire _int_ren_wakeups_0_valid_T_2; // @[core.scala:798:52] wire [3:0] int_ren_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_0_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_0_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_0_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_0_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_0_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_0_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_0_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_0_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_0_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_flags; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_valid; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_0_bits_data; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_predicated; // @[core.scala:148:30] wire int_ren_wakeups_0_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_1_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_1_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_1_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_1_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_1_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_1_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_1_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_1_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_1_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_1_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_2_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_2_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_2_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_2_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_2_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_2_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_2_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_2_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_2_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_2_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_2_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_3_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_3_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_3_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_3_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_3_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_3_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_3_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_3_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_3_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_3_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_3_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_4_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_4_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_4_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_4_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_4_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_4_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_4_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_4_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_4_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_4_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_4_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_5_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_5_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_5_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_5_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_5_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_5_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_5_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_5_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_5_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_5_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_5_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_6_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_6_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_6_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_6_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_6_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_6_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_6_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_6_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_6_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_6_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_6_valid; // @[core.scala:148:30] wire [6:0] iss_uops_1_uopc; // @[core.scala:173:24] wire [31:0] iss_uops_1_inst; // @[core.scala:173:24] wire [31:0] iss_uops_1_debug_inst; // @[core.scala:173:24] wire iss_uops_1_is_rvc; // @[core.scala:173:24] wire [39:0] iss_uops_1_debug_pc; // @[core.scala:173:24] wire [2:0] iss_uops_1_iq_type; // @[core.scala:173:24] wire [9:0] iss_uops_1_fu_code; // @[core.scala:173:24] wire [3:0] iss_uops_1_ctrl_br_type; // @[core.scala:173:24] wire [1:0] iss_uops_1_ctrl_op1_sel; // @[core.scala:173:24] wire [2:0] iss_uops_1_ctrl_op2_sel; // @[core.scala:173:24] wire [2:0] iss_uops_1_ctrl_imm_sel; // @[core.scala:173:24] wire [4:0] iss_uops_1_ctrl_op_fcn; // @[core.scala:173:24] wire iss_uops_1_ctrl_fcn_dw; // @[core.scala:173:24] wire [2:0] iss_uops_1_ctrl_csr_cmd; // @[core.scala:173:24] wire iss_uops_1_ctrl_is_load; // @[core.scala:173:24] wire iss_uops_1_ctrl_is_sta; // @[core.scala:173:24] wire iss_uops_1_ctrl_is_std; // @[core.scala:173:24] wire [1:0] iss_uops_1_iw_state; // @[core.scala:173:24] wire iss_uops_1_iw_p1_poisoned; // @[core.scala:173:24] wire iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24] wire iss_uops_1_is_br; // @[core.scala:173:24] wire iss_uops_1_is_jalr; // @[core.scala:173:24] wire iss_uops_1_is_jal; // @[core.scala:173:24] wire iss_uops_1_is_sfb; // @[core.scala:173:24] wire [15:0] iss_uops_1_br_mask; // @[core.scala:173:24] wire [3:0] iss_uops_1_br_tag; // @[core.scala:173:24] wire [4:0] iss_uops_1_ftq_idx; // @[core.scala:173:24] wire iss_uops_1_edge_inst; // @[core.scala:173:24] wire [5:0] iss_uops_1_pc_lob; // @[core.scala:173:24] wire iss_uops_1_taken; // @[core.scala:173:24] wire [19:0] iss_uops_1_imm_packed; // @[core.scala:173:24] wire [11:0] iss_uops_1_csr_addr; // @[core.scala:173:24] wire [6:0] iss_uops_1_rob_idx; // @[core.scala:173:24] wire [4:0] iss_uops_1_ldq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_1_stq_idx; // @[core.scala:173:24] wire [1:0] iss_uops_1_rxq_idx; // @[core.scala:173:24] wire [6:0] iss_uops_1_pdst; // @[core.scala:173:24] wire [6:0] iss_uops_1_prs1; // @[core.scala:173:24] wire [6:0] iss_uops_1_prs2; // @[core.scala:173:24] wire [6:0] iss_uops_1_prs3; // @[core.scala:173:24] wire [4:0] iss_uops_1_ppred; // @[core.scala:173:24] wire iss_uops_1_prs1_busy; // @[core.scala:173:24] wire iss_uops_1_prs2_busy; // @[core.scala:173:24] wire iss_uops_1_prs3_busy; // @[core.scala:173:24] wire iss_uops_1_ppred_busy; // @[core.scala:173:24] wire [6:0] iss_uops_1_stale_pdst; // @[core.scala:173:24] wire iss_uops_1_exception; // @[core.scala:173:24] wire [63:0] iss_uops_1_exc_cause; // @[core.scala:173:24] wire iss_uops_1_bypassable; // @[core.scala:173:24] wire [4:0] iss_uops_1_mem_cmd; // @[core.scala:173:24] wire [1:0] iss_uops_1_mem_size; // @[core.scala:173:24] wire iss_uops_1_mem_signed; // @[core.scala:173:24] wire iss_uops_1_is_fence; // @[core.scala:173:24] wire iss_uops_1_is_fencei; // @[core.scala:173:24] wire iss_uops_1_is_amo; // @[core.scala:173:24] wire iss_uops_1_uses_ldq; // @[core.scala:173:24] wire iss_uops_1_uses_stq; // @[core.scala:173:24] wire iss_uops_1_is_sys_pc2epc; // @[core.scala:173:24] wire iss_uops_1_is_unique; // @[core.scala:173:24] wire iss_uops_1_flush_on_commit; // @[core.scala:173:24] wire iss_uops_1_ldst_is_rs1; // @[core.scala:173:24] wire [5:0] iss_uops_1_ldst; // @[core.scala:173:24] wire [5:0] iss_uops_1_lrs1; // @[core.scala:173:24] wire [5:0] iss_uops_1_lrs2; // @[core.scala:173:24] wire [5:0] iss_uops_1_lrs3; // @[core.scala:173:24] wire iss_uops_1_ldst_val; // @[core.scala:173:24] wire [1:0] iss_uops_1_dst_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_1_lrs1_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_1_lrs2_rtype; // @[core.scala:173:24] wire iss_uops_1_frs3_en; // @[core.scala:173:24] wire iss_uops_1_fp_val; // @[core.scala:173:24] wire iss_uops_1_fp_single; // @[core.scala:173:24] wire iss_uops_1_xcpt_pf_if; // @[core.scala:173:24] wire iss_uops_1_xcpt_ae_if; // @[core.scala:173:24] wire iss_uops_1_xcpt_ma_if; // @[core.scala:173:24] wire iss_uops_1_bp_debug_if; // @[core.scala:173:24] wire iss_uops_1_bp_xcpt_if; // @[core.scala:173:24] wire [1:0] iss_uops_1_debug_fsrc; // @[core.scala:173:24] wire [1:0] iss_uops_1_debug_tsrc; // @[core.scala:173:24] wire [3:0] pred_wakeup_bits_uop_ctrl_br_type; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ctrl_is_load; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ctrl_is_std; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_uopc; // @[core.scala:149:26] wire [31:0] pred_wakeup_bits_uop_inst; // @[core.scala:149:26] wire [31:0] pred_wakeup_bits_uop_debug_inst; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_rvc; // @[core.scala:149:26] wire [39:0] pred_wakeup_bits_uop_debug_pc; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_uop_iq_type; // @[core.scala:149:26] wire [9:0] pred_wakeup_bits_uop_fu_code; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_iw_state; // @[core.scala:149:26] wire pred_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:149:26] wire pred_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_br; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_jalr; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_jal; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_sfb; // @[core.scala:149:26] wire [15:0] pred_wakeup_bits_uop_br_mask; // @[core.scala:149:26] wire [3:0] pred_wakeup_bits_uop_br_tag; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_ftq_idx; // @[core.scala:149:26] wire pred_wakeup_bits_uop_edge_inst; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_pc_lob; // @[core.scala:149:26] wire pred_wakeup_bits_uop_taken; // @[core.scala:149:26] wire [19:0] pred_wakeup_bits_uop_imm_packed; // @[core.scala:149:26] wire [11:0] pred_wakeup_bits_uop_csr_addr; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_rob_idx; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_ldq_idx; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_stq_idx; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_rxq_idx; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_pdst; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_prs1; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_prs2; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_prs3; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_ppred; // @[core.scala:149:26] wire pred_wakeup_bits_uop_prs1_busy; // @[core.scala:149:26] wire pred_wakeup_bits_uop_prs2_busy; // @[core.scala:149:26] wire pred_wakeup_bits_uop_prs3_busy; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ppred_busy; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_stale_pdst; // @[core.scala:149:26] wire pred_wakeup_bits_uop_exception; // @[core.scala:149:26] wire [63:0] pred_wakeup_bits_uop_exc_cause; // @[core.scala:149:26] wire pred_wakeup_bits_uop_bypassable; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_mem_cmd; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_mem_size; // @[core.scala:149:26] wire pred_wakeup_bits_uop_mem_signed; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_fence; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_fencei; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_amo; // @[core.scala:149:26] wire pred_wakeup_bits_uop_uses_ldq; // @[core.scala:149:26] wire pred_wakeup_bits_uop_uses_stq; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_unique; // @[core.scala:149:26] wire pred_wakeup_bits_uop_flush_on_commit; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_ldst; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_lrs1; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_lrs2; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_lrs3; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ldst_val; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_dst_rtype; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_lrs1_rtype; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_lrs2_rtype; // @[core.scala:149:26] wire pred_wakeup_bits_uop_frs3_en; // @[core.scala:149:26] wire pred_wakeup_bits_uop_fp_val; // @[core.scala:149:26] wire pred_wakeup_bits_uop_fp_single; // @[core.scala:149:26] wire pred_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:149:26] wire pred_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:149:26] wire pred_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:149:26] wire pred_wakeup_bits_uop_bp_debug_if; // @[core.scala:149:26] wire pred_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_debug_fsrc; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_debug_tsrc; // @[core.scala:149:26] wire _dec_valids_0_T_3; // @[core.scala:508:97] wire _dec_valids_1_T_3; // @[core.scala:508:97] wire _dec_valids_2_T_3; // @[core.scala:508:97] wire dec_valids_0; // @[core.scala:157:24] wire dec_valids_1; // @[core.scala:157:24] wire dec_valids_2; // @[core.scala:157:24] wire [6:0] dec_uops_0_uopc; // @[core.scala:158:24] wire [31:0] dec_uops_0_inst; // @[core.scala:158:24] wire [31:0] dec_uops_0_debug_inst; // @[core.scala:158:24] wire dec_uops_0_is_rvc; // @[core.scala:158:24] wire [39:0] dec_uops_0_debug_pc; // @[core.scala:158:24] wire [2:0] dec_uops_0_iq_type; // @[core.scala:158:24] wire [9:0] dec_uops_0_fu_code; // @[core.scala:158:24] wire dec_uops_0_is_br; // @[core.scala:158:24] wire dec_uops_0_is_jalr; // @[core.scala:158:24] wire dec_uops_0_is_jal; // @[core.scala:158:24] wire dec_uops_0_is_sfb; // @[core.scala:158:24] wire [15:0] dec_uops_0_br_mask; // @[core.scala:158:24] wire [3:0] dec_uops_0_br_tag; // @[core.scala:158:24] wire [4:0] dec_uops_0_ftq_idx; // @[core.scala:158:24] wire dec_uops_0_edge_inst; // @[core.scala:158:24] wire [5:0] dec_uops_0_pc_lob; // @[core.scala:158:24] wire dec_uops_0_taken; // @[core.scala:158:24] wire [19:0] dec_uops_0_imm_packed; // @[core.scala:158:24] wire dec_uops_0_exception; // @[core.scala:158:24] wire [63:0] dec_uops_0_exc_cause; // @[core.scala:158:24] wire dec_uops_0_bypassable; // @[core.scala:158:24] wire [4:0] dec_uops_0_mem_cmd; // @[core.scala:158:24] wire [1:0] dec_uops_0_mem_size; // @[core.scala:158:24] wire dec_uops_0_mem_signed; // @[core.scala:158:24] wire dec_uops_0_is_fence; // @[core.scala:158:24] wire dec_uops_0_is_fencei; // @[core.scala:158:24] wire dec_uops_0_is_amo; // @[core.scala:158:24] wire dec_uops_0_uses_ldq; // @[core.scala:158:24] wire dec_uops_0_uses_stq; // @[core.scala:158:24] wire dec_uops_0_is_sys_pc2epc; // @[core.scala:158:24] wire dec_uops_0_is_unique; // @[core.scala:158:24] wire dec_uops_0_flush_on_commit; // @[core.scala:158:24] wire [5:0] dec_uops_0_ldst; // @[core.scala:158:24] wire [5:0] dec_uops_0_lrs1; // @[core.scala:158:24] wire [5:0] dec_uops_0_lrs2; // @[core.scala:158:24] wire [5:0] dec_uops_0_lrs3; // @[core.scala:158:24] wire dec_uops_0_ldst_val; // @[core.scala:158:24] wire [1:0] dec_uops_0_dst_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_0_lrs1_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_0_lrs2_rtype; // @[core.scala:158:24] wire dec_uops_0_frs3_en; // @[core.scala:158:24] wire dec_uops_0_fp_val; // @[core.scala:158:24] wire dec_uops_0_fp_single; // @[core.scala:158:24] wire dec_uops_0_xcpt_pf_if; // @[core.scala:158:24] wire dec_uops_0_xcpt_ae_if; // @[core.scala:158:24] wire dec_uops_0_bp_debug_if; // @[core.scala:158:24] wire dec_uops_0_bp_xcpt_if; // @[core.scala:158:24] wire [1:0] dec_uops_0_debug_fsrc; // @[core.scala:158:24] wire [6:0] dec_uops_1_uopc; // @[core.scala:158:24] wire [31:0] dec_uops_1_inst; // @[core.scala:158:24] wire [31:0] dec_uops_1_debug_inst; // @[core.scala:158:24] wire dec_uops_1_is_rvc; // @[core.scala:158:24] wire [39:0] dec_uops_1_debug_pc; // @[core.scala:158:24] wire [2:0] dec_uops_1_iq_type; // @[core.scala:158:24] wire [9:0] dec_uops_1_fu_code; // @[core.scala:158:24] wire dec_uops_1_is_br; // @[core.scala:158:24] wire dec_uops_1_is_jalr; // @[core.scala:158:24] wire dec_uops_1_is_jal; // @[core.scala:158:24] wire dec_uops_1_is_sfb; // @[core.scala:158:24] wire [15:0] dec_uops_1_br_mask; // @[core.scala:158:24] wire [3:0] dec_uops_1_br_tag; // @[core.scala:158:24] wire [4:0] dec_uops_1_ftq_idx; // @[core.scala:158:24] wire dec_uops_1_edge_inst; // @[core.scala:158:24] wire [5:0] dec_uops_1_pc_lob; // @[core.scala:158:24] wire dec_uops_1_taken; // @[core.scala:158:24] wire [19:0] dec_uops_1_imm_packed; // @[core.scala:158:24] wire dec_uops_1_exception; // @[core.scala:158:24] wire [63:0] dec_uops_1_exc_cause; // @[core.scala:158:24] wire dec_uops_1_bypassable; // @[core.scala:158:24] wire [4:0] dec_uops_1_mem_cmd; // @[core.scala:158:24] wire [1:0] dec_uops_1_mem_size; // @[core.scala:158:24] wire dec_uops_1_mem_signed; // @[core.scala:158:24] wire dec_uops_1_is_fence; // @[core.scala:158:24] wire dec_uops_1_is_fencei; // @[core.scala:158:24] wire dec_uops_1_is_amo; // @[core.scala:158:24] wire dec_uops_1_uses_ldq; // @[core.scala:158:24] wire dec_uops_1_uses_stq; // @[core.scala:158:24] wire dec_uops_1_is_sys_pc2epc; // @[core.scala:158:24] wire dec_uops_1_is_unique; // @[core.scala:158:24] wire dec_uops_1_flush_on_commit; // @[core.scala:158:24] wire [5:0] dec_uops_1_ldst; // @[core.scala:158:24] wire [5:0] dec_uops_1_lrs1; // @[core.scala:158:24] wire [5:0] dec_uops_1_lrs2; // @[core.scala:158:24] wire [5:0] dec_uops_1_lrs3; // @[core.scala:158:24] wire dec_uops_1_ldst_val; // @[core.scala:158:24] wire [1:0] dec_uops_1_dst_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_1_lrs1_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_1_lrs2_rtype; // @[core.scala:158:24] wire dec_uops_1_frs3_en; // @[core.scala:158:24] wire dec_uops_1_fp_val; // @[core.scala:158:24] wire dec_uops_1_fp_single; // @[core.scala:158:24] wire dec_uops_1_xcpt_pf_if; // @[core.scala:158:24] wire dec_uops_1_xcpt_ae_if; // @[core.scala:158:24] wire dec_uops_1_bp_debug_if; // @[core.scala:158:24] wire dec_uops_1_bp_xcpt_if; // @[core.scala:158:24] wire [1:0] dec_uops_1_debug_fsrc; // @[core.scala:158:24] wire [6:0] dec_uops_2_uopc; // @[core.scala:158:24] wire [31:0] dec_uops_2_inst; // @[core.scala:158:24] wire [31:0] dec_uops_2_debug_inst; // @[core.scala:158:24] wire dec_uops_2_is_rvc; // @[core.scala:158:24] wire [39:0] dec_uops_2_debug_pc; // @[core.scala:158:24] wire [2:0] dec_uops_2_iq_type; // @[core.scala:158:24] wire [9:0] dec_uops_2_fu_code; // @[core.scala:158:24] wire dec_uops_2_is_br; // @[core.scala:158:24] wire dec_uops_2_is_jalr; // @[core.scala:158:24] wire dec_uops_2_is_jal; // @[core.scala:158:24] wire dec_uops_2_is_sfb; // @[core.scala:158:24] wire [15:0] dec_uops_2_br_mask; // @[core.scala:158:24] wire [3:0] dec_uops_2_br_tag; // @[core.scala:158:24] wire [4:0] dec_uops_2_ftq_idx; // @[core.scala:158:24] wire dec_uops_2_edge_inst; // @[core.scala:158:24] wire [5:0] dec_uops_2_pc_lob; // @[core.scala:158:24] wire dec_uops_2_taken; // @[core.scala:158:24] wire [19:0] dec_uops_2_imm_packed; // @[core.scala:158:24] wire dec_uops_2_exception; // @[core.scala:158:24] wire [63:0] dec_uops_2_exc_cause; // @[core.scala:158:24] wire dec_uops_2_bypassable; // @[core.scala:158:24] wire [4:0] dec_uops_2_mem_cmd; // @[core.scala:158:24] wire [1:0] dec_uops_2_mem_size; // @[core.scala:158:24] wire dec_uops_2_mem_signed; // @[core.scala:158:24] wire dec_uops_2_is_fence; // @[core.scala:158:24] wire dec_uops_2_is_fencei; // @[core.scala:158:24] wire dec_uops_2_is_amo; // @[core.scala:158:24] wire dec_uops_2_uses_ldq; // @[core.scala:158:24] wire dec_uops_2_uses_stq; // @[core.scala:158:24] wire dec_uops_2_is_sys_pc2epc; // @[core.scala:158:24] wire dec_uops_2_is_unique; // @[core.scala:158:24] wire dec_uops_2_flush_on_commit; // @[core.scala:158:24] wire [5:0] dec_uops_2_ldst; // @[core.scala:158:24] wire [5:0] dec_uops_2_lrs1; // @[core.scala:158:24] wire [5:0] dec_uops_2_lrs2; // @[core.scala:158:24] wire [5:0] dec_uops_2_lrs3; // @[core.scala:158:24] wire dec_uops_2_ldst_val; // @[core.scala:158:24] wire [1:0] dec_uops_2_dst_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_2_lrs1_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_2_lrs2_rtype; // @[core.scala:158:24] wire dec_uops_2_frs3_en; // @[core.scala:158:24] wire dec_uops_2_fp_val; // @[core.scala:158:24] wire dec_uops_2_fp_single; // @[core.scala:158:24] wire dec_uops_2_xcpt_pf_if; // @[core.scala:158:24] wire dec_uops_2_xcpt_ae_if; // @[core.scala:158:24] wire dec_uops_2_bp_debug_if; // @[core.scala:158:24] wire dec_uops_2_bp_xcpt_if; // @[core.scala:158:24] wire [1:0] dec_uops_2_debug_fsrc; // @[core.scala:158:24] wire dec_fire_0; // @[core.scala:159:24] wire dec_fire_1; // @[core.scala:159:24] wire dec_fire_2; // @[core.scala:159:24] assign dec_ready = dec_fire_2; // @[core.scala:159:24, :161:24] assign io_ifu_fetchpacket_ready_0 = dec_ready; // @[core.scala:51:7, :161:24] wire dec_xcpts_0; // @[core.scala:162:24] wire dec_xcpts_1; // @[core.scala:162:24] wire dec_xcpts_2; // @[core.scala:162:24] wire _ren_stalls_0_T_1; // @[core.scala:671:63] wire _ren_stalls_1_T_1; // @[core.scala:671:63] wire _ren_stalls_2_T_1; // @[core.scala:671:63] wire ren_stalls_0; // @[core.scala:163:24] wire ren_stalls_1; // @[core.scala:163:24] wire ren_stalls_2; // @[core.scala:163:24] wire dis_prior_slot_valid_1 = dis_valids_0; // @[core.scala:166:24, :683:71] wire dis_valids_1; // @[core.scala:166:24] wire dis_valids_2; // @[core.scala:166:24] assign io_lsu_dis_uops_0_bits_uopc_0 = dis_uops_0_uopc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_inst_0 = dis_uops_0_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_debug_inst_0 = dis_uops_0_debug_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_rvc_0 = dis_uops_0_is_rvc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_debug_pc_0 = dis_uops_0_debug_pc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_iq_type_0 = dis_uops_0_iq_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_fu_code_0 = dis_uops_0_fu_code; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_br_type_0 = dis_uops_0_ctrl_br_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_op1_sel_0 = dis_uops_0_ctrl_op1_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_op2_sel_0 = dis_uops_0_ctrl_op2_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_imm_sel_0 = dis_uops_0_ctrl_imm_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_op_fcn_0 = dis_uops_0_ctrl_op_fcn; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0 = dis_uops_0_ctrl_fcn_dw; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0 = dis_uops_0_ctrl_csr_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_is_load_0 = dis_uops_0_ctrl_is_load; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_is_sta_0 = dis_uops_0_ctrl_is_sta; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_is_std_0 = dis_uops_0_ctrl_is_std; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_iw_state_0 = dis_uops_0_iw_state; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_iw_p1_poisoned_0 = dis_uops_0_iw_p1_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_iw_p2_poisoned_0 = dis_uops_0_iw_p2_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_br_0 = dis_uops_0_is_br; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_jalr_0 = dis_uops_0_is_jalr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_jal_0 = dis_uops_0_is_jal; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_sfb_0 = dis_uops_0_is_sfb; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_br_mask_0 = dis_uops_0_br_mask; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_br_tag_0 = dis_uops_0_br_tag; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ftq_idx_0 = dis_uops_0_ftq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_edge_inst_0 = dis_uops_0_edge_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_pc_lob_0 = dis_uops_0_pc_lob; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_taken_0 = dis_uops_0_taken; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_imm_packed_0 = dis_uops_0_imm_packed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_csr_addr_0 = dis_uops_0_csr_addr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_rob_idx_0 = dis_uops_0_rob_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ldq_idx_0 = dis_uops_0_ldq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_stq_idx_0 = dis_uops_0_stq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_rxq_idx_0 = dis_uops_0_rxq_idx; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_0_pdst_T_3; // @[core.scala:659:28] assign io_lsu_dis_uops_0_bits_pdst_0 = dis_uops_0_pdst; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_0_prs1_T_3; // @[core.scala:654:28] assign io_lsu_dis_uops_0_bits_prs1_0 = dis_uops_0_prs1; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_0_prs2_T_1; // @[core.scala:656:28] assign io_lsu_dis_uops_0_bits_prs2_0 = dis_uops_0_prs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_prs3_0 = dis_uops_0_prs3; // @[core.scala:51:7, :167:24] wire _dis_uops_0_prs1_busy_T_4; // @[core.scala:664:85] assign io_lsu_dis_uops_0_bits_prs1_busy_0 = dis_uops_0_prs1_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_0_prs2_busy_T_4; // @[core.scala:666:85] assign io_lsu_dis_uops_0_bits_prs2_busy_0 = dis_uops_0_prs2_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_0_prs3_busy_T; // @[core.scala:668:46] assign io_lsu_dis_uops_0_bits_prs3_busy_0 = dis_uops_0_prs3_busy; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_0_stale_pdst_T_1; // @[core.scala:662:34] assign io_lsu_dis_uops_0_bits_stale_pdst_0 = dis_uops_0_stale_pdst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_exception_0 = dis_uops_0_exception; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_exc_cause_0 = dis_uops_0_exc_cause; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_bypassable_0 = dis_uops_0_bypassable; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_mem_cmd_0 = dis_uops_0_mem_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_mem_size_0 = dis_uops_0_mem_size; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_mem_signed_0 = dis_uops_0_mem_signed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_fence_0 = dis_uops_0_is_fence; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_fencei_0 = dis_uops_0_is_fencei; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_amo_0 = dis_uops_0_is_amo; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_uses_ldq_0 = dis_uops_0_uses_ldq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_uses_stq_0 = dis_uops_0_uses_stq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_sys_pc2epc_0 = dis_uops_0_is_sys_pc2epc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_unique_0 = dis_uops_0_is_unique; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_flush_on_commit_0 = dis_uops_0_flush_on_commit; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ldst_is_rs1_0 = dis_uops_0_ldst_is_rs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ldst_0 = dis_uops_0_ldst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs1_0 = dis_uops_0_lrs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs2_0 = dis_uops_0_lrs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs3_0 = dis_uops_0_lrs3; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ldst_val_0 = dis_uops_0_ldst_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_dst_rtype_0 = dis_uops_0_dst_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs1_rtype_0 = dis_uops_0_lrs1_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs2_rtype_0 = dis_uops_0_lrs2_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_frs3_en_0 = dis_uops_0_frs3_en; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_fp_val_0 = dis_uops_0_fp_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_fp_single_0 = dis_uops_0_fp_single; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_xcpt_pf_if_0 = dis_uops_0_xcpt_pf_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_xcpt_ae_if_0 = dis_uops_0_xcpt_ae_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_xcpt_ma_if_0 = dis_uops_0_xcpt_ma_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_bp_debug_if_0 = dis_uops_0_bp_debug_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_bp_xcpt_if_0 = dis_uops_0_bp_xcpt_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_debug_fsrc_0 = dis_uops_0_debug_fsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_debug_tsrc_0 = dis_uops_0_debug_tsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_uopc_0 = dis_uops_1_uopc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_inst_0 = dis_uops_1_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_debug_inst_0 = dis_uops_1_debug_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_rvc_0 = dis_uops_1_is_rvc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_debug_pc_0 = dis_uops_1_debug_pc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_iq_type_0 = dis_uops_1_iq_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_fu_code_0 = dis_uops_1_fu_code; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_br_type_0 = dis_uops_1_ctrl_br_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_op1_sel_0 = dis_uops_1_ctrl_op1_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_op2_sel_0 = dis_uops_1_ctrl_op2_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_imm_sel_0 = dis_uops_1_ctrl_imm_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_op_fcn_0 = dis_uops_1_ctrl_op_fcn; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_fcn_dw_0 = dis_uops_1_ctrl_fcn_dw; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_csr_cmd_0 = dis_uops_1_ctrl_csr_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_is_load_0 = dis_uops_1_ctrl_is_load; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_is_sta_0 = dis_uops_1_ctrl_is_sta; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_is_std_0 = dis_uops_1_ctrl_is_std; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_iw_state_0 = dis_uops_1_iw_state; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_iw_p1_poisoned_0 = dis_uops_1_iw_p1_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_iw_p2_poisoned_0 = dis_uops_1_iw_p2_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_br_0 = dis_uops_1_is_br; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_jalr_0 = dis_uops_1_is_jalr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_jal_0 = dis_uops_1_is_jal; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_sfb_0 = dis_uops_1_is_sfb; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_br_mask_0 = dis_uops_1_br_mask; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_br_tag_0 = dis_uops_1_br_tag; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ftq_idx_0 = dis_uops_1_ftq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_edge_inst_0 = dis_uops_1_edge_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_pc_lob_0 = dis_uops_1_pc_lob; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_taken_0 = dis_uops_1_taken; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_imm_packed_0 = dis_uops_1_imm_packed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_csr_addr_0 = dis_uops_1_csr_addr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_rob_idx_0 = dis_uops_1_rob_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ldq_idx_0 = dis_uops_1_ldq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_stq_idx_0 = dis_uops_1_stq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_rxq_idx_0 = dis_uops_1_rxq_idx; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_1_pdst_T_3; // @[core.scala:659:28] assign io_lsu_dis_uops_1_bits_pdst_0 = dis_uops_1_pdst; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_1_prs1_T_3; // @[core.scala:654:28] assign io_lsu_dis_uops_1_bits_prs1_0 = dis_uops_1_prs1; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_1_prs2_T_1; // @[core.scala:656:28] assign io_lsu_dis_uops_1_bits_prs2_0 = dis_uops_1_prs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_prs3_0 = dis_uops_1_prs3; // @[core.scala:51:7, :167:24] wire _dis_uops_1_prs1_busy_T_4; // @[core.scala:664:85] assign io_lsu_dis_uops_1_bits_prs1_busy_0 = dis_uops_1_prs1_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_1_prs2_busy_T_4; // @[core.scala:666:85] assign io_lsu_dis_uops_1_bits_prs2_busy_0 = dis_uops_1_prs2_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_1_prs3_busy_T; // @[core.scala:668:46] assign io_lsu_dis_uops_1_bits_prs3_busy_0 = dis_uops_1_prs3_busy; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_1_stale_pdst_T_1; // @[core.scala:662:34] assign io_lsu_dis_uops_1_bits_stale_pdst_0 = dis_uops_1_stale_pdst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_exception_0 = dis_uops_1_exception; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_exc_cause_0 = dis_uops_1_exc_cause; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_bypassable_0 = dis_uops_1_bypassable; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_mem_cmd_0 = dis_uops_1_mem_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_mem_size_0 = dis_uops_1_mem_size; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_mem_signed_0 = dis_uops_1_mem_signed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_fence_0 = dis_uops_1_is_fence; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_fencei_0 = dis_uops_1_is_fencei; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_amo_0 = dis_uops_1_is_amo; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_uses_ldq_0 = dis_uops_1_uses_ldq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_uses_stq_0 = dis_uops_1_uses_stq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_sys_pc2epc_0 = dis_uops_1_is_sys_pc2epc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_unique_0 = dis_uops_1_is_unique; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_flush_on_commit_0 = dis_uops_1_flush_on_commit; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ldst_is_rs1_0 = dis_uops_1_ldst_is_rs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ldst_0 = dis_uops_1_ldst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs1_0 = dis_uops_1_lrs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs2_0 = dis_uops_1_lrs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs3_0 = dis_uops_1_lrs3; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ldst_val_0 = dis_uops_1_ldst_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_dst_rtype_0 = dis_uops_1_dst_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs1_rtype_0 = dis_uops_1_lrs1_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs2_rtype_0 = dis_uops_1_lrs2_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_frs3_en_0 = dis_uops_1_frs3_en; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_fp_val_0 = dis_uops_1_fp_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_fp_single_0 = dis_uops_1_fp_single; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_xcpt_pf_if_0 = dis_uops_1_xcpt_pf_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_xcpt_ae_if_0 = dis_uops_1_xcpt_ae_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_xcpt_ma_if_0 = dis_uops_1_xcpt_ma_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_bp_debug_if_0 = dis_uops_1_bp_debug_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_bp_xcpt_if_0 = dis_uops_1_bp_xcpt_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_debug_fsrc_0 = dis_uops_1_debug_fsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_debug_tsrc_0 = dis_uops_1_debug_tsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_uopc_0 = dis_uops_2_uopc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_inst_0 = dis_uops_2_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_debug_inst_0 = dis_uops_2_debug_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_rvc_0 = dis_uops_2_is_rvc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_debug_pc_0 = dis_uops_2_debug_pc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_iq_type_0 = dis_uops_2_iq_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_fu_code_0 = dis_uops_2_fu_code; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_br_type_0 = dis_uops_2_ctrl_br_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_op1_sel_0 = dis_uops_2_ctrl_op1_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_op2_sel_0 = dis_uops_2_ctrl_op2_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_imm_sel_0 = dis_uops_2_ctrl_imm_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_op_fcn_0 = dis_uops_2_ctrl_op_fcn; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_fcn_dw_0 = dis_uops_2_ctrl_fcn_dw; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_csr_cmd_0 = dis_uops_2_ctrl_csr_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_is_load_0 = dis_uops_2_ctrl_is_load; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_is_sta_0 = dis_uops_2_ctrl_is_sta; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_is_std_0 = dis_uops_2_ctrl_is_std; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_iw_state_0 = dis_uops_2_iw_state; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_iw_p1_poisoned_0 = dis_uops_2_iw_p1_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_iw_p2_poisoned_0 = dis_uops_2_iw_p2_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_br_0 = dis_uops_2_is_br; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_jalr_0 = dis_uops_2_is_jalr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_jal_0 = dis_uops_2_is_jal; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_sfb_0 = dis_uops_2_is_sfb; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_br_mask_0 = dis_uops_2_br_mask; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_br_tag_0 = dis_uops_2_br_tag; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ftq_idx_0 = dis_uops_2_ftq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_edge_inst_0 = dis_uops_2_edge_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_pc_lob_0 = dis_uops_2_pc_lob; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_taken_0 = dis_uops_2_taken; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_imm_packed_0 = dis_uops_2_imm_packed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_csr_addr_0 = dis_uops_2_csr_addr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_rob_idx_0 = dis_uops_2_rob_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ldq_idx_0 = dis_uops_2_ldq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_stq_idx_0 = dis_uops_2_stq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_rxq_idx_0 = dis_uops_2_rxq_idx; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_2_pdst_T_3; // @[core.scala:659:28] assign io_lsu_dis_uops_2_bits_pdst_0 = dis_uops_2_pdst; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_2_prs1_T_3; // @[core.scala:654:28] assign io_lsu_dis_uops_2_bits_prs1_0 = dis_uops_2_prs1; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_2_prs2_T_1; // @[core.scala:656:28] assign io_lsu_dis_uops_2_bits_prs2_0 = dis_uops_2_prs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_prs3_0 = dis_uops_2_prs3; // @[core.scala:51:7, :167:24] wire _dis_uops_2_prs1_busy_T_4; // @[core.scala:664:85] assign io_lsu_dis_uops_2_bits_prs1_busy_0 = dis_uops_2_prs1_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_2_prs2_busy_T_4; // @[core.scala:666:85] assign io_lsu_dis_uops_2_bits_prs2_busy_0 = dis_uops_2_prs2_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_2_prs3_busy_T; // @[core.scala:668:46] assign io_lsu_dis_uops_2_bits_prs3_busy_0 = dis_uops_2_prs3_busy; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_2_stale_pdst_T_1; // @[core.scala:662:34] assign io_lsu_dis_uops_2_bits_stale_pdst_0 = dis_uops_2_stale_pdst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_exception_0 = dis_uops_2_exception; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_exc_cause_0 = dis_uops_2_exc_cause; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_bypassable_0 = dis_uops_2_bypassable; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_mem_cmd_0 = dis_uops_2_mem_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_mem_size_0 = dis_uops_2_mem_size; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_mem_signed_0 = dis_uops_2_mem_signed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_fence_0 = dis_uops_2_is_fence; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_fencei_0 = dis_uops_2_is_fencei; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_amo_0 = dis_uops_2_is_amo; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_uses_ldq_0 = dis_uops_2_uses_ldq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_uses_stq_0 = dis_uops_2_uses_stq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_sys_pc2epc_0 = dis_uops_2_is_sys_pc2epc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_unique_0 = dis_uops_2_is_unique; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_flush_on_commit_0 = dis_uops_2_flush_on_commit; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ldst_is_rs1_0 = dis_uops_2_ldst_is_rs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ldst_0 = dis_uops_2_ldst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs1_0 = dis_uops_2_lrs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs2_0 = dis_uops_2_lrs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs3_0 = dis_uops_2_lrs3; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ldst_val_0 = dis_uops_2_ldst_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_dst_rtype_0 = dis_uops_2_dst_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs1_rtype_0 = dis_uops_2_lrs1_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs2_rtype_0 = dis_uops_2_lrs2_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_frs3_en_0 = dis_uops_2_frs3_en; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_fp_val_0 = dis_uops_2_fp_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_fp_single_0 = dis_uops_2_fp_single; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_xcpt_pf_if_0 = dis_uops_2_xcpt_pf_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_xcpt_ae_if_0 = dis_uops_2_xcpt_ae_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_xcpt_ma_if_0 = dis_uops_2_xcpt_ma_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_bp_debug_if_0 = dis_uops_2_bp_debug_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_bp_xcpt_if_0 = dis_uops_2_bp_xcpt_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_debug_fsrc_0 = dis_uops_2_debug_fsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_debug_tsrc_0 = dis_uops_2_debug_tsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_valid_0 = dis_fire_0; // @[core.scala:51:7, :168:24] assign io_lsu_dis_uops_1_valid_0 = dis_fire_1; // @[core.scala:51:7, :168:24] assign io_lsu_dis_uops_2_valid_0 = dis_fire_2; // @[core.scala:51:7, :168:24] wire _dis_ready_T; // @[core.scala:715:16] wire dis_ready; // @[core.scala:169:24] wire iss_valids_0; // @[core.scala:172:24] wire iss_valids_1; // @[core.scala:172:24] wire iss_valids_2; // @[core.scala:172:24] wire iss_valids_3; // @[core.scala:172:24] assign pred_wakeup_bits_uop_uopc = iss_uops_1_uopc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_uopc = iss_uops_1_uopc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_inst = iss_uops_1_inst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_inst = iss_uops_1_inst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_iq_type = iss_uops_1_iq_type; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_iq_type = iss_uops_1_iq_type; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_fu_code = iss_uops_1_fu_code; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_fu_code = iss_uops_1_fu_code; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_iw_state = iss_uops_1_iw_state; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_iw_state = iss_uops_1_iw_state; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_br = iss_uops_1_is_br; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_br = iss_uops_1_is_br; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_jal = iss_uops_1_is_jal; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_jal = iss_uops_1_is_jal; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_br_mask = iss_uops_1_br_mask; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_br_mask = iss_uops_1_br_mask; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_br_tag = iss_uops_1_br_tag; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_br_tag = iss_uops_1_br_tag; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_taken = iss_uops_1_taken; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_taken = iss_uops_1_taken; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_pdst = iss_uops_1_pdst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_pdst = iss_uops_1_pdst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs1 = iss_uops_1_prs1; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs1 = iss_uops_1_prs1; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs2 = iss_uops_1_prs2; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs2 = iss_uops_1_prs2; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs3 = iss_uops_1_prs3; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs3 = iss_uops_1_prs3; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ppred = iss_uops_1_ppred; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ppred = iss_uops_1_ppred; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_exception = iss_uops_1_exception; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_exception = iss_uops_1_exception; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_bypassable = iss_uops_1_bypassable; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_bypassable = iss_uops_1_bypassable; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_mem_size = iss_uops_1_mem_size; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_mem_size = iss_uops_1_mem_size; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_fence = iss_uops_1_is_fence; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_fence = iss_uops_1_is_fence; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_amo = iss_uops_1_is_amo; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_amo = iss_uops_1_is_amo; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_unique = iss_uops_1_is_unique; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_unique = iss_uops_1_is_unique; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ldst = iss_uops_1_ldst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ldst = iss_uops_1_ldst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_fp_val = iss_uops_1_fp_val; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_fp_val = iss_uops_1_fp_val; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_fp_single = iss_uops_1_fp_single; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_fp_single = iss_uops_1_fp_single; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_uopc = iss_uops_2_uopc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_inst = iss_uops_2_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_debug_inst = iss_uops_2_debug_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_rvc = iss_uops_2_is_rvc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_debug_pc = iss_uops_2_debug_pc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_iq_type = iss_uops_2_iq_type; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_fu_code = iss_uops_2_fu_code; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_br_type = iss_uops_2_ctrl_br_type; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_op1_sel = iss_uops_2_ctrl_op1_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_op2_sel = iss_uops_2_ctrl_op2_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_imm_sel = iss_uops_2_ctrl_imm_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_op_fcn = iss_uops_2_ctrl_op_fcn; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_fcn_dw = iss_uops_2_ctrl_fcn_dw; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_csr_cmd = iss_uops_2_ctrl_csr_cmd; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_is_load = iss_uops_2_ctrl_is_load; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_is_sta = iss_uops_2_ctrl_is_sta; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_is_std = iss_uops_2_ctrl_is_std; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_iw_state = iss_uops_2_iw_state; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_iw_p1_poisoned = iss_uops_2_iw_p1_poisoned; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_iw_p2_poisoned = iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_br = iss_uops_2_is_br; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_jalr = iss_uops_2_is_jalr; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_jal = iss_uops_2_is_jal; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_sfb = iss_uops_2_is_sfb; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_br_mask = iss_uops_2_br_mask; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_br_tag = iss_uops_2_br_tag; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ftq_idx = iss_uops_2_ftq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_edge_inst = iss_uops_2_edge_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_pc_lob = iss_uops_2_pc_lob; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_taken = iss_uops_2_taken; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_imm_packed = iss_uops_2_imm_packed; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_csr_addr = iss_uops_2_csr_addr; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_rob_idx = iss_uops_2_rob_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ldq_idx = iss_uops_2_ldq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_stq_idx = iss_uops_2_stq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_rxq_idx = iss_uops_2_rxq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_pdst = iss_uops_2_pdst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs1 = iss_uops_2_prs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs2 = iss_uops_2_prs2; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs3 = iss_uops_2_prs3; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ppred = iss_uops_2_ppred; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs1_busy = iss_uops_2_prs1_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs2_busy = iss_uops_2_prs2_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs3_busy = iss_uops_2_prs3_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ppred_busy = iss_uops_2_ppred_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_stale_pdst = iss_uops_2_stale_pdst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_exception = iss_uops_2_exception; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_exc_cause = iss_uops_2_exc_cause; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_bypassable = iss_uops_2_bypassable; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_mem_cmd = iss_uops_2_mem_cmd; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_mem_size = iss_uops_2_mem_size; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_mem_signed = iss_uops_2_mem_signed; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_fence = iss_uops_2_is_fence; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_fencei = iss_uops_2_is_fencei; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_amo = iss_uops_2_is_amo; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_uses_ldq = iss_uops_2_uses_ldq; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_uses_stq = iss_uops_2_uses_stq; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_sys_pc2epc = iss_uops_2_is_sys_pc2epc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_unique = iss_uops_2_is_unique; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_flush_on_commit = iss_uops_2_flush_on_commit; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ldst_is_rs1 = iss_uops_2_ldst_is_rs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ldst = iss_uops_2_ldst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs1 = iss_uops_2_lrs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs2 = iss_uops_2_lrs2; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs3 = iss_uops_2_lrs3; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ldst_val = iss_uops_2_ldst_val; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_dst_rtype = iss_uops_2_dst_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs1_rtype = iss_uops_2_lrs1_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs2_rtype = iss_uops_2_lrs2_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_frs3_en = iss_uops_2_frs3_en; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_fp_val = iss_uops_2_fp_val; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_fp_single = iss_uops_2_fp_single; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_xcpt_pf_if = iss_uops_2_xcpt_pf_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_xcpt_ae_if = iss_uops_2_xcpt_ae_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_xcpt_ma_if = iss_uops_2_xcpt_ma_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_bp_debug_if = iss_uops_2_bp_debug_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_bp_xcpt_if = iss_uops_2_bp_xcpt_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_debug_fsrc = iss_uops_2_debug_fsrc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_debug_tsrc = iss_uops_2_debug_tsrc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_uopc = iss_uops_3_uopc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_inst = iss_uops_3_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_debug_inst = iss_uops_3_debug_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_rvc = iss_uops_3_is_rvc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_debug_pc = iss_uops_3_debug_pc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_iq_type = iss_uops_3_iq_type; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_fu_code = iss_uops_3_fu_code; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_br_type = iss_uops_3_ctrl_br_type; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_op1_sel = iss_uops_3_ctrl_op1_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_op2_sel = iss_uops_3_ctrl_op2_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_imm_sel = iss_uops_3_ctrl_imm_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_op_fcn = iss_uops_3_ctrl_op_fcn; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_fcn_dw = iss_uops_3_ctrl_fcn_dw; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_csr_cmd = iss_uops_3_ctrl_csr_cmd; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_is_load = iss_uops_3_ctrl_is_load; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_is_sta = iss_uops_3_ctrl_is_sta; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_is_std = iss_uops_3_ctrl_is_std; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_iw_state = iss_uops_3_iw_state; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_iw_p1_poisoned = iss_uops_3_iw_p1_poisoned; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_iw_p2_poisoned = iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_br = iss_uops_3_is_br; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_jalr = iss_uops_3_is_jalr; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_jal = iss_uops_3_is_jal; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_sfb = iss_uops_3_is_sfb; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_br_mask = iss_uops_3_br_mask; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_br_tag = iss_uops_3_br_tag; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ftq_idx = iss_uops_3_ftq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_edge_inst = iss_uops_3_edge_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_pc_lob = iss_uops_3_pc_lob; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_taken = iss_uops_3_taken; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_imm_packed = iss_uops_3_imm_packed; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_csr_addr = iss_uops_3_csr_addr; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_rob_idx = iss_uops_3_rob_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ldq_idx = iss_uops_3_ldq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_stq_idx = iss_uops_3_stq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_rxq_idx = iss_uops_3_rxq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_pdst = iss_uops_3_pdst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs1 = iss_uops_3_prs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs2 = iss_uops_3_prs2; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs3 = iss_uops_3_prs3; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ppred = iss_uops_3_ppred; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs1_busy = iss_uops_3_prs1_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs2_busy = iss_uops_3_prs2_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs3_busy = iss_uops_3_prs3_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ppred_busy = iss_uops_3_ppred_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_stale_pdst = iss_uops_3_stale_pdst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_exception = iss_uops_3_exception; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_exc_cause = iss_uops_3_exc_cause; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_bypassable = iss_uops_3_bypassable; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_mem_cmd = iss_uops_3_mem_cmd; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_mem_size = iss_uops_3_mem_size; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_mem_signed = iss_uops_3_mem_signed; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_fence = iss_uops_3_is_fence; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_fencei = iss_uops_3_is_fencei; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_amo = iss_uops_3_is_amo; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_uses_ldq = iss_uops_3_uses_ldq; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_uses_stq = iss_uops_3_uses_stq; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_sys_pc2epc = iss_uops_3_is_sys_pc2epc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_unique = iss_uops_3_is_unique; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_flush_on_commit = iss_uops_3_flush_on_commit; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ldst_is_rs1 = iss_uops_3_ldst_is_rs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ldst = iss_uops_3_ldst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs1 = iss_uops_3_lrs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs2 = iss_uops_3_lrs2; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs3 = iss_uops_3_lrs3; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ldst_val = iss_uops_3_ldst_val; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_dst_rtype = iss_uops_3_dst_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs1_rtype = iss_uops_3_lrs1_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs2_rtype = iss_uops_3_lrs2_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_frs3_en = iss_uops_3_frs3_en; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_fp_val = iss_uops_3_fp_val; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_fp_single = iss_uops_3_fp_single; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_xcpt_pf_if = iss_uops_3_xcpt_pf_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_xcpt_ae_if = iss_uops_3_xcpt_ae_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_xcpt_ma_if = iss_uops_3_xcpt_ma_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_bp_debug_if = iss_uops_3_bp_debug_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_bp_xcpt_if = iss_uops_3_bp_xcpt_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_debug_fsrc = iss_uops_3_debug_fsrc; // @[core.scala:173:24, :814:29] wire [3:0] iss_uops_0_ctrl_br_type; // @[core.scala:173:24] wire [1:0] iss_uops_0_ctrl_op1_sel; // @[core.scala:173:24] wire [2:0] iss_uops_0_ctrl_op2_sel; // @[core.scala:173:24] wire [2:0] iss_uops_0_ctrl_imm_sel; // @[core.scala:173:24] wire [4:0] iss_uops_0_ctrl_op_fcn; // @[core.scala:173:24] wire iss_uops_0_ctrl_fcn_dw; // @[core.scala:173:24] wire [2:0] iss_uops_0_ctrl_csr_cmd; // @[core.scala:173:24] wire iss_uops_0_ctrl_is_load; // @[core.scala:173:24] wire iss_uops_0_ctrl_is_sta; // @[core.scala:173:24] wire iss_uops_0_ctrl_is_std; // @[core.scala:173:24] assign fast_wakeup_2_bits_uop_debug_tsrc = iss_uops_3_debug_tsrc; // @[core.scala:173:24, :814:29] wire [6:0] iss_uops_0_uopc; // @[core.scala:173:24] wire [31:0] iss_uops_0_inst; // @[core.scala:173:24] wire [31:0] iss_uops_0_debug_inst; // @[core.scala:173:24] wire iss_uops_0_is_rvc; // @[core.scala:173:24] wire [39:0] iss_uops_0_debug_pc; // @[core.scala:173:24] wire [2:0] iss_uops_0_iq_type; // @[core.scala:173:24] wire [9:0] iss_uops_0_fu_code; // @[core.scala:173:24] wire [1:0] iss_uops_0_iw_state; // @[core.scala:173:24] wire iss_uops_0_iw_p1_poisoned; // @[core.scala:173:24] wire iss_uops_0_iw_p2_poisoned; // @[core.scala:173:24] wire iss_uops_0_is_br; // @[core.scala:173:24] wire iss_uops_0_is_jalr; // @[core.scala:173:24] wire iss_uops_0_is_jal; // @[core.scala:173:24] wire iss_uops_0_is_sfb; // @[core.scala:173:24] wire [15:0] iss_uops_0_br_mask; // @[core.scala:173:24] wire [3:0] iss_uops_0_br_tag; // @[core.scala:173:24] wire [4:0] iss_uops_0_ftq_idx; // @[core.scala:173:24] wire iss_uops_0_edge_inst; // @[core.scala:173:24] wire [5:0] iss_uops_0_pc_lob; // @[core.scala:173:24] wire iss_uops_0_taken; // @[core.scala:173:24] wire [19:0] iss_uops_0_imm_packed; // @[core.scala:173:24] wire [11:0] iss_uops_0_csr_addr; // @[core.scala:173:24] wire [6:0] iss_uops_0_rob_idx; // @[core.scala:173:24] wire [4:0] iss_uops_0_ldq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_0_stq_idx; // @[core.scala:173:24] wire [1:0] iss_uops_0_rxq_idx; // @[core.scala:173:24] wire [6:0] iss_uops_0_pdst; // @[core.scala:173:24] wire [6:0] iss_uops_0_prs1; // @[core.scala:173:24] wire [6:0] iss_uops_0_prs2; // @[core.scala:173:24] wire [6:0] iss_uops_0_prs3; // @[core.scala:173:24] wire [4:0] iss_uops_0_ppred; // @[core.scala:173:24] wire iss_uops_0_prs1_busy; // @[core.scala:173:24] wire iss_uops_0_prs2_busy; // @[core.scala:173:24] wire iss_uops_0_prs3_busy; // @[core.scala:173:24] wire iss_uops_0_ppred_busy; // @[core.scala:173:24] wire [6:0] iss_uops_0_stale_pdst; // @[core.scala:173:24] wire iss_uops_0_exception; // @[core.scala:173:24] wire [63:0] iss_uops_0_exc_cause; // @[core.scala:173:24] wire iss_uops_0_bypassable; // @[core.scala:173:24] wire [4:0] iss_uops_0_mem_cmd; // @[core.scala:173:24] wire [1:0] iss_uops_0_mem_size; // @[core.scala:173:24] wire iss_uops_0_mem_signed; // @[core.scala:173:24] wire iss_uops_0_is_fence; // @[core.scala:173:24] wire iss_uops_0_is_fencei; // @[core.scala:173:24] wire iss_uops_0_is_amo; // @[core.scala:173:24] wire iss_uops_0_uses_ldq; // @[core.scala:173:24] wire iss_uops_0_uses_stq; // @[core.scala:173:24] wire iss_uops_0_is_sys_pc2epc; // @[core.scala:173:24] wire iss_uops_0_is_unique; // @[core.scala:173:24] wire iss_uops_0_flush_on_commit; // @[core.scala:173:24] wire iss_uops_0_ldst_is_rs1; // @[core.scala:173:24] wire [5:0] iss_uops_0_ldst; // @[core.scala:173:24] wire [5:0] iss_uops_0_lrs1; // @[core.scala:173:24] wire [5:0] iss_uops_0_lrs2; // @[core.scala:173:24] wire [5:0] iss_uops_0_lrs3; // @[core.scala:173:24] wire iss_uops_0_ldst_val; // @[core.scala:173:24] wire [1:0] iss_uops_0_dst_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_0_lrs1_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_0_lrs2_rtype; // @[core.scala:173:24] wire iss_uops_0_frs3_en; // @[core.scala:173:24] wire iss_uops_0_fp_val; // @[core.scala:173:24] wire iss_uops_0_fp_single; // @[core.scala:173:24] wire iss_uops_0_xcpt_pf_if; // @[core.scala:173:24] wire iss_uops_0_xcpt_ae_if; // @[core.scala:173:24] wire iss_uops_0_xcpt_ma_if; // @[core.scala:173:24] wire iss_uops_0_bp_debug_if; // @[core.scala:173:24] wire iss_uops_0_bp_xcpt_if; // @[core.scala:173:24] wire [1:0] iss_uops_0_debug_fsrc; // @[core.scala:173:24] wire [1:0] iss_uops_0_debug_tsrc; // @[core.scala:173:24] wire [3:0] bypasses_0_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_0_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_0_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_0_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_0_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_0_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_0_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_0_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_0_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_0_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_0_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_0_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_0_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_0_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_0_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_0_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_0_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_0_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_0_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_0_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_0_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_0_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_0_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_0_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_0_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_0_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_0_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_0_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_0_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_0_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_0_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_0_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_0_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_0_bits_data; // @[core.scala:174:24] wire bypasses_0_valid; // @[core.scala:174:24] wire [3:0] bypasses_1_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_1_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_1_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_1_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_1_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_1_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_1_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_1_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_1_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_1_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_1_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_1_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_1_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_1_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_1_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_1_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_1_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_1_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_1_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_1_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_1_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_1_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_1_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_1_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_1_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_1_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_1_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_1_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_1_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_1_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_1_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_1_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_1_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_1_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_1_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_1_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_1_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_1_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_1_bits_data; // @[core.scala:174:24] wire bypasses_1_valid; // @[core.scala:174:24] wire [3:0] bypasses_2_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_2_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_2_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_2_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_2_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_2_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_2_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_2_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_2_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_2_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_2_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_2_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_2_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_2_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_2_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_2_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_2_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_2_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_2_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_2_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_2_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_2_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_2_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_2_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_2_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_2_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_2_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_2_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_2_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_2_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_2_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_2_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_2_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_2_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_2_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_2_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_2_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_2_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_2_bits_data; // @[core.scala:174:24] wire bypasses_2_valid; // @[core.scala:174:24] wire [3:0] bypasses_3_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_3_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_3_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_3_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_3_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_3_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_3_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_3_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_3_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_3_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_3_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_3_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_3_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_3_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_3_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_3_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_3_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_3_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_3_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_3_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_3_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_3_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_3_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_3_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_3_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_3_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_3_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_3_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_3_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_3_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_3_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_3_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_3_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_3_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_3_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_3_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_3_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_3_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_3_bits_data; // @[core.scala:174:24] wire bypasses_3_valid; // @[core.scala:174:24] wire [3:0] bypasses_4_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_4_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_4_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_4_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_4_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_4_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_4_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_4_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_4_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_4_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_4_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_4_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_4_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_4_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_4_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_4_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_4_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_4_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_4_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_4_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_4_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_4_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_4_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_4_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_4_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_4_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_4_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_4_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_4_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_4_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_4_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_4_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_4_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_4_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_4_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_4_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_4_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_4_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_4_bits_data; // @[core.scala:174:24] wire bypasses_4_valid; // @[core.scala:174:24] wire [3:0] pred_bypasses_0_bits_uop_ctrl_br_type; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_ctrl_op1_sel; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_uop_ctrl_op2_sel; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_uop_ctrl_imm_sel; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_ctrl_op_fcn; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ctrl_fcn_dw; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_uop_ctrl_csr_cmd; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ctrl_is_load; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ctrl_is_sta; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ctrl_is_std; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_uopc; // @[core.scala:175:27] wire [31:0] pred_bypasses_0_bits_uop_inst; // @[core.scala:175:27] wire [31:0] pred_bypasses_0_bits_uop_debug_inst; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_rvc; // @[core.scala:175:27] wire [39:0] pred_bypasses_0_bits_uop_debug_pc; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_uop_iq_type; // @[core.scala:175:27] wire [9:0] pred_bypasses_0_bits_uop_fu_code; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_iw_state; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_iw_p1_poisoned; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_iw_p2_poisoned; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_br; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_jalr; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_jal; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_sfb; // @[core.scala:175:27] wire [15:0] pred_bypasses_0_bits_uop_br_mask; // @[core.scala:175:27] wire [3:0] pred_bypasses_0_bits_uop_br_tag; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_ftq_idx; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_edge_inst; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_pc_lob; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_taken; // @[core.scala:175:27] wire [19:0] pred_bypasses_0_bits_uop_imm_packed; // @[core.scala:175:27] wire [11:0] pred_bypasses_0_bits_uop_csr_addr; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_rob_idx; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_ldq_idx; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_stq_idx; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_rxq_idx; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_pdst; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_prs1; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_prs2; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_prs3; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_ppred; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_prs1_busy; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_prs2_busy; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_prs3_busy; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ppred_busy; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_stale_pdst; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_exception; // @[core.scala:175:27] wire [63:0] pred_bypasses_0_bits_uop_exc_cause; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_bypassable; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_mem_cmd; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_mem_size; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_mem_signed; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_fence; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_fencei; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_amo; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_uses_ldq; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_uses_stq; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_unique; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_flush_on_commit; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_ldst; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_lrs1; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_lrs2; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_lrs3; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ldst_val; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_dst_rtype; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_frs3_en; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_fp_val; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_fp_single; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_bp_debug_if; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_debug_fsrc; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_debug_tsrc; // @[core.scala:175:27] wire pred_bypasses_0_bits_data; // @[core.scala:175:27] wire pred_bypasses_0_valid; // @[core.scala:175:27] reg [6:0] brinfos_0_uop_uopc; // @[core.scala:182:20] reg [31:0] brinfos_0_uop_inst; // @[core.scala:182:20] reg [31:0] brinfos_0_uop_debug_inst; // @[core.scala:182:20] reg brinfos_0_uop_is_rvc; // @[core.scala:182:20] reg [39:0] brinfos_0_uop_debug_pc; // @[core.scala:182:20] reg [2:0] brinfos_0_uop_iq_type; // @[core.scala:182:20] reg [9:0] brinfos_0_uop_fu_code; // @[core.scala:182:20] reg [3:0] brinfos_0_uop_ctrl_br_type; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_ctrl_op1_sel; // @[core.scala:182:20] reg [2:0] brinfos_0_uop_ctrl_op2_sel; // @[core.scala:182:20] reg [2:0] brinfos_0_uop_ctrl_imm_sel; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_ctrl_op_fcn; // @[core.scala:182:20] reg brinfos_0_uop_ctrl_fcn_dw; // @[core.scala:182:20] reg [2:0] brinfos_0_uop_ctrl_csr_cmd; // @[core.scala:182:20] reg brinfos_0_uop_ctrl_is_load; // @[core.scala:182:20] reg brinfos_0_uop_ctrl_is_sta; // @[core.scala:182:20] reg brinfos_0_uop_ctrl_is_std; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_iw_state; // @[core.scala:182:20] reg brinfos_0_uop_iw_p1_poisoned; // @[core.scala:182:20] reg brinfos_0_uop_iw_p2_poisoned; // @[core.scala:182:20] reg brinfos_0_uop_is_br; // @[core.scala:182:20] reg brinfos_0_uop_is_jalr; // @[core.scala:182:20] reg brinfos_0_uop_is_jal; // @[core.scala:182:20] reg brinfos_0_uop_is_sfb; // @[core.scala:182:20] reg [15:0] brinfos_0_uop_br_mask; // @[core.scala:182:20] reg [3:0] brinfos_0_uop_br_tag; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_ftq_idx; // @[core.scala:182:20] reg brinfos_0_uop_edge_inst; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_pc_lob; // @[core.scala:182:20] reg brinfos_0_uop_taken; // @[core.scala:182:20] reg [19:0] brinfos_0_uop_imm_packed; // @[core.scala:182:20] reg [11:0] brinfos_0_uop_csr_addr; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_rob_idx; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_ldq_idx; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_stq_idx; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_rxq_idx; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_pdst; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_prs1; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_prs2; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_prs3; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_ppred; // @[core.scala:182:20] reg brinfos_0_uop_prs1_busy; // @[core.scala:182:20] reg brinfos_0_uop_prs2_busy; // @[core.scala:182:20] reg brinfos_0_uop_prs3_busy; // @[core.scala:182:20] reg brinfos_0_uop_ppred_busy; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_stale_pdst; // @[core.scala:182:20] reg brinfos_0_uop_exception; // @[core.scala:182:20] reg [63:0] brinfos_0_uop_exc_cause; // @[core.scala:182:20] reg brinfos_0_uop_bypassable; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_mem_cmd; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_mem_size; // @[core.scala:182:20] reg brinfos_0_uop_mem_signed; // @[core.scala:182:20] reg brinfos_0_uop_is_fence; // @[core.scala:182:20] reg brinfos_0_uop_is_fencei; // @[core.scala:182:20] reg brinfos_0_uop_is_amo; // @[core.scala:182:20] reg brinfos_0_uop_uses_ldq; // @[core.scala:182:20] reg brinfos_0_uop_uses_stq; // @[core.scala:182:20] reg brinfos_0_uop_is_sys_pc2epc; // @[core.scala:182:20] reg brinfos_0_uop_is_unique; // @[core.scala:182:20] reg brinfos_0_uop_flush_on_commit; // @[core.scala:182:20] reg brinfos_0_uop_ldst_is_rs1; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_ldst; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_lrs1; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_lrs2; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_lrs3; // @[core.scala:182:20] reg brinfos_0_uop_ldst_val; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_dst_rtype; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_lrs1_rtype; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_lrs2_rtype; // @[core.scala:182:20] reg brinfos_0_uop_frs3_en; // @[core.scala:182:20] reg brinfos_0_uop_fp_val; // @[core.scala:182:20] reg brinfos_0_uop_fp_single; // @[core.scala:182:20] reg brinfos_0_uop_xcpt_pf_if; // @[core.scala:182:20] reg brinfos_0_uop_xcpt_ae_if; // @[core.scala:182:20] reg brinfos_0_uop_xcpt_ma_if; // @[core.scala:182:20] reg brinfos_0_uop_bp_debug_if; // @[core.scala:182:20] reg brinfos_0_uop_bp_xcpt_if; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_debug_fsrc; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_debug_tsrc; // @[core.scala:182:20] reg brinfos_0_valid; // @[core.scala:182:20] reg brinfos_0_mispredict; // @[core.scala:182:20] reg brinfos_0_taken; // @[core.scala:182:20] reg [2:0] brinfos_0_cfi_type; // @[core.scala:182:20] reg [1:0] brinfos_0_pc_sel; // @[core.scala:182:20] reg [39:0] brinfos_0_jalr_target; // @[core.scala:182:20] reg [20:0] brinfos_0_target_offset; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_uopc; // @[core.scala:182:20] reg [31:0] brinfos_1_uop_inst; // @[core.scala:182:20] reg [31:0] brinfos_1_uop_debug_inst; // @[core.scala:182:20] reg brinfos_1_uop_is_rvc; // @[core.scala:182:20] reg [39:0] brinfos_1_uop_debug_pc; // @[core.scala:182:20] reg [2:0] brinfos_1_uop_iq_type; // @[core.scala:182:20] reg [9:0] brinfos_1_uop_fu_code; // @[core.scala:182:20] reg [3:0] brinfos_1_uop_ctrl_br_type; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_ctrl_op1_sel; // @[core.scala:182:20] reg [2:0] brinfos_1_uop_ctrl_op2_sel; // @[core.scala:182:20] reg [2:0] brinfos_1_uop_ctrl_imm_sel; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_ctrl_op_fcn; // @[core.scala:182:20] reg brinfos_1_uop_ctrl_fcn_dw; // @[core.scala:182:20] reg [2:0] brinfos_1_uop_ctrl_csr_cmd; // @[core.scala:182:20] reg brinfos_1_uop_ctrl_is_load; // @[core.scala:182:20] reg brinfos_1_uop_ctrl_is_sta; // @[core.scala:182:20] reg brinfos_1_uop_ctrl_is_std; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_iw_state; // @[core.scala:182:20] reg brinfos_1_uop_iw_p1_poisoned; // @[core.scala:182:20] reg brinfos_1_uop_iw_p2_poisoned; // @[core.scala:182:20] reg brinfos_1_uop_is_br; // @[core.scala:182:20] reg brinfos_1_uop_is_jalr; // @[core.scala:182:20] reg brinfos_1_uop_is_jal; // @[core.scala:182:20] reg brinfos_1_uop_is_sfb; // @[core.scala:182:20] reg [15:0] brinfos_1_uop_br_mask; // @[core.scala:182:20] reg [3:0] brinfos_1_uop_br_tag; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_ftq_idx; // @[core.scala:182:20] reg brinfos_1_uop_edge_inst; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_pc_lob; // @[core.scala:182:20] reg brinfos_1_uop_taken; // @[core.scala:182:20] reg [19:0] brinfos_1_uop_imm_packed; // @[core.scala:182:20] reg [11:0] brinfos_1_uop_csr_addr; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_rob_idx; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_ldq_idx; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_stq_idx; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_rxq_idx; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_pdst; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_prs1; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_prs2; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_prs3; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_ppred; // @[core.scala:182:20] reg brinfos_1_uop_prs1_busy; // @[core.scala:182:20] reg brinfos_1_uop_prs2_busy; // @[core.scala:182:20] reg brinfos_1_uop_prs3_busy; // @[core.scala:182:20] reg brinfos_1_uop_ppred_busy; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_stale_pdst; // @[core.scala:182:20] reg brinfos_1_uop_exception; // @[core.scala:182:20] reg [63:0] brinfos_1_uop_exc_cause; // @[core.scala:182:20] reg brinfos_1_uop_bypassable; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_mem_cmd; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_mem_size; // @[core.scala:182:20] reg brinfos_1_uop_mem_signed; // @[core.scala:182:20] reg brinfos_1_uop_is_fence; // @[core.scala:182:20] reg brinfos_1_uop_is_fencei; // @[core.scala:182:20] reg brinfos_1_uop_is_amo; // @[core.scala:182:20] reg brinfos_1_uop_uses_ldq; // @[core.scala:182:20] reg brinfos_1_uop_uses_stq; // @[core.scala:182:20] reg brinfos_1_uop_is_sys_pc2epc; // @[core.scala:182:20] reg brinfos_1_uop_is_unique; // @[core.scala:182:20] reg brinfos_1_uop_flush_on_commit; // @[core.scala:182:20] reg brinfos_1_uop_ldst_is_rs1; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_ldst; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_lrs1; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_lrs2; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_lrs3; // @[core.scala:182:20] reg brinfos_1_uop_ldst_val; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_dst_rtype; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_lrs1_rtype; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_lrs2_rtype; // @[core.scala:182:20] reg brinfos_1_uop_frs3_en; // @[core.scala:182:20] reg brinfos_1_uop_fp_val; // @[core.scala:182:20] reg brinfos_1_uop_fp_single; // @[core.scala:182:20] reg brinfos_1_uop_xcpt_pf_if; // @[core.scala:182:20] reg brinfos_1_uop_xcpt_ae_if; // @[core.scala:182:20] reg brinfos_1_uop_xcpt_ma_if; // @[core.scala:182:20] reg brinfos_1_uop_bp_debug_if; // @[core.scala:182:20] reg brinfos_1_uop_bp_xcpt_if; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_debug_fsrc; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_debug_tsrc; // @[core.scala:182:20] reg brinfos_1_valid; // @[core.scala:182:20] reg brinfos_1_mispredict; // @[core.scala:182:20] reg brinfos_1_taken; // @[core.scala:182:20] reg [2:0] brinfos_1_cfi_type; // @[core.scala:182:20] reg [1:0] brinfos_1_pc_sel; // @[core.scala:182:20] reg [20:0] brinfos_1_target_offset; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_uopc; // @[core.scala:182:20] reg [31:0] brinfos_2_uop_inst; // @[core.scala:182:20] reg [31:0] brinfos_2_uop_debug_inst; // @[core.scala:182:20] reg brinfos_2_uop_is_rvc; // @[core.scala:182:20] reg [39:0] brinfos_2_uop_debug_pc; // @[core.scala:182:20] reg [2:0] brinfos_2_uop_iq_type; // @[core.scala:182:20] reg [9:0] brinfos_2_uop_fu_code; // @[core.scala:182:20] reg [3:0] brinfos_2_uop_ctrl_br_type; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_ctrl_op1_sel; // @[core.scala:182:20] reg [2:0] brinfos_2_uop_ctrl_op2_sel; // @[core.scala:182:20] reg [2:0] brinfos_2_uop_ctrl_imm_sel; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_ctrl_op_fcn; // @[core.scala:182:20] reg brinfos_2_uop_ctrl_fcn_dw; // @[core.scala:182:20] reg [2:0] brinfos_2_uop_ctrl_csr_cmd; // @[core.scala:182:20] reg brinfos_2_uop_ctrl_is_load; // @[core.scala:182:20] reg brinfos_2_uop_ctrl_is_sta; // @[core.scala:182:20] reg brinfos_2_uop_ctrl_is_std; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_iw_state; // @[core.scala:182:20] reg brinfos_2_uop_iw_p1_poisoned; // @[core.scala:182:20] reg brinfos_2_uop_iw_p2_poisoned; // @[core.scala:182:20] reg brinfos_2_uop_is_br; // @[core.scala:182:20] reg brinfos_2_uop_is_jalr; // @[core.scala:182:20] reg brinfos_2_uop_is_jal; // @[core.scala:182:20] reg brinfos_2_uop_is_sfb; // @[core.scala:182:20] reg [15:0] brinfos_2_uop_br_mask; // @[core.scala:182:20] reg [3:0] brinfos_2_uop_br_tag; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_ftq_idx; // @[core.scala:182:20] reg brinfos_2_uop_edge_inst; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_pc_lob; // @[core.scala:182:20] reg brinfos_2_uop_taken; // @[core.scala:182:20] reg [19:0] brinfos_2_uop_imm_packed; // @[core.scala:182:20] reg [11:0] brinfos_2_uop_csr_addr; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_rob_idx; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_ldq_idx; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_stq_idx; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_rxq_idx; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_pdst; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_prs1; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_prs2; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_prs3; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_ppred; // @[core.scala:182:20] reg brinfos_2_uop_prs1_busy; // @[core.scala:182:20] reg brinfos_2_uop_prs2_busy; // @[core.scala:182:20] reg brinfos_2_uop_prs3_busy; // @[core.scala:182:20] reg brinfos_2_uop_ppred_busy; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_stale_pdst; // @[core.scala:182:20] reg brinfos_2_uop_exception; // @[core.scala:182:20] reg [63:0] brinfos_2_uop_exc_cause; // @[core.scala:182:20] reg brinfos_2_uop_bypassable; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_mem_cmd; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_mem_size; // @[core.scala:182:20] reg brinfos_2_uop_mem_signed; // @[core.scala:182:20] reg brinfos_2_uop_is_fence; // @[core.scala:182:20] reg brinfos_2_uop_is_fencei; // @[core.scala:182:20] reg brinfos_2_uop_is_amo; // @[core.scala:182:20] reg brinfos_2_uop_uses_ldq; // @[core.scala:182:20] reg brinfos_2_uop_uses_stq; // @[core.scala:182:20] reg brinfos_2_uop_is_sys_pc2epc; // @[core.scala:182:20] reg brinfos_2_uop_is_unique; // @[core.scala:182:20] reg brinfos_2_uop_flush_on_commit; // @[core.scala:182:20] reg brinfos_2_uop_ldst_is_rs1; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_ldst; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_lrs1; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_lrs2; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_lrs3; // @[core.scala:182:20] reg brinfos_2_uop_ldst_val; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_dst_rtype; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_lrs1_rtype; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_lrs2_rtype; // @[core.scala:182:20] reg brinfos_2_uop_frs3_en; // @[core.scala:182:20] reg brinfos_2_uop_fp_val; // @[core.scala:182:20] reg brinfos_2_uop_fp_single; // @[core.scala:182:20] reg brinfos_2_uop_xcpt_pf_if; // @[core.scala:182:20] reg brinfos_2_uop_xcpt_ae_if; // @[core.scala:182:20] reg brinfos_2_uop_xcpt_ma_if; // @[core.scala:182:20] reg brinfos_2_uop_bp_debug_if; // @[core.scala:182:20] reg brinfos_2_uop_bp_xcpt_if; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_debug_fsrc; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_debug_tsrc; // @[core.scala:182:20] reg brinfos_2_valid; // @[core.scala:182:20] reg brinfos_2_mispredict; // @[core.scala:182:20] reg brinfos_2_taken; // @[core.scala:182:20] reg [2:0] brinfos_2_cfi_type; // @[core.scala:182:20] reg [1:0] brinfos_2_pc_sel; // @[core.scala:182:20] reg [20:0] brinfos_2_target_offset; // @[core.scala:182:20] wire [15:0] b1_resolve_mask; // @[core.scala:189:19] assign io_ifu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:51:7, :188:23] wire [15:0] b1_mispredict_mask; // @[core.scala:189:19] assign io_ifu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_valid_0 = brupdate_b2_valid; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_valid_0 = brupdate_b2_valid; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:51:7, :188:23] wire _next_ghist_cfi_in_bank_0_T = brupdate_b2_taken; // @[frontend.scala:104:37] wire _next_ghist_new_history_new_saw_branch_taken_T_1 = brupdate_b2_taken; // @[frontend.scala:119:59] assign io_ifu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:51:7, :188:23] wire [15:0] _b1_resolve_mask_T_4; // @[core.scala:199:72] assign brupdate_b1_resolve_mask = b1_resolve_mask; // @[core.scala:188:23, :189:19] wire [15:0] _b1_mispredict_mask_T_7; // @[core.scala:200:93] assign brupdate_b1_mispredict_mask = b1_mispredict_mask; // @[core.scala:188:23, :189:19] reg [6:0] b2_uop_uopc; // @[core.scala:190:18] assign brupdate_b2_uop_uopc = b2_uop_uopc; // @[core.scala:188:23, :190:18] reg [31:0] b2_uop_inst; // @[core.scala:190:18] assign brupdate_b2_uop_inst = b2_uop_inst; // @[core.scala:188:23, :190:18] reg [31:0] b2_uop_debug_inst; // @[core.scala:190:18] assign brupdate_b2_uop_debug_inst = b2_uop_debug_inst; // @[core.scala:188:23, :190:18] reg b2_uop_is_rvc; // @[core.scala:190:18] assign brupdate_b2_uop_is_rvc = b2_uop_is_rvc; // @[core.scala:188:23, :190:18] reg [39:0] b2_uop_debug_pc; // @[core.scala:190:18] assign brupdate_b2_uop_debug_pc = b2_uop_debug_pc; // @[core.scala:188:23, :190:18] reg [2:0] b2_uop_iq_type; // @[core.scala:190:18] assign brupdate_b2_uop_iq_type = b2_uop_iq_type; // @[core.scala:188:23, :190:18] reg [9:0] b2_uop_fu_code; // @[core.scala:190:18] assign brupdate_b2_uop_fu_code = b2_uop_fu_code; // @[core.scala:188:23, :190:18] reg [3:0] b2_uop_ctrl_br_type; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_br_type = b2_uop_ctrl_br_type; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_ctrl_op1_sel; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_op1_sel = b2_uop_ctrl_op1_sel; // @[core.scala:188:23, :190:18] reg [2:0] b2_uop_ctrl_op2_sel; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_op2_sel = b2_uop_ctrl_op2_sel; // @[core.scala:188:23, :190:18] reg [2:0] b2_uop_ctrl_imm_sel; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_imm_sel = b2_uop_ctrl_imm_sel; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_ctrl_op_fcn; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_op_fcn = b2_uop_ctrl_op_fcn; // @[core.scala:188:23, :190:18] reg b2_uop_ctrl_fcn_dw; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_fcn_dw = b2_uop_ctrl_fcn_dw; // @[core.scala:188:23, :190:18] reg [2:0] b2_uop_ctrl_csr_cmd; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_csr_cmd = b2_uop_ctrl_csr_cmd; // @[core.scala:188:23, :190:18] reg b2_uop_ctrl_is_load; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_is_load = b2_uop_ctrl_is_load; // @[core.scala:188:23, :190:18] reg b2_uop_ctrl_is_sta; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_is_sta = b2_uop_ctrl_is_sta; // @[core.scala:188:23, :190:18] reg b2_uop_ctrl_is_std; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_is_std = b2_uop_ctrl_is_std; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_iw_state; // @[core.scala:190:18] assign brupdate_b2_uop_iw_state = b2_uop_iw_state; // @[core.scala:188:23, :190:18] reg b2_uop_iw_p1_poisoned; // @[core.scala:190:18] assign brupdate_b2_uop_iw_p1_poisoned = b2_uop_iw_p1_poisoned; // @[core.scala:188:23, :190:18] reg b2_uop_iw_p2_poisoned; // @[core.scala:190:18] assign brupdate_b2_uop_iw_p2_poisoned = b2_uop_iw_p2_poisoned; // @[core.scala:188:23, :190:18] reg b2_uop_is_br; // @[core.scala:190:18] assign brupdate_b2_uop_is_br = b2_uop_is_br; // @[core.scala:188:23, :190:18] reg b2_uop_is_jalr; // @[core.scala:190:18] assign brupdate_b2_uop_is_jalr = b2_uop_is_jalr; // @[core.scala:188:23, :190:18] reg b2_uop_is_jal; // @[core.scala:190:18] assign brupdate_b2_uop_is_jal = b2_uop_is_jal; // @[core.scala:188:23, :190:18] reg b2_uop_is_sfb; // @[core.scala:190:18] assign brupdate_b2_uop_is_sfb = b2_uop_is_sfb; // @[core.scala:188:23, :190:18] reg [15:0] b2_uop_br_mask; // @[core.scala:190:18] assign brupdate_b2_uop_br_mask = b2_uop_br_mask; // @[core.scala:188:23, :190:18] reg [3:0] b2_uop_br_tag; // @[core.scala:190:18] assign brupdate_b2_uop_br_tag = b2_uop_br_tag; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_ftq_idx; // @[core.scala:190:18] assign brupdate_b2_uop_ftq_idx = b2_uop_ftq_idx; // @[core.scala:188:23, :190:18] reg b2_uop_edge_inst; // @[core.scala:190:18] assign brupdate_b2_uop_edge_inst = b2_uop_edge_inst; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_pc_lob; // @[core.scala:190:18] assign brupdate_b2_uop_pc_lob = b2_uop_pc_lob; // @[core.scala:188:23, :190:18] reg b2_uop_taken; // @[core.scala:190:18] assign brupdate_b2_uop_taken = b2_uop_taken; // @[core.scala:188:23, :190:18] reg [19:0] b2_uop_imm_packed; // @[core.scala:190:18] assign brupdate_b2_uop_imm_packed = b2_uop_imm_packed; // @[core.scala:188:23, :190:18] reg [11:0] b2_uop_csr_addr; // @[core.scala:190:18] assign brupdate_b2_uop_csr_addr = b2_uop_csr_addr; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_rob_idx; // @[core.scala:190:18] assign brupdate_b2_uop_rob_idx = b2_uop_rob_idx; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_ldq_idx; // @[core.scala:190:18] assign brupdate_b2_uop_ldq_idx = b2_uop_ldq_idx; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_stq_idx; // @[core.scala:190:18] assign brupdate_b2_uop_stq_idx = b2_uop_stq_idx; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_rxq_idx; // @[core.scala:190:18] assign brupdate_b2_uop_rxq_idx = b2_uop_rxq_idx; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_pdst; // @[core.scala:190:18] assign brupdate_b2_uop_pdst = b2_uop_pdst; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_prs1; // @[core.scala:190:18] assign brupdate_b2_uop_prs1 = b2_uop_prs1; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_prs2; // @[core.scala:190:18] assign brupdate_b2_uop_prs2 = b2_uop_prs2; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_prs3; // @[core.scala:190:18] assign brupdate_b2_uop_prs3 = b2_uop_prs3; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_ppred; // @[core.scala:190:18] assign brupdate_b2_uop_ppred = b2_uop_ppred; // @[core.scala:188:23, :190:18] reg b2_uop_prs1_busy; // @[core.scala:190:18] assign brupdate_b2_uop_prs1_busy = b2_uop_prs1_busy; // @[core.scala:188:23, :190:18] reg b2_uop_prs2_busy; // @[core.scala:190:18] assign brupdate_b2_uop_prs2_busy = b2_uop_prs2_busy; // @[core.scala:188:23, :190:18] reg b2_uop_prs3_busy; // @[core.scala:190:18] assign brupdate_b2_uop_prs3_busy = b2_uop_prs3_busy; // @[core.scala:188:23, :190:18] reg b2_uop_ppred_busy; // @[core.scala:190:18] assign brupdate_b2_uop_ppred_busy = b2_uop_ppred_busy; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_stale_pdst; // @[core.scala:190:18] assign brupdate_b2_uop_stale_pdst = b2_uop_stale_pdst; // @[core.scala:188:23, :190:18] reg b2_uop_exception; // @[core.scala:190:18] assign brupdate_b2_uop_exception = b2_uop_exception; // @[core.scala:188:23, :190:18] reg [63:0] b2_uop_exc_cause; // @[core.scala:190:18] assign brupdate_b2_uop_exc_cause = b2_uop_exc_cause; // @[core.scala:188:23, :190:18] reg b2_uop_bypassable; // @[core.scala:190:18] assign brupdate_b2_uop_bypassable = b2_uop_bypassable; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_mem_cmd; // @[core.scala:190:18] assign brupdate_b2_uop_mem_cmd = b2_uop_mem_cmd; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_mem_size; // @[core.scala:190:18] assign brupdate_b2_uop_mem_size = b2_uop_mem_size; // @[core.scala:188:23, :190:18] reg b2_uop_mem_signed; // @[core.scala:190:18] assign brupdate_b2_uop_mem_signed = b2_uop_mem_signed; // @[core.scala:188:23, :190:18] reg b2_uop_is_fence; // @[core.scala:190:18] assign brupdate_b2_uop_is_fence = b2_uop_is_fence; // @[core.scala:188:23, :190:18] reg b2_uop_is_fencei; // @[core.scala:190:18] assign brupdate_b2_uop_is_fencei = b2_uop_is_fencei; // @[core.scala:188:23, :190:18] reg b2_uop_is_amo; // @[core.scala:190:18] assign brupdate_b2_uop_is_amo = b2_uop_is_amo; // @[core.scala:188:23, :190:18] reg b2_uop_uses_ldq; // @[core.scala:190:18] assign brupdate_b2_uop_uses_ldq = b2_uop_uses_ldq; // @[core.scala:188:23, :190:18] reg b2_uop_uses_stq; // @[core.scala:190:18] assign brupdate_b2_uop_uses_stq = b2_uop_uses_stq; // @[core.scala:188:23, :190:18] reg b2_uop_is_sys_pc2epc; // @[core.scala:190:18] assign brupdate_b2_uop_is_sys_pc2epc = b2_uop_is_sys_pc2epc; // @[core.scala:188:23, :190:18] reg b2_uop_is_unique; // @[core.scala:190:18] assign brupdate_b2_uop_is_unique = b2_uop_is_unique; // @[core.scala:188:23, :190:18] reg b2_uop_flush_on_commit; // @[core.scala:190:18] assign brupdate_b2_uop_flush_on_commit = b2_uop_flush_on_commit; // @[core.scala:188:23, :190:18] reg b2_uop_ldst_is_rs1; // @[core.scala:190:18] assign brupdate_b2_uop_ldst_is_rs1 = b2_uop_ldst_is_rs1; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_ldst; // @[core.scala:190:18] assign brupdate_b2_uop_ldst = b2_uop_ldst; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_lrs1; // @[core.scala:190:18] assign brupdate_b2_uop_lrs1 = b2_uop_lrs1; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_lrs2; // @[core.scala:190:18] assign brupdate_b2_uop_lrs2 = b2_uop_lrs2; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_lrs3; // @[core.scala:190:18] assign brupdate_b2_uop_lrs3 = b2_uop_lrs3; // @[core.scala:188:23, :190:18] reg b2_uop_ldst_val; // @[core.scala:190:18] assign brupdate_b2_uop_ldst_val = b2_uop_ldst_val; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_dst_rtype; // @[core.scala:190:18] assign brupdate_b2_uop_dst_rtype = b2_uop_dst_rtype; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_lrs1_rtype; // @[core.scala:190:18] assign brupdate_b2_uop_lrs1_rtype = b2_uop_lrs1_rtype; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_lrs2_rtype; // @[core.scala:190:18] assign brupdate_b2_uop_lrs2_rtype = b2_uop_lrs2_rtype; // @[core.scala:188:23, :190:18] reg b2_uop_frs3_en; // @[core.scala:190:18] assign brupdate_b2_uop_frs3_en = b2_uop_frs3_en; // @[core.scala:188:23, :190:18] reg b2_uop_fp_val; // @[core.scala:190:18] assign brupdate_b2_uop_fp_val = b2_uop_fp_val; // @[core.scala:188:23, :190:18] reg b2_uop_fp_single; // @[core.scala:190:18] assign brupdate_b2_uop_fp_single = b2_uop_fp_single; // @[core.scala:188:23, :190:18] reg b2_uop_xcpt_pf_if; // @[core.scala:190:18] assign brupdate_b2_uop_xcpt_pf_if = b2_uop_xcpt_pf_if; // @[core.scala:188:23, :190:18] reg b2_uop_xcpt_ae_if; // @[core.scala:190:18] assign brupdate_b2_uop_xcpt_ae_if = b2_uop_xcpt_ae_if; // @[core.scala:188:23, :190:18] reg b2_uop_xcpt_ma_if; // @[core.scala:190:18] assign brupdate_b2_uop_xcpt_ma_if = b2_uop_xcpt_ma_if; // @[core.scala:188:23, :190:18] reg b2_uop_bp_debug_if; // @[core.scala:190:18] assign brupdate_b2_uop_bp_debug_if = b2_uop_bp_debug_if; // @[core.scala:188:23, :190:18] reg b2_uop_bp_xcpt_if; // @[core.scala:190:18] assign brupdate_b2_uop_bp_xcpt_if = b2_uop_bp_xcpt_if; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_debug_fsrc; // @[core.scala:190:18] assign brupdate_b2_uop_debug_fsrc = b2_uop_debug_fsrc; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_debug_tsrc; // @[core.scala:190:18] assign brupdate_b2_uop_debug_tsrc = b2_uop_debug_tsrc; // @[core.scala:188:23, :190:18] reg b2_mispredict; // @[core.scala:190:18] assign brupdate_b2_mispredict = b2_mispredict; // @[core.scala:188:23, :190:18] reg b2_taken; // @[core.scala:190:18] assign brupdate_b2_taken = b2_taken; // @[core.scala:188:23, :190:18] reg [2:0] b2_cfi_type; // @[core.scala:190:18] assign brupdate_b2_cfi_type = b2_cfi_type; // @[core.scala:188:23, :190:18] reg [1:0] b2_pc_sel; // @[core.scala:190:18] assign brupdate_b2_pc_sel = b2_pc_sel; // @[core.scala:188:23, :190:18] reg [39:0] b2_jalr_target; // @[core.scala:190:18] assign brupdate_b2_jalr_target = b2_jalr_target; // @[core.scala:188:23, :190:18] reg [20:0] b2_target_offset; // @[core.scala:190:18] assign brupdate_b2_target_offset = b2_target_offset; // @[core.scala:188:23, :190:18] wire _brinfos_0_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37] wire _brinfos_0_valid_T_1 = _alu_exe_unit_io_brinfo_valid & _brinfos_0_valid_T; // @[execution-units.scala:119:32] wire _brinfos_1_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37] wire _brinfos_1_valid_T_1 = _alu_exe_unit_1_io_brinfo_valid & _brinfos_1_valid_T; // @[execution-units.scala:119:32] wire _brinfos_2_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37] wire _brinfos_2_valid_T_1 = _alu_exe_unit_2_io_brinfo_valid & _brinfos_2_valid_T; // @[execution-units.scala:119:32] wire [15:0] _GEN = {12'h0, brinfos_0_uop_br_tag}; // @[core.scala:182:20, :199:47] wire [15:0] _b1_resolve_mask_T = {15'h0, brinfos_0_valid} << _GEN; // @[core.scala:182:20, :199:47] wire [15:0] _GEN_0 = {12'h0, brinfos_1_uop_br_tag}; // @[core.scala:182:20, :199:47] wire [15:0] _b1_resolve_mask_T_1 = {15'h0, brinfos_1_valid} << _GEN_0; // @[core.scala:182:20, :199:47] wire [15:0] _GEN_1 = {12'h0, brinfos_2_uop_br_tag}; // @[core.scala:182:20, :199:47] wire [15:0] _b1_resolve_mask_T_2 = {15'h0, brinfos_2_valid} << _GEN_1; // @[core.scala:182:20, :199:47] wire [15:0] _b1_resolve_mask_T_3 = _b1_resolve_mask_T | _b1_resolve_mask_T_1; // @[core.scala:199:{47,72}] assign _b1_resolve_mask_T_4 = _b1_resolve_mask_T_3 | _b1_resolve_mask_T_2; // @[core.scala:199:{47,72}] assign b1_resolve_mask = _b1_resolve_mask_T_4; // @[core.scala:189:19, :199:72] wire _T_1 = brinfos_0_valid & brinfos_0_mispredict; // @[core.scala:182:20, :200:51] wire _b1_mispredict_mask_T; // @[core.scala:200:51] assign _b1_mispredict_mask_T = _T_1; // @[core.scala:200:51] wire _use_this_mispredict_T_1; // @[core.scala:207:13] assign _use_this_mispredict_T_1 = _T_1; // @[core.scala:200:51, :207:13] wire [15:0] _b1_mispredict_mask_T_1 = {15'h0, _b1_mispredict_mask_T} << _GEN; // @[core.scala:199:47, :200:{51,68}] wire _T_3 = brinfos_1_valid & brinfos_1_mispredict; // @[core.scala:182:20, :200:51] wire _b1_mispredict_mask_T_2; // @[core.scala:200:51] assign _b1_mispredict_mask_T_2 = _T_3; // @[core.scala:200:51] wire _use_this_mispredict_T_9; // @[core.scala:207:13] assign _use_this_mispredict_T_9 = _T_3; // @[core.scala:200:51, :207:13] wire [15:0] _b1_mispredict_mask_T_3 = {15'h0, _b1_mispredict_mask_T_2} << _GEN_0; // @[core.scala:199:47, :200:{51,68}] wire _T_6 = brinfos_2_valid & brinfos_2_mispredict; // @[core.scala:182:20, :200:51] wire _b1_mispredict_mask_T_4; // @[core.scala:200:51] assign _b1_mispredict_mask_T_4 = _T_6; // @[core.scala:200:51] wire _use_this_mispredict_T_17; // @[core.scala:207:13] assign _use_this_mispredict_T_17 = _T_6; // @[core.scala:200:51, :207:13] wire [15:0] _b1_mispredict_mask_T_5 = {15'h0, _b1_mispredict_mask_T_4} << _GEN_1; // @[core.scala:199:47, :200:{51,68}] wire [15:0] _b1_mispredict_mask_T_6 = _b1_mispredict_mask_T_1 | _b1_mispredict_mask_T_3; // @[core.scala:200:{68,93}] assign _b1_mispredict_mask_T_7 = _b1_mispredict_mask_T_6 | _b1_mispredict_mask_T_5; // @[core.scala:200:{68,93}] assign b1_mispredict_mask = _b1_mispredict_mask_T_7; // @[core.scala:189:19, :200:93] wire _GEN_2 = brinfos_0_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64] wire _use_this_mispredict_T_3; // @[util.scala:363:64] assign _use_this_mispredict_T_3 = _GEN_2; // @[util.scala:363:64] wire _use_this_mispredict_T_5; // @[util.scala:363:78] assign _use_this_mispredict_T_5 = _GEN_2; // @[util.scala:363:{64,78}] wire _use_this_mispredict_T_13; // @[util.scala:363:78] assign _use_this_mispredict_T_13 = _GEN_2; // @[util.scala:363:{64,78}] wire _use_this_mispredict_T_4 = _use_this_mispredict_T_3; // @[util.scala:363:{58,64}] wire _use_this_mispredict_T_6 = _use_this_mispredict_T_4 ^ _use_this_mispredict_T_5; // @[util.scala:363:{58,72,78}] wire _use_this_mispredict_T_7 = _use_this_mispredict_T_1 & _use_this_mispredict_T_6; // @[util.scala:363:72] wire _use_this_mispredict_T_8 = ~_T_1; // @[core.scala:200:51, :206:31] wire _use_this_mispredict_T_10 = brinfos_1_uop_rob_idx < brinfos_0_uop_rob_idx; // @[util.scala:363:52] wire _use_this_mispredict_T_11 = brinfos_1_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64] wire _use_this_mispredict_T_12 = _use_this_mispredict_T_10 ^ _use_this_mispredict_T_11; // @[util.scala:363:{52,58,64}] wire _use_this_mispredict_T_14 = _use_this_mispredict_T_12 ^ _use_this_mispredict_T_13; // @[util.scala:363:{58,72,78}] wire _use_this_mispredict_T_15 = _use_this_mispredict_T_9 & _use_this_mispredict_T_14; // @[util.scala:363:72] wire use_this_mispredict_1 = _use_this_mispredict_T_8 | _use_this_mispredict_T_15; // @[core.scala:206:{31,47}, :207:29] wire _T_4 = _T_1 | _T_3; // @[core.scala:200:51, :209:37] wire [6:0] _T_5_uop_rob_idx = use_this_mispredict_1 ? brinfos_1_uop_rob_idx : brinfos_0_uop_rob_idx; // @[core.scala:182:20, :206:47, :210:28] wire _use_this_mispredict_T_16 = ~_T_4; // @[core.scala:206:31, :209:37] wire _use_this_mispredict_T_18 = brinfos_2_uop_rob_idx < _T_5_uop_rob_idx; // @[util.scala:363:52] wire _use_this_mispredict_T_19 = brinfos_2_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64] wire _use_this_mispredict_T_20 = _use_this_mispredict_T_18 ^ _use_this_mispredict_T_19; // @[util.scala:363:{52,58,64}] wire _use_this_mispredict_T_21 = _T_5_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:78] wire _use_this_mispredict_T_22 = _use_this_mispredict_T_20 ^ _use_this_mispredict_T_21; // @[util.scala:363:{58,72,78}] wire _use_this_mispredict_T_23 = _use_this_mispredict_T_17 & _use_this_mispredict_T_22; // @[util.scala:363:72] wire use_this_mispredict_2 = _use_this_mispredict_T_16 | _use_this_mispredict_T_23; // @[core.scala:206:{31,47}, :207:29] wire [6:0] b2_uop_out_uopc = use_this_mispredict_2 ? brinfos_2_uop_uopc : use_this_mispredict_1 ? brinfos_1_uop_uopc : brinfos_0_uop_uopc; // @[util.scala:96:23] wire [31:0] b2_uop_out_inst = use_this_mispredict_2 ? brinfos_2_uop_inst : use_this_mispredict_1 ? brinfos_1_uop_inst : brinfos_0_uop_inst; // @[util.scala:96:23] wire [31:0] b2_uop_out_debug_inst = use_this_mispredict_2 ? brinfos_2_uop_debug_inst : use_this_mispredict_1 ? brinfos_1_uop_debug_inst : brinfos_0_uop_debug_inst; // @[util.scala:96:23] wire b2_uop_out_is_rvc = use_this_mispredict_2 ? brinfos_2_uop_is_rvc : use_this_mispredict_1 ? brinfos_1_uop_is_rvc : brinfos_0_uop_is_rvc; // @[util.scala:96:23] wire [39:0] b2_uop_out_debug_pc = use_this_mispredict_2 ? brinfos_2_uop_debug_pc : use_this_mispredict_1 ? brinfos_1_uop_debug_pc : brinfos_0_uop_debug_pc; // @[util.scala:96:23] wire [2:0] b2_uop_out_iq_type = use_this_mispredict_2 ? brinfos_2_uop_iq_type : use_this_mispredict_1 ? brinfos_1_uop_iq_type : brinfos_0_uop_iq_type; // @[util.scala:96:23] wire [9:0] b2_uop_out_fu_code = use_this_mispredict_2 ? brinfos_2_uop_fu_code : use_this_mispredict_1 ? brinfos_1_uop_fu_code : brinfos_0_uop_fu_code; // @[util.scala:96:23] wire [3:0] b2_uop_out_ctrl_br_type = use_this_mispredict_2 ? brinfos_2_uop_ctrl_br_type : use_this_mispredict_1 ? brinfos_1_uop_ctrl_br_type : brinfos_0_uop_ctrl_br_type; // @[util.scala:96:23] wire [1:0] b2_uop_out_ctrl_op1_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op1_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op1_sel : brinfos_0_uop_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] b2_uop_out_ctrl_op2_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op2_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op2_sel : brinfos_0_uop_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] b2_uop_out_ctrl_imm_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_imm_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_imm_sel : brinfos_0_uop_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] b2_uop_out_ctrl_op_fcn = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op_fcn : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op_fcn : brinfos_0_uop_ctrl_op_fcn; // @[util.scala:96:23] wire b2_uop_out_ctrl_fcn_dw = use_this_mispredict_2 ? brinfos_2_uop_ctrl_fcn_dw : use_this_mispredict_1 ? brinfos_1_uop_ctrl_fcn_dw : brinfos_0_uop_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] b2_uop_out_ctrl_csr_cmd = use_this_mispredict_2 ? brinfos_2_uop_ctrl_csr_cmd : use_this_mispredict_1 ? brinfos_1_uop_ctrl_csr_cmd : brinfos_0_uop_ctrl_csr_cmd; // @[util.scala:96:23] wire b2_uop_out_ctrl_is_load = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_load : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_load : brinfos_0_uop_ctrl_is_load; // @[util.scala:96:23] wire b2_uop_out_ctrl_is_sta = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_sta : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_sta : brinfos_0_uop_ctrl_is_sta; // @[util.scala:96:23] wire b2_uop_out_ctrl_is_std = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_std : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_std : brinfos_0_uop_ctrl_is_std; // @[util.scala:96:23] wire [1:0] b2_uop_out_iw_state = use_this_mispredict_2 ? brinfos_2_uop_iw_state : use_this_mispredict_1 ? brinfos_1_uop_iw_state : brinfos_0_uop_iw_state; // @[util.scala:96:23] wire b2_uop_out_iw_p1_poisoned = use_this_mispredict_2 ? brinfos_2_uop_iw_p1_poisoned : use_this_mispredict_1 ? brinfos_1_uop_iw_p1_poisoned : brinfos_0_uop_iw_p1_poisoned; // @[util.scala:96:23] wire b2_uop_out_iw_p2_poisoned = use_this_mispredict_2 ? brinfos_2_uop_iw_p2_poisoned : use_this_mispredict_1 ? brinfos_1_uop_iw_p2_poisoned : brinfos_0_uop_iw_p2_poisoned; // @[util.scala:96:23] wire b2_uop_out_is_br = use_this_mispredict_2 ? brinfos_2_uop_is_br : use_this_mispredict_1 ? brinfos_1_uop_is_br : brinfos_0_uop_is_br; // @[util.scala:96:23] wire b2_uop_out_is_jalr = use_this_mispredict_2 ? brinfos_2_uop_is_jalr : use_this_mispredict_1 ? brinfos_1_uop_is_jalr : brinfos_0_uop_is_jalr; // @[util.scala:96:23] wire b2_uop_out_is_jal = use_this_mispredict_2 ? brinfos_2_uop_is_jal : use_this_mispredict_1 ? brinfos_1_uop_is_jal : brinfos_0_uop_is_jal; // @[util.scala:96:23] wire b2_uop_out_is_sfb = use_this_mispredict_2 ? brinfos_2_uop_is_sfb : use_this_mispredict_1 ? brinfos_1_uop_is_sfb : brinfos_0_uop_is_sfb; // @[util.scala:96:23] wire [3:0] b2_uop_out_br_tag = use_this_mispredict_2 ? brinfos_2_uop_br_tag : use_this_mispredict_1 ? brinfos_1_uop_br_tag : brinfos_0_uop_br_tag; // @[util.scala:96:23] wire [4:0] _T_8_uop_ftq_idx = use_this_mispredict_2 ? brinfos_2_uop_ftq_idx : use_this_mispredict_1 ? brinfos_1_uop_ftq_idx : brinfos_0_uop_ftq_idx; // @[core.scala:182:20, :206:47, :210:28] assign io_ifu_get_pc_1_ftq_idx_0 = _T_8_uop_ftq_idx; // @[core.scala:51:7, :210:28] wire [4:0] b2_uop_out_ftq_idx; // @[util.scala:96:23] assign b2_uop_out_ftq_idx = _T_8_uop_ftq_idx; // @[util.scala:96:23] wire b2_uop_out_edge_inst = use_this_mispredict_2 ? brinfos_2_uop_edge_inst : use_this_mispredict_1 ? brinfos_1_uop_edge_inst : brinfos_0_uop_edge_inst; // @[util.scala:96:23] wire [5:0] b2_uop_out_pc_lob = use_this_mispredict_2 ? brinfos_2_uop_pc_lob : use_this_mispredict_1 ? brinfos_1_uop_pc_lob : brinfos_0_uop_pc_lob; // @[util.scala:96:23] wire b2_uop_out_taken = use_this_mispredict_2 ? brinfos_2_uop_taken : use_this_mispredict_1 ? brinfos_1_uop_taken : brinfos_0_uop_taken; // @[util.scala:96:23] wire [19:0] b2_uop_out_imm_packed = use_this_mispredict_2 ? brinfos_2_uop_imm_packed : use_this_mispredict_1 ? brinfos_1_uop_imm_packed : brinfos_0_uop_imm_packed; // @[util.scala:96:23] wire [11:0] b2_uop_out_csr_addr = use_this_mispredict_2 ? brinfos_2_uop_csr_addr : use_this_mispredict_1 ? brinfos_1_uop_csr_addr : brinfos_0_uop_csr_addr; // @[util.scala:96:23] wire [6:0] b2_uop_out_rob_idx = use_this_mispredict_2 ? brinfos_2_uop_rob_idx : _T_5_uop_rob_idx; // @[util.scala:96:23] wire [4:0] b2_uop_out_ldq_idx = use_this_mispredict_2 ? brinfos_2_uop_ldq_idx : use_this_mispredict_1 ? brinfos_1_uop_ldq_idx : brinfos_0_uop_ldq_idx; // @[util.scala:96:23] wire [4:0] b2_uop_out_stq_idx = use_this_mispredict_2 ? brinfos_2_uop_stq_idx : use_this_mispredict_1 ? brinfos_1_uop_stq_idx : brinfos_0_uop_stq_idx; // @[util.scala:96:23] wire [1:0] b2_uop_out_rxq_idx = use_this_mispredict_2 ? brinfos_2_uop_rxq_idx : use_this_mispredict_1 ? brinfos_1_uop_rxq_idx : brinfos_0_uop_rxq_idx; // @[util.scala:96:23] wire [6:0] b2_uop_out_pdst = use_this_mispredict_2 ? brinfos_2_uop_pdst : use_this_mispredict_1 ? brinfos_1_uop_pdst : brinfos_0_uop_pdst; // @[util.scala:96:23] wire [6:0] b2_uop_out_prs1 = use_this_mispredict_2 ? brinfos_2_uop_prs1 : use_this_mispredict_1 ? brinfos_1_uop_prs1 : brinfos_0_uop_prs1; // @[util.scala:96:23] wire [6:0] b2_uop_out_prs2 = use_this_mispredict_2 ? brinfos_2_uop_prs2 : use_this_mispredict_1 ? brinfos_1_uop_prs2 : brinfos_0_uop_prs2; // @[util.scala:96:23] wire [6:0] b2_uop_out_prs3 = use_this_mispredict_2 ? brinfos_2_uop_prs3 : use_this_mispredict_1 ? brinfos_1_uop_prs3 : brinfos_0_uop_prs3; // @[util.scala:96:23] wire [4:0] b2_uop_out_ppred = use_this_mispredict_2 ? brinfos_2_uop_ppred : use_this_mispredict_1 ? brinfos_1_uop_ppred : brinfos_0_uop_ppred; // @[util.scala:96:23] wire b2_uop_out_prs1_busy = use_this_mispredict_2 ? brinfos_2_uop_prs1_busy : use_this_mispredict_1 ? brinfos_1_uop_prs1_busy : brinfos_0_uop_prs1_busy; // @[util.scala:96:23] wire b2_uop_out_prs2_busy = use_this_mispredict_2 ? brinfos_2_uop_prs2_busy : use_this_mispredict_1 ? brinfos_1_uop_prs2_busy : brinfos_0_uop_prs2_busy; // @[util.scala:96:23] wire b2_uop_out_prs3_busy = use_this_mispredict_2 ? brinfos_2_uop_prs3_busy : use_this_mispredict_1 ? brinfos_1_uop_prs3_busy : brinfos_0_uop_prs3_busy; // @[util.scala:96:23] wire b2_uop_out_ppred_busy = use_this_mispredict_2 ? brinfos_2_uop_ppred_busy : use_this_mispredict_1 ? brinfos_1_uop_ppred_busy : brinfos_0_uop_ppred_busy; // @[util.scala:96:23] wire [6:0] b2_uop_out_stale_pdst = use_this_mispredict_2 ? brinfos_2_uop_stale_pdst : use_this_mispredict_1 ? brinfos_1_uop_stale_pdst : brinfos_0_uop_stale_pdst; // @[util.scala:96:23] wire b2_uop_out_exception = use_this_mispredict_2 ? brinfos_2_uop_exception : use_this_mispredict_1 ? brinfos_1_uop_exception : brinfos_0_uop_exception; // @[util.scala:96:23] wire [63:0] b2_uop_out_exc_cause = use_this_mispredict_2 ? brinfos_2_uop_exc_cause : use_this_mispredict_1 ? brinfos_1_uop_exc_cause : brinfos_0_uop_exc_cause; // @[util.scala:96:23] wire b2_uop_out_bypassable = use_this_mispredict_2 ? brinfos_2_uop_bypassable : use_this_mispredict_1 ? brinfos_1_uop_bypassable : brinfos_0_uop_bypassable; // @[util.scala:96:23] wire [4:0] b2_uop_out_mem_cmd = use_this_mispredict_2 ? brinfos_2_uop_mem_cmd : use_this_mispredict_1 ? brinfos_1_uop_mem_cmd : brinfos_0_uop_mem_cmd; // @[util.scala:96:23] wire [1:0] b2_uop_out_mem_size = use_this_mispredict_2 ? brinfos_2_uop_mem_size : use_this_mispredict_1 ? brinfos_1_uop_mem_size : brinfos_0_uop_mem_size; // @[util.scala:96:23] wire b2_uop_out_mem_signed = use_this_mispredict_2 ? brinfos_2_uop_mem_signed : use_this_mispredict_1 ? brinfos_1_uop_mem_signed : brinfos_0_uop_mem_signed; // @[util.scala:96:23] wire b2_uop_out_is_fence = use_this_mispredict_2 ? brinfos_2_uop_is_fence : use_this_mispredict_1 ? brinfos_1_uop_is_fence : brinfos_0_uop_is_fence; // @[util.scala:96:23] wire b2_uop_out_is_fencei = use_this_mispredict_2 ? brinfos_2_uop_is_fencei : use_this_mispredict_1 ? brinfos_1_uop_is_fencei : brinfos_0_uop_is_fencei; // @[util.scala:96:23] wire b2_uop_out_is_amo = use_this_mispredict_2 ? brinfos_2_uop_is_amo : use_this_mispredict_1 ? brinfos_1_uop_is_amo : brinfos_0_uop_is_amo; // @[util.scala:96:23] wire b2_uop_out_uses_ldq = use_this_mispredict_2 ? brinfos_2_uop_uses_ldq : use_this_mispredict_1 ? brinfos_1_uop_uses_ldq : brinfos_0_uop_uses_ldq; // @[util.scala:96:23] wire b2_uop_out_uses_stq = use_this_mispredict_2 ? brinfos_2_uop_uses_stq : use_this_mispredict_1 ? brinfos_1_uop_uses_stq : brinfos_0_uop_uses_stq; // @[util.scala:96:23] wire b2_uop_out_is_sys_pc2epc = use_this_mispredict_2 ? brinfos_2_uop_is_sys_pc2epc : use_this_mispredict_1 ? brinfos_1_uop_is_sys_pc2epc : brinfos_0_uop_is_sys_pc2epc; // @[util.scala:96:23] wire b2_uop_out_is_unique = use_this_mispredict_2 ? brinfos_2_uop_is_unique : use_this_mispredict_1 ? brinfos_1_uop_is_unique : brinfos_0_uop_is_unique; // @[util.scala:96:23] wire b2_uop_out_flush_on_commit = use_this_mispredict_2 ? brinfos_2_uop_flush_on_commit : use_this_mispredict_1 ? brinfos_1_uop_flush_on_commit : brinfos_0_uop_flush_on_commit; // @[util.scala:96:23] wire b2_uop_out_ldst_is_rs1 = use_this_mispredict_2 ? brinfos_2_uop_ldst_is_rs1 : use_this_mispredict_1 ? brinfos_1_uop_ldst_is_rs1 : brinfos_0_uop_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] b2_uop_out_ldst = use_this_mispredict_2 ? brinfos_2_uop_ldst : use_this_mispredict_1 ? brinfos_1_uop_ldst : brinfos_0_uop_ldst; // @[util.scala:96:23] wire [5:0] b2_uop_out_lrs1 = use_this_mispredict_2 ? brinfos_2_uop_lrs1 : use_this_mispredict_1 ? brinfos_1_uop_lrs1 : brinfos_0_uop_lrs1; // @[util.scala:96:23] wire [5:0] b2_uop_out_lrs2 = use_this_mispredict_2 ? brinfos_2_uop_lrs2 : use_this_mispredict_1 ? brinfos_1_uop_lrs2 : brinfos_0_uop_lrs2; // @[util.scala:96:23] wire [5:0] b2_uop_out_lrs3 = use_this_mispredict_2 ? brinfos_2_uop_lrs3 : use_this_mispredict_1 ? brinfos_1_uop_lrs3 : brinfos_0_uop_lrs3; // @[util.scala:96:23] wire b2_uop_out_ldst_val = use_this_mispredict_2 ? brinfos_2_uop_ldst_val : use_this_mispredict_1 ? brinfos_1_uop_ldst_val : brinfos_0_uop_ldst_val; // @[util.scala:96:23] wire [1:0] b2_uop_out_dst_rtype = use_this_mispredict_2 ? brinfos_2_uop_dst_rtype : use_this_mispredict_1 ? brinfos_1_uop_dst_rtype : brinfos_0_uop_dst_rtype; // @[util.scala:96:23] wire [1:0] b2_uop_out_lrs1_rtype = use_this_mispredict_2 ? brinfos_2_uop_lrs1_rtype : use_this_mispredict_1 ? brinfos_1_uop_lrs1_rtype : brinfos_0_uop_lrs1_rtype; // @[util.scala:96:23] wire [1:0] b2_uop_out_lrs2_rtype = use_this_mispredict_2 ? brinfos_2_uop_lrs2_rtype : use_this_mispredict_1 ? brinfos_1_uop_lrs2_rtype : brinfos_0_uop_lrs2_rtype; // @[util.scala:96:23] wire b2_uop_out_frs3_en = use_this_mispredict_2 ? brinfos_2_uop_frs3_en : use_this_mispredict_1 ? brinfos_1_uop_frs3_en : brinfos_0_uop_frs3_en; // @[util.scala:96:23] wire b2_uop_out_fp_val = use_this_mispredict_2 ? brinfos_2_uop_fp_val : use_this_mispredict_1 ? brinfos_1_uop_fp_val : brinfos_0_uop_fp_val; // @[util.scala:96:23] wire b2_uop_out_fp_single = use_this_mispredict_2 ? brinfos_2_uop_fp_single : use_this_mispredict_1 ? brinfos_1_uop_fp_single : brinfos_0_uop_fp_single; // @[util.scala:96:23] wire b2_uop_out_xcpt_pf_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_pf_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_pf_if : brinfos_0_uop_xcpt_pf_if; // @[util.scala:96:23] wire b2_uop_out_xcpt_ae_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_ae_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_ae_if : brinfos_0_uop_xcpt_ae_if; // @[util.scala:96:23] wire b2_uop_out_xcpt_ma_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_ma_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_ma_if : brinfos_0_uop_xcpt_ma_if; // @[util.scala:96:23] wire b2_uop_out_bp_debug_if = use_this_mispredict_2 ? brinfos_2_uop_bp_debug_if : use_this_mispredict_1 ? brinfos_1_uop_bp_debug_if : brinfos_0_uop_bp_debug_if; // @[util.scala:96:23] wire b2_uop_out_bp_xcpt_if = use_this_mispredict_2 ? brinfos_2_uop_bp_xcpt_if : use_this_mispredict_1 ? brinfos_1_uop_bp_xcpt_if : brinfos_0_uop_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] b2_uop_out_debug_fsrc = use_this_mispredict_2 ? brinfos_2_uop_debug_fsrc : use_this_mispredict_1 ? brinfos_1_uop_debug_fsrc : brinfos_0_uop_debug_fsrc; // @[util.scala:96:23] wire [1:0] b2_uop_out_debug_tsrc = use_this_mispredict_2 ? brinfos_2_uop_debug_tsrc : use_this_mispredict_1 ? brinfos_1_uop_debug_tsrc : brinfos_0_uop_debug_tsrc; // @[util.scala:96:23] wire [15:0] _b2_uop_out_br_mask_T_1; // @[util.scala:85:25] wire [15:0] b2_uop_out_br_mask; // @[util.scala:96:23] wire [15:0] _b2_uop_out_br_mask_T = ~brupdate_b1_resolve_mask; // @[util.scala:85:27] assign _b2_uop_out_br_mask_T_1 = (use_this_mispredict_2 ? brinfos_2_uop_br_mask : use_this_mispredict_1 ? brinfos_1_uop_br_mask : brinfos_0_uop_br_mask) & _b2_uop_out_br_mask_T; // @[util.scala:85:{25,27}] assign b2_uop_out_br_mask = _b2_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [39:0] b2_jalr_target_REG; // @[core.scala:218:28] wire custom_csrs_csrs_0_ren; // @[core.scala:276:25] wire custom_csrs_csrs_0_wen; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_0_wdata; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_0_value; // @[core.scala:276:25] wire custom_csrs_csrs_1_ren; // @[core.scala:276:25] wire custom_csrs_csrs_1_wen; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_1_wdata; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_1_value; // @[core.scala:276:25] reg [63:0] debug_tsc_reg; // @[core.scala:288:30] assign io_lsu_tsc_reg_0 = debug_tsc_reg; // @[core.scala:51:7, :288:30] reg [63:0] debug_irt_reg; // @[core.scala:289:30] reg [63:0] debug_brs_0; // @[core.scala:290:26] reg [63:0] debug_brs_1; // @[core.scala:290:26] reg [63:0] debug_brs_2; // @[core.scala:290:26] reg [63:0] debug_brs_3; // @[core.scala:290:26] reg [63:0] debug_jals_0; // @[core.scala:291:26] reg [63:0] debug_jals_1; // @[core.scala:291:26] reg [63:0] debug_jals_2; // @[core.scala:291:26] reg [63:0] debug_jals_3; // @[core.scala:291:26] reg [63:0] debug_jalrs_0; // @[core.scala:292:26] reg [63:0] debug_jalrs_1; // @[core.scala:292:26] reg [63:0] debug_jalrs_2; // @[core.scala:292:26] reg [63:0] debug_jalrs_3; // @[core.scala:292:26] wire _GEN_3 = _rob_io_commit_uops_0_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41] wire _debug_brs_0_T; // @[core.scala:297:41] assign _debug_brs_0_T = _GEN_3; // @[core.scala:297:41] wire _debug_jals_0_T; // @[core.scala:302:41] assign _debug_jals_0_T = _GEN_3; // @[core.scala:297:41, :302:41] wire _debug_jalrs_0_T; // @[core.scala:307:41] assign _debug_jalrs_0_T = _GEN_3; // @[core.scala:297:41, :307:41] wire _debug_brs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_0_T; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_0_T_2 = _debug_brs_0_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_0_WIRE_0 = _debug_brs_0_T_2; // @[core.scala:295:52, :297:50] wire _GEN_4 = _rob_io_commit_uops_1_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41] wire _debug_brs_0_T_3; // @[core.scala:297:41] assign _debug_brs_0_T_3 = _GEN_4; // @[core.scala:297:41] wire _debug_jals_0_T_3; // @[core.scala:302:41] assign _debug_jals_0_T_3 = _GEN_4; // @[core.scala:297:41, :302:41] wire _debug_jalrs_0_T_3; // @[core.scala:307:41] assign _debug_jalrs_0_T_3 = _GEN_4; // @[core.scala:297:41, :307:41] wire _debug_brs_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_0_T_3; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_0_T_5 = _debug_brs_0_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_0_WIRE_1 = _debug_brs_0_T_5; // @[core.scala:295:52, :297:50] wire _GEN_5 = _rob_io_commit_uops_2_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41] wire _debug_brs_0_T_6; // @[core.scala:297:41] assign _debug_brs_0_T_6 = _GEN_5; // @[core.scala:297:41] wire _debug_jals_0_T_6; // @[core.scala:302:41] assign _debug_jals_0_T_6 = _GEN_5; // @[core.scala:297:41, :302:41] wire _debug_jalrs_0_T_6; // @[core.scala:307:41] assign _debug_jalrs_0_T_6 = _GEN_5; // @[core.scala:297:41, :307:41] wire _debug_brs_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_0_T_6; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_0_T_8 = _debug_brs_0_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_0_WIRE_2 = _debug_brs_0_T_8; // @[core.scala:295:52, :297:50] wire [1:0] _debug_brs_0_T_9 = {1'h0, _debug_brs_0_WIRE_1} + {1'h0, _debug_brs_0_WIRE_2}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_0_T_10 = _debug_brs_0_T_9; // @[core.scala:295:44] wire [2:0] _debug_brs_0_T_11 = {2'h0, _debug_brs_0_WIRE_0} + {1'h0, _debug_brs_0_T_10}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_0_T_12 = _debug_brs_0_T_11[1:0]; // @[core.scala:295:44] wire [64:0] _debug_brs_0_T_13 = {1'h0, debug_brs_0} + {63'h0, _debug_brs_0_T_12}; // @[core.scala:290:26, :295:{34,44}] wire [63:0] _debug_brs_0_T_14 = _debug_brs_0_T_13[63:0]; // @[core.scala:295:34] wire _debug_jals_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_0_T; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_0_T_2 = _debug_jals_0_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_0_WIRE_0 = _debug_jals_0_T_2; // @[core.scala:300:54, :302:50] wire _debug_jals_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_0_T_3; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_0_T_5 = _debug_jals_0_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_0_WIRE_1 = _debug_jals_0_T_5; // @[core.scala:300:54, :302:50] wire _debug_jals_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_0_T_6; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_0_T_8 = _debug_jals_0_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_0_WIRE_2 = _debug_jals_0_T_8; // @[core.scala:300:54, :302:50] wire [1:0] _debug_jals_0_T_9 = {1'h0, _debug_jals_0_WIRE_1} + {1'h0, _debug_jals_0_WIRE_2}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_0_T_10 = _debug_jals_0_T_9; // @[core.scala:300:46] wire [2:0] _debug_jals_0_T_11 = {2'h0, _debug_jals_0_WIRE_0} + {1'h0, _debug_jals_0_T_10}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_0_T_12 = _debug_jals_0_T_11[1:0]; // @[core.scala:300:46] wire [64:0] _debug_jals_0_T_13 = {1'h0, debug_jals_0} + {63'h0, _debug_jals_0_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}] wire [63:0] _debug_jals_0_T_14 = _debug_jals_0_T_13[63:0]; // @[core.scala:300:36] wire _debug_jalrs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_0_T; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_0_T_2 = _debug_jalrs_0_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_0_WIRE_0 = _debug_jalrs_0_T_2; // @[core.scala:305:56, :307:50] wire _debug_jalrs_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_0_T_3; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_0_T_5 = _debug_jalrs_0_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_0_WIRE_1 = _debug_jalrs_0_T_5; // @[core.scala:305:56, :307:50] wire _debug_jalrs_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_0_T_6; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_0_T_8 = _debug_jalrs_0_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_0_WIRE_2 = _debug_jalrs_0_T_8; // @[core.scala:305:56, :307:50] wire [1:0] _debug_jalrs_0_T_9 = {1'h0, _debug_jalrs_0_WIRE_1} + {1'h0, _debug_jalrs_0_WIRE_2}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_0_T_10 = _debug_jalrs_0_T_9; // @[core.scala:305:48] wire [2:0] _debug_jalrs_0_T_11 = {2'h0, _debug_jalrs_0_WIRE_0} + {1'h0, _debug_jalrs_0_T_10}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_0_T_12 = _debug_jalrs_0_T_11[1:0]; // @[core.scala:305:48] wire [64:0] _debug_jalrs_0_T_13 = {1'h0, debug_jalrs_0} + {63'h0, _debug_jalrs_0_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}] wire [63:0] _debug_jalrs_0_T_14 = _debug_jalrs_0_T_13[63:0]; // @[core.scala:305:38] wire _GEN_6 = _rob_io_commit_uops_0_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41] wire _debug_brs_1_T; // @[core.scala:297:41] assign _debug_brs_1_T = _GEN_6; // @[core.scala:297:41] wire _debug_jals_1_T; // @[core.scala:302:41] assign _debug_jals_1_T = _GEN_6; // @[core.scala:297:41, :302:41] wire _debug_jalrs_1_T; // @[core.scala:307:41] assign _debug_jalrs_1_T = _GEN_6; // @[core.scala:297:41, :307:41] wire _debug_brs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_1_T; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_1_T_2 = _debug_brs_1_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_1_WIRE_0 = _debug_brs_1_T_2; // @[core.scala:295:52, :297:50] wire _GEN_7 = _rob_io_commit_uops_1_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41] wire _debug_brs_1_T_3; // @[core.scala:297:41] assign _debug_brs_1_T_3 = _GEN_7; // @[core.scala:297:41] wire _debug_jals_1_T_3; // @[core.scala:302:41] assign _debug_jals_1_T_3 = _GEN_7; // @[core.scala:297:41, :302:41] wire _debug_jalrs_1_T_3; // @[core.scala:307:41] assign _debug_jalrs_1_T_3 = _GEN_7; // @[core.scala:297:41, :307:41] wire _debug_brs_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_1_T_3; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_1_T_5 = _debug_brs_1_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_1_WIRE_1 = _debug_brs_1_T_5; // @[core.scala:295:52, :297:50] wire _GEN_8 = _rob_io_commit_uops_2_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41] wire _debug_brs_1_T_6; // @[core.scala:297:41] assign _debug_brs_1_T_6 = _GEN_8; // @[core.scala:297:41] wire _debug_jals_1_T_6; // @[core.scala:302:41] assign _debug_jals_1_T_6 = _GEN_8; // @[core.scala:297:41, :302:41] wire _debug_jalrs_1_T_6; // @[core.scala:307:41] assign _debug_jalrs_1_T_6 = _GEN_8; // @[core.scala:297:41, :307:41] wire _debug_brs_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_1_T_6; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_1_T_8 = _debug_brs_1_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_1_WIRE_2 = _debug_brs_1_T_8; // @[core.scala:295:52, :297:50] wire [1:0] _debug_brs_1_T_9 = {1'h0, _debug_brs_1_WIRE_1} + {1'h0, _debug_brs_1_WIRE_2}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_1_T_10 = _debug_brs_1_T_9; // @[core.scala:295:44] wire [2:0] _debug_brs_1_T_11 = {2'h0, _debug_brs_1_WIRE_0} + {1'h0, _debug_brs_1_T_10}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_1_T_12 = _debug_brs_1_T_11[1:0]; // @[core.scala:295:44] wire [64:0] _debug_brs_1_T_13 = {1'h0, debug_brs_1} + {63'h0, _debug_brs_1_T_12}; // @[core.scala:290:26, :295:{34,44}] wire [63:0] _debug_brs_1_T_14 = _debug_brs_1_T_13[63:0]; // @[core.scala:295:34] wire _debug_jals_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_1_T; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_1_T_2 = _debug_jals_1_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_1_WIRE_0 = _debug_jals_1_T_2; // @[core.scala:300:54, :302:50] wire _debug_jals_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_1_T_3; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_1_T_5 = _debug_jals_1_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_1_WIRE_1 = _debug_jals_1_T_5; // @[core.scala:300:54, :302:50] wire _debug_jals_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_1_T_6; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_1_T_8 = _debug_jals_1_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_1_WIRE_2 = _debug_jals_1_T_8; // @[core.scala:300:54, :302:50] wire [1:0] _debug_jals_1_T_9 = {1'h0, _debug_jals_1_WIRE_1} + {1'h0, _debug_jals_1_WIRE_2}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_1_T_10 = _debug_jals_1_T_9; // @[core.scala:300:46] wire [2:0] _debug_jals_1_T_11 = {2'h0, _debug_jals_1_WIRE_0} + {1'h0, _debug_jals_1_T_10}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_1_T_12 = _debug_jals_1_T_11[1:0]; // @[core.scala:300:46] wire [64:0] _debug_jals_1_T_13 = {1'h0, debug_jals_1} + {63'h0, _debug_jals_1_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}] wire [63:0] _debug_jals_1_T_14 = _debug_jals_1_T_13[63:0]; // @[core.scala:300:36] wire _debug_jalrs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_1_T; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_1_T_2 = _debug_jalrs_1_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_1_WIRE_0 = _debug_jalrs_1_T_2; // @[core.scala:305:56, :307:50] wire _debug_jalrs_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_1_T_3; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_1_T_5 = _debug_jalrs_1_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_1_WIRE_1 = _debug_jalrs_1_T_5; // @[core.scala:305:56, :307:50] wire _debug_jalrs_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_1_T_6; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_1_T_8 = _debug_jalrs_1_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_1_WIRE_2 = _debug_jalrs_1_T_8; // @[core.scala:305:56, :307:50] wire [1:0] _debug_jalrs_1_T_9 = {1'h0, _debug_jalrs_1_WIRE_1} + {1'h0, _debug_jalrs_1_WIRE_2}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_1_T_10 = _debug_jalrs_1_T_9; // @[core.scala:305:48] wire [2:0] _debug_jalrs_1_T_11 = {2'h0, _debug_jalrs_1_WIRE_0} + {1'h0, _debug_jalrs_1_T_10}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_1_T_12 = _debug_jalrs_1_T_11[1:0]; // @[core.scala:305:48] wire [64:0] _debug_jalrs_1_T_13 = {1'h0, debug_jalrs_1} + {63'h0, _debug_jalrs_1_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}] wire [63:0] _debug_jalrs_1_T_14 = _debug_jalrs_1_T_13[63:0]; // @[core.scala:305:38] wire _GEN_9 = _rob_io_commit_uops_0_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41] wire _debug_brs_2_T; // @[core.scala:297:41] assign _debug_brs_2_T = _GEN_9; // @[core.scala:297:41] wire _debug_jals_2_T; // @[core.scala:302:41] assign _debug_jals_2_T = _GEN_9; // @[core.scala:297:41, :302:41] wire _debug_jalrs_2_T; // @[core.scala:307:41] assign _debug_jalrs_2_T = _GEN_9; // @[core.scala:297:41, :307:41] wire _debug_brs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_2_T; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_2_T_2 = _debug_brs_2_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_2_WIRE_0 = _debug_brs_2_T_2; // @[core.scala:295:52, :297:50] wire _GEN_10 = _rob_io_commit_uops_1_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41] wire _debug_brs_2_T_3; // @[core.scala:297:41] assign _debug_brs_2_T_3 = _GEN_10; // @[core.scala:297:41] wire _debug_jals_2_T_3; // @[core.scala:302:41] assign _debug_jals_2_T_3 = _GEN_10; // @[core.scala:297:41, :302:41] wire _debug_jalrs_2_T_3; // @[core.scala:307:41] assign _debug_jalrs_2_T_3 = _GEN_10; // @[core.scala:297:41, :307:41] wire _debug_brs_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_2_T_3; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_2_T_5 = _debug_brs_2_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_2_WIRE_1 = _debug_brs_2_T_5; // @[core.scala:295:52, :297:50] wire _GEN_11 = _rob_io_commit_uops_2_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41] wire _debug_brs_2_T_6; // @[core.scala:297:41] assign _debug_brs_2_T_6 = _GEN_11; // @[core.scala:297:41] wire _debug_jals_2_T_6; // @[core.scala:302:41] assign _debug_jals_2_T_6 = _GEN_11; // @[core.scala:297:41, :302:41] wire _debug_jalrs_2_T_6; // @[core.scala:307:41] assign _debug_jalrs_2_T_6 = _GEN_11; // @[core.scala:297:41, :307:41] wire _debug_brs_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_2_T_6; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_2_T_8 = _debug_brs_2_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_2_WIRE_2 = _debug_brs_2_T_8; // @[core.scala:295:52, :297:50] wire [1:0] _debug_brs_2_T_9 = {1'h0, _debug_brs_2_WIRE_1} + {1'h0, _debug_brs_2_WIRE_2}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_2_T_10 = _debug_brs_2_T_9; // @[core.scala:295:44] wire [2:0] _debug_brs_2_T_11 = {2'h0, _debug_brs_2_WIRE_0} + {1'h0, _debug_brs_2_T_10}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_2_T_12 = _debug_brs_2_T_11[1:0]; // @[core.scala:295:44] wire [64:0] _debug_brs_2_T_13 = {1'h0, debug_brs_2} + {63'h0, _debug_brs_2_T_12}; // @[core.scala:290:26, :295:{34,44}] wire [63:0] _debug_brs_2_T_14 = _debug_brs_2_T_13[63:0]; // @[core.scala:295:34] wire _debug_jals_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_2_T; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_2_T_2 = _debug_jals_2_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_2_WIRE_0 = _debug_jals_2_T_2; // @[core.scala:300:54, :302:50] wire _debug_jals_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_2_T_3; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_2_T_5 = _debug_jals_2_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_2_WIRE_1 = _debug_jals_2_T_5; // @[core.scala:300:54, :302:50] wire _debug_jals_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_2_T_6; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_2_T_8 = _debug_jals_2_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_2_WIRE_2 = _debug_jals_2_T_8; // @[core.scala:300:54, :302:50] wire [1:0] _debug_jals_2_T_9 = {1'h0, _debug_jals_2_WIRE_1} + {1'h0, _debug_jals_2_WIRE_2}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_2_T_10 = _debug_jals_2_T_9; // @[core.scala:300:46] wire [2:0] _debug_jals_2_T_11 = {2'h0, _debug_jals_2_WIRE_0} + {1'h0, _debug_jals_2_T_10}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_2_T_12 = _debug_jals_2_T_11[1:0]; // @[core.scala:300:46] wire [64:0] _debug_jals_2_T_13 = {1'h0, debug_jals_2} + {63'h0, _debug_jals_2_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}] wire [63:0] _debug_jals_2_T_14 = _debug_jals_2_T_13[63:0]; // @[core.scala:300:36] wire _debug_jalrs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_2_T; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_2_T_2 = _debug_jalrs_2_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_2_WIRE_0 = _debug_jalrs_2_T_2; // @[core.scala:305:56, :307:50] wire _debug_jalrs_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_2_T_3; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_2_T_5 = _debug_jalrs_2_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_2_WIRE_1 = _debug_jalrs_2_T_5; // @[core.scala:305:56, :307:50] wire _debug_jalrs_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_2_T_6; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_2_T_8 = _debug_jalrs_2_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_2_WIRE_2 = _debug_jalrs_2_T_8; // @[core.scala:305:56, :307:50] wire [1:0] _debug_jalrs_2_T_9 = {1'h0, _debug_jalrs_2_WIRE_1} + {1'h0, _debug_jalrs_2_WIRE_2}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_2_T_10 = _debug_jalrs_2_T_9; // @[core.scala:305:48] wire [2:0] _debug_jalrs_2_T_11 = {2'h0, _debug_jalrs_2_WIRE_0} + {1'h0, _debug_jalrs_2_T_10}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_2_T_12 = _debug_jalrs_2_T_11[1:0]; // @[core.scala:305:48] wire [64:0] _debug_jalrs_2_T_13 = {1'h0, debug_jalrs_2} + {63'h0, _debug_jalrs_2_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}] wire [63:0] _debug_jalrs_2_T_14 = _debug_jalrs_2_T_13[63:0]; // @[core.scala:305:38] wire _debug_brs_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41] wire _debug_brs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_3_T; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_3_T_2 = _debug_brs_3_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_3_WIRE_0 = _debug_brs_3_T_2; // @[core.scala:295:52, :297:50] wire _debug_brs_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41] wire _debug_brs_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_3_T_3; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_3_T_5 = _debug_brs_3_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_3_WIRE_1 = _debug_brs_3_T_5; // @[core.scala:295:52, :297:50] wire _debug_brs_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41] wire _debug_brs_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_3_T_6; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_3_T_8 = _debug_brs_3_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_3_WIRE_2 = _debug_brs_3_T_8; // @[core.scala:295:52, :297:50] wire [1:0] _debug_brs_3_T_9 = {1'h0, _debug_brs_3_WIRE_1} + {1'h0, _debug_brs_3_WIRE_2}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_3_T_10 = _debug_brs_3_T_9; // @[core.scala:295:44] wire [2:0] _debug_brs_3_T_11 = {2'h0, _debug_brs_3_WIRE_0} + {1'h0, _debug_brs_3_T_10}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_3_T_12 = _debug_brs_3_T_11[1:0]; // @[core.scala:295:44] wire [64:0] _debug_brs_3_T_13 = {1'h0, debug_brs_3} + {63'h0, _debug_brs_3_T_12}; // @[core.scala:290:26, :295:{34,44}] wire [63:0] _debug_brs_3_T_14 = _debug_brs_3_T_13[63:0]; // @[core.scala:295:34] wire _debug_jals_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41] wire _debug_jals_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_3_T; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_3_T_2 = _debug_jals_3_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_3_WIRE_0 = _debug_jals_3_T_2; // @[core.scala:300:54, :302:50] wire _debug_jals_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41] wire _debug_jals_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_3_T_3; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_3_T_5 = _debug_jals_3_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_3_WIRE_1 = _debug_jals_3_T_5; // @[core.scala:300:54, :302:50] wire _debug_jals_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41] wire _debug_jals_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_3_T_6; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_3_T_8 = _debug_jals_3_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_3_WIRE_2 = _debug_jals_3_T_8; // @[core.scala:300:54, :302:50] wire [1:0] _debug_jals_3_T_9 = {1'h0, _debug_jals_3_WIRE_1} + {1'h0, _debug_jals_3_WIRE_2}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_3_T_10 = _debug_jals_3_T_9; // @[core.scala:300:46] wire [2:0] _debug_jals_3_T_11 = {2'h0, _debug_jals_3_WIRE_0} + {1'h0, _debug_jals_3_T_10}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_3_T_12 = _debug_jals_3_T_11[1:0]; // @[core.scala:300:46] wire [64:0] _debug_jals_3_T_13 = {1'h0, debug_jals_3} + {63'h0, _debug_jals_3_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}] wire [63:0] _debug_jals_3_T_14 = _debug_jals_3_T_13[63:0]; // @[core.scala:300:36] wire _debug_jalrs_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41] wire _debug_jalrs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_3_T; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_3_T_2 = _debug_jalrs_3_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_3_WIRE_0 = _debug_jalrs_3_T_2; // @[core.scala:305:56, :307:50] wire _debug_jalrs_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41] wire _debug_jalrs_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_3_T_3; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_3_T_5 = _debug_jalrs_3_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_3_WIRE_1 = _debug_jalrs_3_T_5; // @[core.scala:305:56, :307:50] wire _debug_jalrs_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41] wire _debug_jalrs_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_3_T_6; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_3_T_8 = _debug_jalrs_3_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_3_WIRE_2 = _debug_jalrs_3_T_8; // @[core.scala:305:56, :307:50] wire [1:0] _debug_jalrs_3_T_9 = {1'h0, _debug_jalrs_3_WIRE_1} + {1'h0, _debug_jalrs_3_WIRE_2}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_3_T_10 = _debug_jalrs_3_T_9; // @[core.scala:305:48] wire [2:0] _debug_jalrs_3_T_11 = {2'h0, _debug_jalrs_3_WIRE_0} + {1'h0, _debug_jalrs_3_T_10}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_3_T_12 = _debug_jalrs_3_T_11[1:0]; // @[core.scala:305:48] wire [64:0] _debug_jalrs_3_T_13 = {1'h0, debug_jalrs_3} + {63'h0, _debug_jalrs_3_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}] wire [63:0] _debug_jalrs_3_T_14 = _debug_jalrs_3_T_13[63:0]; // @[core.scala:305:38] wire [64:0] _debug_tsc_reg_T = {1'h0, debug_tsc_reg} + 65'h1; // @[core.scala:288:30, :316:34] wire [63:0] _debug_tsc_reg_T_1 = _debug_tsc_reg_T[63:0]; // @[core.scala:316:34] wire [1:0] _GEN_12 = {_rob_io_commit_arch_valids_2, _rob_io_commit_arch_valids_1}; // @[core.scala:143:32, :317:71] wire [1:0] debug_irt_reg_hi; // @[core.scala:317:71] assign debug_irt_reg_hi = _GEN_12; // @[core.scala:317:71] wire [1:0] csr_io_retire_hi; // @[core.scala:1015:66] assign csr_io_retire_hi = _GEN_12; // @[core.scala:317:71, :1015:66] wire [2:0] _debug_irt_reg_T = {debug_irt_reg_hi, _rob_io_commit_arch_valids_0}; // @[core.scala:143:32, :317:71] wire _debug_irt_reg_T_1 = _debug_irt_reg_T[0]; // @[core.scala:317:{44,71}] wire _debug_irt_reg_T_2 = _debug_irt_reg_T[1]; // @[core.scala:317:{44,71}] wire _debug_irt_reg_T_3 = _debug_irt_reg_T[2]; // @[core.scala:317:{44,71}] wire [1:0] _debug_irt_reg_T_4 = {1'h0, _debug_irt_reg_T_2} + {1'h0, _debug_irt_reg_T_3}; // @[core.scala:317:44] wire [1:0] _debug_irt_reg_T_5 = _debug_irt_reg_T_4; // @[core.scala:317:44] wire [2:0] _debug_irt_reg_T_6 = {2'h0, _debug_irt_reg_T_1} + {1'h0, _debug_irt_reg_T_5}; // @[core.scala:317:44] wire [1:0] _debug_irt_reg_T_7 = _debug_irt_reg_T_6[1:0]; // @[core.scala:317:44] wire [64:0] _debug_irt_reg_T_8 = {1'h0, debug_irt_reg} + {63'h0, _debug_irt_reg_T_7}; // @[core.scala:289:30, :295:34, :317:{34,44}] wire [63:0] _debug_irt_reg_T_9 = _debug_irt_reg_T_8[63:0]; // @[core.scala:317:34] wire _io_ifu_flush_icache_T = _rob_io_commit_arch_valids_0 & _rob_io_commit_uops_0_is_fencei; // @[core.scala:143:32, :388:35] wire _io_ifu_flush_icache_T_1 = dec_valids_0 & dec_uops_0_is_jalr; // @[core.scala:157:24, :158:24, :389:28] wire _io_ifu_flush_icache_T_2 = _io_ifu_flush_icache_T_1 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}] reg io_ifu_flush_icache_REG; // @[core.scala:389:13] wire _io_ifu_flush_icache_T_3 = _io_ifu_flush_icache_T | io_ifu_flush_icache_REG; // @[core.scala:388:{35,71}, :389:13] wire _io_ifu_flush_icache_T_4 = _rob_io_commit_arch_valids_1 & _rob_io_commit_uops_1_is_fencei; // @[core.scala:143:32, :388:35] wire _io_ifu_flush_icache_T_5 = dec_valids_1 & dec_uops_1_is_jalr; // @[core.scala:157:24, :158:24, :389:28] wire _io_ifu_flush_icache_T_6 = _io_ifu_flush_icache_T_5 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}] reg io_ifu_flush_icache_REG_1; // @[core.scala:389:13] wire _io_ifu_flush_icache_T_7 = _io_ifu_flush_icache_T_4 | io_ifu_flush_icache_REG_1; // @[core.scala:388:{35,71}, :389:13] wire _io_ifu_flush_icache_T_8 = _rob_io_commit_arch_valids_2 & _rob_io_commit_uops_2_is_fencei; // @[core.scala:143:32, :388:35] wire _io_ifu_flush_icache_T_9 = dec_valids_2 & dec_uops_2_is_jalr; // @[core.scala:157:24, :158:24, :389:28] wire _io_ifu_flush_icache_T_10 = _io_ifu_flush_icache_T_9 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}] reg io_ifu_flush_icache_REG_2; // @[core.scala:389:13] wire _io_ifu_flush_icache_T_11 = _io_ifu_flush_icache_T_8 | io_ifu_flush_icache_REG_2; // @[core.scala:388:{35,71}, :389:13] wire _io_ifu_flush_icache_T_12 = _io_ifu_flush_icache_T_3 | _io_ifu_flush_icache_T_7; // @[core.scala:388:71, :390:13] assign _io_ifu_flush_icache_T_13 = _io_ifu_flush_icache_T_12 | _io_ifu_flush_icache_T_11; // @[core.scala:388:71, :390:13] assign io_ifu_flush_icache_0 = _io_ifu_flush_icache_T_13; // @[core.scala:51:7, :390:13] reg REG; // @[core.scala:401:16] reg [2:0] flush_typ; // @[core.scala:404:28] wire _io_ifu_redirect_pc_T = flush_typ == 3'h3; // @[core.scala:404:28, :411:44] reg [39:0] io_ifu_redirect_pc_REG; // @[core.scala:412:49] reg [39:0] io_ifu_redirect_pc_REG_1; // @[core.scala:412:41] wire [39:0] _io_ifu_redirect_pc_T_1 = _io_ifu_redirect_pc_T ? io_ifu_redirect_pc_REG_1 : _csr_io_evec; // @[core.scala:271:19, :411:{33,44}, :412:41] wire [39:0] _flush_pc_T = ~io_ifu_get_pc_0_pc_0; // @[util.scala:237:7] wire [39:0] _flush_pc_T_1 = {_flush_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}] wire [39:0] _flush_pc_T_2 = ~_flush_pc_T_1; // @[util.scala:237:{5,11}] reg [5:0] flush_pc_REG; // @[core.scala:416:32] wire [40:0] _flush_pc_T_3 = {1'h0, _flush_pc_T_2} + {35'h0, flush_pc_REG}; // @[util.scala:237:5] wire [39:0] _flush_pc_T_4 = _flush_pc_T_3[39:0]; // @[core.scala:416:23] reg flush_pc_REG_1; // @[core.scala:417:36] wire [1:0] _flush_pc_T_5 = {flush_pc_REG_1, 1'h0}; // @[core.scala:417:{28,36}] wire [40:0] _flush_pc_T_6 = {1'h0, _flush_pc_T_4} - {39'h0, _flush_pc_T_5}; // @[core.scala:416:23, :417:{23,28}] wire [39:0] flush_pc = _flush_pc_T_6[39:0]; // @[core.scala:417:23] reg flush_pc_next_REG; // @[core.scala:418:49] wire [2:0] _flush_pc_next_T = flush_pc_next_REG ? 3'h2 : 3'h4; // @[core.scala:418:{41,49}] wire [40:0] _flush_pc_next_T_1 = {1'h0, flush_pc} + {38'h0, _flush_pc_next_T}; // @[core.scala:417:23, :418:{36,41}] wire [39:0] flush_pc_next = _flush_pc_next_T_1[39:0]; // @[core.scala:418:36] wire _io_ifu_redirect_pc_T_2 = flush_typ == 3'h2; // @[rob.scala:167:40] wire [39:0] _io_ifu_redirect_pc_T_3 = _io_ifu_redirect_pc_T_2 ? flush_pc : flush_pc_next; // @[rob.scala:167:40] reg [4:0] io_ifu_redirect_ftq_idx_REG; // @[core.scala:423:39] reg REG_1; // @[core.scala:424:50] wire _T_18 = brupdate_b2_mispredict & ~REG_1; // @[core.scala:188:23, :424:{39,42,50}] wire [39:0] _block_pc_T = ~io_ifu_get_pc_1_pc_0; // @[util.scala:237:7] wire [39:0] _block_pc_T_1 = {_block_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}] wire [39:0] block_pc = ~_block_pc_T_1; // @[util.scala:237:{5,11}] wire [39:0] uop_maybe_pc = {block_pc[39:6], block_pc[5:0] | brupdate_b2_uop_pc_lob}; // @[util.scala:237:5] wire [39:0] _jal_br_target_T = uop_maybe_pc; // @[core.scala:426:33, :429:36] wire _npc_T = brupdate_b2_uop_is_rvc | brupdate_b2_uop_edge_inst; // @[core.scala:188:23, :427:57] wire [2:0] _npc_T_1 = _npc_T ? 3'h2 : 3'h4; // @[core.scala:427:{33,57}] wire [40:0] _npc_T_2 = {1'h0, uop_maybe_pc} + {38'h0, _npc_T_1}; // @[core.scala:418:36, :426:33, :427:{28,33}] wire [39:0] npc = _npc_T_2[39:0]; // @[core.scala:427:28] wire [39:0] _jal_br_target_T_10; // @[core.scala:430:75] wire [39:0] jal_br_target; // @[core.scala:428:29] wire [40:0] _jal_br_target_T_1 = {_jal_br_target_T[39], _jal_br_target_T} + {{20{brupdate_b2_target_offset[20]}}, brupdate_b2_target_offset}; // @[core.scala:188:23, :429:{36,43}] wire [39:0] _jal_br_target_T_2 = _jal_br_target_T_1[39:0]; // @[core.scala:429:43] wire [39:0] _jal_br_target_T_3 = _jal_br_target_T_2; // @[core.scala:429:43] wire [38:0] _jal_br_target_T_4 = {39{brupdate_b2_uop_edge_inst}}; // @[core.scala:188:23, :430:12] wire [39:0] _jal_br_target_T_5 = {_jal_br_target_T_4, 1'h0}; // @[core.scala:430:{12,61}] wire [39:0] _jal_br_target_T_6 = _jal_br_target_T_5; // @[core.scala:430:{61,67}] wire [40:0] _jal_br_target_T_7 = {_jal_br_target_T_3[39], _jal_br_target_T_3} + {_jal_br_target_T_6[39], _jal_br_target_T_6}; // @[core.scala:429:{43,71}, :430:67] wire [39:0] _jal_br_target_T_8 = _jal_br_target_T_7[39:0]; // @[core.scala:429:71] wire [39:0] _jal_br_target_T_9 = _jal_br_target_T_8; // @[core.scala:429:71] assign _jal_br_target_T_10 = _jal_br_target_T_9; // @[core.scala:429:71, :430:75] assign jal_br_target = _jal_br_target_T_10; // @[core.scala:428:29, :430:75] wire _bj_addr_T = brupdate_b2_cfi_type == 3'h3; // @[core.scala:188:23, :431:44] wire [39:0] bj_addr = _bj_addr_T ? brupdate_b2_jalr_target : jal_br_target; // @[core.scala:188:23, :428:29, :431:{22,44}] wire _mispredict_target_T = brupdate_b2_pc_sel == 2'h0; // @[core.scala:188:23, :432:52] wire [39:0] mispredict_target = _mispredict_target_T ? npc : bj_addr; // @[core.scala:427:28, :431:22, :432:{32,52}] assign io_ifu_redirect_val_0 = REG | _T_18; // @[core.scala:51:7, :401:{16,38}, :402:27, :424:{39,72}] assign io_ifu_redirect_pc_0 = REG ? (flush_typ[0] ? _io_ifu_redirect_pc_T_1 : _io_ifu_redirect_pc_T_3) : mispredict_target; // @[rob.scala:166:40] assign io_ifu_redirect_ftq_idx_0 = REG ? io_ifu_redirect_ftq_idx_REG : brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23, :401:{16,38}, :423:{29,39}, :424:72] wire _GEN_13 = brupdate_b2_cfi_type == 3'h1; // @[core.scala:188:23, :437:48] wire _use_same_ghist_T; // @[core.scala:437:48] assign _use_same_ghist_T = _GEN_13; // @[core.scala:437:48] wire _next_ghist_T; // @[core.scala:447:28] assign _next_ghist_T = _GEN_13; // @[core.scala:437:48, :447:28] wire _use_same_ghist_T_1 = ~brupdate_b2_taken; // @[core.scala:188:23, :438:27] wire _use_same_ghist_T_2 = _use_same_ghist_T & _use_same_ghist_T_1; // @[core.scala:437:{48,59}, :438:27] wire [39:0] _use_same_ghist_T_3 = ~block_pc; // @[util.scala:237:5] wire [39:0] _use_same_ghist_T_4 = {_use_same_ghist_T_3[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _use_same_ghist_T_5 = ~_use_same_ghist_T_4; // @[frontend.scala:160:{31,39}] wire [39:0] _use_same_ghist_T_6 = ~npc; // @[frontend.scala:160:33] wire [39:0] _use_same_ghist_T_7 = {_use_same_ghist_T_6[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _use_same_ghist_T_8 = ~_use_same_ghist_T_7; // @[frontend.scala:160:{31,39}] wire _use_same_ghist_T_9 = _use_same_ghist_T_5 == _use_same_ghist_T_8; // @[frontend.scala:160:31] wire use_same_ghist = _use_same_ghist_T_2 & _use_same_ghist_T_9; // @[core.scala:437:59, :438:46, :439:47] wire [3:0] _cfi_idx_T_2 = {_cfi_idx_T, 3'h0}; // @[core.scala:442:{10,32}] wire [5:0] _cfi_idx_T_3 = {brupdate_b2_uop_pc_lob[5:4], brupdate_b2_uop_pc_lob[3:0] ^ _cfi_idx_T_2}; // @[core.scala:188:23, :441:43, :442:10] wire [2:0] cfi_idx = _cfi_idx_T_3[3:1]; // @[core.scala:441:43, :442:74] wire [2:0] next_ghist_cfi_idx_fixed = cfi_idx; // @[frontend.scala:85:32] wire _GEN_14 = io_ifu_get_pc_1_entry_cfi_idx_bits_0 == cfi_idx; // @[core.scala:51:7, :442:74, :451:55] wire _next_ghist_T_1; // @[core.scala:451:55] assign _next_ghist_T_1 = _GEN_14; // @[core.scala:451:55] wire _next_ghist_T_3; // @[core.scala:452:55] assign _next_ghist_T_3 = _GEN_14; // @[core.scala:451:55, :452:55] wire _next_ghist_T_2 = io_ifu_get_pc_1_entry_cfi_is_call_0 & _next_ghist_T_1; // @[core.scala:51:7, :451:{29,55}] wire _next_ghist_new_history_ras_idx_T = _next_ghist_T_2; // @[frontend.scala:123:42] wire _next_ghist_T_4 = io_ifu_get_pc_1_entry_cfi_is_ret_0 & _next_ghist_T_3; // @[core.scala:51:7, :452:{29,55}] wire _next_ghist_new_history_ras_idx_T_4 = _next_ghist_T_4; // @[frontend.scala:124:42] wire [7:0] next_ghist_cfi_idx_oh = 8'h1 << next_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T = next_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31] wire [63:0] next_ghist_old_history; // @[frontend.scala:87:27] wire next_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27] wire next_ghist_new_saw_branch_taken; // @[frontend.scala:87:27] wire [4:0] next_ghist_ras_idx; // @[frontend.scala:87:27] wire [7:0] _next_ghist_not_taken_branches_T_1 = {1'h0, next_ghist_cfi_idx_oh[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_2 = {2'h0, next_ghist_cfi_idx_oh[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_3 = {3'h0, next_ghist_cfi_idx_oh[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_4 = {4'h0, next_ghist_cfi_idx_oh[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_5 = {5'h0, next_ghist_cfi_idx_oh[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_6 = {6'h0, next_ghist_cfi_idx_oh[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_7 = {7'h0, next_ghist_cfi_idx_oh[7]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_8 = _next_ghist_not_taken_branches_T | _next_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_9 = _next_ghist_not_taken_branches_T_8 | _next_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_10 = _next_ghist_not_taken_branches_T_9 | _next_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_11 = _next_ghist_not_taken_branches_T_10 | _next_ghist_not_taken_branches_T_4; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_12 = _next_ghist_not_taken_branches_T_11 | _next_ghist_not_taken_branches_T_5; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_13 = _next_ghist_not_taken_branches_T_12 | _next_ghist_not_taken_branches_T_6; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_14 = _next_ghist_not_taken_branches_T_13 | _next_ghist_not_taken_branches_T_7; // @[util.scala:373:{29,45}] wire _next_ghist_not_taken_branches_T_15 = _next_ghist_T & brupdate_b2_taken; // @[frontend.scala:90:84] wire [7:0] _next_ghist_not_taken_branches_T_16 = _next_ghist_not_taken_branches_T_15 ? next_ghist_cfi_idx_oh : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_17 = ~_next_ghist_not_taken_branches_T_16; // @[frontend.scala:90:{69,73}] wire [7:0] _next_ghist_not_taken_branches_T_18 = _next_ghist_not_taken_branches_T_14 & _next_ghist_not_taken_branches_T_17; // @[util.scala:373:45] wire [7:0] _next_ghist_not_taken_branches_T_20 = _next_ghist_not_taken_branches_T_18; // @[frontend.scala:89:44, :90:67] wire [7:0] next_ghist_not_taken_branches = io_ifu_get_pc_1_entry_br_mask_0 & _next_ghist_not_taken_branches_T_20; // @[frontend.scala:89:{39,44}] wire [64:0] _GEN_15 = {io_ifu_get_pc_1_ghist_old_history_0, 1'h0}; // @[frontend.scala:67:75] wire [64:0] _next_ghist_base_T; // @[frontend.scala:67:75] assign _next_ghist_base_T = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_base_T_2; // @[frontend.scala:68:75] assign _next_ghist_base_T_2 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_new_history_old_history_T; // @[frontend.scala:67:75] assign _next_ghist_new_history_old_history_T = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_new_history_old_history_T_2; // @[frontend.scala:68:75] assign _next_ghist_new_history_old_history_T_2 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_new_history_old_history_T_6; // @[frontend.scala:67:75] assign _next_ghist_new_history_old_history_T_6 = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_new_history_old_history_T_8; // @[frontend.scala:68:75] assign _next_ghist_new_history_old_history_T_8 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_new_history_old_history_T_13; // @[frontend.scala:67:75] assign _next_ghist_new_history_old_history_T_13 = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_new_history_old_history_T_15; // @[frontend.scala:68:75] assign _next_ghist_new_history_old_history_T_15 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_new_history_old_history_T_19; // @[frontend.scala:67:75] assign _next_ghist_new_history_old_history_T_19 = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_new_history_old_history_T_21; // @[frontend.scala:68:75] assign _next_ghist_new_history_old_history_T_21 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_base_T_1 = {_next_ghist_base_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _GEN_16 = {1'h0, io_ifu_get_pc_1_ghist_old_history_0}; // @[frontend.scala:68:12] wire [64:0] _next_ghist_base_T_3 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_base_T_2 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] next_ghist_base = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_base_T_1 : _next_ghist_base_T_3; // @[frontend.scala:67:{12,80}, :68:12] wire _next_ghist_cfi_in_bank_0_T_1 = ~(next_ghist_cfi_idx_fixed[2]); // @[frontend.scala:85:32, :104:67] wire next_ghist_cfi_in_bank_0 = _next_ghist_cfi_in_bank_0_T & _next_ghist_cfi_in_bank_0_T_1; // @[frontend.scala:104:{37,50,67}] wire [2:0] _next_ghist_ignore_second_bank_T = io_ifu_get_pc_1_pc_0[5:3]; // @[frontend.scala:152:28] wire _next_ghist_ignore_second_bank_T_1 = &_next_ghist_ignore_second_bank_T; // @[frontend.scala:152:{28,66}] wire _next_ghist_ignore_second_bank_T_2 = _next_ghist_ignore_second_bank_T_1; // @[frontend.scala:152:{21,66}] wire next_ghist_ignore_second_bank = next_ghist_cfi_in_bank_0 | _next_ghist_ignore_second_bank_T_2; // @[frontend.scala:104:50, :105:46, :152:21] wire [3:0] _next_ghist_first_bank_saw_not_taken_T = next_ghist_not_taken_branches[3:0]; // @[frontend.scala:89:39, :107:56] wire _next_ghist_first_bank_saw_not_taken_T_1 = |_next_ghist_first_bank_saw_not_taken_T; // @[frontend.scala:107:{56,72}] wire next_ghist_first_bank_saw_not_taken = _next_ghist_first_bank_saw_not_taken_T_1 | io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[frontend.scala:107:{72,80}] wire [64:0] _next_ghist_new_history_old_history_T_1 = {_next_ghist_new_history_old_history_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _next_ghist_new_history_old_history_T_3 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_2 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] _next_ghist_new_history_old_history_T_4 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_1 : _next_ghist_new_history_old_history_T_3; // @[frontend.scala:67:{12,80}, :68:12] wire _GEN_17 = _next_ghist_T & next_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :112:59] wire _next_ghist_new_history_new_saw_branch_taken_T; // @[frontend.scala:112:59] assign _next_ghist_new_history_new_saw_branch_taken_T = _GEN_17; // @[frontend.scala:112:59] wire _next_ghist_new_history_old_history_T_5; // @[frontend.scala:114:50] assign _next_ghist_new_history_old_history_T_5 = _GEN_17; // @[frontend.scala:112:59, :114:50] wire [64:0] _next_ghist_new_history_old_history_T_7 = {_next_ghist_new_history_old_history_T_6[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _next_ghist_new_history_old_history_T_9 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_8 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] _next_ghist_new_history_old_history_T_10 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_7 : _next_ghist_new_history_old_history_T_9; // @[frontend.scala:67:{12,80}, :68:12] wire [65:0] _next_ghist_new_history_old_history_T_11 = {_next_ghist_new_history_old_history_T_10, 1'h0}; // @[frontend.scala:67:12, :114:110] wire [65:0] _next_ghist_new_history_old_history_T_12 = {_next_ghist_new_history_old_history_T_11[65:1], 1'h1}; // @[frontend.scala:114:{110,115}] wire [64:0] _next_ghist_new_history_old_history_T_14 = {_next_ghist_new_history_old_history_T_13[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _next_ghist_new_history_old_history_T_16 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_15 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] _next_ghist_new_history_old_history_T_17 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_14 : _next_ghist_new_history_old_history_T_16; // @[frontend.scala:67:{12,80}, :68:12] wire [65:0] _next_ghist_new_history_old_history_T_18 = {_next_ghist_new_history_old_history_T_17, 1'h0}; // @[frontend.scala:67:12, :115:110] wire [64:0] _next_ghist_new_history_old_history_T_20 = {_next_ghist_new_history_old_history_T_19[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _next_ghist_new_history_old_history_T_22 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_21 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] _next_ghist_new_history_old_history_T_23 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_20 : _next_ghist_new_history_old_history_T_22; // @[frontend.scala:67:{12,80}, :68:12] wire [65:0] _next_ghist_new_history_old_history_T_24 = next_ghist_first_bank_saw_not_taken ? _next_ghist_new_history_old_history_T_18 : {1'h0, _next_ghist_new_history_old_history_T_23}; // @[frontend.scala:67:12, :107:80, :115:{39,110}] wire [65:0] _next_ghist_new_history_old_history_T_25 = _next_ghist_new_history_old_history_T_5 ? _next_ghist_new_history_old_history_T_12 : _next_ghist_new_history_old_history_T_24; // @[frontend.scala:114:{39,50,115}, :115:39] assign next_ghist_old_history = next_ghist_ignore_second_bank ? _next_ghist_new_history_old_history_T_4[63:0] : _next_ghist_new_history_old_history_T_25[63:0]; // @[frontend.scala:67:12, :87:27, :105:46, :109:33, :110:33, :114:{33,39}] wire [3:0] _next_ghist_new_history_new_saw_branch_not_taken_T = next_ghist_not_taken_branches[7:4]; // @[frontend.scala:89:39, :118:67] wire _next_ghist_new_history_new_saw_branch_not_taken_T_1 = |_next_ghist_new_history_new_saw_branch_not_taken_T; // @[frontend.scala:118:{67,92}] assign next_ghist_new_saw_branch_not_taken = next_ghist_ignore_second_bank ? next_ghist_first_bank_saw_not_taken : _next_ghist_new_history_new_saw_branch_not_taken_T_1; // @[frontend.scala:87:27, :105:46, :107:80, :109:33, :111:46, :118:{46,92}] wire _next_ghist_new_history_new_saw_branch_taken_T_2 = _next_ghist_new_history_new_saw_branch_taken_T_1 & _next_ghist_T; // @[frontend.scala:119:{59,72}] wire _next_ghist_new_history_new_saw_branch_taken_T_3 = ~next_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :119:88] wire _next_ghist_new_history_new_saw_branch_taken_T_4 = _next_ghist_new_history_new_saw_branch_taken_T_2 & _next_ghist_new_history_new_saw_branch_taken_T_3; // @[frontend.scala:119:{72,85,88}] assign next_ghist_new_saw_branch_taken = next_ghist_ignore_second_bank ? _next_ghist_new_history_new_saw_branch_taken_T : _next_ghist_new_history_new_saw_branch_taken_T_4; // @[frontend.scala:87:27, :105:46, :109:33, :112:{46,59}, :119:{46,85}] wire [5:0] _GEN_18 = {1'h0, io_ifu_get_pc_1_ghist_ras_idx_0}; // @[util.scala:203:14] wire [5:0] _next_ghist_new_history_ras_idx_T_1 = _GEN_18 + 6'h1; // @[util.scala:203:14] wire [4:0] _next_ghist_new_history_ras_idx_T_2 = _next_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14] wire [4:0] _next_ghist_new_history_ras_idx_T_3 = _next_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}] wire [5:0] _next_ghist_new_history_ras_idx_T_5 = _GEN_18 - 6'h1; // @[util.scala:203:14, :220:14] wire [4:0] _next_ghist_new_history_ras_idx_T_6 = _next_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14] wire [4:0] _next_ghist_new_history_ras_idx_T_7 = _next_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}] wire [4:0] _next_ghist_new_history_ras_idx_T_8 = _next_ghist_new_history_ras_idx_T_4 ? _next_ghist_new_history_ras_idx_T_7 : io_ifu_get_pc_1_ghist_ras_idx_0; // @[util.scala:220:20] assign _next_ghist_new_history_ras_idx_T_9 = _next_ghist_new_history_ras_idx_T ? _next_ghist_new_history_ras_idx_T_3 : _next_ghist_new_history_ras_idx_T_8; // @[util.scala:203:20] assign next_ghist_ras_idx = _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31] wire [63:0] _io_ifu_redirect_ghist_T_old_history = use_same_ghist ? io_ifu_get_pc_1_ghist_old_history_0 : next_ghist_old_history; // @[frontend.scala:87:27] wire _io_ifu_redirect_ghist_T_current_saw_branch_not_taken = use_same_ghist & io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[core.scala:51:7, :438:46, :455:35] wire _io_ifu_redirect_ghist_T_new_saw_branch_not_taken = use_same_ghist ? io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 : next_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27] wire _io_ifu_redirect_ghist_T_new_saw_branch_taken = use_same_ghist ? io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 : next_ghist_new_saw_branch_taken; // @[frontend.scala:87:27] wire [4:0] _io_ifu_redirect_ghist_T_ras_idx = use_same_ghist ? io_ifu_get_pc_1_ghist_ras_idx_0 : next_ghist_ras_idx; // @[frontend.scala:87:27] assign io_ifu_redirect_ghist_old_history_0 = REG ? 64'h0 : _io_ifu_redirect_ghist_T_old_history; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35] assign io_ifu_redirect_ghist_new_saw_branch_not_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_not_taken; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35] assign io_ifu_redirect_ghist_new_saw_branch_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_taken; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35] assign io_ifu_redirect_ghist_ras_idx_0 = REG ? new_ghist_ras_idx : _io_ifu_redirect_ghist_T_ras_idx; // @[core.scala:51:7, :401:{16,38}, :406:29, :409:27, :424:72, :455:35] assign io_ifu_redirect_ghist_current_saw_branch_not_taken_0 = REG | use_same_ghist; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :438:46] assign io_ifu_redirect_flush_0 = REG | _T_18 | (|{_rob_io_flush_frontend, brupdate_b1_mispredict_mask}); // @[core.scala:51:7, :143:32, :188:23, :224:42, :401:{16,38}, :403:27, :424:{39,72}, :435:29, :460:{38,78}] wire [1:0] _youngest_com_idx_T = _rob_io_commit_valids_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70] wire [1:0] _youngest_com_idx_T_1 = _rob_io_commit_valids_2 ? 2'h0 : _youngest_com_idx_T; // @[Mux.scala:50:70] wire [2:0] _youngest_com_idx_T_2 = 3'h2 - {1'h0, _youngest_com_idx_T_1}; // @[Mux.scala:50:70] wire [1:0] youngest_com_idx = _youngest_com_idx_T_2[1:0]; // @[core.scala:465:42] wire _io_ifu_commit_valid_T = _rob_io_commit_valids_0 | _rob_io_commit_valids_1; // @[core.scala:143:32, :466:55] wire _io_ifu_commit_valid_T_1 = _io_ifu_commit_valid_T | _rob_io_commit_valids_2; // @[core.scala:143:32, :466:55] wire _io_ifu_commit_valid_T_2 = _io_ifu_commit_valid_T_1 | _rob_io_com_xcpt_valid; // @[core.scala:143:32, :466:{55,59}] wire [3:0][4:0] _GEN_19 = {{_rob_io_commit_uops_0_ftq_idx}, {_rob_io_commit_uops_2_ftq_idx}, {_rob_io_commit_uops_1_ftq_idx}, {_rob_io_commit_uops_0_ftq_idx}}; // @[core.scala:143:32, :467:29] wire [4:0] _io_ifu_commit_bits_T = _rob_io_com_xcpt_valid ? _rob_io_com_xcpt_bits_ftq_idx : _GEN_19[youngest_com_idx]; // @[core.scala:143:32, :465:42, :467:29] reg REG_2; // @[core.scala:475:18] reg io_ifu_sfence_REG_valid; // @[core.scala:476:31] assign io_ifu_sfence_valid_0 = io_ifu_sfence_REG_valid; // @[core.scala:51:7, :476:31] reg io_ifu_sfence_REG_bits_rs1; // @[core.scala:476:31] assign io_ifu_sfence_bits_rs1_0 = io_ifu_sfence_REG_bits_rs1; // @[core.scala:51:7, :476:31] reg io_ifu_sfence_REG_bits_rs2; // @[core.scala:476:31] assign io_ifu_sfence_bits_rs2_0 = io_ifu_sfence_REG_bits_rs2; // @[core.scala:51:7, :476:31] reg [38:0] io_ifu_sfence_REG_bits_addr; // @[core.scala:476:31] assign io_ifu_sfence_bits_addr_0 = io_ifu_sfence_REG_bits_addr; // @[core.scala:51:7, :476:31] reg io_ifu_sfence_REG_bits_asid; // @[core.scala:476:31] assign io_ifu_sfence_bits_asid_0 = io_ifu_sfence_REG_bits_asid; // @[core.scala:51:7, :476:31] reg [2:0] dec_finished_mask; // @[core.scala:496:34] wire _dec_valids_0_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_0_valid_0; // @[core.scala:51:7, :508:68] wire _dec_valids_0_T_1 = dec_finished_mask[0]; // @[core.scala:496:34, :509:61] wire _dec_brmask_logic_io_is_branch_0_T = dec_finished_mask[0]; // @[core.scala:496:34, :509:61, :600:59] wire _dec_valids_0_T_2 = ~_dec_valids_0_T_1; // @[core.scala:509:{43,61}] assign _dec_valids_0_T_3 = _dec_valids_0_T & _dec_valids_0_T_2; // @[core.scala:508:{68,97}, :509:43] assign dec_valids_0 = _dec_valids_0_T_3; // @[core.scala:157:24, :508:97] wire _dec_valids_1_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_1_valid_0; // @[core.scala:51:7, :508:68] wire _dec_valids_1_T_1 = dec_finished_mask[1]; // @[core.scala:496:34, :509:61] wire _dec_brmask_logic_io_is_branch_1_T = dec_finished_mask[1]; // @[core.scala:496:34, :509:61, :600:59] wire _dec_valids_1_T_2 = ~_dec_valids_1_T_1; // @[core.scala:509:{43,61}] assign _dec_valids_1_T_3 = _dec_valids_1_T & _dec_valids_1_T_2; // @[core.scala:508:{68,97}, :509:43] assign dec_valids_1 = _dec_valids_1_T_3; // @[core.scala:157:24, :508:97] wire _dec_valids_2_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_2_valid_0; // @[core.scala:51:7, :508:68] wire _dec_valids_2_T_1 = dec_finished_mask[2]; // @[core.scala:496:34, :509:61] wire _dec_brmask_logic_io_is_branch_2_T = dec_finished_mask[2]; // @[core.scala:496:34, :509:61, :600:59] wire _dec_valids_2_T_2 = ~_dec_valids_2_T_1; // @[core.scala:509:{43,61}] assign _dec_valids_2_T_3 = _dec_valids_2_T & _dec_valids_2_T_2; // @[core.scala:508:{68,97}, :509:43] assign dec_valids_2 = _dec_valids_2_T_3; // @[core.scala:157:24, :508:97] wire jmp_pc_req_ready; // @[core.scala:522:25] wire jmp_pc_req_valid; // @[core.scala:522:25] wire [4:0] jmp_pc_req_bits; // @[core.scala:522:25] wire _xcpt_pc_req_valid_T_1; // @[core.scala:551:45] wire xcpt_pc_req_ready; // @[core.scala:523:25] wire xcpt_pc_req_valid; // @[core.scala:523:25] wire [4:0] xcpt_pc_req_bits; // @[core.scala:523:25] wire flush_pc_req_valid; // @[core.scala:524:26] wire [4:0] flush_pc_req_bits; // @[core.scala:524:26] wire _jmp_pc_req_valid_T = iss_uops_1_fu_code == 10'h2; // @[core.scala:173:24, :539:90] wire _jmp_pc_req_valid_T_1 = iss_valids_1 & _jmp_pc_req_valid_T; // @[core.scala:172:24, :539:{56,90}] reg jmp_pc_req_valid_REG; // @[core.scala:539:30] assign jmp_pc_req_valid = jmp_pc_req_valid_REG; // @[core.scala:522:25, :539:30] reg [4:0] jmp_pc_req_bits_REG; // @[core.scala:540:30] assign jmp_pc_req_bits = jmp_pc_req_bits_REG; // @[core.scala:522:25, :540:30] wire [1:0] _xcpt_idx_T = dec_xcpts_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70] wire [1:0] xcpt_idx = dec_xcpts_0 ? 2'h0 : _xcpt_idx_T; // @[Mux.scala:50:70] wire _GEN_20 = dec_xcpts_0 | dec_xcpts_1; // @[core.scala:162:24, :551:45] wire _xcpt_pc_req_valid_T; // @[core.scala:551:45] assign _xcpt_pc_req_valid_T = _GEN_20; // @[core.scala:551:45] wire _dec_xcpt_stall_T; // @[core.scala:567:42] assign _dec_xcpt_stall_T = _GEN_20; // @[core.scala:551:45, :567:42] assign _xcpt_pc_req_valid_T_1 = _xcpt_pc_req_valid_T | dec_xcpts_2; // @[core.scala:162:24, :551:45] assign xcpt_pc_req_valid = _xcpt_pc_req_valid_T_1; // @[core.scala:523:25, :551:45] wire [3:0][4:0] _GEN_21 = {{dec_uops_0_ftq_idx}, {dec_uops_2_ftq_idx}, {dec_uops_1_ftq_idx}, {dec_uops_0_ftq_idx}}; // @[core.scala:158:24, :552:24] assign xcpt_pc_req_bits = _GEN_21[xcpt_idx]; // @[Mux.scala:50:70] assign dec_xcpts_0 = dec_uops_0_exception & dec_valids_0; // @[core.scala:157:24, :158:24, :162:24, :566:71] assign dec_xcpts_1 = dec_uops_1_exception & dec_valids_1; // @[core.scala:157:24, :158:24, :162:24, :566:71] assign dec_xcpts_2 = dec_uops_2_exception & dec_valids_2; // @[core.scala:157:24, :158:24, :162:24, :566:71] wire _dec_xcpt_stall_T_1 = _dec_xcpt_stall_T | dec_xcpts_2; // @[core.scala:162:24, :567:42] wire _dec_xcpt_stall_T_2 = ~xcpt_pc_req_ready; // @[core.scala:523:25, :567:50] wire dec_xcpt_stall = _dec_xcpt_stall_T_1 & _dec_xcpt_stall_T_2; // @[core.scala:567:{42,47,50}] wire branch_mask_full_0; // @[core.scala:569:30] wire branch_mask_full_1; // @[core.scala:569:30] wire branch_mask_full_2; // @[core.scala:569:30] wire _dec_hazards_T = ~dis_ready; // @[core.scala:169:24, :573:26] wire _dec_hazards_T_1 = _dec_hazards_T | _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23] wire _dec_hazards_T_2 = _dec_hazards_T_1 | dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23] wire _dec_hazards_T_3 = _dec_hazards_T_2 | branch_mask_full_0; // @[core.scala:569:30, :575:23, :576:23] wire _dec_hazards_T_4 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54] wire _dec_hazards_T_5 = _dec_hazards_T_3 | _dec_hazards_T_4; // @[core.scala:576:23, :577:{23,54}] wire _dec_hazards_T_6 = _dec_hazards_T_5 | brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23] wire _dec_hazards_T_7 = _dec_hazards_T_6 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23] wire dec_hazards_0 = dec_valids_0 & _dec_hazards_T_7; // @[core.scala:157:24, :572:37, :579:23] wire dec_stalls_0 = dec_hazards_0; // @[core.scala:572:37, :581:62] wire _dec_hazards_T_8 = ~dis_ready; // @[core.scala:169:24, :573:26] wire _dec_hazards_T_9 = _dec_hazards_T_8 | _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23] wire _dec_hazards_T_10 = _dec_hazards_T_9 | dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23] wire _dec_hazards_T_11 = _dec_hazards_T_10 | branch_mask_full_1; // @[core.scala:569:30, :575:23, :576:23] wire _dec_hazards_T_12 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54] wire _dec_hazards_T_13 = _dec_hazards_T_11 | _dec_hazards_T_12; // @[core.scala:576:23, :577:{23,54}] wire _dec_hazards_T_14 = _dec_hazards_T_13 | brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23] wire _dec_hazards_T_15 = _dec_hazards_T_14 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23] wire dec_hazards_1 = dec_valids_1 & _dec_hazards_T_15; // @[core.scala:157:24, :572:37, :579:23] wire _dec_hazards_T_16 = ~dis_ready; // @[core.scala:169:24, :573:26] wire _dec_hazards_T_17 = _dec_hazards_T_16 | _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23] wire _dec_hazards_T_18 = _dec_hazards_T_17 | dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23] wire _dec_hazards_T_19 = _dec_hazards_T_18 | branch_mask_full_2; // @[core.scala:569:30, :575:23, :576:23] wire _dec_hazards_T_20 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54] wire _dec_hazards_T_21 = _dec_hazards_T_19 | _dec_hazards_T_20; // @[core.scala:576:23, :577:{23,54}] wire _dec_hazards_T_22 = _dec_hazards_T_21 | brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23] wire _dec_hazards_T_23 = _dec_hazards_T_22 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23] wire dec_hazards_2 = dec_valids_2 & _dec_hazards_T_23; // @[core.scala:157:24, :572:37, :579:23] wire dec_stalls_1 = dec_stalls_0 | dec_hazards_1; // @[core.scala:572:37, :581:62] wire dec_stalls_2 = dec_stalls_1 | dec_hazards_2; // @[core.scala:572:37, :581:62] assign dec_fire_0 = dec_valids_0 & ~dec_stalls_0; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}] assign dec_fire_1 = dec_valids_1 & ~dec_stalls_1; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}] assign dec_fire_2 = dec_valids_2 & ~dec_stalls_2; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}] wire [1:0] dec_finished_mask_hi = {dec_fire_2, dec_fire_1}; // @[core.scala:159:24, :590:35] wire [2:0] _dec_finished_mask_T = {dec_finished_mask_hi, dec_fire_0}; // @[core.scala:159:24, :590:35] wire [2:0] _dec_finished_mask_T_1 = _dec_finished_mask_T | dec_finished_mask; // @[core.scala:496:34, :590:{35,42}] reg dec_brmask_logic_io_flush_pipeline_REG; // @[core.scala:597:48] wire _dec_brmask_logic_io_is_branch_0_T_1 = ~_dec_brmask_logic_io_is_branch_0_T; // @[core.scala:600:{41,59}] wire _dec_brmask_logic_io_is_branch_0_T_2 = ~dec_uops_0_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_0_T_3 = dec_uops_0_is_br & _dec_brmask_logic_io_is_branch_0_T_2; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_0_T_4 = _dec_brmask_logic_io_is_branch_0_T_3 | dec_uops_0_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_0_T_5 = _dec_brmask_logic_io_is_branch_0_T_1 & _dec_brmask_logic_io_is_branch_0_T_4; // @[core.scala:600:{41,63}] wire _dec_brmask_logic_io_will_fire_0_T = ~dec_uops_0_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_0_T_1 = dec_uops_0_is_br & _dec_brmask_logic_io_will_fire_0_T; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_0_T_2 = _dec_brmask_logic_io_will_fire_0_T_1 | dec_uops_0_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_0_T_3 = dec_fire_0 & _dec_brmask_logic_io_will_fire_0_T_2; // @[core.scala:159:24, :601:54] wire _dec_brmask_logic_io_is_branch_1_T_1 = ~_dec_brmask_logic_io_is_branch_1_T; // @[core.scala:600:{41,59}] wire _dec_brmask_logic_io_is_branch_1_T_2 = ~dec_uops_1_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_1_T_3 = dec_uops_1_is_br & _dec_brmask_logic_io_is_branch_1_T_2; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_1_T_4 = _dec_brmask_logic_io_is_branch_1_T_3 | dec_uops_1_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_1_T_5 = _dec_brmask_logic_io_is_branch_1_T_1 & _dec_brmask_logic_io_is_branch_1_T_4; // @[core.scala:600:{41,63}] wire _dec_brmask_logic_io_will_fire_1_T = ~dec_uops_1_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_1_T_1 = dec_uops_1_is_br & _dec_brmask_logic_io_will_fire_1_T; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_1_T_2 = _dec_brmask_logic_io_will_fire_1_T_1 | dec_uops_1_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_1_T_3 = dec_fire_1 & _dec_brmask_logic_io_will_fire_1_T_2; // @[core.scala:159:24, :601:54] wire _dec_brmask_logic_io_is_branch_2_T_1 = ~_dec_brmask_logic_io_is_branch_2_T; // @[core.scala:600:{41,59}] wire _dec_brmask_logic_io_is_branch_2_T_2 = ~dec_uops_2_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_2_T_3 = dec_uops_2_is_br & _dec_brmask_logic_io_is_branch_2_T_2; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_2_T_4 = _dec_brmask_logic_io_is_branch_2_T_3 | dec_uops_2_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_2_T_5 = _dec_brmask_logic_io_is_branch_2_T_1 & _dec_brmask_logic_io_is_branch_2_T_4; // @[core.scala:600:{41,63}] wire _dec_brmask_logic_io_will_fire_2_T = ~dec_uops_2_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_2_T_1 = dec_uops_2_is_br & _dec_brmask_logic_io_will_fire_2_T; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_2_T_2 = _dec_brmask_logic_io_will_fire_2_T_1 | dec_uops_2_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_2_T_3 = dec_fire_2 & _dec_brmask_logic_io_will_fire_2_T_2; // @[core.scala:159:24, :601:54] wire _GEN_22 = dis_uops_0_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52] wire _dis_uops_0_prs1_T; // @[core.scala:654:52] assign _dis_uops_0_prs1_T = _GEN_22; // @[core.scala:654:52] wire _dis_uops_0_prs1_busy_T_2; // @[core.scala:665:73] assign _dis_uops_0_prs1_busy_T_2 = _GEN_22; // @[core.scala:654:52, :665:73] wire _GEN_23 = dis_uops_0_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52] wire _dis_uops_0_prs1_T_1; // @[core.scala:655:52] assign _dis_uops_0_prs1_T_1 = _GEN_23; // @[core.scala:655:52] wire _dis_uops_0_prs1_busy_T; // @[core.scala:664:73] assign _dis_uops_0_prs1_busy_T = _GEN_23; // @[core.scala:655:52, :664:73] wire [6:0] _dis_uops_0_prs1_T_2 = _dis_uops_0_prs1_T_1 ? _rename_stage_io_ren2_uops_0_prs1 : {1'h0, dis_uops_0_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}] assign _dis_uops_0_prs1_T_3 = _dis_uops_0_prs1_T ? _fp_rename_stage_io_ren2_uops_0_prs1 : _dis_uops_0_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28] assign dis_uops_0_prs1 = _dis_uops_0_prs1_T_3; // @[core.scala:167:24, :654:28] wire _GEN_24 = dis_uops_0_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52] wire _dis_uops_0_prs2_T; // @[core.scala:656:52] assign _dis_uops_0_prs2_T = _GEN_24; // @[core.scala:656:52] wire _dis_uops_0_prs2_busy_T_2; // @[core.scala:667:73] assign _dis_uops_0_prs2_busy_T_2 = _GEN_24; // @[core.scala:656:52, :667:73] assign _dis_uops_0_prs2_T_1 = _dis_uops_0_prs2_T ? _fp_rename_stage_io_ren2_uops_0_prs2 : _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}] assign dis_uops_0_prs2 = _dis_uops_0_prs2_T_1; // @[core.scala:167:24, :656:28] wire _GEN_25 = dis_uops_0_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52] wire _dis_uops_0_pdst_T; // @[core.scala:659:52] assign _dis_uops_0_pdst_T = _GEN_25; // @[core.scala:659:52] wire _dis_uops_0_stale_pdst_T; // @[core.scala:662:57] assign _dis_uops_0_stale_pdst_T = _GEN_25; // @[core.scala:659:52, :662:57] wire _dis_uops_0_pdst_T_1 = dis_uops_0_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52] wire [6:0] _dis_uops_0_pdst_T_2 = _dis_uops_0_pdst_T_1 ? _rename_stage_io_ren2_uops_0_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}] assign _dis_uops_0_pdst_T_3 = _dis_uops_0_pdst_T ? _fp_rename_stage_io_ren2_uops_0_pdst : _dis_uops_0_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28] assign dis_uops_0_pdst = _dis_uops_0_pdst_T_3; // @[core.scala:167:24, :659:28] assign _dis_uops_0_stale_pdst_T_1 = _dis_uops_0_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_0_stale_pdst : _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}] assign dis_uops_0_stale_pdst = _dis_uops_0_stale_pdst_T_1; // @[core.scala:167:24, :662:34] wire _dis_uops_0_prs1_busy_T_1 = _rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}] wire _dis_uops_0_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}] assign _dis_uops_0_prs1_busy_T_4 = _dis_uops_0_prs1_busy_T_1 | _dis_uops_0_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46] assign dis_uops_0_prs1_busy = _dis_uops_0_prs1_busy_T_4; // @[core.scala:167:24, :664:85] wire _dis_uops_0_prs2_busy_T = dis_uops_0_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73] wire _dis_uops_0_prs2_busy_T_1 = _rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}] wire _dis_uops_0_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}] assign _dis_uops_0_prs2_busy_T_4 = _dis_uops_0_prs2_busy_T_1 | _dis_uops_0_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46] assign dis_uops_0_prs2_busy = _dis_uops_0_prs2_busy_T_4; // @[core.scala:167:24, :666:85] assign _dis_uops_0_prs3_busy_T = _fp_rename_stage_io_ren2_uops_0_prs3_busy & dis_uops_0_frs3_en; // @[core.scala:104:46, :167:24, :668:46] assign dis_uops_0_prs3_busy = _dis_uops_0_prs3_busy_T; // @[core.scala:167:24, :668:46] wire _dis_uops_0_ppred_busy_T = ~dis_uops_0_is_br; // @[core.scala:167:24] wire _dis_uops_0_ppred_busy_T_1 = _dis_uops_0_ppred_busy_T & dis_uops_0_is_sfb; // @[core.scala:167:24] wire _ren_stalls_0_T = _rename_stage_io_ren_stalls_0 | _fp_rename_stage_io_ren_stalls_0; // @[core.scala:103:32, :104:46, :671:52] assign _ren_stalls_0_T_1 = _ren_stalls_0_T; // @[core.scala:671:{52,63}] assign ren_stalls_0 = _ren_stalls_0_T_1; // @[core.scala:163:24, :671:63] wire _GEN_26 = dis_uops_1_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52] wire _dis_uops_1_prs1_T; // @[core.scala:654:52] assign _dis_uops_1_prs1_T = _GEN_26; // @[core.scala:654:52] wire _dis_uops_1_prs1_busy_T_2; // @[core.scala:665:73] assign _dis_uops_1_prs1_busy_T_2 = _GEN_26; // @[core.scala:654:52, :665:73] wire _GEN_27 = dis_uops_1_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52] wire _dis_uops_1_prs1_T_1; // @[core.scala:655:52] assign _dis_uops_1_prs1_T_1 = _GEN_27; // @[core.scala:655:52] wire _dis_uops_1_prs1_busy_T; // @[core.scala:664:73] assign _dis_uops_1_prs1_busy_T = _GEN_27; // @[core.scala:655:52, :664:73] wire [6:0] _dis_uops_1_prs1_T_2 = _dis_uops_1_prs1_T_1 ? _rename_stage_io_ren2_uops_1_prs1 : {1'h0, dis_uops_1_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}] assign _dis_uops_1_prs1_T_3 = _dis_uops_1_prs1_T ? _fp_rename_stage_io_ren2_uops_1_prs1 : _dis_uops_1_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28] assign dis_uops_1_prs1 = _dis_uops_1_prs1_T_3; // @[core.scala:167:24, :654:28] wire _GEN_28 = dis_uops_1_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52] wire _dis_uops_1_prs2_T; // @[core.scala:656:52] assign _dis_uops_1_prs2_T = _GEN_28; // @[core.scala:656:52] wire _dis_uops_1_prs2_busy_T_2; // @[core.scala:667:73] assign _dis_uops_1_prs2_busy_T_2 = _GEN_28; // @[core.scala:656:52, :667:73] assign _dis_uops_1_prs2_T_1 = _dis_uops_1_prs2_T ? _fp_rename_stage_io_ren2_uops_1_prs2 : _rename_stage_io_ren2_uops_1_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}] assign dis_uops_1_prs2 = _dis_uops_1_prs2_T_1; // @[core.scala:167:24, :656:28] wire _GEN_29 = dis_uops_1_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52] wire _dis_uops_1_pdst_T; // @[core.scala:659:52] assign _dis_uops_1_pdst_T = _GEN_29; // @[core.scala:659:52] wire _dis_uops_1_stale_pdst_T; // @[core.scala:662:57] assign _dis_uops_1_stale_pdst_T = _GEN_29; // @[core.scala:659:52, :662:57] wire _dis_uops_1_pdst_T_1 = dis_uops_1_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52] wire [6:0] _dis_uops_1_pdst_T_2 = _dis_uops_1_pdst_T_1 ? _rename_stage_io_ren2_uops_1_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}] assign _dis_uops_1_pdst_T_3 = _dis_uops_1_pdst_T ? _fp_rename_stage_io_ren2_uops_1_pdst : _dis_uops_1_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28] assign dis_uops_1_pdst = _dis_uops_1_pdst_T_3; // @[core.scala:167:24, :659:28] assign _dis_uops_1_stale_pdst_T_1 = _dis_uops_1_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_1_stale_pdst : _rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}] assign dis_uops_1_stale_pdst = _dis_uops_1_stale_pdst_T_1; // @[core.scala:167:24, :662:34] wire _dis_uops_1_prs1_busy_T_1 = _rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}] wire _dis_uops_1_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}] assign _dis_uops_1_prs1_busy_T_4 = _dis_uops_1_prs1_busy_T_1 | _dis_uops_1_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46] assign dis_uops_1_prs1_busy = _dis_uops_1_prs1_busy_T_4; // @[core.scala:167:24, :664:85] wire _dis_uops_1_prs2_busy_T = dis_uops_1_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73] wire _dis_uops_1_prs2_busy_T_1 = _rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}] wire _dis_uops_1_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}] assign _dis_uops_1_prs2_busy_T_4 = _dis_uops_1_prs2_busy_T_1 | _dis_uops_1_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46] assign dis_uops_1_prs2_busy = _dis_uops_1_prs2_busy_T_4; // @[core.scala:167:24, :666:85] assign _dis_uops_1_prs3_busy_T = _fp_rename_stage_io_ren2_uops_1_prs3_busy & dis_uops_1_frs3_en; // @[core.scala:104:46, :167:24, :668:46] assign dis_uops_1_prs3_busy = _dis_uops_1_prs3_busy_T; // @[core.scala:167:24, :668:46] wire _dis_uops_1_ppred_busy_T = ~dis_uops_1_is_br; // @[core.scala:167:24] wire _dis_uops_1_ppred_busy_T_1 = _dis_uops_1_ppred_busy_T & dis_uops_1_is_sfb; // @[core.scala:167:24] wire _ren_stalls_1_T = _rename_stage_io_ren_stalls_1 | _fp_rename_stage_io_ren_stalls_1; // @[core.scala:103:32, :104:46, :671:52] assign _ren_stalls_1_T_1 = _ren_stalls_1_T; // @[core.scala:671:{52,63}] assign ren_stalls_1 = _ren_stalls_1_T_1; // @[core.scala:163:24, :671:63] wire _GEN_30 = dis_uops_2_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52] wire _dis_uops_2_prs1_T; // @[core.scala:654:52] assign _dis_uops_2_prs1_T = _GEN_30; // @[core.scala:654:52] wire _dis_uops_2_prs1_busy_T_2; // @[core.scala:665:73] assign _dis_uops_2_prs1_busy_T_2 = _GEN_30; // @[core.scala:654:52, :665:73] wire _GEN_31 = dis_uops_2_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52] wire _dis_uops_2_prs1_T_1; // @[core.scala:655:52] assign _dis_uops_2_prs1_T_1 = _GEN_31; // @[core.scala:655:52] wire _dis_uops_2_prs1_busy_T; // @[core.scala:664:73] assign _dis_uops_2_prs1_busy_T = _GEN_31; // @[core.scala:655:52, :664:73] wire [6:0] _dis_uops_2_prs1_T_2 = _dis_uops_2_prs1_T_1 ? _rename_stage_io_ren2_uops_2_prs1 : {1'h0, dis_uops_2_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}] assign _dis_uops_2_prs1_T_3 = _dis_uops_2_prs1_T ? _fp_rename_stage_io_ren2_uops_2_prs1 : _dis_uops_2_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28] assign dis_uops_2_prs1 = _dis_uops_2_prs1_T_3; // @[core.scala:167:24, :654:28] wire _GEN_32 = dis_uops_2_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52] wire _dis_uops_2_prs2_T; // @[core.scala:656:52] assign _dis_uops_2_prs2_T = _GEN_32; // @[core.scala:656:52] wire _dis_uops_2_prs2_busy_T_2; // @[core.scala:667:73] assign _dis_uops_2_prs2_busy_T_2 = _GEN_32; // @[core.scala:656:52, :667:73] assign _dis_uops_2_prs2_T_1 = _dis_uops_2_prs2_T ? _fp_rename_stage_io_ren2_uops_2_prs2 : _rename_stage_io_ren2_uops_2_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}] assign dis_uops_2_prs2 = _dis_uops_2_prs2_T_1; // @[core.scala:167:24, :656:28] wire _GEN_33 = dis_uops_2_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52] wire _dis_uops_2_pdst_T; // @[core.scala:659:52] assign _dis_uops_2_pdst_T = _GEN_33; // @[core.scala:659:52] wire _dis_uops_2_stale_pdst_T; // @[core.scala:662:57] assign _dis_uops_2_stale_pdst_T = _GEN_33; // @[core.scala:659:52, :662:57] wire _dis_uops_2_pdst_T_1 = dis_uops_2_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52] wire [6:0] _dis_uops_2_pdst_T_2 = _dis_uops_2_pdst_T_1 ? _rename_stage_io_ren2_uops_2_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}] assign _dis_uops_2_pdst_T_3 = _dis_uops_2_pdst_T ? _fp_rename_stage_io_ren2_uops_2_pdst : _dis_uops_2_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28] assign dis_uops_2_pdst = _dis_uops_2_pdst_T_3; // @[core.scala:167:24, :659:28] assign _dis_uops_2_stale_pdst_T_1 = _dis_uops_2_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_2_stale_pdst : _rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}] assign dis_uops_2_stale_pdst = _dis_uops_2_stale_pdst_T_1; // @[core.scala:167:24, :662:34] wire _dis_uops_2_prs1_busy_T_1 = _rename_stage_io_ren2_uops_2_prs1_busy & _dis_uops_2_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}] wire _dis_uops_2_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_2_prs1_busy & _dis_uops_2_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}] assign _dis_uops_2_prs1_busy_T_4 = _dis_uops_2_prs1_busy_T_1 | _dis_uops_2_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46] assign dis_uops_2_prs1_busy = _dis_uops_2_prs1_busy_T_4; // @[core.scala:167:24, :664:85] wire _dis_uops_2_prs2_busy_T = dis_uops_2_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73] wire _dis_uops_2_prs2_busy_T_1 = _rename_stage_io_ren2_uops_2_prs2_busy & _dis_uops_2_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}] wire _dis_uops_2_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_2_prs2_busy & _dis_uops_2_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}] assign _dis_uops_2_prs2_busy_T_4 = _dis_uops_2_prs2_busy_T_1 | _dis_uops_2_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46] assign dis_uops_2_prs2_busy = _dis_uops_2_prs2_busy_T_4; // @[core.scala:167:24, :666:85] assign _dis_uops_2_prs3_busy_T = _fp_rename_stage_io_ren2_uops_2_prs3_busy & dis_uops_2_frs3_en; // @[core.scala:104:46, :167:24, :668:46] assign dis_uops_2_prs3_busy = _dis_uops_2_prs3_busy_T; // @[core.scala:167:24, :668:46] wire _dis_uops_2_ppred_busy_T = ~dis_uops_2_is_br; // @[core.scala:167:24] wire _dis_uops_2_ppred_busy_T_1 = _dis_uops_2_ppred_busy_T & dis_uops_2_is_sfb; // @[core.scala:167:24] wire _ren_stalls_2_T = _rename_stage_io_ren_stalls_2 | _fp_rename_stage_io_ren_stalls_2; // @[core.scala:103:32, :104:46, :671:52] assign _ren_stalls_2_T_1 = _ren_stalls_2_T; // @[core.scala:671:{52,63}] assign ren_stalls_2 = _ren_stalls_2_T_1; // @[core.scala:163:24, :671:63] wire dis_prior_slot_valid_2 = dis_prior_slot_valid_1 | dis_valids_1; // @[core.scala:166:24, :683:71] wire dis_prior_slot_valid_3 = dis_prior_slot_valid_2 | dis_valids_2; // @[core.scala:166:24, :683:71] wire _dis_prior_slot_unique_T = dis_valids_0 & dis_uops_0_is_unique; // @[core.scala:166:24, :167:24, :684:101] wire dis_prior_slot_unique_1 = _dis_prior_slot_unique_T; // @[core.scala:684:{96,101}] wire _dis_prior_slot_unique_T_1 = dis_valids_1 & dis_uops_1_is_unique; // @[core.scala:166:24, :167:24, :684:101] wire dis_prior_slot_unique_2 = dis_prior_slot_unique_1 | _dis_prior_slot_unique_T_1; // @[core.scala:684:{96,101}] wire _dis_prior_slot_unique_T_2 = dis_valids_2 & dis_uops_2_is_unique; // @[core.scala:166:24, :167:24, :684:101] wire dis_prior_slot_unique_3 = dis_prior_slot_unique_2 | _dis_prior_slot_unique_T_2; // @[core.scala:684:{96,101}] wire _wait_for_empty_pipeline_T = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25] wire _wait_for_empty_pipeline_T_6 = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25] wire _wait_for_empty_pipeline_T_12 = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25] wire _wait_for_empty_pipeline_T_1 = dis_uops_0_is_unique | _wait_for_empty_pipeline_T; // @[core.scala:167:24, :685:85] wire _wait_for_empty_pipeline_T_2 = ~_rob_io_empty; // @[core.scala:143:32, :686:36] wire _wait_for_empty_pipeline_T_3 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53] wire _wait_for_empty_pipeline_T_4 = _wait_for_empty_pipeline_T_2 | _wait_for_empty_pipeline_T_3; // @[core.scala:686:{36,50,53}] wire _wait_for_empty_pipeline_T_5 = _wait_for_empty_pipeline_T_4; // @[core.scala:686:{50,72}] wire wait_for_empty_pipeline_0 = _wait_for_empty_pipeline_T_1 & _wait_for_empty_pipeline_T_5; // @[core.scala:685:{85,112}, :686:72] wire _wait_for_empty_pipeline_T_7 = dis_uops_1_is_unique | _wait_for_empty_pipeline_T_6; // @[core.scala:167:24, :685:85] wire _wait_for_empty_pipeline_T_8 = ~_rob_io_empty; // @[core.scala:143:32, :686:36] wire _wait_for_empty_pipeline_T_9 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53] wire _wait_for_empty_pipeline_T_10 = _wait_for_empty_pipeline_T_8 | _wait_for_empty_pipeline_T_9; // @[core.scala:686:{36,50,53}] wire _wait_for_empty_pipeline_T_11 = _wait_for_empty_pipeline_T_10 | dis_prior_slot_valid_1; // @[core.scala:683:71, :686:{50,72}] wire wait_for_empty_pipeline_1 = _wait_for_empty_pipeline_T_7 & _wait_for_empty_pipeline_T_11; // @[core.scala:685:{85,112}, :686:72] wire _wait_for_empty_pipeline_T_13 = dis_uops_2_is_unique | _wait_for_empty_pipeline_T_12; // @[core.scala:167:24, :685:85] wire _wait_for_empty_pipeline_T_14 = ~_rob_io_empty; // @[core.scala:143:32, :686:36] wire _wait_for_empty_pipeline_T_15 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53] wire _wait_for_empty_pipeline_T_16 = _wait_for_empty_pipeline_T_14 | _wait_for_empty_pipeline_T_15; // @[core.scala:686:{36,50,53}] wire _wait_for_empty_pipeline_T_17 = _wait_for_empty_pipeline_T_16 | dis_prior_slot_valid_2; // @[core.scala:683:71, :686:{50,72}] wire wait_for_empty_pipeline_2 = _wait_for_empty_pipeline_T_13 & _wait_for_empty_pipeline_T_17; // @[core.scala:685:{85,112}, :686:72] wire _wait_for_rocc_T = dis_uops_0_is_fence | dis_uops_0_is_fencei; // @[core.scala:167:24, :689:47] wire _wait_for_rocc_T_2 = dis_uops_1_is_fence | dis_uops_1_is_fencei; // @[core.scala:167:24, :689:47] wire _wait_for_rocc_T_4 = dis_uops_2_is_fence | dis_uops_2_is_fencei; // @[core.scala:167:24, :689:47] wire _GEN_34 = dis_uops_0_uopc == 7'h6C; // @[core.scala:167:24, :691:76] wire _block_rocc_T; // @[core.scala:691:76] assign _block_rocc_T = _GEN_34; // @[core.scala:691:76] wire _dis_rocc_alloc_stall_T; // @[core.scala:692:51] assign _dis_rocc_alloc_stall_T = _GEN_34; // @[core.scala:691:76, :692:51] wire _block_rocc_T_1 = dis_valids_0 & _block_rocc_T; // @[core.scala:166:24, :691:{66,76}] wire block_rocc_1 = _block_rocc_T_1; // @[core.scala:691:{66,109}] wire _GEN_35 = dis_uops_1_uopc == 7'h6C; // @[core.scala:167:24, :691:76] wire _block_rocc_T_2; // @[core.scala:691:76] assign _block_rocc_T_2 = _GEN_35; // @[core.scala:691:76] wire _dis_rocc_alloc_stall_T_1; // @[core.scala:692:51] assign _dis_rocc_alloc_stall_T_1 = _GEN_35; // @[core.scala:691:76, :692:51] wire _block_rocc_T_3 = dis_valids_1 & _block_rocc_T_2; // @[core.scala:166:24, :691:{66,76}] wire _GEN_36 = dis_uops_2_uopc == 7'h6C; // @[core.scala:167:24, :691:76] wire _block_rocc_T_4; // @[core.scala:691:76] assign _block_rocc_T_4 = _GEN_36; // @[core.scala:691:76] wire _dis_rocc_alloc_stall_T_2; // @[core.scala:692:51] assign _dis_rocc_alloc_stall_T_2 = _GEN_36; // @[core.scala:691:76, :692:51] wire _block_rocc_T_5 = dis_valids_2 & _block_rocc_T_4; // @[core.scala:166:24, :691:{66,76}] wire block_rocc_2 = block_rocc_1 | _block_rocc_T_3; // @[core.scala:691:{66,109}] wire block_rocc_3 = block_rocc_2 | _block_rocc_T_5; // @[core.scala:691:{66,109}] wire _dis_hazards_T = ~_rob_io_ready; // @[core.scala:143:32, :697:26] wire _dis_hazards_T_1 = _dis_hazards_T | ren_stalls_0; // @[core.scala:163:24, :697:26, :698:23] wire _dis_hazards_T_2 = io_lsu_ldq_full_0_0 & dis_uops_0_uses_ldq; // @[core.scala:51:7, :167:24, :699:45] wire _dis_hazards_T_3 = _dis_hazards_T_1 | _dis_hazards_T_2; // @[core.scala:698:23, :699:{23,45}] wire _dis_hazards_T_4 = io_lsu_stq_full_0_0 & dis_uops_0_uses_stq; // @[core.scala:51:7, :167:24, :700:45] wire _dis_hazards_T_5 = _dis_hazards_T_3 | _dis_hazards_T_4; // @[core.scala:699:23, :700:{23,45}] wire _dis_hazards_T_6 = ~_dispatcher_io_ren_uops_0_ready; // @[core.scala:114:32, :701:26] wire _dis_hazards_T_7 = _dis_hazards_T_5 | _dis_hazards_T_6; // @[core.scala:700:23, :701:{23,26}] wire _dis_hazards_T_8 = _dis_hazards_T_7 | wait_for_empty_pipeline_0; // @[core.scala:685:112, :701:23, :702:23] wire _dis_hazards_T_9 = _dis_hazards_T_8; // @[core.scala:702:23, :703:23] wire _dis_hazards_T_10 = _dis_hazards_T_9; // @[core.scala:703:23, :704:23] wire _dis_hazards_T_11 = _dis_hazards_T_10; // @[core.scala:704:23, :705:23] wire _dis_hazards_T_12 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54] wire _dis_hazards_T_13 = _dis_hazards_T_11 | _dis_hazards_T_12; // @[core.scala:705:23, :706:{23,54}] wire _dis_hazards_T_14 = _dis_hazards_T_13 | brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23] wire _dis_hazards_T_15 = _dis_hazards_T_14 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23] wire dis_hazards_0 = dis_valids_0 & _dis_hazards_T_15; // @[core.scala:166:24, :696:37, :708:23] wire dis_stalls_0 = dis_hazards_0; // @[core.scala:696:37, :713:62] wire _dis_hazards_T_16 = ~_rob_io_ready; // @[core.scala:143:32, :697:26] wire _dis_hazards_T_17 = _dis_hazards_T_16 | ren_stalls_1; // @[core.scala:163:24, :697:26, :698:23] wire _dis_hazards_T_18 = io_lsu_ldq_full_1_0 & dis_uops_1_uses_ldq; // @[core.scala:51:7, :167:24, :699:45] wire _dis_hazards_T_19 = _dis_hazards_T_17 | _dis_hazards_T_18; // @[core.scala:698:23, :699:{23,45}] wire _dis_hazards_T_20 = io_lsu_stq_full_1_0 & dis_uops_1_uses_stq; // @[core.scala:51:7, :167:24, :700:45] wire _dis_hazards_T_21 = _dis_hazards_T_19 | _dis_hazards_T_20; // @[core.scala:699:23, :700:{23,45}] wire _dis_hazards_T_22 = ~_dispatcher_io_ren_uops_1_ready; // @[core.scala:114:32, :701:26] wire _dis_hazards_T_23 = _dis_hazards_T_21 | _dis_hazards_T_22; // @[core.scala:700:23, :701:{23,26}] wire _dis_hazards_T_24 = _dis_hazards_T_23 | wait_for_empty_pipeline_1; // @[core.scala:685:112, :701:23, :702:23] wire _dis_hazards_T_25 = _dis_hazards_T_24; // @[core.scala:702:23, :703:23] wire _dis_hazards_T_26 = _dis_hazards_T_25 | dis_prior_slot_unique_1; // @[core.scala:684:96, :703:23, :704:23] wire _dis_hazards_T_27 = _dis_hazards_T_26; // @[core.scala:704:23, :705:23] wire _dis_hazards_T_28 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54] wire _dis_hazards_T_29 = _dis_hazards_T_27 | _dis_hazards_T_28; // @[core.scala:705:23, :706:{23,54}] wire _dis_hazards_T_30 = _dis_hazards_T_29 | brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23] wire _dis_hazards_T_31 = _dis_hazards_T_30 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23] wire dis_hazards_1 = dis_valids_1 & _dis_hazards_T_31; // @[core.scala:166:24, :696:37, :708:23] wire _dis_hazards_T_32 = ~_rob_io_ready; // @[core.scala:143:32, :697:26] wire _dis_hazards_T_33 = _dis_hazards_T_32 | ren_stalls_2; // @[core.scala:163:24, :697:26, :698:23] wire _dis_hazards_T_34 = io_lsu_ldq_full_2_0 & dis_uops_2_uses_ldq; // @[core.scala:51:7, :167:24, :699:45] wire _dis_hazards_T_35 = _dis_hazards_T_33 | _dis_hazards_T_34; // @[core.scala:698:23, :699:{23,45}] wire _dis_hazards_T_36 = io_lsu_stq_full_2_0 & dis_uops_2_uses_stq; // @[core.scala:51:7, :167:24, :700:45] wire _dis_hazards_T_37 = _dis_hazards_T_35 | _dis_hazards_T_36; // @[core.scala:699:23, :700:{23,45}] wire _dis_hazards_T_38 = ~_dispatcher_io_ren_uops_2_ready; // @[core.scala:114:32, :701:26] wire _dis_hazards_T_39 = _dis_hazards_T_37 | _dis_hazards_T_38; // @[core.scala:700:23, :701:{23,26}] wire _dis_hazards_T_40 = _dis_hazards_T_39 | wait_for_empty_pipeline_2; // @[core.scala:685:112, :701:23, :702:23] wire _dis_hazards_T_41 = _dis_hazards_T_40; // @[core.scala:702:23, :703:23] wire _dis_hazards_T_42 = _dis_hazards_T_41 | dis_prior_slot_unique_2; // @[core.scala:684:96, :703:23, :704:23] wire _dis_hazards_T_43 = _dis_hazards_T_42; // @[core.scala:704:23, :705:23] wire _dis_hazards_T_44 = |brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54] wire _dis_hazards_T_45 = _dis_hazards_T_43 | _dis_hazards_T_44; // @[core.scala:705:23, :706:{23,54}] wire _dis_hazards_T_46 = _dis_hazards_T_45 | brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23] wire _dis_hazards_T_47 = _dis_hazards_T_46 | io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23] wire dis_hazards_2 = dis_valids_2 & _dis_hazards_T_47; // @[core.scala:166:24, :696:37, :708:23] wire _io_lsu_fence_dmem_T = dis_valids_0 & wait_for_empty_pipeline_0; // @[core.scala:166:24, :685:112, :711:86] wire _io_lsu_fence_dmem_T_1 = dis_valids_1 & wait_for_empty_pipeline_1; // @[core.scala:166:24, :685:112, :711:86] wire _io_lsu_fence_dmem_T_2 = dis_valids_2 & wait_for_empty_pipeline_2; // @[core.scala:166:24, :685:112, :711:86] wire _io_lsu_fence_dmem_T_3 = _io_lsu_fence_dmem_T | _io_lsu_fence_dmem_T_1; // @[core.scala:711:{86,101}] assign _io_lsu_fence_dmem_T_4 = _io_lsu_fence_dmem_T_3 | _io_lsu_fence_dmem_T_2; // @[core.scala:711:{86,101}] assign io_lsu_fence_dmem_0 = _io_lsu_fence_dmem_T_4; // @[core.scala:51:7, :711:101] wire dis_stalls_1 = dis_stalls_0 | dis_hazards_1; // @[core.scala:696:37, :713:62] wire dis_stalls_2 = dis_stalls_1 | dis_hazards_2; // @[core.scala:696:37, :713:62] assign dis_fire_0 = dis_valids_0 & ~dis_stalls_0; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}] assign dis_fire_1 = dis_valids_1 & ~dis_stalls_1; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}] assign dis_fire_2 = dis_valids_2 & ~dis_stalls_2; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}] assign _dis_ready_T = ~dis_stalls_2; // @[core.scala:713:62, :714:65, :715:16] assign dis_ready = _dis_ready_T; // @[core.scala:169:24, :715:16] reg REG_3; // @[core.scala:738:16] assign io_ifu_commit_valid_0 = REG_3 | _io_ifu_commit_valid_T_2; // @[core.scala:51:7, :466:{23,59}, :738:{16,94}, :739:25] wire [1:0] _io_ifu_commit_bits_T_1 = dis_valids_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70] wire [1:0] _io_ifu_commit_bits_T_2 = dis_valids_0 ? 2'h0 : _io_ifu_commit_bits_T_1; // @[Mux.scala:50:70] reg [4:0] io_ifu_commit_bits_REG; // @[core.scala:740:35] assign io_ifu_commit_bits_0 = {27'h0, REG_3 ? io_ifu_commit_bits_REG : _io_ifu_commit_bits_T}; // @[core.scala:51:7, :467:{23,29}, :738:{16,94}, :740:{25,35}] wire [6:0] _GEN_37 = {2'h0, _rob_io_rob_tail_idx[6:2]}; // @[core.scala:143:32, :749:54] wire [6:0] _dis_uops_0_rob_idx_T; // @[core.scala:749:54] assign _dis_uops_0_rob_idx_T = _GEN_37; // @[core.scala:749:54] wire [6:0] _dis_uops_1_rob_idx_T; // @[core.scala:749:54] assign _dis_uops_1_rob_idx_T = _GEN_37; // @[core.scala:749:54] wire [6:0] _dis_uops_2_rob_idx_T; // @[core.scala:749:54] assign _dis_uops_2_rob_idx_T = _GEN_37; // @[core.scala:749:54] wire [8:0] _dis_uops_0_rob_idx_T_1 = {_dis_uops_0_rob_idx_T, 2'h0}; // @[core.scala:749:{33,54}] assign dis_uops_0_rob_idx = _dis_uops_0_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}] wire [8:0] _dis_uops_1_rob_idx_T_1 = {_dis_uops_1_rob_idx_T, 2'h1}; // @[core.scala:749:{33,54}] assign dis_uops_1_rob_idx = _dis_uops_1_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}] wire [8:0] _dis_uops_2_rob_idx_T_1 = {_dis_uops_2_rob_idx_T, 2'h2}; // @[core.scala:749:{33,54}] assign dis_uops_2_rob_idx = _dis_uops_2_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}] wire _GEN_38 = _ll_wbarb_io_out_bits_uop_dst_rtype == 2'h0; // @[core.scala:132:32, :795:90] wire _int_iss_wakeups_0_valid_T_1; // @[core.scala:795:90] assign _int_iss_wakeups_0_valid_T_1 = _GEN_38; // @[core.scala:795:90] wire _int_ren_wakeups_0_valid_T_1; // @[core.scala:798:90] assign _int_ren_wakeups_0_valid_T_1 = _GEN_38; // @[core.scala:795:90, :798:90] wire _iregfile_io_write_ports_0_wport_valid_T; // @[regfile.scala:57:61] assign _iregfile_io_write_ports_0_wport_valid_T = _GEN_38; // @[regfile.scala:57:61] wire _int_iss_wakeups_0_valid_T; // @[Decoupled.scala:51:35] assign _int_iss_wakeups_0_valid_T_2 = _int_iss_wakeups_0_valid_T & _int_iss_wakeups_0_valid_T_1; // @[Decoupled.scala:51:35] assign int_iss_wakeups_0_valid = _int_iss_wakeups_0_valid_T_2; // @[core.scala:147:30, :795:52] wire _int_ren_wakeups_0_valid_T; // @[Decoupled.scala:51:35] assign _int_ren_wakeups_0_valid_T_2 = _int_ren_wakeups_0_valid_T & _int_ren_wakeups_0_valid_T_1; // @[Decoupled.scala:51:35] assign int_ren_wakeups_0_valid = _int_ren_wakeups_0_valid_T_2; // @[core.scala:148:30, :798:52] wire _fast_wakeup_valid_T_7; // @[core.scala:827:52] assign int_iss_wakeups_1_valid = fast_wakeup_valid; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_valid = fast_wakeup_valid; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29] wire _slow_wakeup_valid_T_5; // @[core.scala:834:59] assign int_iss_wakeups_2_valid = slow_wakeup_valid; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_valid = slow_wakeup_valid; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29] wire _T_99 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T; // @[micro-op.scala:149:36] assign _slow_wakeup_valid_T = _T_99; // @[micro-op.scala:149:36] wire _iregfile_io_write_ports_1_valid_T; // @[micro-op.scala:149:36] assign _iregfile_io_write_ports_1_valid_T = _T_99; // @[micro-op.scala:149:36] wire _rob_io_debug_wb_valids_1_T; // @[micro-op.scala:149:36] assign _rob_io_debug_wb_valids_1_T = _T_99; // @[micro-op.scala:149:36] wire _fast_wakeup_valid_T = iss_valids_1 & iss_uops_1_bypassable; // @[core.scala:172:24, :173:24, :824:45] wire _fast_wakeup_valid_T_1 = iss_uops_1_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53] wire _fast_wakeup_valid_T_2 = _fast_wakeup_valid_T & _fast_wakeup_valid_T_1; // @[core.scala:824:45, :825:54, :826:53] wire _fast_wakeup_valid_T_3 = _fast_wakeup_valid_T_2 & iss_uops_1_ldst_val; // @[core.scala:173:24, :825:54, :826:64] wire _GEN_39 = iss_uops_1_iw_p1_poisoned | iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24, :828:79] wire _fast_wakeup_valid_T_4; // @[core.scala:828:79] assign _fast_wakeup_valid_T_4 = _GEN_39; // @[core.scala:828:79] wire _pred_wakeup_valid_T_3; // @[core.scala:864:84] assign _pred_wakeup_valid_T_3 = _GEN_39; // @[core.scala:828:79, :864:84] wire _iregister_read_io_iss_valids_1_T; // @[core.scala:981:72] assign _iregister_read_io_iss_valids_1_T = _GEN_39; // @[core.scala:828:79, :981:72] wire _fast_wakeup_valid_T_5 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_4; // @[core.scala:51:7, :828:{48,79}] wire _fast_wakeup_valid_T_6 = ~_fast_wakeup_valid_T_5; // @[core.scala:828:{31,48}] assign _fast_wakeup_valid_T_7 = _fast_wakeup_valid_T_3 & _fast_wakeup_valid_T_6; // @[core.scala:826:64, :827:52, :828:31] assign fast_wakeup_valid = _fast_wakeup_valid_T_7; // @[core.scala:814:29, :827:52] wire _slow_wakeup_valid_T_1 = _alu_exe_unit_io_iresp_valid & _slow_wakeup_valid_T; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_2 = ~_alu_exe_unit_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_3 = _slow_wakeup_valid_T_1 & _slow_wakeup_valid_T_2; // @[core.scala:832:42, :833:54, :834:33] wire _T_93 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_4; // @[core.scala:835:57] assign _slow_wakeup_valid_T_4 = _T_93; // @[core.scala:835:57] wire _iregfile_io_write_ports_1_valid_T_2; // @[core.scala:1160:77] assign _iregfile_io_write_ports_1_valid_T_2 = _T_93; // @[core.scala:835:57, :1160:77] wire _rob_io_debug_wb_valids_1_T_2; // @[core.scala:1240:86] assign _rob_io_debug_wb_valids_1_T_2 = _T_93; // @[core.scala:835:57, :1240:86] assign _slow_wakeup_valid_T_5 = _slow_wakeup_valid_T_3 & _slow_wakeup_valid_T_4; // @[core.scala:833:54, :834:59, :835:57] assign slow_wakeup_valid = _slow_wakeup_valid_T_5; // @[core.scala:815:29, :834:59] wire _fast_wakeup_valid_T_15; // @[core.scala:827:52] assign int_iss_wakeups_3_valid = fast_wakeup_1_valid; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_valid = fast_wakeup_1_valid; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_uopc = fast_wakeup_1_bits_uop_uopc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_uopc = fast_wakeup_1_bits_uop_uopc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_inst = fast_wakeup_1_bits_uop_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_inst = fast_wakeup_1_bits_uop_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_debug_inst = fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_debug_inst = fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_rvc = fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_rvc = fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_debug_pc = fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_debug_pc = fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_iq_type = fast_wakeup_1_bits_uop_iq_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_iq_type = fast_wakeup_1_bits_uop_iq_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_fu_code = fast_wakeup_1_bits_uop_fu_code; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_fu_code = fast_wakeup_1_bits_uop_fu_code; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_br_type = fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_br_type = fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_op1_sel = fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_op1_sel = fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_op2_sel = fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_op2_sel = fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_imm_sel = fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_imm_sel = fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_op_fcn = fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_op_fcn = fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_fcn_dw = fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_fcn_dw = fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_csr_cmd = fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_csr_cmd = fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_is_load = fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_is_load = fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_is_sta = fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_is_sta = fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_is_std = fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_is_std = fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_iw_state = fast_wakeup_1_bits_uop_iw_state; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_iw_state = fast_wakeup_1_bits_uop_iw_state; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_iw_p1_poisoned = fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_iw_p1_poisoned = fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_iw_p2_poisoned = fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_iw_p2_poisoned = fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_br = fast_wakeup_1_bits_uop_is_br; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_br = fast_wakeup_1_bits_uop_is_br; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_jalr = fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_jalr = fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_jal = fast_wakeup_1_bits_uop_is_jal; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_jal = fast_wakeup_1_bits_uop_is_jal; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_sfb = fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_sfb = fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_br_mask = fast_wakeup_1_bits_uop_br_mask; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_br_mask = fast_wakeup_1_bits_uop_br_mask; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_br_tag = fast_wakeup_1_bits_uop_br_tag; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_br_tag = fast_wakeup_1_bits_uop_br_tag; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ftq_idx = fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ftq_idx = fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_edge_inst = fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_edge_inst = fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_pc_lob = fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_pc_lob = fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_taken = fast_wakeup_1_bits_uop_taken; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_taken = fast_wakeup_1_bits_uop_taken; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_imm_packed = fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_imm_packed = fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_csr_addr = fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_csr_addr = fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_rob_idx = fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_rob_idx = fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ldq_idx = fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ldq_idx = fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_stq_idx = fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_stq_idx = fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_rxq_idx = fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_rxq_idx = fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_pdst = fast_wakeup_1_bits_uop_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_pdst = fast_wakeup_1_bits_uop_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs1 = fast_wakeup_1_bits_uop_prs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs1 = fast_wakeup_1_bits_uop_prs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs2 = fast_wakeup_1_bits_uop_prs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs2 = fast_wakeup_1_bits_uop_prs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs3 = fast_wakeup_1_bits_uop_prs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs3 = fast_wakeup_1_bits_uop_prs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ppred = fast_wakeup_1_bits_uop_ppred; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ppred = fast_wakeup_1_bits_uop_ppred; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs1_busy = fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs1_busy = fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs2_busy = fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs2_busy = fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs3_busy = fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs3_busy = fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ppred_busy = fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ppred_busy = fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_stale_pdst = fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_stale_pdst = fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_exception = fast_wakeup_1_bits_uop_exception; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_exception = fast_wakeup_1_bits_uop_exception; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_exc_cause = fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_exc_cause = fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_bypassable = fast_wakeup_1_bits_uop_bypassable; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_bypassable = fast_wakeup_1_bits_uop_bypassable; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_mem_cmd = fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_mem_cmd = fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_mem_size = fast_wakeup_1_bits_uop_mem_size; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_mem_size = fast_wakeup_1_bits_uop_mem_size; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_mem_signed = fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_mem_signed = fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_fence = fast_wakeup_1_bits_uop_is_fence; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_fence = fast_wakeup_1_bits_uop_is_fence; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_fencei = fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_fencei = fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_amo = fast_wakeup_1_bits_uop_is_amo; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_amo = fast_wakeup_1_bits_uop_is_amo; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_uses_ldq = fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_uses_ldq = fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_uses_stq = fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_uses_stq = fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_sys_pc2epc = fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_sys_pc2epc = fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_unique = fast_wakeup_1_bits_uop_is_unique; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_unique = fast_wakeup_1_bits_uop_is_unique; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_flush_on_commit = fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_flush_on_commit = fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ldst_is_rs1 = fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ldst_is_rs1 = fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ldst = fast_wakeup_1_bits_uop_ldst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ldst = fast_wakeup_1_bits_uop_ldst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs1 = fast_wakeup_1_bits_uop_lrs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs1 = fast_wakeup_1_bits_uop_lrs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs2 = fast_wakeup_1_bits_uop_lrs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs2 = fast_wakeup_1_bits_uop_lrs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs3 = fast_wakeup_1_bits_uop_lrs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs3 = fast_wakeup_1_bits_uop_lrs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ldst_val = fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ldst_val = fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_dst_rtype = fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_dst_rtype = fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs1_rtype = fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs1_rtype = fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs2_rtype = fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs2_rtype = fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_frs3_en = fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_frs3_en = fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_fp_val = fast_wakeup_1_bits_uop_fp_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_fp_val = fast_wakeup_1_bits_uop_fp_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_fp_single = fast_wakeup_1_bits_uop_fp_single; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_fp_single = fast_wakeup_1_bits_uop_fp_single; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_xcpt_pf_if = fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_xcpt_pf_if = fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_xcpt_ae_if = fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_xcpt_ae_if = fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_xcpt_ma_if = fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_xcpt_ma_if = fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_bp_debug_if = fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_bp_debug_if = fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_bp_xcpt_if = fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_bp_xcpt_if = fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_debug_fsrc = fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_debug_fsrc = fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_debug_tsrc = fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_debug_tsrc = fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29] wire _slow_wakeup_valid_T_11; // @[core.scala:834:59] assign int_iss_wakeups_4_valid = slow_wakeup_1_valid; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_valid = slow_wakeup_1_valid; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_uopc = slow_wakeup_1_bits_uop_uopc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_uopc = slow_wakeup_1_bits_uop_uopc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_inst = slow_wakeup_1_bits_uop_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_inst = slow_wakeup_1_bits_uop_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_debug_inst = slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_debug_inst = slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_rvc = slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_rvc = slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_debug_pc = slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_debug_pc = slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_iq_type = slow_wakeup_1_bits_uop_iq_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_iq_type = slow_wakeup_1_bits_uop_iq_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_fu_code = slow_wakeup_1_bits_uop_fu_code; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_fu_code = slow_wakeup_1_bits_uop_fu_code; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_br_type = slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_br_type = slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_op1_sel = slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_op1_sel = slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_op2_sel = slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_op2_sel = slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_imm_sel = slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_imm_sel = slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_op_fcn = slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_op_fcn = slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_fcn_dw = slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_fcn_dw = slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_csr_cmd = slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_csr_cmd = slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_is_load = slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_is_load = slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_is_sta = slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_is_sta = slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_is_std = slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_is_std = slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_iw_state = slow_wakeup_1_bits_uop_iw_state; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_iw_state = slow_wakeup_1_bits_uop_iw_state; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_iw_p1_poisoned = slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_iw_p1_poisoned = slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_iw_p2_poisoned = slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_iw_p2_poisoned = slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_br = slow_wakeup_1_bits_uop_is_br; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_br = slow_wakeup_1_bits_uop_is_br; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_jalr = slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_jalr = slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_jal = slow_wakeup_1_bits_uop_is_jal; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_jal = slow_wakeup_1_bits_uop_is_jal; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_sfb = slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_sfb = slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_br_mask = slow_wakeup_1_bits_uop_br_mask; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_br_mask = slow_wakeup_1_bits_uop_br_mask; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_br_tag = slow_wakeup_1_bits_uop_br_tag; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_br_tag = slow_wakeup_1_bits_uop_br_tag; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ftq_idx = slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ftq_idx = slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_edge_inst = slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_edge_inst = slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_pc_lob = slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_pc_lob = slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_taken = slow_wakeup_1_bits_uop_taken; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_taken = slow_wakeup_1_bits_uop_taken; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_imm_packed = slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_imm_packed = slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_csr_addr = slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_csr_addr = slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_rob_idx = slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_rob_idx = slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ldq_idx = slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ldq_idx = slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_stq_idx = slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_stq_idx = slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_rxq_idx = slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_rxq_idx = slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_pdst = slow_wakeup_1_bits_uop_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_pdst = slow_wakeup_1_bits_uop_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs1 = slow_wakeup_1_bits_uop_prs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs1 = slow_wakeup_1_bits_uop_prs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs2 = slow_wakeup_1_bits_uop_prs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs2 = slow_wakeup_1_bits_uop_prs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs3 = slow_wakeup_1_bits_uop_prs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs3 = slow_wakeup_1_bits_uop_prs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ppred = slow_wakeup_1_bits_uop_ppred; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ppred = slow_wakeup_1_bits_uop_ppred; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs1_busy = slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs1_busy = slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs2_busy = slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs2_busy = slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs3_busy = slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs3_busy = slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ppred_busy = slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ppred_busy = slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_stale_pdst = slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_stale_pdst = slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_exception = slow_wakeup_1_bits_uop_exception; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_exception = slow_wakeup_1_bits_uop_exception; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_exc_cause = slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_exc_cause = slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_bypassable = slow_wakeup_1_bits_uop_bypassable; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_bypassable = slow_wakeup_1_bits_uop_bypassable; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_mem_cmd = slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_mem_cmd = slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_mem_size = slow_wakeup_1_bits_uop_mem_size; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_mem_size = slow_wakeup_1_bits_uop_mem_size; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_mem_signed = slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_mem_signed = slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_fence = slow_wakeup_1_bits_uop_is_fence; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_fence = slow_wakeup_1_bits_uop_is_fence; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_fencei = slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_fencei = slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_amo = slow_wakeup_1_bits_uop_is_amo; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_amo = slow_wakeup_1_bits_uop_is_amo; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_uses_ldq = slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_uses_ldq = slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_uses_stq = slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_uses_stq = slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_sys_pc2epc = slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_sys_pc2epc = slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_unique = slow_wakeup_1_bits_uop_is_unique; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_unique = slow_wakeup_1_bits_uop_is_unique; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_flush_on_commit = slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_flush_on_commit = slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ldst_is_rs1 = slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ldst_is_rs1 = slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ldst = slow_wakeup_1_bits_uop_ldst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ldst = slow_wakeup_1_bits_uop_ldst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs1 = slow_wakeup_1_bits_uop_lrs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs1 = slow_wakeup_1_bits_uop_lrs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs2 = slow_wakeup_1_bits_uop_lrs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs2 = slow_wakeup_1_bits_uop_lrs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs3 = slow_wakeup_1_bits_uop_lrs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs3 = slow_wakeup_1_bits_uop_lrs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ldst_val = slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ldst_val = slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_dst_rtype = slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_dst_rtype = slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs1_rtype = slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs1_rtype = slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs2_rtype = slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs2_rtype = slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_frs3_en = slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_frs3_en = slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_fp_val = slow_wakeup_1_bits_uop_fp_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_fp_val = slow_wakeup_1_bits_uop_fp_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_fp_single = slow_wakeup_1_bits_uop_fp_single; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_fp_single = slow_wakeup_1_bits_uop_fp_single; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_xcpt_pf_if = slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_xcpt_pf_if = slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_xcpt_ae_if = slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_xcpt_ae_if = slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_xcpt_ma_if = slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_xcpt_ma_if = slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_bp_debug_if = slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_bp_debug_if = slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_bp_xcpt_if = slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_bp_xcpt_if = slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_debug_fsrc = slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_debug_fsrc = slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_debug_tsrc = slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_debug_tsrc = slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29] wire _T_124 = _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_6; // @[micro-op.scala:149:36] assign _slow_wakeup_valid_T_6 = _T_124; // @[micro-op.scala:149:36] wire _iregfile_io_write_ports_2_valid_T; // @[micro-op.scala:149:36] assign _iregfile_io_write_ports_2_valid_T = _T_124; // @[micro-op.scala:149:36] wire _rob_io_debug_wb_valids_2_T; // @[micro-op.scala:149:36] assign _rob_io_debug_wb_valids_2_T = _T_124; // @[micro-op.scala:149:36] wire _fast_wakeup_valid_T_8 = iss_valids_2 & iss_uops_2_bypassable; // @[core.scala:172:24, :173:24, :824:45] wire _fast_wakeup_valid_T_9 = iss_uops_2_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53] wire _fast_wakeup_valid_T_10 = _fast_wakeup_valid_T_8 & _fast_wakeup_valid_T_9; // @[core.scala:824:45, :825:54, :826:53] wire _fast_wakeup_valid_T_11 = _fast_wakeup_valid_T_10 & iss_uops_2_ldst_val; // @[core.scala:173:24, :825:54, :826:64] wire _GEN_40 = iss_uops_2_iw_p1_poisoned | iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24, :828:79] wire _fast_wakeup_valid_T_12; // @[core.scala:828:79] assign _fast_wakeup_valid_T_12 = _GEN_40; // @[core.scala:828:79] wire _iregister_read_io_iss_valids_2_T; // @[core.scala:981:72] assign _iregister_read_io_iss_valids_2_T = _GEN_40; // @[core.scala:828:79, :981:72] wire _fast_wakeup_valid_T_13 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_12; // @[core.scala:51:7, :828:{48,79}] wire _fast_wakeup_valid_T_14 = ~_fast_wakeup_valid_T_13; // @[core.scala:828:{31,48}] assign _fast_wakeup_valid_T_15 = _fast_wakeup_valid_T_11 & _fast_wakeup_valid_T_14; // @[core.scala:826:64, :827:52, :828:31] assign fast_wakeup_1_valid = _fast_wakeup_valid_T_15; // @[core.scala:814:29, :827:52] wire _slow_wakeup_valid_T_7 = _alu_exe_unit_1_io_iresp_valid & _slow_wakeup_valid_T_6; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_8 = ~_alu_exe_unit_1_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_9 = _slow_wakeup_valid_T_7 & _slow_wakeup_valid_T_8; // @[core.scala:832:42, :833:54, :834:33] wire _T_118 = _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_10; // @[core.scala:835:57] assign _slow_wakeup_valid_T_10 = _T_118; // @[core.scala:835:57] wire _iregfile_io_write_ports_2_valid_T_2; // @[core.scala:1160:77] assign _iregfile_io_write_ports_2_valid_T_2 = _T_118; // @[core.scala:835:57, :1160:77] wire _rob_io_debug_wb_valids_2_T_2; // @[core.scala:1240:86] assign _rob_io_debug_wb_valids_2_T_2 = _T_118; // @[core.scala:835:57, :1240:86] assign _slow_wakeup_valid_T_11 = _slow_wakeup_valid_T_9 & _slow_wakeup_valid_T_10; // @[core.scala:833:54, :834:59, :835:57] assign slow_wakeup_1_valid = _slow_wakeup_valid_T_11; // @[core.scala:815:29, :834:59] wire _fast_wakeup_valid_T_23; // @[core.scala:827:52] assign int_iss_wakeups_5_valid = fast_wakeup_2_valid; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_valid = fast_wakeup_2_valid; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_uopc = fast_wakeup_2_bits_uop_uopc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_uopc = fast_wakeup_2_bits_uop_uopc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_inst = fast_wakeup_2_bits_uop_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_inst = fast_wakeup_2_bits_uop_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_debug_inst = fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_debug_inst = fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_rvc = fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_rvc = fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_debug_pc = fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_debug_pc = fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_iq_type = fast_wakeup_2_bits_uop_iq_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_iq_type = fast_wakeup_2_bits_uop_iq_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_fu_code = fast_wakeup_2_bits_uop_fu_code; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_fu_code = fast_wakeup_2_bits_uop_fu_code; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_br_type = fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_br_type = fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_op1_sel = fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_op1_sel = fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_op2_sel = fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_op2_sel = fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_imm_sel = fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_imm_sel = fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_op_fcn = fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_op_fcn = fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_fcn_dw = fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_fcn_dw = fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_csr_cmd = fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_csr_cmd = fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_is_load = fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_is_load = fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_is_sta = fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_is_sta = fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_is_std = fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_is_std = fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_iw_state = fast_wakeup_2_bits_uop_iw_state; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_iw_state = fast_wakeup_2_bits_uop_iw_state; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_iw_p1_poisoned = fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_iw_p1_poisoned = fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_iw_p2_poisoned = fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_iw_p2_poisoned = fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_br = fast_wakeup_2_bits_uop_is_br; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_br = fast_wakeup_2_bits_uop_is_br; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_jalr = fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_jalr = fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_jal = fast_wakeup_2_bits_uop_is_jal; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_jal = fast_wakeup_2_bits_uop_is_jal; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_sfb = fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_sfb = fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_br_mask = fast_wakeup_2_bits_uop_br_mask; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_br_mask = fast_wakeup_2_bits_uop_br_mask; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_br_tag = fast_wakeup_2_bits_uop_br_tag; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_br_tag = fast_wakeup_2_bits_uop_br_tag; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ftq_idx = fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ftq_idx = fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_edge_inst = fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_edge_inst = fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_pc_lob = fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_pc_lob = fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_taken = fast_wakeup_2_bits_uop_taken; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_taken = fast_wakeup_2_bits_uop_taken; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_imm_packed = fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_imm_packed = fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_csr_addr = fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_csr_addr = fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_rob_idx = fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_rob_idx = fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ldq_idx = fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ldq_idx = fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_stq_idx = fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_stq_idx = fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_rxq_idx = fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_rxq_idx = fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_pdst = fast_wakeup_2_bits_uop_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_pdst = fast_wakeup_2_bits_uop_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs1 = fast_wakeup_2_bits_uop_prs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs1 = fast_wakeup_2_bits_uop_prs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs2 = fast_wakeup_2_bits_uop_prs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs2 = fast_wakeup_2_bits_uop_prs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs3 = fast_wakeup_2_bits_uop_prs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs3 = fast_wakeup_2_bits_uop_prs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ppred = fast_wakeup_2_bits_uop_ppred; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ppred = fast_wakeup_2_bits_uop_ppred; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs1_busy = fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs1_busy = fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs2_busy = fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs2_busy = fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs3_busy = fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs3_busy = fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ppred_busy = fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ppred_busy = fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_stale_pdst = fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_stale_pdst = fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_exception = fast_wakeup_2_bits_uop_exception; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_exception = fast_wakeup_2_bits_uop_exception; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_exc_cause = fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_exc_cause = fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_bypassable = fast_wakeup_2_bits_uop_bypassable; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_bypassable = fast_wakeup_2_bits_uop_bypassable; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_mem_cmd = fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_mem_cmd = fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_mem_size = fast_wakeup_2_bits_uop_mem_size; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_mem_size = fast_wakeup_2_bits_uop_mem_size; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_mem_signed = fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_mem_signed = fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_fence = fast_wakeup_2_bits_uop_is_fence; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_fence = fast_wakeup_2_bits_uop_is_fence; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_fencei = fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_fencei = fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_amo = fast_wakeup_2_bits_uop_is_amo; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_amo = fast_wakeup_2_bits_uop_is_amo; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_uses_ldq = fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_uses_ldq = fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_uses_stq = fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_uses_stq = fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_sys_pc2epc = fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_sys_pc2epc = fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_unique = fast_wakeup_2_bits_uop_is_unique; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_unique = fast_wakeup_2_bits_uop_is_unique; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_flush_on_commit = fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_flush_on_commit = fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ldst_is_rs1 = fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ldst_is_rs1 = fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ldst = fast_wakeup_2_bits_uop_ldst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ldst = fast_wakeup_2_bits_uop_ldst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs1 = fast_wakeup_2_bits_uop_lrs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs1 = fast_wakeup_2_bits_uop_lrs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs2 = fast_wakeup_2_bits_uop_lrs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs2 = fast_wakeup_2_bits_uop_lrs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs3 = fast_wakeup_2_bits_uop_lrs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs3 = fast_wakeup_2_bits_uop_lrs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ldst_val = fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ldst_val = fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_dst_rtype = fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_dst_rtype = fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs1_rtype = fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs1_rtype = fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs2_rtype = fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs2_rtype = fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_frs3_en = fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_frs3_en = fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_fp_val = fast_wakeup_2_bits_uop_fp_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_fp_val = fast_wakeup_2_bits_uop_fp_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_fp_single = fast_wakeup_2_bits_uop_fp_single; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_fp_single = fast_wakeup_2_bits_uop_fp_single; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_xcpt_pf_if = fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_xcpt_pf_if = fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_xcpt_ae_if = fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_xcpt_ae_if = fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_xcpt_ma_if = fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_xcpt_ma_if = fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_bp_debug_if = fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_bp_debug_if = fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_bp_xcpt_if = fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_bp_xcpt_if = fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_debug_fsrc = fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_debug_fsrc = fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_debug_tsrc = fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_debug_tsrc = fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29] wire _slow_wakeup_valid_T_17; // @[core.scala:834:59] assign int_iss_wakeups_6_valid = slow_wakeup_2_valid; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_valid = slow_wakeup_2_valid; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_uopc = slow_wakeup_2_bits_uop_uopc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_uopc = slow_wakeup_2_bits_uop_uopc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_inst = slow_wakeup_2_bits_uop_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_inst = slow_wakeup_2_bits_uop_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_debug_inst = slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_debug_inst = slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_rvc = slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_rvc = slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_debug_pc = slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_debug_pc = slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_iq_type = slow_wakeup_2_bits_uop_iq_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_iq_type = slow_wakeup_2_bits_uop_iq_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_fu_code = slow_wakeup_2_bits_uop_fu_code; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_fu_code = slow_wakeup_2_bits_uop_fu_code; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_br_type = slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_br_type = slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_op1_sel = slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_op1_sel = slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_op2_sel = slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_op2_sel = slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_imm_sel = slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_imm_sel = slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_op_fcn = slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_op_fcn = slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_fcn_dw = slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_fcn_dw = slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_csr_cmd = slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_csr_cmd = slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_is_load = slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_is_load = slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_is_sta = slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_is_sta = slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_is_std = slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_is_std = slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_iw_state = slow_wakeup_2_bits_uop_iw_state; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_iw_state = slow_wakeup_2_bits_uop_iw_state; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_iw_p1_poisoned = slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_iw_p1_poisoned = slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_iw_p2_poisoned = slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_iw_p2_poisoned = slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_br = slow_wakeup_2_bits_uop_is_br; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_br = slow_wakeup_2_bits_uop_is_br; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_jalr = slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_jalr = slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_jal = slow_wakeup_2_bits_uop_is_jal; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_jal = slow_wakeup_2_bits_uop_is_jal; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_sfb = slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_sfb = slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_br_mask = slow_wakeup_2_bits_uop_br_mask; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_br_mask = slow_wakeup_2_bits_uop_br_mask; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_br_tag = slow_wakeup_2_bits_uop_br_tag; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_br_tag = slow_wakeup_2_bits_uop_br_tag; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ftq_idx = slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ftq_idx = slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_edge_inst = slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_edge_inst = slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_pc_lob = slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_pc_lob = slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_taken = slow_wakeup_2_bits_uop_taken; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_taken = slow_wakeup_2_bits_uop_taken; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_imm_packed = slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_imm_packed = slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_csr_addr = slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_csr_addr = slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_rob_idx = slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_rob_idx = slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ldq_idx = slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ldq_idx = slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_stq_idx = slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_stq_idx = slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_rxq_idx = slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_rxq_idx = slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_pdst = slow_wakeup_2_bits_uop_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_pdst = slow_wakeup_2_bits_uop_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs1 = slow_wakeup_2_bits_uop_prs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs1 = slow_wakeup_2_bits_uop_prs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs2 = slow_wakeup_2_bits_uop_prs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs2 = slow_wakeup_2_bits_uop_prs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs3 = slow_wakeup_2_bits_uop_prs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs3 = slow_wakeup_2_bits_uop_prs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ppred = slow_wakeup_2_bits_uop_ppred; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ppred = slow_wakeup_2_bits_uop_ppred; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs1_busy = slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs1_busy = slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs2_busy = slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs2_busy = slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs3_busy = slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs3_busy = slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ppred_busy = slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ppred_busy = slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_stale_pdst = slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_stale_pdst = slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_exception = slow_wakeup_2_bits_uop_exception; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_exception = slow_wakeup_2_bits_uop_exception; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_exc_cause = slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_exc_cause = slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_bypassable = slow_wakeup_2_bits_uop_bypassable; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_bypassable = slow_wakeup_2_bits_uop_bypassable; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_mem_cmd = slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_mem_cmd = slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_mem_size = slow_wakeup_2_bits_uop_mem_size; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_mem_size = slow_wakeup_2_bits_uop_mem_size; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_mem_signed = slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_mem_signed = slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_fence = slow_wakeup_2_bits_uop_is_fence; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_fence = slow_wakeup_2_bits_uop_is_fence; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_fencei = slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_fencei = slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_amo = slow_wakeup_2_bits_uop_is_amo; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_amo = slow_wakeup_2_bits_uop_is_amo; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_uses_ldq = slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_uses_ldq = slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_uses_stq = slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_uses_stq = slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_sys_pc2epc = slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_sys_pc2epc = slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_unique = slow_wakeup_2_bits_uop_is_unique; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_unique = slow_wakeup_2_bits_uop_is_unique; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_flush_on_commit = slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_flush_on_commit = slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ldst_is_rs1 = slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ldst_is_rs1 = slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ldst = slow_wakeup_2_bits_uop_ldst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ldst = slow_wakeup_2_bits_uop_ldst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs1 = slow_wakeup_2_bits_uop_lrs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs1 = slow_wakeup_2_bits_uop_lrs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs2 = slow_wakeup_2_bits_uop_lrs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs2 = slow_wakeup_2_bits_uop_lrs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs3 = slow_wakeup_2_bits_uop_lrs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs3 = slow_wakeup_2_bits_uop_lrs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ldst_val = slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ldst_val = slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_dst_rtype = slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_dst_rtype = slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs1_rtype = slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs1_rtype = slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs2_rtype = slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs2_rtype = slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_frs3_en = slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_frs3_en = slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_fp_val = slow_wakeup_2_bits_uop_fp_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_fp_val = slow_wakeup_2_bits_uop_fp_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_fp_single = slow_wakeup_2_bits_uop_fp_single; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_fp_single = slow_wakeup_2_bits_uop_fp_single; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_xcpt_pf_if = slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_xcpt_pf_if = slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_xcpt_ae_if = slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_xcpt_ae_if = slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_xcpt_ma_if = slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_xcpt_ma_if = slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_bp_debug_if = slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_bp_debug_if = slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_bp_xcpt_if = slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_bp_xcpt_if = slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_debug_fsrc = slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_debug_fsrc = slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_debug_tsrc = slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_debug_tsrc = slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29] wire _T_149 = _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_12; // @[micro-op.scala:149:36] assign _slow_wakeup_valid_T_12 = _T_149; // @[micro-op.scala:149:36] wire _iregfile_io_write_ports_3_valid_T; // @[micro-op.scala:149:36] assign _iregfile_io_write_ports_3_valid_T = _T_149; // @[micro-op.scala:149:36] wire _rob_io_debug_wb_valids_3_T; // @[micro-op.scala:149:36] assign _rob_io_debug_wb_valids_3_T = _T_149; // @[micro-op.scala:149:36] wire _fast_wakeup_valid_T_16 = iss_valids_3 & iss_uops_3_bypassable; // @[core.scala:172:24, :173:24, :824:45] wire _fast_wakeup_valid_T_17 = iss_uops_3_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53] wire _fast_wakeup_valid_T_18 = _fast_wakeup_valid_T_16 & _fast_wakeup_valid_T_17; // @[core.scala:824:45, :825:54, :826:53] wire _fast_wakeup_valid_T_19 = _fast_wakeup_valid_T_18 & iss_uops_3_ldst_val; // @[core.scala:173:24, :825:54, :826:64] wire _GEN_41 = iss_uops_3_iw_p1_poisoned | iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24, :828:79] wire _fast_wakeup_valid_T_20; // @[core.scala:828:79] assign _fast_wakeup_valid_T_20 = _GEN_41; // @[core.scala:828:79] wire _iregister_read_io_iss_valids_3_T; // @[core.scala:981:72] assign _iregister_read_io_iss_valids_3_T = _GEN_41; // @[core.scala:828:79, :981:72] wire _fast_wakeup_valid_T_21 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_20; // @[core.scala:51:7, :828:{48,79}] wire _fast_wakeup_valid_T_22 = ~_fast_wakeup_valid_T_21; // @[core.scala:828:{31,48}] assign _fast_wakeup_valid_T_23 = _fast_wakeup_valid_T_19 & _fast_wakeup_valid_T_22; // @[core.scala:826:64, :827:52, :828:31] assign fast_wakeup_2_valid = _fast_wakeup_valid_T_23; // @[core.scala:814:29, :827:52] wire _slow_wakeup_valid_T_13 = _alu_exe_unit_2_io_iresp_valid & _slow_wakeup_valid_T_12; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_14 = ~_alu_exe_unit_2_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_15 = _slow_wakeup_valid_T_13 & _slow_wakeup_valid_T_14; // @[core.scala:832:42, :833:54, :834:33] wire _T_143 = _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_16; // @[core.scala:835:57] assign _slow_wakeup_valid_T_16 = _T_143; // @[core.scala:835:57] wire _iregfile_io_write_ports_3_valid_T_2; // @[core.scala:1160:77] assign _iregfile_io_write_ports_3_valid_T_2 = _T_143; // @[core.scala:835:57, :1160:77] wire _rob_io_debug_wb_valids_3_T_2; // @[core.scala:1240:86] assign _rob_io_debug_wb_valids_3_T_2 = _T_143; // @[core.scala:835:57, :1240:86] assign _slow_wakeup_valid_T_17 = _slow_wakeup_valid_T_15 & _slow_wakeup_valid_T_16; // @[core.scala:833:54, :834:59, :835:57] assign slow_wakeup_2_valid = _slow_wakeup_valid_T_17; // @[core.scala:815:29, :834:59] wire _pred_wakeup_valid_T = iss_uops_1_is_br & iss_uops_1_is_sfb; // @[core.scala:173:24] wire _pred_wakeup_valid_T_4 = io_lsu_ld_miss_0 & _pred_wakeup_valid_T_3; // @[core.scala:51:7, :864:{42,84}] wire _pred_wakeup_valid_T_5 = ~_pred_wakeup_valid_T_4; // @[core.scala:864:{25,42}] wire loads_saturating = _mem_issue_unit_io_iss_valids_0 & _mem_issue_unit_io_iss_uops_0_uses_ldq; // @[core.scala:108:32, :908:57] reg [4:0] saturating_loads_counter; // @[core.scala:909:41] wire [5:0] _saturating_loads_counter_T = {1'h0, saturating_loads_counter} + 6'h1; // @[core.scala:909:41, :910:82] wire [4:0] _saturating_loads_counter_T_1 = _saturating_loads_counter_T[4:0]; // @[core.scala:910:82] reg pause_mem_REG; // @[core.scala:912:26] wire _pause_mem_T_1 = &saturating_loads_counter; // @[core.scala:909:41, :912:73] wire pause_mem = pause_mem_REG & _pause_mem_T_1; // @[core.scala:912:{26,45,73}] wire [9:0] _mem_issue_unit_io_fu_types_0_T = {7'h0, ~pause_mem, 2'h0}; // @[core.scala:912:45, :931:53] wire [9:0] _idiv_issued_T = iss_uops_1_fu_code & 10'h10; // @[core.scala:173:24] wire _idiv_issued_T_1 = |_idiv_issued_T; // @[micro-op.scala:154:{40,47}] wire idiv_issued = iss_valids_1 & _idiv_issued_T_1; // @[core.scala:172:24, :924:47] reg [9:0] REG_4; // @[core.scala:925:38] wire [9:0] _idiv_issued_T_2 = iss_uops_3_fu_code & 10'h10; // @[core.scala:173:24] wire _idiv_issued_T_3 = |_idiv_issued_T_2; // @[micro-op.scala:154:{40,47}] wire idiv_issued_1 = iss_valids_3 & _idiv_issued_T_3; // @[core.scala:172:24, :924:47] reg [9:0] REG_5; // @[core.scala:925:38] reg mem_issue_unit_io_flush_pipeline_REG; // @[core.scala:946:49] reg int_issue_unit_io_flush_pipeline_REG; // @[core.scala:946:49] reg memExeUnit_io_com_exception_REG; // @[core.scala:952:51] wire _GEN_42 = int_iss_wakeups_0_bits_uop_iw_p1_poisoned | int_iss_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_42; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_42; // @[core.scala:961:61] wire _GEN_43 = int_iss_wakeups_1_bits_uop_iw_p1_poisoned | int_iss_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_43; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_43; // @[core.scala:961:61] wire _GEN_44 = int_iss_wakeups_2_bits_uop_iw_p1_poisoned | int_iss_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_44; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_44; // @[core.scala:961:61] wire _GEN_45 = int_iss_wakeups_3_bits_uop_iw_p1_poisoned | int_iss_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T = _GEN_45; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T = _GEN_45; // @[core.scala:961:61] wire _GEN_46 = int_iss_wakeups_4_bits_uop_iw_p1_poisoned | int_iss_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T = _GEN_46; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T = _GEN_46; // @[core.scala:961:61] wire _GEN_47 = int_iss_wakeups_5_bits_uop_iw_p1_poisoned | int_iss_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T = _GEN_47; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T = _GEN_47; // @[core.scala:961:61] wire _GEN_48 = int_iss_wakeups_6_bits_uop_iw_p1_poisoned | int_iss_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T = _GEN_48; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T = _GEN_48; // @[core.scala:961:61] wire _iregister_read_io_iss_valids_0_T = iss_uops_0_iw_p1_poisoned | iss_uops_0_iw_p2_poisoned; // @[core.scala:173:24, :981:72] wire _iregister_read_io_iss_valids_0_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_0_T; // @[core.scala:51:7, :981:{41,72}] wire _iregister_read_io_iss_valids_0_T_2 = ~_iregister_read_io_iss_valids_0_T_1; // @[core.scala:981:{24,41}] wire _iregister_read_io_iss_valids_0_T_3 = iss_valids_0 & _iregister_read_io_iss_valids_0_T_2; // @[core.scala:172:24, :981:{21,24}] wire _iregister_read_io_iss_valids_1_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_1_T; // @[core.scala:51:7, :981:{41,72}] wire _iregister_read_io_iss_valids_1_T_2 = ~_iregister_read_io_iss_valids_1_T_1; // @[core.scala:981:{24,41}] wire _iregister_read_io_iss_valids_1_T_3 = iss_valids_1 & _iregister_read_io_iss_valids_1_T_2; // @[core.scala:172:24, :981:{21,24}] wire _iregister_read_io_iss_valids_2_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_2_T; // @[core.scala:51:7, :981:{41,72}] wire _iregister_read_io_iss_valids_2_T_2 = ~_iregister_read_io_iss_valids_2_T_1; // @[core.scala:981:{24,41}] wire _iregister_read_io_iss_valids_2_T_3 = iss_valids_2 & _iregister_read_io_iss_valids_2_T_2; // @[core.scala:172:24, :981:{21,24}] wire _iregister_read_io_iss_valids_3_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_3_T; // @[core.scala:51:7, :981:{41,72}] wire _iregister_read_io_iss_valids_3_T_2 = ~_iregister_read_io_iss_valids_3_T_1; // @[core.scala:981:{24,41}] wire _iregister_read_io_iss_valids_3_T_3 = iss_valids_3 & _iregister_read_io_iss_valids_3_T_2; // @[core.scala:172:24, :981:{21,24}] reg iregister_read_io_kill_REG; // @[core.scala:987:38] wire [2:0] _csr_io_rw_cmd_T = {~_alu_exe_unit_1_io_iresp_valid, 2'h0}; // @[CSR.scala:183:15] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = _alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd & _csr_io_rw_cmd_T_1; // @[CSR.scala:183:{9,11}] wire [2:0] _csr_io_retire_T = {csr_io_retire_hi, _rob_io_commit_arch_valids_0}; // @[core.scala:143:32, :1015:66] wire _csr_io_retire_T_1 = _csr_io_retire_T[0]; // @[core.scala:1015:{39,66}] wire _csr_io_retire_T_2 = _csr_io_retire_T[1]; // @[core.scala:1015:{39,66}] wire _csr_io_retire_T_3 = _csr_io_retire_T[2]; // @[core.scala:1015:{39,66}] wire [1:0] _csr_io_retire_T_4 = {1'h0, _csr_io_retire_T_2} + {1'h0, _csr_io_retire_T_3}; // @[core.scala:1015:39] wire [1:0] _csr_io_retire_T_5 = _csr_io_retire_T_4; // @[core.scala:1015:39] wire [2:0] _csr_io_retire_T_6 = {2'h0, _csr_io_retire_T_1} + {1'h0, _csr_io_retire_T_5}; // @[core.scala:1015:39] wire [1:0] _csr_io_retire_T_7 = _csr_io_retire_T_6[1:0]; // @[core.scala:1015:39] reg [1:0] csr_io_retire_REG; // @[core.scala:1015:30] reg csr_io_exception_REG; // @[core.scala:1016:30] wire [39:0] _csr_io_pc_T = ~io_ifu_get_pc_0_com_pc_0; // @[util.scala:237:7] wire [39:0] _csr_io_pc_T_1 = {_csr_io_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}] wire [39:0] _csr_io_pc_T_2 = ~_csr_io_pc_T_1; // @[util.scala:237:{5,11}] reg [5:0] csr_io_pc_REG; // @[core.scala:1020:31] wire [40:0] _csr_io_pc_T_3 = {1'h0, _csr_io_pc_T_2} + {35'h0, csr_io_pc_REG}; // @[util.scala:237:5] wire [39:0] _csr_io_pc_T_4 = _csr_io_pc_T_3[39:0]; // @[core.scala:1020:22] reg csr_io_pc_REG_1; // @[core.scala:1021:35] wire [1:0] _csr_io_pc_T_5 = {csr_io_pc_REG_1, 1'h0}; // @[core.scala:1021:{27,35}] wire [40:0] _csr_io_pc_T_6 = {1'h0, _csr_io_pc_T_4} - {39'h0, _csr_io_pc_T_5}; // @[core.scala:1020:22, :1021:{22,27}] wire [39:0] _csr_io_pc_T_7 = _csr_io_pc_T_6[39:0]; // @[core.scala:1021:22] reg [63:0] csr_io_cause_REG; // @[core.scala:1023:30] wire _tval_valid_T = csr_io_cause_REG == 64'h3; // @[package.scala:16:47] wire _tval_valid_T_1 = csr_io_cause_REG == 64'h4; // @[package.scala:16:47] wire _tval_valid_T_2 = csr_io_cause_REG == 64'h6; // @[package.scala:16:47] wire _tval_valid_T_3 = csr_io_cause_REG == 64'h5; // @[package.scala:16:47] wire _tval_valid_T_4 = csr_io_cause_REG == 64'h7; // @[package.scala:16:47] wire _tval_valid_T_5 = csr_io_cause_REG == 64'h1; // @[package.scala:16:47] wire _tval_valid_T_6 = csr_io_cause_REG == 64'hD; // @[package.scala:16:47] wire _tval_valid_T_7 = csr_io_cause_REG == 64'hF; // @[package.scala:16:47] wire _tval_valid_T_8 = csr_io_cause_REG == 64'hC; // @[package.scala:16:47] wire _tval_valid_T_9 = _tval_valid_T | _tval_valid_T_1; // @[package.scala:16:47, :81:59] wire _tval_valid_T_10 = _tval_valid_T_9 | _tval_valid_T_2; // @[package.scala:16:47, :81:59] wire _tval_valid_T_11 = _tval_valid_T_10 | _tval_valid_T_3; // @[package.scala:16:47, :81:59] wire _tval_valid_T_12 = _tval_valid_T_11 | _tval_valid_T_4; // @[package.scala:16:47, :81:59] wire _tval_valid_T_13 = _tval_valid_T_12 | _tval_valid_T_5; // @[package.scala:16:47, :81:59] wire _tval_valid_T_14 = _tval_valid_T_13 | _tval_valid_T_6; // @[package.scala:16:47, :81:59] wire _tval_valid_T_15 = _tval_valid_T_14 | _tval_valid_T_7; // @[package.scala:16:47, :81:59] wire _tval_valid_T_16 = _tval_valid_T_15 | _tval_valid_T_8; // @[package.scala:16:47, :81:59] wire tval_valid = csr_io_exception_REG & _tval_valid_T_16; // @[package.scala:81:59] wire [63:0] _csr_io_tval_a_T; // @[core.scala:1049:18] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T[63:39]; // @[core.scala:1049:{18,25}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[core.scala:1049:25, :1050:23] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[core.scala:1049:25, :1050:36] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T | _csr_io_tval_msb_T_1; // @[core.scala:1050:{23,31,36}] wire _csr_io_tval_msb_T_3 = _rob_io_com_xcpt_bits_badvaddr[39]; // @[core.scala:143:32, :1050:48] wire _csr_io_tval_msb_T_4 = _rob_io_com_xcpt_bits_badvaddr[38]; // @[core.scala:143:32, :1050:64] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[core.scala:1050:{61,64}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[core.scala:1050:{20,31,48,61}] wire [38:0] _csr_io_tval_T = _rob_io_com_xcpt_bits_badvaddr[38:0]; // @[core.scala:143:32, :1051:18] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[core.scala:1050:20, :1051:{10,18}] reg [39:0] csr_io_tval_REG; // @[core.scala:1040:12] wire [39:0] _csr_io_tval_T_2 = tval_valid ? csr_io_tval_REG : 40'h0; // @[core.scala:1026:37, :1039:21, :1040:12] assign bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32] assign bypasses_1_bits_data = _alu_exe_unit_1_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32] assign bypasses_2_bits_data = _alu_exe_unit_2_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32] assign bypasses_3_bits_data = _alu_exe_unit_2_io_bypass_1_bits_data[63:0]; // @[execution-units.scala:119:32] assign bypasses_4_bits_data = _alu_exe_unit_2_io_bypass_2_bits_data[63:0]; // @[execution-units.scala:119:32] assign pred_bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[0]; // @[execution-units.scala:119:32] reg io_lsu_exception_REG; // @[core.scala:1124:30] assign io_lsu_exception_0 = io_lsu_exception_REG; // @[core.scala:51:7, :1124:30] wire _iregfile_io_write_ports_0_wport_valid_T_1; // @[regfile.scala:57:35] wire [6:0] iregfile_io_write_ports_0_wport_bits_addr; // @[regfile.scala:55:22] wire [63:0] iregfile_io_write_ports_0_wport_bits_data; // @[regfile.scala:55:22] wire iregfile_io_write_ports_0_wport_valid; // @[regfile.scala:55:22] assign _iregfile_io_write_ports_0_wport_valid_T_1 = _ll_wbarb_io_out_valid & _iregfile_io_write_ports_0_wport_valid_T; // @[regfile.scala:57:{35,61}] assign iregfile_io_write_ports_0_wport_valid = _iregfile_io_write_ports_0_wport_valid_T_1; // @[regfile.scala:55:22, :57:35] wire wbReadsCSR = |_alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_1_valid_T_1 = _alu_exe_unit_io_iresp_valid & _iregfile_io_write_ports_1_valid_T; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_1_valid_T_3 = _iregfile_io_write_ports_1_valid_T_1 & _iregfile_io_write_ports_1_valid_T_2; // @[core.scala:1160:{22,48,77}] wire wbReadsCSR_1 = |_alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_2_valid_T_1 = _alu_exe_unit_1_io_iresp_valid & _iregfile_io_write_ports_2_valid_T; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_2_valid_T_3 = _iregfile_io_write_ports_2_valid_T_1 & _iregfile_io_write_ports_2_valid_T_2; // @[core.scala:1160:{22,48,77}] wire [64:0] _GEN_49 = {1'h0, _csr_io_rw_rdata}; // @[core.scala:271:19, :1167:56] wire [64:0] _iregfile_io_write_ports_2_bits_data_T = wbReadsCSR_1 ? _GEN_49 : _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32] wire wbReadsCSR_2 = |_alu_exe_unit_2_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_3_valid_T_1 = _alu_exe_unit_2_io_iresp_valid & _iregfile_io_write_ports_3_valid_T; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_3_valid_T_3 = _iregfile_io_write_ports_3_valid_T_1 & _iregfile_io_write_ports_3_valid_T_2; // @[core.scala:1160:{22,48,77}] wire _rob_io_wb_resps_0_valid_T = ~_ll_wbarb_io_out_bits_uop_is_amo; // @[core.scala:132:32, :1217:78] wire _rob_io_wb_resps_0_valid_T_1 = _ll_wbarb_io_out_bits_uop_uses_stq & _rob_io_wb_resps_0_valid_T; // @[core.scala:132:32, :1217:{75,78}] wire _rob_io_wb_resps_0_valid_T_2 = ~_rob_io_wb_resps_0_valid_T_1; // @[core.scala:1217:{57,75}] wire _rob_io_wb_resps_0_valid_T_3 = _ll_wbarb_io_out_valid & _rob_io_wb_resps_0_valid_T_2; // @[core.scala:132:32, :1217:{54,57}] wire _rob_io_debug_wb_valids_0_T = _ll_wbarb_io_out_bits_uop_dst_rtype != 2'h2; // @[core.scala:132:32, :1219:74] wire _rob_io_debug_wb_valids_0_T_1 = _ll_wbarb_io_out_valid & _rob_io_debug_wb_valids_0_T; // @[core.scala:132:32, :1219:{54,74}] wire _rob_io_wb_resps_1_valid_T = ~_alu_exe_unit_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_1_valid_T_1 = _alu_exe_unit_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_1_valid_T; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_1_valid_T_2 = ~_rob_io_wb_resps_1_valid_T_1; // @[core.scala:1238:{51,69}] wire _rob_io_wb_resps_1_valid_T_3 = _alu_exe_unit_io_iresp_valid & _rob_io_wb_resps_1_valid_T_2; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_1_T_1 = _alu_exe_unit_io_iresp_valid & _rob_io_debug_wb_valids_1_T; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_1_T_3 = _rob_io_debug_wb_valids_1_T_1 & _rob_io_debug_wb_valids_1_T_2; // @[core.scala:1240:{49,66,86}] wire _rob_io_wb_resps_2_valid_T = ~_alu_exe_unit_1_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_2_valid_T_1 = _alu_exe_unit_1_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_2_valid_T; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_2_valid_T_2 = ~_rob_io_wb_resps_2_valid_T_1; // @[core.scala:1238:{51,69}] wire _rob_io_wb_resps_2_valid_T_3 = _alu_exe_unit_1_io_iresp_valid & _rob_io_wb_resps_2_valid_T_2; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_2_T_1 = _alu_exe_unit_1_io_iresp_valid & _rob_io_debug_wb_valids_2_T; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_2_T_3 = _rob_io_debug_wb_valids_2_T_1 & _rob_io_debug_wb_valids_2_T_2; // @[core.scala:1240:{49,66,86}] wire _rob_io_debug_wb_wdata_2_T = |_alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire [64:0] _rob_io_debug_wb_wdata_2_T_1 = _rob_io_debug_wb_wdata_2_T ? _GEN_49 : _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_3_valid_T = ~_alu_exe_unit_2_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_3_valid_T_1 = _alu_exe_unit_2_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_3_valid_T; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_3_valid_T_2 = ~_rob_io_wb_resps_3_valid_T_1; // @[core.scala:1238:{51,69}] wire _rob_io_wb_resps_3_valid_T_3 = _alu_exe_unit_2_io_iresp_valid & _rob_io_wb_resps_3_valid_T_2; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_3_T_1 = _alu_exe_unit_2_io_iresp_valid & _rob_io_debug_wb_valids_3_T; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_3_T_3 = _rob_io_debug_wb_valids_3_T_1 & _rob_io_debug_wb_valids_3_T_2; // @[core.scala:1240:{49,66,86}] reg REG_6; // @[core.scala:1306:45] reg memExeUnit_io_req_bits_kill_REG; // @[core.scala:1310:45] reg alu_exe_unit_io_req_bits_kill_REG; // @[core.scala:1310:45] reg alu_exe_unit_io_req_bits_kill_REG_1; // @[core.scala:1310:45] reg alu_exe_unit_io_req_bits_kill_REG_2; // @[core.scala:1310:45] reg [4:0] small_0; // @[Counters.scala:45:41] wire [5:0] nextSmall = {1'h0, small_0} + 6'h1; // @[Counters.scala:45:41, :46:33] reg [26:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[5]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T; // @[Counters.scala:51:{20,33}] wire [27:0] _large_r_T = {1'h0, large_0} + 28'h1; // @[Counters.scala:50:31, :51:55] wire [26:0] _large_r_T_1 = _large_r_T[26:0]; // @[Counters.scala:51:55] wire [31:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire [1:0] hi = {_rob_io_commit_valids_2, _rob_io_commit_valids_1}; // @[core.scala:143:32, :1324:30]
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLAToNoC_3( // @[TilelinkAdapters.scala:112:7] input clock, // @[TilelinkAdapters.scala:112:7] input reset, // @[TilelinkAdapters.scala:112:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}] wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [12:0] _tail_beats1_decode_T = 13'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire [2:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 3'h0 : ~(_tail_beats1_decode_T[5:3]); // @[package.scala:243:{46,71,76}] reg [2:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}] wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 3'h1 | tail_beats1 == 3'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}] assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}] wire _GEN_0 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7] if (reset) begin // @[TilelinkAdapters.scala:112:7] head_counter <= 3'h0; // @[Edges.scala:229:27] tail_counter <= 3'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7] end else begin // @[TilelinkAdapters.scala:112:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 3'h0 : ~(_tail_beats1_decode_T[5:3])) : head_counter - 3'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 3'h0 ? tail_beats1 : tail_counter - 3'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN_0 & io_flit_bits_tail_0) & (_GEN_0 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }
module IntSyncCrossingSource_n1x1_25( // @[Crossing.scala:41:9] input clock, // @[Crossing.scala:41:9] input reset // @[Crossing.scala:41:9] ); wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9] wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9] wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17] AsyncResetRegVec_w1_i0_25 reg_0 ( // @[AsyncResetReg.scala:86:21] .clock (clock), .reset (reset) ); // @[AsyncResetReg.scala:86:21] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_44( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_33 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_35 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_41 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_36 = _source_ok_T_35 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_54 = _source_ok_T_53 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire _source_ok_T_60 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_67 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _T_975 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_975; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_975; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1043 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1043; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1043; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_908 = _T_975 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_908 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_908 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_908 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_908 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_908 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_954 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_954 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_923 = _T_1043 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_923 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_923 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_923 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1019 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1019 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1001 = _T_1043 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1001 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1001 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1001 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File icache.scala: //****************************************************************************** // Copyright (c) 2017 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // ICache //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.ifu import chisel3._ import chisel3.util._ import chisel3.util.random._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property._ import freechips.rocketchip.rocket.{HasL1ICacheParameters, ICacheParams, ICacheErrors, ICacheReq} import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} /** * ICache module * * @param icacheParams parameters for the icache * @param hartId the id of the hardware thread in the cache * @param enableBlackBox use a blackbox icache */ class ICache( val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new ICacheModule(this) val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint name = s"Core ${staticIdForMetadataUseOnly} ICache"))))) val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes private val wordBytes = icacheParams.fetchBytes } /** * IO Signals leaving the ICache * * @param outer top level ICache class */ class ICacheResp(val outer: ICache) extends Bundle { val data = UInt((outer.icacheParams.fetchBytes*8).W) val replay = Bool() val ae = Bool() } /** * IO Signals for interacting with the ICache * * @param outer top level ICache class */ class ICacheBundle(val outer: ICache) extends BoomBundle()(outer.p) with HasBoomFrontendParameters { val req = Flipped(Decoupled(new ICacheReq)) val s1_paddr = Input(UInt(paddrBits.W)) // delayed one cycle w.r.t. req val s1_kill = Input(Bool()) // delayed one cycle w.r.t. req val s2_kill = Input(Bool()) // delayed two cycles; prevents I$ miss emission val resp = Valid(new ICacheResp(outer)) val invalidate = Input(Bool()) val perf = Output(new Bundle { val acquire = Bool() }) } /** * Get a tile-specific property without breaking deduplication */ object GetPropertyByHartId { def apply[T <: Data](tiles: Seq[RocketTileParams], f: RocketTileParams => Option[T], hartId: UInt): T = { PriorityMux(tiles.collect { case t if f(t).isDefined => (t.tileId.U === hartId) -> f(t).get }) } } /** * Main ICache module * * @param outer top level ICache class */ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) with HasBoomFrontendParameters { val enableICacheDelay = tileParams.core.asInstanceOf[BoomCoreParams].enableICacheDelay val io = IO(new ICacheBundle(outer)) val (tl_out, edge_out) = outer.masterNode.out(0) require(isPow2(nSets) && isPow2(nWays)) require(usingVM) require(pgIdxBits >= untagBits) // How many bits do we intend to fetch at most every cycle? val wordBits = outer.icacheParams.fetchBytes*8 // Each of these cases require some special-case handling. require (tl_out.d.bits.data.getWidth == wordBits || (2*tl_out.d.bits.data.getWidth == wordBits && nBanks == 2)) // If TL refill is half the wordBits size and we have two banks, then the // refill writes to only one bank per cycle (instead of across two banks every // cycle). val refillsToOneBank = (2*tl_out.d.bits.data.getWidth == wordBits) val s0_valid = io.req.fire val s0_vaddr = io.req.bits.addr val s1_valid = RegNext(s0_valid) val s1_tag_hit = Wire(Vec(nWays, Bool())) val s1_hit = s1_tag_hit.reduce(_||_) val s2_valid = RegNext(s1_valid && !io.s1_kill) val s2_hit = RegNext(s1_hit) val invalidated = Reg(Bool()) val refill_valid = RegInit(false.B) val refill_fire = tl_out.a.fire val s2_miss = s2_valid && !s2_hit && !RegNext(refill_valid) val refill_paddr = RegEnable(io.s1_paddr, s1_valid && !(refill_valid || s2_miss)) val refill_tag = refill_paddr(tagBits+untagBits-1,untagBits) val refill_idx = refill_paddr(untagBits-1,blockOffBits) val refill_one_beat = tl_out.d.fire && edge_out.hasData(tl_out.d.bits) io.req.ready := !refill_one_beat val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d) val refill_done = refill_one_beat && d_done tl_out.d.ready := true.B require (edge_out.manager.minLatency > 0) val repl_way = if (isDM) 0.U else LFSR(16, refill_fire)(log2Ceil(nWays)-1,0) val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(tagBits.W))) val tag_rdata = tag_array.read(s0_vaddr(untagBits-1, blockOffBits), !refill_done && s0_valid) when (refill_done) { tag_array.write(refill_idx, VecInit(Seq.fill(nWays)(refill_tag)), Seq.tabulate(nWays)(repl_way === _.U)) } val vb_array = RegInit(0.U((nSets*nWays).W)) when (refill_one_beat) { vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated) } when (io.invalidate) { vb_array := 0.U invalidated := true.B } val s2_dout = Wire(Vec(nWays, UInt(wordBits.W))) val s1_bankid = Wire(Bool()) for (i <- 0 until nWays) { val s1_idx = io.s1_paddr(untagBits-1,blockOffBits) val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits) val s1_vb = vb_array(Cat(i.U, s1_idx)) val tag = tag_rdata(i) s1_tag_hit(i) := s1_vb && tag === s1_tag } assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid) val ramDepth = if (refillsToOneBank && nBanks == 2) { nSets * refillCycles / 2 } else { nSets * refillCycles } val dataArrays = if (nBanks == 1) { // Use unbanked icache for narrow accesses. (0 until nWays).map { x => DescribedSRAM( name = s"dataArrayWay_${x}", desc = "ICache Data Array", size = ramDepth, data = UInt((wordBits).W) ) } } else { // Use two banks, interleaved. (0 until nWays).map { x => DescribedSRAM( name = s"dataArrayB0Way_${x}", desc = "ICache Data Array", size = ramDepth, data = UInt((wordBits/nBanks).W) )} ++ (0 until nWays).map { x => DescribedSRAM( name = s"dataArrayB1Way_${x}", desc = "ICache Data Array", size = ramDepth, data = UInt((wordBits/nBanks).W) )} } if (nBanks == 1) { // Use unbanked icache for narrow accesses. s1_bankid := 0.U for ((dataArray, i) <- dataArrays.zipWithIndex) { def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) val s0_ren = s0_valid val wen = (refill_one_beat && !invalidated) && repl_way === i.U val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, row(s0_vaddr)) when (wen) { dataArray.write(mem_idx, tl_out.d.bits.data) } if (enableICacheDelay) s2_dout(i) := dataArray.read(RegNext(mem_idx), RegNext(!wen && s0_ren)) else s2_dout(i) := RegNext(dataArray.read(mem_idx, !wen && s0_ren)) } } else { // Use two banks, interleaved. val dataArraysB0 = dataArrays.take(nWays) val dataArraysB1 = dataArrays.drop(nWays) require (nBanks == 2) // Bank0 row's id wraps around if Bank1 is the starting bank. def b0Row(addr: UInt) = if (refillsToOneBank) { addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)+1) + bank(addr) } else { addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) + bank(addr) } // Bank1 row's id stays the same regardless of which Bank has the fetch address. def b1Row(addr: UInt) = if (refillsToOneBank) { addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)+1) } else { addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) } s1_bankid := RegNext(bank(s0_vaddr)) for (i <- 0 until nWays) { val s0_ren = s0_valid val wen = (refill_one_beat && !invalidated)&& repl_way === i.U var mem_idx0: UInt = null var mem_idx1: UInt = null if (refillsToOneBank) { // write a refill beat across only one beat. mem_idx0 = Mux(refill_one_beat, (refill_idx << (log2Ceil(refillCycles)-1)) | (refill_cnt >> 1.U), b0Row(s0_vaddr)) mem_idx1 = Mux(refill_one_beat, (refill_idx << (log2Ceil(refillCycles)-1)) | (refill_cnt >> 1.U), b1Row(s0_vaddr)) when (wen && refill_cnt(0) === 0.U) { dataArraysB0(i).write(mem_idx0, tl_out.d.bits.data) } when (wen && refill_cnt(0) === 1.U) { dataArraysB1(i).write(mem_idx1, tl_out.d.bits.data) } } else { // write a refill beat across both banks. mem_idx0 = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, b0Row(s0_vaddr)) mem_idx1 = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt, b1Row(s0_vaddr)) when (wen) { val data = tl_out.d.bits.data dataArraysB0(i).write(mem_idx0, data(wordBits/2-1, 0)) dataArraysB1(i).write(mem_idx1, data(wordBits-1, wordBits/2)) } } if (enableICacheDelay) { s2_dout(i) := Cat(dataArraysB1(i).read(RegNext(mem_idx1), RegNext(!wen && s0_ren)), dataArraysB0(i).read(RegNext(mem_idx0), RegNext(!wen && s0_ren))) } else { s2_dout(i) := RegNext(Cat(dataArraysB1(i).read(mem_idx1, !wen && s0_ren), dataArraysB0(i).read(mem_idx0, !wen && s0_ren))) } } } val s2_tag_hit = RegNext(s1_tag_hit) val s2_hit_way = OHToUInt(s2_tag_hit) val s2_bankid = RegNext(s1_bankid) val s2_way_mux = Mux1H(s2_tag_hit, s2_dout) val s2_unbanked_data = s2_way_mux val sz = s2_way_mux.getWidth val s2_bank0_data = s2_way_mux(sz/2-1,0) val s2_bank1_data = s2_way_mux(sz-1,sz/2) val s2_data = if (nBanks == 2) { Mux(s2_bankid, Cat(s2_bank0_data, s2_bank1_data), Cat(s2_bank1_data, s2_bank0_data)) } else { s2_unbanked_data } io.resp.bits.ae := DontCare io.resp.bits.replay := DontCare io.resp.bits.data := s2_data io.resp.valid := s2_valid && s2_hit tl_out.a.valid := s2_miss && !refill_valid && !io.s2_kill tl_out.a.bits := edge_out.Get( fromSource = 0.U, toAddress = (refill_paddr >> blockOffBits) << blockOffBits, lgSize = lgCacheBlockBytes.U)._2 tl_out.b.ready := true.B tl_out.c.valid := false.B tl_out.e.valid := false.B io.perf.acquire := tl_out.a.fire when (!refill_valid) { invalidated := false.B } when (refill_fire) { refill_valid := true.B } when (refill_done) { refill_valid := false.B } override def toString: String = BoomCoreStringPrefix( "==L1-ICache==", "Fetch bytes : " + cacheParams.fetchBytes, "Block bytes : " + (1 << blockOffBits), "Row bytes : " + rowBytes, "Word bits : " + wordBits, "Sets : " + nSets, "Ways : " + nWays, "Refill cycles : " + refillCycles, "RAMs : (" + wordBits/nBanks + " x " + nSets*refillCycles + ") using " + nBanks + " banks", "" + (if (nBanks == 2) "Dual-banked" else "Single-banked"), "I-TLB ways : " + cacheParams.nTLBWays + "\n") }
module tag_array_0( // @[icache.scala:153:30] input [5:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [79:0] RW0_wdata, output [79:0] RW0_rdata, input [3:0] RW0_wmask ); tag_array_0_ext tag_array_0_ext ( // @[icache.scala:153:30] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[icache.scala:153:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_35( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands */ class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def *(t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def *(t: UInt) = self * t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros | ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def *(t: SInt) = self * t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros | ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid || output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid || output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def *(t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def *(t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }
module PE_492( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_236 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File BankBinder.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCustomNode { private val bit = mask & -mask val maxXfer = TransferSizes(1, if (bit == 0 || bit > 4096) 4096 else bit.toInt) val ids = AddressSet.enumerateMask(mask) def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { val ports = ids.size val oStar = if (oStars == 0) 0 else (ports - oKnown) / oStars val iStar = if (iStars == 0) 0 else (ports - iKnown) / iStars require (ports == iKnown + iStar*iStars, s"${name} must have ${ports} inputs, but has ${iKnown} + ${iStar}*${iStars} (at ${lazyModule.line})") require (ports == oKnown + oStar*oStars, s"${name} must have ${ports} outputs, but has ${oKnown} + ${oStar}*${oStars} (at ${lazyModule.line})") (iStar, oStar) } def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = (p zip ids) map { case (cp, id) => cp.v1copy(clients = cp.clients.map { c => c.v1copy( visibility = c.visibility.flatMap { a => a.intersect(AddressSet(id, ~mask))}, supportsProbe = c.supports.probe intersect maxXfer, supportsArithmetic = c.supports.arithmetic intersect maxXfer, supportsLogical = c.supports.logical intersect maxXfer, supportsGet = c.supports.get intersect maxXfer, supportsPutFull = c.supports.putFull intersect maxXfer, supportsPutPartial = c.supports.putPartial intersect maxXfer, supportsHint = c.supports.hint intersect maxXfer)})} def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = (p zip ids) map { case (mp, id) => mp.v1copy(managers = mp.managers.flatMap { m => val addresses = m.address.flatMap(a => a.intersect(AddressSet(id, ~mask))) if (addresses.nonEmpty) Some(m.v1copy( address = addresses, supportsAcquireT = m.supportsAcquireT intersect maxXfer, supportsAcquireB = m.supportsAcquireB intersect maxXfer, supportsArithmetic = m.supportsArithmetic intersect maxXfer, supportsLogical = m.supportsLogical intersect maxXfer, supportsGet = m.supportsGet intersect maxXfer, supportsPutFull = m.supportsPutFull intersect maxXfer, supportsPutPartial = m.supportsPutPartial intersect maxXfer, supportsHint = m.supportsHint intersect maxXfer)) else None })} } /* A BankBinder is used to divide contiguous memory regions into banks, suitable for a cache */ class BankBinder(mask: BigInt)(implicit p: Parameters) extends LazyModule { val node = BankBinderNode(mask) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in } } } object BankBinder { def apply(mask: BigInt)(implicit p: Parameters): TLNode = { val binder = LazyModule(new BankBinder(mask)) binder.node } def apply(nBanks: Int, granularity: Int)(implicit p: Parameters): TLNode = { if (nBanks > 0) apply(granularity * (nBanks-1)) else TLTempNode() } } File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Filter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes} class TLFilter( mfilter: TLFilter.ManagerFilter = TLFilter.mIdentity, cfilter: TLFilter.ClientFilter = TLFilter.cIdentity )(implicit p: Parameters) extends LazyModule { val node = new TLAdapterNode( clientFn = { cp => cp.v1copy(clients = cp.clients.flatMap { c => val out = cfilter(c) out.map { o => // Confirm the filter only REMOVES capability require (c.sourceId.contains(o.sourceId)) require (c.supports.probe.contains(o.supports.probe)) require (c.supports.arithmetic.contains(o.supports.arithmetic)) require (c.supports.logical.contains(o.supports.logical)) require (c.supports.get.contains(o.supports.get)) require (c.supports.putFull.contains(o.supports.putFull)) require (c.supports.putPartial.contains(o.supports.putPartial)) require (c.supports.hint.contains(o.supports.hint)) require (!c.requestFifo || o.requestFifo) } out })}, managerFn = { mp => val managers = mp.managers.flatMap { m => val out = mfilter(m) out.map { o => // Confirm the filter only REMOVES capability o.address.foreach { a => require (m.address.map(_.contains(a)).reduce(_||_)) } require (o.regionType <= m.regionType) // we allow executable to be changed both ways require (m.supportsAcquireT.contains(o.supportsAcquireT)) require (m.supportsAcquireB.contains(o.supportsAcquireB)) require (m.supportsArithmetic.contains(o.supportsArithmetic)) require (m.supportsLogical.contains(o.supportsLogical)) require (m.supportsGet.contains(o.supportsGet)) require (m.supportsPutFull.contains(o.supportsPutFull)) require (m.supportsPutPartial.contains(o.supportsPutPartial)) require (m.supportsHint.contains(o.supportsHint)) require (!o.fifoId.isDefined || m.fifoId == o.fifoId) } out } mp.v1copy(managers = managers, endSinkId = if (managers.exists(_.supportsAcquireB)) mp.endSinkId else 0) } ) { override def circuitIdentity = true } lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in // In case the inner interface removes Acquire, tie-off the channels if (!edgeIn.manager.anySupportAcquireB) { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFilter { type ManagerFilter = TLSlaveParameters => Option[TLSlaveParameters] type ClientFilter = TLMasterParameters => Option[TLMasterParameters] // preserve manager visibility def mIdentity: ManagerFilter = { m => Some(m) } // preserve client visibility def cIdentity: ClientFilter = { c => Some(c) } // make only the intersected address sets visible def mSelectIntersect(select: AddressSet): ManagerFilter = { m => val filtered = m.address.map(_.intersect(select)).flatten val alignment = select.alignment /* alignment 0 means 'select' selected everything */ transferSizeHelper(m, filtered, alignment) } // make everything except the intersected address sets visible def mSubtract(excepts: Seq[AddressSet]): ManagerFilter = { m => val filtered = excepts.foldLeft(m.address) { (a,e) => a.flatMap(_.subtract(e)) } val alignment: BigInt = if (filtered.isEmpty) 0 else filtered.map(_.alignment).min transferSizeHelper(m, filtered, alignment) } def mSubtract(except: AddressSet): ManagerFilter = { m => mSubtract(Seq(except))(m) } // adjust supported transfer sizes based on filtered intersection private def transferSizeHelper(m: TLSlaveParameters, filtered: Seq[AddressSet], alignment: BigInt): Option[TLSlaveParameters] = { val maxTransfer = 1 << 30 val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt val cap = TransferSizes(1, capTransfer) if (filtered.isEmpty) { None } else { Some(m.v1copy( address = filtered, supportsAcquireT = m.supportsAcquireT .intersect(cap), supportsAcquireB = m.supportsAcquireB .intersect(cap), supportsArithmetic = m.supportsArithmetic.intersect(cap), supportsLogical = m.supportsLogical .intersect(cap), supportsGet = m.supportsGet .intersect(cap), supportsPutFull = m.supportsPutFull .intersect(cap), supportsPutPartial = m.supportsPutPartial.intersect(cap), supportsHint = m.supportsHint .intersect(cap))) } } // hide any fully contained address sets def mHideContained(containedBy: AddressSet): ManagerFilter = { m => val filtered = m.address.filterNot(containedBy.contains(_)) if (filtered.isEmpty) None else Some(m.v1copy(address = filtered)) } // hide all cacheable managers def mHideCacheable: ManagerFilter = { m => if (m.supportsAcquireB) None else Some(m) } // make visible only cacheable managers def mSelectCacheable: ManagerFilter = { m => if (m.supportsAcquireB) Some(m) else None } // cacheable managers cannot be acquired from def mMaskCacheable: ManagerFilter = { m => if (m.supportsAcquireB) { Some(m.v1copy( regionType = RegionType.UNCACHED, supportsAcquireB = TransferSizes.none, supportsAcquireT = TransferSizes.none, alwaysGrantsT = false)) } else { Some(m) } } // only cacheable managers are visible, but cannot be acquired from def mSelectAndMaskCacheable: ManagerFilter = { m => if (m.supportsAcquireB) { Some(m.v1copy( regionType = RegionType.UNCACHED, supportsAcquireB = TransferSizes.none, supportsAcquireT = TransferSizes.none, alwaysGrantsT = false)) } else { None } } // hide all caching clients def cHideCaching: ClientFilter = { c => if (c.supports.probe) None else Some(c) } // onyl caching clients are visible def cSelectCaching: ClientFilter = { c => if (c.supports.probe) Some(c) else None } // removes resources from managers def mResourceRemover: ManagerFilter = { m => Some(m.v2copy(resources=Nil)) } // default application applies neither type of filter unless overridden def apply( mfilter: ManagerFilter = TLFilter.mIdentity, cfilter: ClientFilter = TLFilter.cIdentity )(implicit p: Parameters): TLNode = { val filter = LazyModule(new TLFilter(mfilter, cfilter)) filter.node } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File Jbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet class TLJbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule { val node: TLJunctionNode = new TLJunctionNode( clientFn = { seq => Seq.fill(node.dRatio)(seq(0).v1copy( minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } )) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() Seq.fill(node.uRatio)(seq(0).v1copy( minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } )) }) { override def circuitIdentity = uRatio == 1 && dRatio == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { node.inoutGrouped.foreach { case (in, out) => TLXbar.circuit(policy, in, out) } } } object TLJbar { def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) = { val jbar = LazyModule(new TLJbar(policy)) jbar.node } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLJbarTestImp(nClients: Int, nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val jbar = LazyModule(new TLJbar) val fuzzers = Seq.fill(nClients) { val fuzzer = LazyModule(new TLFuzzer(txns)) jbar.node :*= TLXbar() := TLDelayer(0.1) := fuzzer.node fuzzer } for (n <- 0 until nManagers) { TLRAM(AddressSet(0x0+0x400*n, 0x3ff)) := TLFragmenter(4, 256) := TLDelayer(0.1) := jbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.map(_.module.io.finished).reduce(_ && _) } } class TLJbarTest(nClients: Int, nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLJbarTestImp(nClients, nManagers, txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in || corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ || !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready || !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit || !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel | count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Configs.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.tilelink._ import sifive.blocks.inclusivecache._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.inclusivecache.InclusiveCacheParameters case class InclusiveCacheParams( ways: Int, sets: Int, writeBytes: Int, // backing store update granularity portFactor: Int, // numSubBanks = (widest TL port * portFactor) / writeBytes memCycles: Int, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) physicalFilter: Option[PhysicalFilterParams] = None, hintsSkipProbe: Boolean = false, // do hints probe the same client bankedControl: Boolean = false, // bank the cache ctrl with the cache banks ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress), // Interior/Exterior refer to placement either inside the Scheduler or outside it // Inner/Outer refer to buffers on the front (towards cores) or back (towards DDR) of the L2 bufInnerInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, bufInnerExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.flowAD, bufOuterInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.full, bufOuterExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.none) case object InclusiveCacheKey extends Field[InclusiveCacheParams] class WithInclusiveCache( nWays: Int = 8, capacityKB: Int = 512, outerLatencyCycles: Int = 40, subBankingFactor: Int = 4, hintsSkipProbe: Boolean = false, bankedControl: Boolean = false, ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress), writeBytes: Int = 8 ) extends Config((site, here, up) => { case InclusiveCacheKey => InclusiveCacheParams( sets = (capacityKB * 1024)/(site(CacheBlockBytes) * nWays * up(SubsystemBankedCoherenceKey, site).nBanks), ways = nWays, memCycles = outerLatencyCycles, writeBytes = writeBytes, portFactor = subBankingFactor, hintsSkipProbe = hintsSkipProbe, bankedControl = bankedControl, ctrlAddr = ctrlAddr) case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = { context => implicit val p = context.p val sbus = context.tlBusWrapperLocationMap(SBUS) val cbus = context.tlBusWrapperLocationMap.lift(CBUS).getOrElse(sbus) val InclusiveCacheParams( ways, sets, writeBytes, portFactor, memCycles, physicalFilter, hintsSkipProbe, bankedControl, ctrlAddr, bufInnerInterior, bufInnerExterior, bufOuterInterior, bufOuterExterior) = p(InclusiveCacheKey) val l2Ctrl = ctrlAddr.map { addr => InclusiveCacheControlParameters( address = addr, beatBytes = cbus.beatBytes, bankedControl = bankedControl) } val l2 = LazyModule(new InclusiveCache( CacheParameters( level = 2, ways = ways, sets = sets, blockBytes = sbus.blockBytes, beatBytes = sbus.beatBytes, hintsSkipProbe = hintsSkipProbe), InclusiveCacheMicroParameters( writeBytes = writeBytes, portFactor = portFactor, memCycles = memCycles, innerBuf = bufInnerInterior, outerBuf = bufOuterInterior), l2Ctrl)) def skipMMIO(x: TLClientParameters) = { val dcacheMMIO = x.requestFifo && x.sourceId.start % 2 == 1 && // 1 => dcache issues acquires from another master x.nodePath.last.name == "dcache.node" if (dcacheMMIO) None else Some(x) } val filter = LazyModule(new TLFilter(cfilter = skipMMIO)) val l2_inner_buffer = bufInnerExterior() val l2_outer_buffer = bufOuterExterior() val cork = LazyModule(new TLCacheCork) val lastLevelNode = cork.node l2_inner_buffer.suggestName("InclusiveCache_inner_TLBuffer") l2_outer_buffer.suggestName("InclusiveCache_outer_TLBuffer") l2_inner_buffer.node :*= filter.node l2.node :*= l2_inner_buffer.node l2_outer_buffer.node :*= l2.node /* PhysicalFilters need to be on the TL-C side of a CacheCork to prevent Acquire.NtoB -> Grant.toT */ physicalFilter match { case None => lastLevelNode :*= l2_outer_buffer.node case Some(fp) => { val physicalFilter = LazyModule(new PhysicalFilter(fp.copy(controlBeatBytes = cbus.beatBytes))) lastLevelNode :*= physicalFilter.node :*= l2_outer_buffer.node physicalFilter.controlNode := cbus.coupleTo("physical_filter") { TLBuffer(1) := TLFragmenter(cbus, Some("LLCPhysicalFilter")) := _ } } } l2.ctrls.foreach { _.ctrlnode := cbus.coupleTo("l2_ctrl") { TLBuffer(1) := TLFragmenter(cbus, Some("LLCCtrl")) := _ } } ElaborationArtefacts.add("l2.json", l2.module.json) (filter.node, lastLevelNode, None) }) }) File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (8*32)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source | r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source | r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) || (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }
module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9] input auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coherent_jbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_coherent_jbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coherent_jbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coherent_jbar_anon_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coherent_jbar_anon_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coherent_jbar_anon_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_coherent_jbar_anon_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [127:0] auto_coherent_jbar_anon_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coherent_jbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coherent_jbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coherent_jbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coherent_jbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [127:0] auto_coherent_jbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coherent_jbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coherent_jbar_anon_in_e_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coherent_jbar_anon_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25] input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25] ); wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [3:0] coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [3:0] coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire filter_auto_anon_out_d_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_ready; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_valid; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_e_valid; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_d_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_in_d_bits_denied; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_in_d_bits_sink; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_d_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_d_bits_size; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_in_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_d_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9] wire filter_auto_anon_in_b_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_b_ready; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_b_bits_address; // @[Filter.scala:60:9] wire [1:0] filter_auto_anon_in_b_bits_param; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_valid; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_ready; // @[Filter.scala:60:9] wire filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9] wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire _binder_auto_in_a_ready; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_valid; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_d_bits_opcode; // @[BankBinder.scala:71:28] wire [1:0] _binder_auto_in_d_bits_param; // @[BankBinder.scala:71:28] wire [2:0] _binder_auto_in_d_bits_size; // @[BankBinder.scala:71:28] wire [4:0] _binder_auto_in_d_bits_source; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_sink; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_denied; // @[BankBinder.scala:71:28] wire [63:0] _binder_auto_in_d_bits_data; // @[BankBinder.scala:71:28] wire _binder_auto_in_d_bits_corrupt; // @[BankBinder.scala:71:28] wire _cork_auto_out_a_valid; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_opcode; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_param; // @[Configs.scala:120:26] wire [2:0] _cork_auto_out_a_bits_size; // @[Configs.scala:120:26] wire [4:0] _cork_auto_out_a_bits_source; // @[Configs.scala:120:26] wire [31:0] _cork_auto_out_a_bits_address; // @[Configs.scala:120:26] wire [7:0] _cork_auto_out_a_bits_mask; // @[Configs.scala:120:26] wire [63:0] _cork_auto_out_a_bits_data; // @[Configs.scala:120:26] wire _cork_auto_out_a_bits_corrupt; // @[Configs.scala:120:26] wire _cork_auto_out_d_ready; // @[Configs.scala:120:26] wire _InclusiveCache_inner_TLBuffer_auto_out_a_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_size; // @[Parameters.scala:56:69] wire [6:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_address; // @[Parameters.scala:56:69] wire [15:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask; // @[Parameters.scala:56:69] wire [127:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_b_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_c_valid; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_param; // @[Parameters.scala:56:69] wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_size; // @[Parameters.scala:56:69] wire [6:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_source; // @[Parameters.scala:56:69] wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_address; // @[Parameters.scala:56:69] wire [127:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_data; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_d_ready; // @[Parameters.scala:56:69] wire _InclusiveCache_inner_TLBuffer_auto_out_e_valid; // @[Parameters.scala:56:69] wire [3:0] _InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink; // @[Parameters.scala:56:69] wire _l2_auto_in_a_ready; // @[Configs.scala:93:24] wire _l2_auto_in_b_valid; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_b_bits_param; // @[Configs.scala:93:24] wire [31:0] _l2_auto_in_b_bits_address; // @[Configs.scala:93:24] wire _l2_auto_in_c_ready; // @[Configs.scala:93:24] wire _l2_auto_in_d_valid; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_d_bits_opcode; // @[Configs.scala:93:24] wire [1:0] _l2_auto_in_d_bits_param; // @[Configs.scala:93:24] wire [2:0] _l2_auto_in_d_bits_size; // @[Configs.scala:93:24] wire [6:0] _l2_auto_in_d_bits_source; // @[Configs.scala:93:24] wire [3:0] _l2_auto_in_d_bits_sink; // @[Configs.scala:93:24] wire _l2_auto_in_d_bits_denied; // @[Configs.scala:93:24] wire [127:0] _l2_auto_in_d_bits_data; // @[Configs.scala:93:24] wire _l2_auto_in_d_bits_corrupt; // @[Configs.scala:93:24] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_valid_0 = auto_coherent_jbar_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_opcode_0 = auto_coherent_jbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_param_0 = auto_coherent_jbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_a_bits_size_0 = auto_coherent_jbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_a_bits_source_0 = auto_coherent_jbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_a_bits_address_0 = auto_coherent_jbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [15:0] auto_coherent_jbar_anon_in_a_bits_mask_0 = auto_coherent_jbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_a_bits_data_0 = auto_coherent_jbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_bits_corrupt_0 = auto_coherent_jbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_b_ready_0 = auto_coherent_jbar_anon_in_b_ready; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_valid_0 = auto_coherent_jbar_anon_in_c_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_opcode_0 = auto_coherent_jbar_anon_in_c_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_param_0 = auto_coherent_jbar_anon_in_c_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_c_bits_size_0 = auto_coherent_jbar_anon_in_c_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_c_bits_source_0 = auto_coherent_jbar_anon_in_c_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_c_bits_address_0 = auto_coherent_jbar_anon_in_c_bits_address; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_c_bits_data_0 = auto_coherent_jbar_anon_in_c_bits_data; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_bits_corrupt_0 = auto_coherent_jbar_anon_in_c_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_ready_0 = auto_coherent_jbar_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_e_valid_0 = auto_coherent_jbar_anon_in_e_valid; // @[ClockDomain.scala:14:9] wire [3:0] auto_coherent_jbar_anon_in_e_bits_sink_0 = auto_coherent_jbar_anon_in_e_bits_sink; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_valid_0 = auto_l2_ctrls_ctrl_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode_0 = auto_l2_ctrls_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_param_0 = auto_l2_ctrls_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [1:0] auto_l2_ctrls_ctrl_in_a_bits_size_0 = auto_l2_ctrls_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [11:0] auto_l2_ctrls_ctrl_in_a_bits_source_0 = auto_l2_ctrls_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [25:0] auto_l2_ctrls_ctrl_in_a_bits_address_0 = auto_l2_ctrls_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask_0 = auto_l2_ctrls_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_l2_ctrls_ctrl_in_a_bits_data_0 = auto_l2_ctrls_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_bits_corrupt_0 = auto_l2_ctrls_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_ready_0 = auto_l2_ctrls_ctrl_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_coh_clock_groups_in_member_coh_0_clock_0 = auto_coh_clock_groups_in_member_coh_0_clock; // @[ClockDomain.scala:14:9] wire auto_coh_clock_groups_in_member_coh_0_reset_0 = auto_coh_clock_groups_in_member_coh_0_reset; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9] wire [2:0] filter_auto_anon_in_b_bits_opcode = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_in_b_bits_size = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_b_bits_opcode = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_b_bits_size = 3'h6; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] filter_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] filter_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_in_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_b_bits_size = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_out_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_out_b_bits_size = 3'h6; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coherent_jbar_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17] wire [2:0] coherent_jbar_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_in_0_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_b_bits_size = 3'h6; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_out_0_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_b_bits_size = 3'h6; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24] wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_size = 3'h6; // @[Xbar.scala:352:24] wire [6:0] auto_coherent_jbar_anon_in_b_bits_source = 7'h20; // @[ClockDomain.scala:14:9] wire [6:0] filter_auto_anon_in_b_bits_source = 7'h20; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_b_bits_source = 7'h20; // @[Filter.scala:60:9] wire [6:0] filter_anonOut_b_bits_source = 7'h20; // @[MixedNode.scala:542:17] wire [6:0] filter_anonIn_b_bits_source = 7'h20; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_auto_anon_in_b_bits_source = 7'h20; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_out_b_bits_source = 7'h20; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_b_bits_source = 7'h20; // @[MixedNode.scala:542:17] wire [6:0] coherent_jbar_anonIn_b_bits_source = 7'h20; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_in_0_b_bits_source = 7'h20; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__anonIn_b_bits_source_T = 7'h20; // @[Xbar.scala:156:69] wire [6:0] coherent_jbar_out_0_b_bits_source = 7'h20; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar__requestBOI_uncommonBits_T = 7'h20; // @[Parameters.scala:52:29] wire [6:0] coherent_jbar_requestBOI_uncommonBits = 7'h20; // @[Parameters.scala:52:56] wire [6:0] coherent_jbar_portsBIO_filtered_0_bits_source = 7'h20; // @[Xbar.scala:352:24] wire [15:0] auto_coherent_jbar_anon_in_b_bits_mask = 16'hFFFF; // @[ClockDomain.scala:14:9] wire [15:0] filter_auto_anon_in_b_bits_mask = 16'hFFFF; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_out_b_bits_mask = 16'hFFFF; // @[Filter.scala:60:9] wire [15:0] filter_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] filter_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coherent_jbar_auto_anon_in_b_bits_mask = 16'hFFFF; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_auto_anon_out_b_bits_mask = 16'hFFFF; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonOut_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:542:17] wire [15:0] coherent_jbar_anonIn_b_bits_mask = 16'hFFFF; // @[MixedNode.scala:551:17] wire [15:0] coherent_jbar_in_0_b_bits_mask = 16'hFFFF; // @[Xbar.scala:159:18] wire [15:0] coherent_jbar_out_0_b_bits_mask = 16'hFFFF; // @[Xbar.scala:216:19] wire [15:0] coherent_jbar_portsBIO_filtered_0_bits_mask = 16'hFFFF; // @[Xbar.scala:352:24] wire [127:0] auto_coherent_jbar_anon_in_b_bits_data = 128'h0; // @[ClockDomain.scala:14:9] wire [127:0] filter_auto_anon_in_b_bits_data = 128'h0; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_b_bits_data = 128'h0; // @[Filter.scala:60:9] wire [127:0] filter_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] filter_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_auto_anon_in_b_bits_data = 128'h0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_out_b_bits_data = 128'h0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_b_bits_data = 128'h0; // @[MixedNode.scala:542:17] wire [127:0] coherent_jbar_anonIn_b_bits_data = 128'h0; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_in_0_b_bits_data = 128'h0; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_out_0_b_bits_data = 128'h0; // @[Xbar.scala:216:19] wire [127:0] coherent_jbar_portsBIO_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24] wire auto_coherent_jbar_anon_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire coh_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire coh_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire coh_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire filter_auto_anon_in_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9] wire filter_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire filter_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_auto_in_b_valid = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_valid = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_b_valid = 1'h0; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_in_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coherent_jbar_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coherent_jbar_in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire coherent_jbar_out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire coherent_jbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire coherent_jbar_beatsBO_opdata = 1'h0; // @[Edges.scala:97:28] wire coherent_jbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire auto_coherent_jbar_anon_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9] wire filter_auto_anon_in_e_ready = 1'h1; // @[Filter.scala:60:9] wire filter_auto_anon_out_e_ready = 1'h1; // @[Filter.scala:60:9] wire filter_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire filter_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_auto_in_b_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_e_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_b_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_e_ready = 1'h1; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_b_ready = 1'h1; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_in_e_ready = 1'h1; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_e_ready = 1'h1; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17] wire coherent_jbar_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17] wire coherent_jbar_in_0_e_ready = 1'h1; // @[Xbar.scala:159:18] wire coherent_jbar_out_0_e_ready = 1'h1; // @[Xbar.scala:216:19] wire coherent_jbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire coherent_jbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire coherent_jbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire coherent_jbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire coherent_jbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire coherent_jbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire coherent_jbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire coherent_jbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire coherent_jbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire coherent_jbar__beatsBO_opdata_T = 1'h1; // @[Edges.scala:97:37] wire coherent_jbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire coherent_jbar_portsEOI_filtered_0_ready = 1'h1; // @[Xbar.scala:352:24] wire coherent_jbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_param = 2'h0; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_beatsBO_0 = 2'h0; // @[Edges.scala:221:14] wire [1:0] coherent_jbar_beatsBO_decode = 2'h3; // @[Edges.scala:220:59] wire [5:0] coherent_jbar__beatsBO_decode_T_2 = 6'h3F; // @[package.scala:243:46] wire [5:0] coherent_jbar__beatsBO_decode_T_1 = 6'h0; // @[package.scala:243:76] wire [12:0] coherent_jbar__beatsBO_decode_T = 13'hFC0; // @[package.scala:243:71] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_size = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_size = 3'h0; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_size = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_source = 4'h0; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_source = 4'h0; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_source = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_source = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_address = 32'h0; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_address = 32'h0; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_address = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17] wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_mask = 8'h0; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_mask = 8'h0; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_mask = 8'h0; // @[MixedNode.scala:542:17] wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_data = 64'h0; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_data = 64'h0; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [32:0] coherent_jbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] coherent_jbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [31:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire coherent_jbar_auto_anon_in_a_valid = auto_coherent_jbar_anon_in_a_valid_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_opcode = auto_coherent_jbar_anon_in_a_bits_opcode_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_param = auto_coherent_jbar_anon_in_a_bits_param_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_a_bits_size = auto_coherent_jbar_anon_in_a_bits_size_0; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_a_bits_source = auto_coherent_jbar_anon_in_a_bits_source_0; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_a_bits_address = auto_coherent_jbar_anon_in_a_bits_address_0; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_auto_anon_in_a_bits_mask = auto_coherent_jbar_anon_in_a_bits_mask_0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_a_bits_data = auto_coherent_jbar_anon_in_a_bits_data_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_a_bits_corrupt = auto_coherent_jbar_anon_in_a_bits_corrupt_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_b_ready = auto_coherent_jbar_anon_in_b_ready_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_valid = auto_coherent_jbar_anon_in_c_valid_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_opcode = auto_coherent_jbar_anon_in_c_bits_opcode_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_param = auto_coherent_jbar_anon_in_c_bits_param_0; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_c_bits_size = auto_coherent_jbar_anon_in_c_bits_size_0; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_c_bits_source = auto_coherent_jbar_anon_in_c_bits_source_0; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_auto_anon_in_c_bits_address = auto_coherent_jbar_anon_in_c_bits_address_0; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_c_bits_data = auto_coherent_jbar_anon_in_c_bits_data_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_c_bits_corrupt = auto_coherent_jbar_anon_in_c_bits_corrupt_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_ready = auto_coherent_jbar_anon_in_d_ready_0; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_in_e_valid = auto_coherent_jbar_anon_in_e_valid_0; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_auto_anon_in_e_bits_sink = auto_coherent_jbar_anon_in_e_bits_sink_0; // @[Jbar.scala:44:9] wire coh_clock_groups_auto_in_member_coh_0_clock = auto_coh_clock_groups_in_member_coh_0_clock_0; // @[ClockGroup.scala:53:9] wire coh_clock_groups_auto_in_member_coh_0_reset = auto_coh_clock_groups_in_member_coh_0_reset_0; // @[ClockGroup.scala:53:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [4:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9] wire [31:0] auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [127:0] auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire coh_clock_groups_nodeIn_member_coh_0_clock = coh_clock_groups_auto_in_member_coh_0_clock; // @[ClockGroup.scala:53:9] wire coh_clock_groups_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17] wire coh_clock_groups_nodeIn_member_coh_0_reset = coh_clock_groups_auto_in_member_coh_0_reset; // @[ClockGroup.scala:53:9] wire coh_clock_groups_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_coh_0_clock = coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_coh_0_reset = coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign coh_clock_groups_auto_out_member_coh_0_clock = coh_clock_groups_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9] assign coh_clock_groups_auto_out_member_coh_0_reset = coh_clock_groups_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9] assign coh_clock_groups_nodeOut_member_coh_0_clock = coh_clock_groups_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17] assign coh_clock_groups_nodeOut_member_coh_0_reset = coh_clock_groups_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_coh_0_clock = clockGroup_auto_in_member_coh_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_coh_0_reset = clockGroup_auto_in_member_coh_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9] wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17] wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9] wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17] wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9] wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17] assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9] assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9] assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9] assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9] assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17] assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17] wire filter_anonIn_a_ready; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_a_ready = filter_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9] wire filter_anonIn_a_valid = filter_auto_anon_in_a_valid; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_opcode = filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_param = filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_a_bits_size = filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9] wire [6:0] coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_a_bits_source = filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9] wire [31:0] coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_a_bits_address = filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9] wire [15:0] coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9] wire [15:0] filter_anonIn_a_bits_mask = filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9] wire [127:0] coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_a_bits_data = filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9] wire filter_anonIn_a_bits_corrupt = filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9] wire filter_anonIn_b_ready = filter_auto_anon_in_b_ready; // @[Filter.scala:60:9] wire filter_anonIn_b_valid; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_b_valid = filter_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] filter_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_auto_anon_out_b_bits_param = filter_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [31:0] coherent_jbar_auto_anon_out_b_bits_address = filter_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire filter_anonIn_c_ready; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_c_ready = filter_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9] wire filter_anonIn_c_valid = filter_auto_anon_in_c_valid; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_opcode = filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_param = filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9] wire [2:0] coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_c_bits_size = filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9] wire [6:0] coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_c_bits_source = filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9] wire [31:0] coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9] wire [31:0] filter_anonIn_c_bits_address = filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9] wire [127:0] coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_c_bits_data = filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9] wire filter_anonIn_c_bits_corrupt = filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9] wire coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9] wire filter_anonIn_d_ready = filter_auto_anon_in_d_ready; // @[Filter.scala:60:9] wire filter_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] filter_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_d_valid = filter_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [1:0] filter_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_out_d_bits_opcode = filter_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] filter_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] coherent_jbar_auto_anon_out_d_bits_param = filter_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [6:0] filter_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] coherent_jbar_auto_anon_out_d_bits_size = filter_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [3:0] filter_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [6:0] coherent_jbar_auto_anon_out_d_bits_source = filter_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire filter_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [3:0] coherent_jbar_auto_anon_out_d_bits_sink = filter_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire [127:0] filter_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire coherent_jbar_auto_anon_out_d_bits_denied = filter_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire filter_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [127:0] coherent_jbar_auto_anon_out_d_bits_data = filter_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_d_bits_corrupt = filter_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9] wire filter_anonIn_e_valid = filter_auto_anon_in_e_valid; // @[Filter.scala:60:9] wire [3:0] coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9] wire [3:0] filter_anonIn_e_bits_sink = filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9] wire filter_anonOut_a_ready = filter_auto_anon_out_a_ready; // @[Filter.scala:60:9] wire filter_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] filter_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] filter_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] filter_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] filter_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire filter_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire filter_anonOut_b_ready; // @[MixedNode.scala:542:17] wire filter_anonOut_b_valid = filter_auto_anon_out_b_valid; // @[Filter.scala:60:9] wire [1:0] filter_anonOut_b_bits_param = filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9] wire [31:0] filter_anonOut_b_bits_address = filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9] wire filter_anonOut_c_ready = filter_auto_anon_out_c_ready; // @[Filter.scala:60:9] wire filter_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] filter_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire [6:0] filter_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] filter_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] filter_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire filter_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire filter_anonOut_d_ready; // @[MixedNode.scala:542:17] wire filter_anonOut_d_valid = filter_auto_anon_out_d_valid; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_d_bits_opcode = filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9] wire [1:0] filter_anonOut_d_bits_param = filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_anonOut_d_bits_size = filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_anonOut_d_bits_source = filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9] wire [3:0] filter_anonOut_d_bits_sink = filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9] wire filter_anonOut_d_bits_denied = filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9] wire [127:0] filter_anonOut_d_bits_data = filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9] wire filter_anonOut_d_bits_corrupt = filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9] wire filter_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] filter_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] filter_auto_anon_out_a_bits_opcode; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_a_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_a_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_a_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_a_bits_address; // @[Filter.scala:60:9] wire [15:0] filter_auto_anon_out_a_bits_mask; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_a_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_bits_corrupt; // @[Filter.scala:60:9] wire filter_auto_anon_out_a_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_b_ready; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_opcode; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_param; // @[Filter.scala:60:9] wire [2:0] filter_auto_anon_out_c_bits_size; // @[Filter.scala:60:9] wire [6:0] filter_auto_anon_out_c_bits_source; // @[Filter.scala:60:9] wire [31:0] filter_auto_anon_out_c_bits_address; // @[Filter.scala:60:9] wire [127:0] filter_auto_anon_out_c_bits_data; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_bits_corrupt; // @[Filter.scala:60:9] wire filter_auto_anon_out_c_valid; // @[Filter.scala:60:9] wire filter_auto_anon_out_d_ready; // @[Filter.scala:60:9] wire [3:0] filter_auto_anon_out_e_bits_sink; // @[Filter.scala:60:9] wire filter_auto_anon_out_e_valid; // @[Filter.scala:60:9] assign filter_anonIn_a_ready = filter_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_a_valid = filter_anonOut_a_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_opcode = filter_anonOut_a_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_param = filter_anonOut_a_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_size = filter_anonOut_a_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_source = filter_anonOut_a_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_address = filter_anonOut_a_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_mask = filter_anonOut_a_bits_mask; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_data = filter_anonOut_a_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_out_a_bits_corrupt = filter_anonOut_a_bits_corrupt; // @[Filter.scala:60:9] assign filter_auto_anon_out_b_ready = filter_anonOut_b_ready; // @[Filter.scala:60:9] assign filter_anonIn_b_valid = filter_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_param = filter_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_b_bits_address = filter_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_c_ready = filter_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_c_valid = filter_anonOut_c_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_opcode = filter_anonOut_c_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_param = filter_anonOut_c_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_size = filter_anonOut_c_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_source = filter_anonOut_c_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_address = filter_anonOut_c_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_data = filter_anonOut_c_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_out_c_bits_corrupt = filter_anonOut_c_bits_corrupt; // @[Filter.scala:60:9] assign filter_auto_anon_out_d_ready = filter_anonOut_d_ready; // @[Filter.scala:60:9] assign filter_anonIn_d_valid = filter_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_opcode = filter_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_param = filter_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_size = filter_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_source = filter_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_sink = filter_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_denied = filter_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_data = filter_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonIn_d_bits_corrupt = filter_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_out_e_valid = filter_anonOut_e_valid; // @[Filter.scala:60:9] assign filter_auto_anon_out_e_bits_sink = filter_anonOut_e_bits_sink; // @[Filter.scala:60:9] assign filter_auto_anon_in_a_ready = filter_anonIn_a_ready; // @[Filter.scala:60:9] assign filter_anonOut_a_valid = filter_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_opcode = filter_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_param = filter_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_size = filter_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_source = filter_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_address = filter_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_mask = filter_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_data = filter_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_a_bits_corrupt = filter_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_b_ready = filter_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_in_b_valid = filter_anonIn_b_valid; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_param = filter_anonIn_b_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_in_b_bits_address = filter_anonIn_b_bits_address; // @[Filter.scala:60:9] assign filter_auto_anon_in_c_ready = filter_anonIn_c_ready; // @[Filter.scala:60:9] assign filter_anonOut_c_valid = filter_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_opcode = filter_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_param = filter_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_size = filter_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_source = filter_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_address = filter_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_data = filter_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_c_bits_corrupt = filter_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_d_ready = filter_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign filter_auto_anon_in_d_valid = filter_anonIn_d_valid; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_opcode = filter_anonIn_d_bits_opcode; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_param = filter_anonIn_d_bits_param; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_size = filter_anonIn_d_bits_size; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_source = filter_anonIn_d_bits_source; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_sink = filter_anonIn_d_bits_sink; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_denied = filter_anonIn_d_bits_denied; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_data = filter_anonIn_d_bits_data; // @[Filter.scala:60:9] assign filter_auto_anon_in_d_bits_corrupt = filter_anonIn_d_bits_corrupt; // @[Filter.scala:60:9] assign filter_anonOut_e_valid = filter_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign filter_anonOut_e_bits_sink = filter_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_a_valid = InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param = InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size = InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source = InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address = InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask = InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data = InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_c_valid = InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param = InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size = InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source = InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address = InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data = InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_d_ready = InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire InclusiveCache_outer_TLBuffer_nodeIn_e_valid = InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink = InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_a_ready = InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_c_ready = InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_nodeOut_d_valid = InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode = InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param = InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size = InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source = InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink = InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied = InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data = InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire InclusiveCache_outer_TLBuffer_auto_in_a_ready; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_c_ready; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_in_d_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_a_valid; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_param; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_size; // @[Buffer.scala:40:9] wire [3:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_data; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_c_valid; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_d_ready; // @[Buffer.scala:40:9] wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9] wire InclusiveCache_outer_TLBuffer_auto_out_e_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_a_ready = InclusiveCache_outer_TLBuffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_a_valid = InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_c_ready = InclusiveCache_outer_TLBuffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_c_valid = InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_d_ready = InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeIn_d_valid = InclusiveCache_outer_TLBuffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_out_e_valid = InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_a_ready = InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_a_valid = InclusiveCache_outer_TLBuffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_in_c_ready = InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_c_valid = InclusiveCache_outer_TLBuffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_d_ready = InclusiveCache_outer_TLBuffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_auto_in_d_valid = InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign InclusiveCache_outer_TLBuffer_nodeOut_e_valid = InclusiveCache_outer_TLBuffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] wire coherent_jbar_anonIn_a_ready; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_a_ready_0 = coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_a_valid = coherent_jbar_auto_anon_in_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_opcode = coherent_jbar_auto_anon_in_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_param = coherent_jbar_auto_anon_in_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_a_bits_size = coherent_jbar_auto_anon_in_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_a_bits_source = coherent_jbar_auto_anon_in_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_a_bits_address = coherent_jbar_auto_anon_in_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonIn_a_bits_mask = coherent_jbar_auto_anon_in_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_a_bits_data = coherent_jbar_auto_anon_in_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_a_bits_corrupt = coherent_jbar_auto_anon_in_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_b_ready = coherent_jbar_auto_anon_in_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_b_valid; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_valid_0 = coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_param_0 = coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_b_bits_address_0 = coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_ready; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_c_ready_0 = coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_valid = coherent_jbar_auto_anon_in_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_opcode = coherent_jbar_auto_anon_in_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_param = coherent_jbar_auto_anon_in_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_c_bits_size = coherent_jbar_auto_anon_in_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_c_bits_source = coherent_jbar_auto_anon_in_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonIn_c_bits_address = coherent_jbar_auto_anon_in_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_c_bits_data = coherent_jbar_auto_anon_in_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_c_bits_corrupt = coherent_jbar_auto_anon_in_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_ready = coherent_jbar_auto_anon_in_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_valid; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_valid_0 = coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_opcode_0 = coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_param_0 = coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_size_0 = coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_source_0 = coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_sink_0 = coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_denied_0 = coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_data_0 = coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign auto_coherent_jbar_anon_in_d_bits_corrupt_0 = coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonIn_e_valid = coherent_jbar_auto_anon_in_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonIn_e_bits_sink = coherent_jbar_auto_anon_in_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_ready = coherent_jbar_auto_anon_out_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_valid = coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_opcode = coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_param = coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_size = coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_source = coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_address = coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_mask = coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_data = coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_a_bits_corrupt = coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_ready; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_b_ready = coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_b_valid = coherent_jbar_auto_anon_out_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonOut_b_bits_param = coherent_jbar_auto_anon_out_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_b_bits_address = coherent_jbar_auto_anon_out_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_ready = coherent_jbar_auto_anon_out_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_valid = coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_opcode = coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_param = coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_size = coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_source = coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_address = coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_data = coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_c_bits_corrupt = coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_ready; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_d_ready = coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_valid = coherent_jbar_auto_anon_out_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_d_bits_opcode = coherent_jbar_auto_anon_out_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_anonOut_d_bits_param = coherent_jbar_auto_anon_out_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_anonOut_d_bits_size = coherent_jbar_auto_anon_out_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_anonOut_d_bits_source = coherent_jbar_auto_anon_out_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonOut_d_bits_sink = coherent_jbar_auto_anon_out_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_bits_denied = coherent_jbar_auto_anon_out_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_anonOut_d_bits_data = coherent_jbar_auto_anon_out_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_d_bits_corrupt = coherent_jbar_auto_anon_out_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_anonOut_e_valid; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_e_valid = coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign filter_auto_anon_in_e_bits_sink = coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_a_ready = coherent_jbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_valid = coherent_jbar_anonOut_a_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_opcode = coherent_jbar_anonOut_a_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_param = coherent_jbar_anonOut_a_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_size = coherent_jbar_anonOut_a_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_source = coherent_jbar_anonOut_a_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_address = coherent_jbar_anonOut_a_bits_address; // @[Jbar.scala:44:9] wire [15:0] coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_mask = coherent_jbar_anonOut_a_bits_mask; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_data = coherent_jbar_anonOut_a_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_a_bits_corrupt = coherent_jbar_anonOut_a_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_b_ready = coherent_jbar_anonOut_b_ready; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_b_valid = coherent_jbar_anonOut_b_valid; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_out_0_b_bits_param = coherent_jbar_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [31:0] coherent_jbar_out_0_b_bits_address = coherent_jbar_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_c_ready = coherent_jbar_anonOut_c_ready; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_valid = coherent_jbar_anonOut_c_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_opcode = coherent_jbar_anonOut_c_bits_opcode; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_param = coherent_jbar_anonOut_c_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_size = coherent_jbar_anonOut_c_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_source = coherent_jbar_anonOut_c_bits_source; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_address = coherent_jbar_anonOut_c_bits_address; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_data = coherent_jbar_anonOut_c_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_c_bits_corrupt = coherent_jbar_anonOut_c_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_d_ready = coherent_jbar_anonOut_d_ready; // @[Jbar.scala:44:9] wire coherent_jbar_out_0_d_valid = coherent_jbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_d_bits_opcode = coherent_jbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_out_0_d_bits_param = coherent_jbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] coherent_jbar_out_0_d_bits_size = coherent_jbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [6:0] coherent_jbar_out_0_d_bits_source = coherent_jbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [3:0] coherent_jbar__out_0_d_bits_sink_T = coherent_jbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire coherent_jbar_out_0_d_bits_denied = coherent_jbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [127:0] coherent_jbar_out_0_d_bits_data = coherent_jbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_d_bits_corrupt = coherent_jbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19] assign coherent_jbar_auto_anon_out_e_valid = coherent_jbar_anonOut_e_valid; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_out_e_bits_sink = coherent_jbar_anonOut_e_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_a_ready = coherent_jbar_anonIn_a_ready; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_a_valid = coherent_jbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_opcode = coherent_jbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_param = coherent_jbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_a_bits_size = coherent_jbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__in_0_a_bits_source_T = coherent_jbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] coherent_jbar_in_0_a_bits_address = coherent_jbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [15:0] coherent_jbar_in_0_a_bits_mask = coherent_jbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_in_0_a_bits_data = coherent_jbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_a_bits_corrupt = coherent_jbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_b_ready = coherent_jbar_anonIn_b_ready; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_valid = coherent_jbar_anonIn_b_valid; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_bits_param = coherent_jbar_anonIn_b_bits_param; // @[Jbar.scala:44:9] wire [31:0] coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_b_bits_address = coherent_jbar_anonIn_b_bits_address; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_c_ready = coherent_jbar_anonIn_c_ready; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_c_valid = coherent_jbar_anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_opcode = coherent_jbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_param = coherent_jbar_anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_in_0_c_bits_size = coherent_jbar_anonIn_c_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar__in_0_c_bits_source_T = coherent_jbar_anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] coherent_jbar_in_0_c_bits_address = coherent_jbar_anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_in_0_c_bits_data = coherent_jbar_anonIn_c_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_c_bits_corrupt = coherent_jbar_anonIn_c_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_d_ready = coherent_jbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_valid = coherent_jbar_anonIn_d_valid; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_opcode = coherent_jbar_anonIn_d_bits_opcode; // @[Jbar.scala:44:9] wire [1:0] coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_param = coherent_jbar_anonIn_d_bits_param; // @[Jbar.scala:44:9] wire [2:0] coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_size = coherent_jbar_anonIn_d_bits_size; // @[Jbar.scala:44:9] wire [6:0] coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_auto_anon_in_d_bits_source = coherent_jbar_anonIn_d_bits_source; // @[Jbar.scala:44:9] wire [3:0] coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_sink = coherent_jbar_anonIn_d_bits_sink; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_denied = coherent_jbar_anonIn_d_bits_denied; // @[Jbar.scala:44:9] wire [127:0] coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_data = coherent_jbar_anonIn_d_bits_data; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign coherent_jbar_auto_anon_in_d_bits_corrupt = coherent_jbar_anonIn_d_bits_corrupt; // @[Jbar.scala:44:9] wire coherent_jbar_in_0_e_valid = coherent_jbar_anonIn_e_valid; // @[Xbar.scala:159:18] wire [3:0] coherent_jbar_in_0_e_bits_sink = coherent_jbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_a_ready = coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18] wire coherent_jbar__portsAOI_filtered_0_valid_T_1 = coherent_jbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_opcode = coherent_jbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_param = coherent_jbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_size = coherent_jbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] coherent_jbar_portsAOI_filtered_0_bits_source = coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] coherent_jbar__requestAIO_T = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_address = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [15:0] coherent_jbar_portsAOI_filtered_0_bits_mask = coherent_jbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [127:0] coherent_jbar_portsAOI_filtered_0_bits_data = coherent_jbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsAOI_filtered_0_bits_corrupt = coherent_jbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsBIO_filtered_0_ready = coherent_jbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_valid = coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_bits_param = coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_b_bits_address = coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18] wire coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_c_ready = coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18] wire coherent_jbar__portsCOI_filtered_0_valid_T_1 = coherent_jbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_opcode = coherent_jbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_param = coherent_jbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_size = coherent_jbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire [6:0] coherent_jbar_portsCOI_filtered_0_bits_source = coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] coherent_jbar__requestCIO_T = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] coherent_jbar_portsCOI_filtered_0_bits_address = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [127:0] coherent_jbar_portsCOI_filtered_0_bits_data = coherent_jbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsCOI_filtered_0_bits_corrupt = coherent_jbar_in_0_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsDIO_filtered_0_ready = coherent_jbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_valid = coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_opcode = coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_param = coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_size = coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire [6:0] coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign coherent_jbar__anonIn_d_bits_source_T = coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [3:0] coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_sink = coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_denied = coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [127:0] coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_data = coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign coherent_jbar_anonIn_d_bits_corrupt = coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire coherent_jbar__portsEOI_filtered_0_valid_T_1 = coherent_jbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [3:0] coherent_jbar__requestEIO_uncommonBits_T = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18] wire [3:0] coherent_jbar_portsEOI_filtered_0_bits_sink = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_a_bits_source = coherent_jbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign coherent_jbar_in_0_c_bits_source = coherent_jbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign coherent_jbar_anonIn_d_bits_source = coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign coherent_jbar_portsAOI_filtered_0_ready = coherent_jbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_a_valid = coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_opcode = coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_param = coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_size = coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_source = coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_address = coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_mask = coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_data = coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_a_bits_corrupt = coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_b_ready = coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19] wire coherent_jbar__portsBIO_filtered_0_valid_T_1 = coherent_jbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40] assign coherent_jbar_portsBIO_filtered_0_bits_param = coherent_jbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsBIO_filtered_0_bits_address = coherent_jbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsCOI_filtered_0_ready = coherent_jbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_c_valid = coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_opcode = coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_param = coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_size = coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_source = coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_address = coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_data = coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_c_bits_corrupt = coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19] assign coherent_jbar_anonOut_d_ready = coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19] wire coherent_jbar__portsDIO_filtered_0_valid_T_1 = coherent_jbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign coherent_jbar_portsDIO_filtered_0_bits_opcode = coherent_jbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_param = coherent_jbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_size = coherent_jbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [6:0] coherent_jbar__requestDOI_uncommonBits_T = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign coherent_jbar_portsDIO_filtered_0_bits_source = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_sink = coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_denied = coherent_jbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_data = coherent_jbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsDIO_filtered_0_bits_corrupt = coherent_jbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign coherent_jbar_anonOut_e_valid = coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19] assign coherent_jbar__anonOut_e_bits_sink_T = coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign coherent_jbar_out_0_d_bits_sink = coherent_jbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign coherent_jbar_anonOut_e_bits_sink = coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] coherent_jbar__requestAIO_T_1 = {1'h0, coherent_jbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] coherent_jbar__requestCIO_T_1 = {1'h0, coherent_jbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire [6:0] coherent_jbar_requestDOI_uncommonBits = coherent_jbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] coherent_jbar_requestEIO_uncommonBits = coherent_jbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] coherent_jbar__beatsAI_decode_T = 13'h3F << coherent_jbar_in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsAI_decode_T_1 = coherent_jbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsAI_decode_T_2 = ~coherent_jbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsAI_decode = coherent_jbar__beatsAI_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar__beatsAI_opdata_T = coherent_jbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire coherent_jbar_beatsAI_opdata = ~coherent_jbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [1:0] coherent_jbar_beatsAI_0 = coherent_jbar_beatsAI_opdata ? coherent_jbar_beatsAI_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] coherent_jbar__beatsCI_decode_T = 13'h3F << coherent_jbar_in_0_c_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsCI_decode_T_1 = coherent_jbar__beatsCI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsCI_decode_T_2 = ~coherent_jbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsCI_decode = coherent_jbar__beatsCI_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar_beatsCI_opdata = coherent_jbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [1:0] coherent_jbar_beatsCI_0 = coherent_jbar_beatsCI_opdata ? coherent_jbar_beatsCI_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [12:0] coherent_jbar__beatsDO_decode_T = 13'h3F << coherent_jbar_out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] coherent_jbar__beatsDO_decode_T_1 = coherent_jbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] coherent_jbar__beatsDO_decode_T_2 = ~coherent_jbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [1:0] coherent_jbar_beatsDO_decode = coherent_jbar__beatsDO_decode_T_2[5:4]; // @[package.scala:243:46] wire coherent_jbar_beatsDO_opdata = coherent_jbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [1:0] coherent_jbar_beatsDO_0 = coherent_jbar_beatsDO_opdata ? coherent_jbar_beatsDO_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign coherent_jbar_in_0_a_ready = coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_out_0_a_valid = coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_opcode = coherent_jbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_param = coherent_jbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_size = coherent_jbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_source = coherent_jbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_address = coherent_jbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_mask = coherent_jbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_data = coherent_jbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_a_bits_corrupt = coherent_jbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsAOI_filtered_0_valid = coherent_jbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_b_ready = coherent_jbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_in_0_b_valid = coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_param = coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_b_bits_address = coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_portsBIO_filtered_0_valid = coherent_jbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_in_0_c_ready = coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_out_0_c_valid = coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_opcode = coherent_jbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_param = coherent_jbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_size = coherent_jbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_source = coherent_jbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_address = coherent_jbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_data = coherent_jbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_c_bits_corrupt = coherent_jbar_portsCOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsCOI_filtered_0_valid = coherent_jbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_d_ready = coherent_jbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_in_0_d_valid = coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_opcode = coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_param = coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_size = coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_source = coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_sink = coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_denied = coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_data = coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_in_0_d_bits_corrupt = coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign coherent_jbar_portsDIO_filtered_0_valid = coherent_jbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign coherent_jbar_out_0_e_valid = coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_out_0_e_bits_sink = coherent_jbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign coherent_jbar_portsEOI_filtered_0_valid = coherent_jbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingOut_a_ready = coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [4:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [31:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_mbus_bus_xingOut_d_valid = coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_param = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_size = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [4:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_source = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_data = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [4:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [31:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [4:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [31:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [4:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonIn_a_ready = coupler_to_bus_named_mbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonIn_d_valid = coupler_to_bus_named_mbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_param = coupler_to_bus_named_mbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_size = coupler_to_bus_named_mbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_source = coupler_to_bus_named_mbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_data = coupler_to_bus_named_mbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_anonOut_a_valid = coupler_to_bus_named_mbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_param = coupler_to_bus_named_mbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_size = coupler_to_bus_named_mbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_source = coupler_to_bus_named_mbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_address = coupler_to_bus_named_mbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_data = coupler_to_bus_named_mbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_anonOut_d_ready = coupler_to_bus_named_mbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_bus_xingIn_a_ready = coupler_to_bus_named_mbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_valid = coupler_to_bus_named_mbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_param = coupler_to_bus_named_mbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_size = coupler_to_bus_named_mbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_source = coupler_to_bus_named_mbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_data = coupler_to_bus_named_mbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_bus_xingOut_a_valid = coupler_to_bus_named_mbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_param = coupler_to_bus_named_mbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_size = coupler_to_bus_named_mbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_source = coupler_to_bus_named_mbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_address = coupler_to_bus_named_mbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_data = coupler_to_bus_named_mbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_bus_xingOut_d_ready = coupler_to_bus_named_mbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] InclusiveCache l2 ( // @[Configs.scala:93:24] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready_0), .auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid_0), .auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode_0), .auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size_0), .auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source_0), .auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data_0), .auto_in_a_ready (_l2_auto_in_a_ready), .auto_in_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), // @[Parameters.scala:56:69] .auto_in_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), // @[Parameters.scala:56:69] .auto_in_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), // @[Parameters.scala:56:69] .auto_in_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), // @[Parameters.scala:56:69] .auto_in_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), // @[Parameters.scala:56:69] .auto_in_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), // @[Parameters.scala:56:69] .auto_in_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), // @[Parameters.scala:56:69] .auto_in_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), // @[Parameters.scala:56:69] .auto_in_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), // @[Parameters.scala:56:69] .auto_in_b_valid (_l2_auto_in_b_valid), .auto_in_b_bits_param (_l2_auto_in_b_bits_param), .auto_in_b_bits_address (_l2_auto_in_b_bits_address), .auto_in_c_ready (_l2_auto_in_c_ready), .auto_in_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), // @[Parameters.scala:56:69] .auto_in_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), // @[Parameters.scala:56:69] .auto_in_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), // @[Parameters.scala:56:69] .auto_in_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), // @[Parameters.scala:56:69] .auto_in_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), // @[Parameters.scala:56:69] .auto_in_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), // @[Parameters.scala:56:69] .auto_in_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), // @[Parameters.scala:56:69] .auto_in_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), // @[Parameters.scala:56:69] .auto_in_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), // @[Parameters.scala:56:69] .auto_in_d_valid (_l2_auto_in_d_valid), .auto_in_d_bits_opcode (_l2_auto_in_d_bits_opcode), .auto_in_d_bits_param (_l2_auto_in_d_bits_param), .auto_in_d_bits_size (_l2_auto_in_d_bits_size), .auto_in_d_bits_source (_l2_auto_in_d_bits_source), .auto_in_d_bits_sink (_l2_auto_in_d_bits_sink), .auto_in_d_bits_denied (_l2_auto_in_d_bits_denied), .auto_in_d_bits_data (_l2_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), .auto_in_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), // @[Parameters.scala:56:69] .auto_in_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink), // @[Parameters.scala:56:69] .auto_out_a_ready (InclusiveCache_outer_TLBuffer_auto_in_a_ready), // @[Buffer.scala:40:9] .auto_out_a_valid (InclusiveCache_outer_TLBuffer_auto_in_a_valid), .auto_out_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode), .auto_out_a_bits_param (InclusiveCache_outer_TLBuffer_auto_in_a_bits_param), .auto_out_a_bits_size (InclusiveCache_outer_TLBuffer_auto_in_a_bits_size), .auto_out_a_bits_source (InclusiveCache_outer_TLBuffer_auto_in_a_bits_source), .auto_out_a_bits_address (InclusiveCache_outer_TLBuffer_auto_in_a_bits_address), .auto_out_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask), .auto_out_a_bits_data (InclusiveCache_outer_TLBuffer_auto_in_a_bits_data), .auto_out_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt), .auto_out_c_ready (InclusiveCache_outer_TLBuffer_auto_in_c_ready), // @[Buffer.scala:40:9] .auto_out_c_valid (InclusiveCache_outer_TLBuffer_auto_in_c_valid), .auto_out_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode), .auto_out_c_bits_param (InclusiveCache_outer_TLBuffer_auto_in_c_bits_param), .auto_out_c_bits_size (InclusiveCache_outer_TLBuffer_auto_in_c_bits_size), .auto_out_c_bits_source (InclusiveCache_outer_TLBuffer_auto_in_c_bits_source), .auto_out_c_bits_address (InclusiveCache_outer_TLBuffer_auto_in_c_bits_address), .auto_out_c_bits_data (InclusiveCache_outer_TLBuffer_auto_in_c_bits_data), .auto_out_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt), .auto_out_d_ready (InclusiveCache_outer_TLBuffer_auto_in_d_ready), .auto_out_d_valid (InclusiveCache_outer_TLBuffer_auto_in_d_valid), // @[Buffer.scala:40:9] .auto_out_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode), // @[Buffer.scala:40:9] .auto_out_d_bits_param (InclusiveCache_outer_TLBuffer_auto_in_d_bits_param), // @[Buffer.scala:40:9] .auto_out_d_bits_size (InclusiveCache_outer_TLBuffer_auto_in_d_bits_size), // @[Buffer.scala:40:9] .auto_out_d_bits_source (InclusiveCache_outer_TLBuffer_auto_in_d_bits_source), // @[Buffer.scala:40:9] .auto_out_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink), // @[Buffer.scala:40:9] .auto_out_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied), // @[Buffer.scala:40:9] .auto_out_d_bits_data (InclusiveCache_outer_TLBuffer_auto_in_d_bits_data), // @[Buffer.scala:40:9] .auto_out_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt), // @[Buffer.scala:40:9] .auto_out_e_valid (InclusiveCache_outer_TLBuffer_auto_in_e_valid), .auto_out_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink) ); // @[Configs.scala:93:24] TLBuffer_a32d128s7k4z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (filter_auto_anon_out_a_ready), .auto_in_a_valid (filter_auto_anon_out_a_valid), // @[Filter.scala:60:9] .auto_in_a_bits_opcode (filter_auto_anon_out_a_bits_opcode), // @[Filter.scala:60:9] .auto_in_a_bits_param (filter_auto_anon_out_a_bits_param), // @[Filter.scala:60:9] .auto_in_a_bits_size (filter_auto_anon_out_a_bits_size), // @[Filter.scala:60:9] .auto_in_a_bits_source (filter_auto_anon_out_a_bits_source), // @[Filter.scala:60:9] .auto_in_a_bits_address (filter_auto_anon_out_a_bits_address), // @[Filter.scala:60:9] .auto_in_a_bits_mask (filter_auto_anon_out_a_bits_mask), // @[Filter.scala:60:9] .auto_in_a_bits_data (filter_auto_anon_out_a_bits_data), // @[Filter.scala:60:9] .auto_in_a_bits_corrupt (filter_auto_anon_out_a_bits_corrupt), // @[Filter.scala:60:9] .auto_in_b_ready (filter_auto_anon_out_b_ready), // @[Filter.scala:60:9] .auto_in_b_valid (filter_auto_anon_out_b_valid), .auto_in_b_bits_param (filter_auto_anon_out_b_bits_param), .auto_in_b_bits_address (filter_auto_anon_out_b_bits_address), .auto_in_c_ready (filter_auto_anon_out_c_ready), .auto_in_c_valid (filter_auto_anon_out_c_valid), // @[Filter.scala:60:9] .auto_in_c_bits_opcode (filter_auto_anon_out_c_bits_opcode), // @[Filter.scala:60:9] .auto_in_c_bits_param (filter_auto_anon_out_c_bits_param), // @[Filter.scala:60:9] .auto_in_c_bits_size (filter_auto_anon_out_c_bits_size), // @[Filter.scala:60:9] .auto_in_c_bits_source (filter_auto_anon_out_c_bits_source), // @[Filter.scala:60:9] .auto_in_c_bits_address (filter_auto_anon_out_c_bits_address), // @[Filter.scala:60:9] .auto_in_c_bits_data (filter_auto_anon_out_c_bits_data), // @[Filter.scala:60:9] .auto_in_c_bits_corrupt (filter_auto_anon_out_c_bits_corrupt), // @[Filter.scala:60:9] .auto_in_d_ready (filter_auto_anon_out_d_ready), // @[Filter.scala:60:9] .auto_in_d_valid (filter_auto_anon_out_d_valid), .auto_in_d_bits_opcode (filter_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (filter_auto_anon_out_d_bits_param), .auto_in_d_bits_size (filter_auto_anon_out_d_bits_size), .auto_in_d_bits_source (filter_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (filter_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (filter_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (filter_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (filter_auto_anon_out_d_bits_corrupt), .auto_in_e_valid (filter_auto_anon_out_e_valid), // @[Filter.scala:60:9] .auto_in_e_bits_sink (filter_auto_anon_out_e_bits_sink), // @[Filter.scala:60:9] .auto_out_a_ready (_l2_auto_in_a_ready), // @[Configs.scala:93:24] .auto_out_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), .auto_out_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), .auto_out_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), .auto_out_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), .auto_out_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), .auto_out_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), .auto_out_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), .auto_out_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), .auto_out_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), .auto_out_b_valid (_l2_auto_in_b_valid), // @[Configs.scala:93:24] .auto_out_b_bits_param (_l2_auto_in_b_bits_param), // @[Configs.scala:93:24] .auto_out_b_bits_address (_l2_auto_in_b_bits_address), // @[Configs.scala:93:24] .auto_out_c_ready (_l2_auto_in_c_ready), // @[Configs.scala:93:24] .auto_out_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), .auto_out_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), .auto_out_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), .auto_out_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), .auto_out_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), .auto_out_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), .auto_out_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), .auto_out_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), .auto_out_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), .auto_out_d_valid (_l2_auto_in_d_valid), // @[Configs.scala:93:24] .auto_out_d_bits_opcode (_l2_auto_in_d_bits_opcode), // @[Configs.scala:93:24] .auto_out_d_bits_param (_l2_auto_in_d_bits_param), // @[Configs.scala:93:24] .auto_out_d_bits_size (_l2_auto_in_d_bits_size), // @[Configs.scala:93:24] .auto_out_d_bits_source (_l2_auto_in_d_bits_source), // @[Configs.scala:93:24] .auto_out_d_bits_sink (_l2_auto_in_d_bits_sink), // @[Configs.scala:93:24] .auto_out_d_bits_denied (_l2_auto_in_d_bits_denied), // @[Configs.scala:93:24] .auto_out_d_bits_data (_l2_auto_in_d_bits_data), // @[Configs.scala:93:24] .auto_out_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), // @[Configs.scala:93:24] .auto_out_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), .auto_out_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink) ); // @[Parameters.scala:56:69] TLCacheCork cork ( // @[Configs.scala:120:26] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (InclusiveCache_outer_TLBuffer_auto_out_a_ready), .auto_in_a_valid (InclusiveCache_outer_TLBuffer_auto_out_a_valid), // @[Buffer.scala:40:9] .auto_in_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode), // @[Buffer.scala:40:9] .auto_in_a_bits_param (InclusiveCache_outer_TLBuffer_auto_out_a_bits_param), // @[Buffer.scala:40:9] .auto_in_a_bits_size (InclusiveCache_outer_TLBuffer_auto_out_a_bits_size), // @[Buffer.scala:40:9] .auto_in_a_bits_source (InclusiveCache_outer_TLBuffer_auto_out_a_bits_source), // @[Buffer.scala:40:9] .auto_in_a_bits_address (InclusiveCache_outer_TLBuffer_auto_out_a_bits_address), // @[Buffer.scala:40:9] .auto_in_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask), // @[Buffer.scala:40:9] .auto_in_a_bits_data (InclusiveCache_outer_TLBuffer_auto_out_a_bits_data), // @[Buffer.scala:40:9] .auto_in_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9] .auto_in_c_ready (InclusiveCache_outer_TLBuffer_auto_out_c_ready), .auto_in_c_valid (InclusiveCache_outer_TLBuffer_auto_out_c_valid), // @[Buffer.scala:40:9] .auto_in_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode), // @[Buffer.scala:40:9] .auto_in_c_bits_param (InclusiveCache_outer_TLBuffer_auto_out_c_bits_param), // @[Buffer.scala:40:9] .auto_in_c_bits_size (InclusiveCache_outer_TLBuffer_auto_out_c_bits_size), // @[Buffer.scala:40:9] .auto_in_c_bits_source (InclusiveCache_outer_TLBuffer_auto_out_c_bits_source), // @[Buffer.scala:40:9] .auto_in_c_bits_address (InclusiveCache_outer_TLBuffer_auto_out_c_bits_address), // @[Buffer.scala:40:9] .auto_in_c_bits_data (InclusiveCache_outer_TLBuffer_auto_out_c_bits_data), // @[Buffer.scala:40:9] .auto_in_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt), // @[Buffer.scala:40:9] .auto_in_d_ready (InclusiveCache_outer_TLBuffer_auto_out_d_ready), // @[Buffer.scala:40:9] .auto_in_d_valid (InclusiveCache_outer_TLBuffer_auto_out_d_valid), .auto_in_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode), .auto_in_d_bits_param (InclusiveCache_outer_TLBuffer_auto_out_d_bits_param), .auto_in_d_bits_size (InclusiveCache_outer_TLBuffer_auto_out_d_bits_size), .auto_in_d_bits_source (InclusiveCache_outer_TLBuffer_auto_out_d_bits_source), .auto_in_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink), .auto_in_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied), .auto_in_d_bits_data (InclusiveCache_outer_TLBuffer_auto_out_d_bits_data), .auto_in_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt), .auto_in_e_valid (InclusiveCache_outer_TLBuffer_auto_out_e_valid), // @[Buffer.scala:40:9] .auto_in_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink), // @[Buffer.scala:40:9] .auto_out_a_ready (_binder_auto_in_a_ready), // @[BankBinder.scala:71:28] .auto_out_a_valid (_cork_auto_out_a_valid), .auto_out_a_bits_opcode (_cork_auto_out_a_bits_opcode), .auto_out_a_bits_param (_cork_auto_out_a_bits_param), .auto_out_a_bits_size (_cork_auto_out_a_bits_size), .auto_out_a_bits_source (_cork_auto_out_a_bits_source), .auto_out_a_bits_address (_cork_auto_out_a_bits_address), .auto_out_a_bits_mask (_cork_auto_out_a_bits_mask), .auto_out_a_bits_data (_cork_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), .auto_out_d_ready (_cork_auto_out_d_ready), .auto_out_d_valid (_binder_auto_in_d_valid), // @[BankBinder.scala:71:28] .auto_out_d_bits_opcode (_binder_auto_in_d_bits_opcode), // @[BankBinder.scala:71:28] .auto_out_d_bits_param (_binder_auto_in_d_bits_param), // @[BankBinder.scala:71:28] .auto_out_d_bits_size (_binder_auto_in_d_bits_size), // @[BankBinder.scala:71:28] .auto_out_d_bits_source (_binder_auto_in_d_bits_source), // @[BankBinder.scala:71:28] .auto_out_d_bits_sink (_binder_auto_in_d_bits_sink), // @[BankBinder.scala:71:28] .auto_out_d_bits_denied (_binder_auto_in_d_bits_denied), // @[BankBinder.scala:71:28] .auto_out_d_bits_data (_binder_auto_in_d_bits_data), // @[BankBinder.scala:71:28] .auto_out_d_bits_corrupt (_binder_auto_in_d_bits_corrupt) // @[BankBinder.scala:71:28] ); // @[Configs.scala:120:26] BankBinder binder ( // @[BankBinder.scala:71:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_binder_auto_in_a_ready), .auto_in_a_valid (_cork_auto_out_a_valid), // @[Configs.scala:120:26] .auto_in_a_bits_opcode (_cork_auto_out_a_bits_opcode), // @[Configs.scala:120:26] .auto_in_a_bits_param (_cork_auto_out_a_bits_param), // @[Configs.scala:120:26] .auto_in_a_bits_size (_cork_auto_out_a_bits_size), // @[Configs.scala:120:26] .auto_in_a_bits_source (_cork_auto_out_a_bits_source), // @[Configs.scala:120:26] .auto_in_a_bits_address (_cork_auto_out_a_bits_address), // @[Configs.scala:120:26] .auto_in_a_bits_mask (_cork_auto_out_a_bits_mask), // @[Configs.scala:120:26] .auto_in_a_bits_data (_cork_auto_out_a_bits_data), // @[Configs.scala:120:26] .auto_in_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), // @[Configs.scala:120:26] .auto_in_d_ready (_cork_auto_out_d_ready), // @[Configs.scala:120:26] .auto_in_d_valid (_binder_auto_in_d_valid), .auto_in_d_bits_opcode (_binder_auto_in_d_bits_opcode), .auto_in_d_bits_param (_binder_auto_in_d_bits_param), .auto_in_d_bits_size (_binder_auto_in_d_bits_size), .auto_in_d_bits_source (_binder_auto_in_d_bits_source), .auto_in_d_bits_sink (_binder_auto_in_d_bits_sink), .auto_in_d_bits_denied (_binder_auto_in_d_bits_denied), .auto_in_d_bits_data (_binder_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_binder_auto_in_d_bits_corrupt), .auto_out_a_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_out_a_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid), .auto_out_a_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode), .auto_out_a_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param), .auto_out_a_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size), .auto_out_a_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source), .auto_out_a_bits_address (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address), .auto_out_a_bits_mask (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask), .auto_out_a_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data), .auto_out_a_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt), .auto_out_d_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready), .auto_out_d_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_sink (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_denied (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7] ); // @[BankBinder.scala:71:28] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_a_ready = auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_valid = auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_param = auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_b_bits_address = auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_c_ready = auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_valid = auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_opcode = auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_param = auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_size = auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_source = auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_sink = auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_denied = auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_data = auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coherent_jbar_anon_in_d_bits_corrupt = auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_a_ready = auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_valid = auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_opcode = auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_size = auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_source = auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_l2_ctrls_ctrl_in_d_bits_data = auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }
module Tile_254( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_510 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_52( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_3( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_349( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module IntSyncSyncCrossingSink_n1x1_34( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body || !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body || !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) || protocol.ready protocol.valid := (!is_const || io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_||_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) || o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source | sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink | sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) }
module TLDFromNoC_9( // @[TilelinkAdapters.scala:185:7] input clock, // @[TilelinkAdapters.scala:185:7] input reset, // @[TilelinkAdapters.scala:185:7] input io_protocol_ready, // @[TilelinkAdapters.scala:56:14] output io_protocol_valid, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14] output [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14] output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14] output [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_sink, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_denied, // @[TilelinkAdapters.scala:56:14] output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14] output io_flit_ready, // @[TilelinkAdapters.scala:56:14] input io_flit_valid, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14] input [64:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14] ); reg is_const; // @[TilelinkAdapters.scala:68:25] reg [17:0] const_reg; // @[TilelinkAdapters.scala:69:22] wire [17:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[17:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18] wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}] wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:185:7] if (reset) // @[TilelinkAdapters.scala:185:7] is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :185:7] else // @[TilelinkAdapters.scala:185:7] is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35] if (_GEN_0) // @[TilelinkAdapters.scala:84:22] const_reg <= io_flit_bits_payload[17:0]; // @[TilelinkAdapters.scala:56:14, :69:22] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File AsyncResetReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ /** This black-boxes an Async Reset * (or Set) * Register. * * Because Chisel doesn't support * parameterized black boxes, * we unfortunately have to * instantiate a number of these. * * We also have to hard-code the set/ * reset behavior. * * Do not confuse an asynchronous * reset signal with an asynchronously * reset reg. You should still * properly synchronize your reset * deassertion. * * @param d Data input * @param q Data Output * @param clk Clock Input * @param rst Reset Input * @param en Write Enable Input * */ class AsyncResetReg(resetValue: Int = 0) extends RawModule { val io = IO(new Bundle { val d = Input(Bool()) val q = Output(Bool()) val en = Input(Bool()) val clk = Input(Clock()) val rst = Input(Reset()) }) val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W))) when (io.en) { reg := io.d } io.q := reg } class SimpleRegIO(val w: Int) extends Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) } class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module { override def desiredName = s"AsyncResetRegVec_w${w}_i${init}" val io = IO(new SimpleRegIO(w)) val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W))) when (io.en) { reg := io.d } io.q := reg } object AsyncResetReg { // Create Single Registers def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = { val reg = Module(new AsyncResetReg(if (init) 1 else 0)) reg.io.d := d reg.io.clk := clk reg.io.rst := rst reg.io.en := true.B name.foreach(reg.suggestName(_)) reg.io.q } def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None) def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name)) // Create Vectors of Registers def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = { val w = updateData.getWidth max resetData.bitLength val reg = Module(new AsyncResetRegVec(w, resetData)) name.foreach(reg.suggestName(_)) reg.io.d := updateData reg.io.en := enable reg.io.q } def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData, resetData, enable, Some(name)) def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B) def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name)) def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable) def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name)) def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B) def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name)) }
module AsyncResetRegVec_w1_i0_37( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File RouteComputer.scala: package constellation.router import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.{TruthTable, decoder} import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import freechips.rocketchip.rocket.DecodeLogic import constellation.channel._ import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo} import constellation.noc.{HasNoCParams} class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams { val src_virt_id = UInt(virtualChannelBits.W) val flow = new FlowRoutingBundle } class RouteComputerResp( val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) } class RouteComputer( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams with HasNoCParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) }) val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) }) }) (io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) => req.ready := true.B if (outParams.size == 0) { assert(!req.valid) resp.vc_sel := DontCare } else { def toUInt(t: (Int, FlowRoutingInfo)): UInt = { val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) | t._2.vNetId val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) | t._2.ingressNode val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) | t._2.ingressNodeId val l5 = ( l4 << req.bits.flow.egress_node .getWidth) | t._2.egressNode val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) | t._2.egressNodeId l6.U(req.bits.getWidth.W) } val flow = req.bits.flow val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI => allInParams(i).channelRoutingInfos.map { cI => var row: String = "b" (0 until nOutputs).foreach { o => (0 until outParams(o).nVirtualChannels).foreach { outVId => row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0") } } ((cI.vc, pI), row) } }.flatten val addr = req.bits.asUInt val width = outParams.map(_.nVirtualChannels).reduce(_+_) val decoded = if (table.size > 0) { val truthTable = TruthTable( table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) }, BitPat("b" + "?" * width) ) Reverse(decoder(addr, truthTable)) } else { 0.U(width.W) } var idx = 0 (0 until nAllOutputs).foreach { o => if (o < nOutputs) { (0 until outParams(o).nVirtualChannels).foreach { outVId => resp.vc_sel(o)(outVId) := decoded(idx) idx += 1 } } else { resp.vc_sel(o)(0) := false.B } } } } }
module RouteComputer_6( // @[RouteComputer.scala:29:7] input [3:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_4_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_3_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_3_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_1 = ~{io_req_1_bits_src_virt_id, io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_2 = ~{io_req_2_bits_src_virt_id, io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [16:0] decoded_invInputs_3 = ~{io_req_3_bits_src_virt_id, io_req_3_bits_flow_vnet_id, io_req_3_bits_flow_ingress_node, io_req_3_bits_flow_ingress_node_id, io_req_3_bits_flow_egress_node, io_req_3_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [3:0] _GEN = ~io_req_4_bits_flow_egress_node; // @[pla.scala:78:21] wire [1:0] _GEN_0 = ~io_req_4_bits_flow_egress_node_id; // @[pla.scala:78:21] assign io_resp_4_vc_sel_3_0 = &{_GEN[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], io_req_4_bits_flow_egress_node[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_2_0 = &{_GEN_0[0], _GEN_0[1], io_req_4_bits_flow_egress_node[0], io_req_4_bits_flow_egress_node[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_0 = |{&{_GEN_0[0], _GEN_0[1], _GEN[1]}, &{_GEN[1], _GEN[2], _GEN[3]}}; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_4_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_0 = &{_GEN[0], io_req_4_bits_flow_egress_node[1], _GEN[2], _GEN[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_4_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_4_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_3_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_0 = |{&{decoded_invInputs_3[0], decoded_invInputs_3[14], decoded_invInputs_3[15]}, &{decoded_invInputs_3[0], decoded_invInputs_3[14], decoded_invInputs_3[16]}}; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_3_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_3_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_3_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_3_1 = |{&{io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_3_2 = |{&{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_1_1 = |{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[16]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[15]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[3], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[14], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_1_2 = |{&{decoded_invInputs_2[0], decoded_invInputs_2[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[15]}, &{decoded_invInputs_2[0], decoded_invInputs_2[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], io_req_2_bits_flow_ingress_node[1], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_2_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_3_0 = |{&{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_1 = |{&{io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[3], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[3], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_3_2 = |{&{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_0 = |{&{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[0], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_0 = |{&{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15]}, &{decoded_invInputs_1[0], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], io_req_1_bits_flow_ingress_node[2], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_1_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_3_0 = |{&{decoded_invInputs[0], decoded_invInputs[14], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[14], decoded_invInputs[16]}}; // @[pla.scala:78:21, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_1 = |{&{io_req_0_bits_flow_egress_node_id[0], io_req_0_bits_flow_egress_node[3], io_req_0_bits_flow_ingress_node_id[0], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], io_req_0_bits_flow_egress_node[3], io_req_0_bits_flow_ingress_node_id[0], io_req_0_bits_flow_ingress_node_id[1], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[16]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[0], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[16]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[15]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node[1], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[14], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_3_2 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[15]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_2_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_1_2 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7] assign io_resp_0_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry */ case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns * 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic */ val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } /* Write request logic */ // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) /* Read/write response logic */ val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B /* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */ def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } /* ReservableListBuffer logic, and associated classes. */ class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */ abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index */ class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) | validSet used := (used & ~usedClr) | usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet /* Reservation logic signals */ val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) /* Response logic signals */ val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) /* Reservation logic */ reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } /* Response logic */ // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } /* Response unwind logic */ // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire || unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) | usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }
module dataMems_439( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways * sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2*cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relLists*cache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x | 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ || _) (matches, bits.U) } expanded | Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) || (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) || ((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(*toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put* => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB || param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
module MSHR_6( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 7'h20; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 7'h20; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 7'h20; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_32( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_43 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File Nodes.scala: package constellation.channel import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy._ case class EmptyParams() case class ChannelEdgeParams(cp: ChannelParams, p: Parameters) object ChannelImp extends SimpleNodeImp[EmptyParams, ChannelParams, ChannelEdgeParams, Channel] { def edge(pd: EmptyParams, pu: ChannelParams, p: Parameters, sourceInfo: SourceInfo) = { ChannelEdgeParams(pu, p) } def bundle(e: ChannelEdgeParams) = new Channel(e.cp)(e.p) def render(e: ChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#0000ff", label = e.cp.payloadBits.toString) } override def monitor(bundle: Channel, edge: ChannelEdgeParams): Unit = { val monitor = Module(new NoCMonitor(edge.cp)(edge.p)) monitor.io.in := bundle } // TODO: Add nodepath stuff? override def mixO, override def mixI } case class ChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(ChannelImp)(Seq(EmptyParams())) case class ChannelDestNode(val destParams: ChannelParams)(implicit valName: ValName) extends SinkNode(ChannelImp)(Seq(destParams)) case class ChannelAdapterNode( slaveFn: ChannelParams => ChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(ChannelImp)((e: EmptyParams) => e, slaveFn) case class ChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(ChannelImp)() case class ChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(ChannelImp)() case class IngressChannelEdgeParams(cp: IngressChannelParams, p: Parameters) case class EgressChannelEdgeParams(cp: EgressChannelParams, p: Parameters) object IngressChannelImp extends SimpleNodeImp[EmptyParams, IngressChannelParams, IngressChannelEdgeParams, IngressChannel] { def edge(pd: EmptyParams, pu: IngressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { IngressChannelEdgeParams(pu, p) } def bundle(e: IngressChannelEdgeParams) = new IngressChannel(e.cp)(e.p) def render(e: IngressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#00ff00", label = e.cp.payloadBits.toString) } } object EgressChannelImp extends SimpleNodeImp[EmptyParams, EgressChannelParams, EgressChannelEdgeParams, EgressChannel] { def edge(pd: EmptyParams, pu: EgressChannelParams, p: Parameters, sourceInfo: SourceInfo) = { EgressChannelEdgeParams(pu, p) } def bundle(e: EgressChannelEdgeParams) = new EgressChannel(e.cp)(e.p) def render(e: EgressChannelEdgeParams) = if (e.cp.possibleFlows.size == 0) { RenderedEdge(colour = "ffffff", label = "X") } else { RenderedEdge(colour = "#ff0000", label = e.cp.payloadBits.toString) } } case class IngressChannelSourceNode(val destId: Int)(implicit valName: ValName) extends SourceNode(IngressChannelImp)(Seq(EmptyParams())) case class IngressChannelDestNode(val destParams: IngressChannelParams)(implicit valName: ValName) extends SinkNode(IngressChannelImp)(Seq(destParams)) case class EgressChannelSourceNode(val egressId: Int)(implicit valName: ValName) extends SourceNode(EgressChannelImp)(Seq(EmptyParams())) case class EgressChannelDestNode(val destParams: EgressChannelParams)(implicit valName: ValName) extends SinkNode(EgressChannelImp)(Seq(destParams)) case class IngressChannelAdapterNode( slaveFn: IngressChannelParams => IngressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(IngressChannelImp)(m => m, slaveFn) case class EgressChannelAdapterNode( slaveFn: EgressChannelParams => EgressChannelParams = { d => d })( implicit valName: ValName) extends AdapterNode(EgressChannelImp)(m => m, slaveFn) case class IngressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(IngressChannelImp)() case class EgressChannelIdentityNode()(implicit valName: ValName) extends IdentityNode(EgressChannelImp)() case class IngressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(IngressChannelImp)() case class EgressChannelEphemeralNode()(implicit valName: ValName) extends EphemeralNode(EgressChannelImp)() File Router.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{RoutingRelation} import constellation.noc.{HasNoCParams} case class UserRouterParams( // Payload width. Must match payload width on all channels attached to this routing node payloadBits: Int = 64, // Combines SA and ST stages (removes pipeline register) combineSAST: Boolean = false, // Combines RC and VA stages (removes pipeline register) combineRCVA: Boolean = false, // Adds combinational path from SA to VA coupleSAVA: Boolean = false, vcAllocator: VCAllocatorParams => Parameters => VCAllocator = (vP) => (p) => new RotatingSingleVCAllocator(vP)(p) ) case class RouterParams( nodeId: Int, nIngress: Int, nEgress: Int, user: UserRouterParams ) trait HasRouterOutputParams { def outParams: Seq[ChannelParams] def egressParams: Seq[EgressChannelParams] def allOutParams = outParams ++ egressParams def nOutputs = outParams.size def nEgress = egressParams.size def nAllOutputs = allOutParams.size } trait HasRouterInputParams { def inParams: Seq[ChannelParams] def ingressParams: Seq[IngressChannelParams] def allInParams = inParams ++ ingressParams def nInputs = inParams.size def nIngress = ingressParams.size def nAllInputs = allInParams.size } trait HasRouterParams { def routerParams: RouterParams def nodeId = routerParams.nodeId def payloadBits = routerParams.user.payloadBits } class DebugBundle(val nIn: Int) extends Bundle { val va_stall = Vec(nIn, UInt()) val sa_stall = Vec(nIn, UInt()) } class Router( val routerParams: RouterParams, preDiplomaticInParams: Seq[ChannelParams], preDiplomaticIngressParams: Seq[IngressChannelParams], outDests: Seq[Int], egressIds: Seq[Int] )(implicit p: Parameters) extends LazyModule with HasNoCParams with HasRouterParams { val allPreDiplomaticInParams = preDiplomaticInParams ++ preDiplomaticIngressParams val destNodes = preDiplomaticInParams.map(u => ChannelDestNode(u)) val sourceNodes = outDests.map(u => ChannelSourceNode(u)) val ingressNodes = preDiplomaticIngressParams.map(u => IngressChannelDestNode(u)) val egressNodes = egressIds.map(u => EgressChannelSourceNode(u)) val debugNode = BundleBridgeSource(() => new DebugBundle(allPreDiplomaticInParams.size)) val ctrlNode = if (hasCtrl) Some(BundleBridgeSource(() => new RouterCtrlBundle)) else None def inParams = module.inParams def outParams = module.outParams def ingressParams = module.ingressParams def egressParams = module.egressParams lazy val module = new LazyModuleImp(this) with HasRouterInputParams with HasRouterOutputParams { val (io_in, edgesIn) = destNodes.map(_.in(0)).unzip val (io_out, edgesOut) = sourceNodes.map(_.out(0)).unzip val (io_ingress, edgesIngress) = ingressNodes.map(_.in(0)).unzip val (io_egress, edgesEgress) = egressNodes.map(_.out(0)).unzip val io_debug = debugNode.out(0)._1 val inParams = edgesIn.map(_.cp) val outParams = edgesOut.map(_.cp) val ingressParams = edgesIngress.map(_.cp) val egressParams = edgesEgress.map(_.cp) allOutParams.foreach(u => require(u.srcId == nodeId && u.payloadBits == routerParams.user.payloadBits)) allInParams.foreach(u => require(u.destId == nodeId && u.payloadBits == routerParams.user.payloadBits)) require(nIngress == routerParams.nIngress) require(nEgress == routerParams.nEgress) require(nAllInputs >= 1) require(nAllOutputs >= 1) require(nodeId < (1 << nodeIdBits)) val input_units = inParams.zipWithIndex.map { case (u,i) => Module(new InputUnit(u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"input_unit_${i}_from_${u.srcId}") } val ingress_units = ingressParams.zipWithIndex.map { case (u,i) => Module(new IngressUnit(i, u, outParams, egressParams, routerParams.user.combineRCVA, routerParams.user.combineSAST)) .suggestName(s"ingress_unit_${i+nInputs}_from_${u.ingressId}") } val all_input_units = input_units ++ ingress_units val output_units = outParams.zipWithIndex.map { case (u,i) => Module(new OutputUnit(inParams, ingressParams, u)) .suggestName(s"output_unit_${i}_to_${u.destId}")} val egress_units = egressParams.zipWithIndex.map { case (u,i) => Module(new EgressUnit(routerParams.user.coupleSAVA && all_input_units.size == 1, routerParams.user.combineSAST, inParams, ingressParams, u)) .suggestName(s"egress_unit_${i+nOutputs}_to_${u.egressId}")} val all_output_units = output_units ++ egress_units val switch = Module(new Switch(routerParams, inParams, outParams, ingressParams, egressParams)) val switch_allocator = Module(new SwitchAllocator(routerParams, inParams, outParams, ingressParams, egressParams)) val vc_allocator = Module(routerParams.user.vcAllocator( VCAllocatorParams(routerParams, inParams, outParams, ingressParams, egressParams) )(p)) val route_computer = Module(new RouteComputer(routerParams, inParams, outParams, ingressParams, egressParams)) val fires_count = WireInit(PopCount(vc_allocator.io.req.map(_.fire))) dontTouch(fires_count) (io_in zip input_units ).foreach { case (i,u) => u.io.in <> i } (io_ingress zip ingress_units).foreach { case (i,u) => u.io.in <> i.flit } (output_units zip io_out ).foreach { case (u,o) => o <> u.io.out } (egress_units zip io_egress).foreach { case (u,o) => o.flit <> u.io.out } (route_computer.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.router_req } (all_input_units zip route_computer.io.resp).foreach { case (u,o) => u.io.router_resp <> o } (vc_allocator.io.req zip all_input_units).foreach { case (i,u) => i <> u.io.vcalloc_req } (all_input_units zip vc_allocator.io.resp).foreach { case (u,o) => u.io.vcalloc_resp <> o } (all_output_units zip vc_allocator.io.out_allocs).foreach { case (u,a) => u.io.allocs <> a } (vc_allocator.io.channel_status zip all_output_units).foreach { case (a,u) => a := u.io.channel_status } all_input_units.foreach(in => all_output_units.zipWithIndex.foreach { case (out,outIdx) => in.io.out_credit_available(outIdx) := out.io.credit_available }) (all_input_units zip switch_allocator.io.req).foreach { case (u,r) => r <> u.io.salloc_req } (all_output_units zip switch_allocator.io.credit_alloc).foreach { case (u,a) => u.io.credit_alloc := a } (switch.io.in zip all_input_units).foreach { case (i,u) => i <> u.io.out } (all_output_units zip switch.io.out).foreach { case (u,o) => u.io.in <> o } switch.io.sel := (if (routerParams.user.combineSAST) { switch_allocator.io.switch_sel } else { RegNext(switch_allocator.io.switch_sel) }) if (hasCtrl) { val io_ctrl = ctrlNode.get.out(0)._1 val ctrl = Module(new RouterControlUnit(routerParams, inParams, outParams, ingressParams, egressParams)) io_ctrl <> ctrl.io.ctrl (all_input_units zip ctrl.io.in_block ).foreach { case (l,r) => l.io.block := r } (all_input_units zip ctrl.io.in_fire ).foreach { case (l,r) => r := l.io.out.map(_.valid) } } else { input_units.foreach(_.io.block := false.B) ingress_units.foreach(_.io.block := false.B) } (io_debug.va_stall zip all_input_units.map(_.io.debug.va_stall)).map { case (l,r) => l := r } (io_debug.sa_stall zip all_input_units.map(_.io.debug.sa_stall)).map { case (l,r) => l := r } val debug_tsc = RegInit(0.U(64.W)) debug_tsc := debug_tsc + 1.U val debug_sample = RegInit(0.U(64.W)) debug_sample := debug_sample + 1.U val sample_rate = PlusArg("noc_util_sample_rate", width=20) when (debug_sample === sample_rate - 1.U) { debug_sample := 0.U } def sample(fire: Bool, s: String) = { val util_ctr = RegInit(0.U(64.W)) val fired = RegInit(false.B) util_ctr := util_ctr + fire fired := fired || fire when (sample_rate =/= 0.U && debug_sample === sample_rate - 1.U && fired) { val fmtStr = s"nocsample %d $s %d\n" printf(fmtStr, debug_tsc, util_ctr); fired := fire } } destNodes.map(_.in(0)).foreach { case (in, edge) => in.flit.map { f => sample(f.fire, s"${edge.cp.srcId} $nodeId") } } ingressNodes.map(_.in(0)).foreach { case (in, edge) => sample(in.flit.fire, s"i${edge.cp.asInstanceOf[IngressChannelParams].ingressId} $nodeId") } egressNodes.map(_.out(0)).foreach { case (out, edge) => sample(out.flit.fire, s"$nodeId e${edge.cp.asInstanceOf[EgressChannelParams].egressId}") } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }
module Router_13( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [1:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [1:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_nodes_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input auto_ingress_nodes_in_flit_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_ingress_nodes_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [3:0] auto_ingress_nodes_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [3:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [3:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_0_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_0_3; // @[Router.scala:136:32] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [36:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _egress_unit_1_to_1_io_credit_available_0; // @[Router.scala:125:13] wire _egress_unit_1_to_1_io_channel_status_0_occupied; // @[Router.scala:125:13] wire _egress_unit_1_to_1_io_out_valid; // @[Router.scala:125:13] wire _output_unit_0_to_1_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_1_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _ingress_unit_1_from_1_io_vcalloc_req_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_salloc_req_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_salloc_req_0_bits_tail; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_out_0_valid; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_out_0_bits_flit_head; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_out_0_bits_flit_tail; // @[Router.scala:116:13] wire [36:0] _ingress_unit_1_from_1_io_out_0_bits_flit_payload; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_1_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13] wire [3:0] _ingress_unit_1_from_1_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13] wire [1:0] _ingress_unit_1_from_1_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13] wire _ingress_unit_1_from_1_io_in_ready; // @[Router.scala:116:13] wire [1:0] _input_unit_0_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [36:0] _input_unit_0_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [3:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_12_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_1_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a28d64s4k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_54 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_8( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ /*---------------------------------------------------------------------------- | In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be | set. *----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }
module RecFNToRecFN_39( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical */) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File MulAddRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //*** UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //*** REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //*** NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR || reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) || isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra || CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny || (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) || (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) || (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA || io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros || (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) || (io.fromPreMul.isInfC && opSignC) || (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) || (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd || opSignC)) || (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }
module MulAddRecFNToRaw_postMul_e8_s24_18( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7] wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7] wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7] wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7] wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16] wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7] wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14] wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29] wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7] wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7] wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45] wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31] wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32] wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61] wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35] wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31] wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26] wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46] wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35] wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48] wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49] wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36] wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32] wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57] wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44] wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25] wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50] wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26] wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25] wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7] wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42] wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32] wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47] wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47] wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47] wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28] wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28] wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12] wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69] wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43] wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}] wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43] wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43] wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20] wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}] wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46] wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46] wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23] wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23] wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71] wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21] wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}] wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}] wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19] wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}] wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37] wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24] wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}] wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36] wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}] wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30] wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33] assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15] assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20] wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51] wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20] wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73] wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25] wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25] wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}] wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}] wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}] wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61] wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36] wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20] wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19] wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}] wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}] wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41] wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41] wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57] wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30] wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33] assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15] assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20] wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20] wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20] wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20] wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20] wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20] wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20] wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70] wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70] wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70] wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76] wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}] wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46] wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46] assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26] wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27] wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}] wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20] wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}] wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57] wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30] wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54] wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33] assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}] assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54] wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15] assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}] assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57] wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20] wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20] wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20] wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20] wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20] wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70] wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21] wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56] wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22] wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20] wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22] wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20] wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20] wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20] wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20] wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20] wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11] wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28] wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28] wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}] wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}] wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39] assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25] wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21] wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54] wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42] wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36] wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36] wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17] assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}] wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26] wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57] assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57] wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10] wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36] assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48] assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42] assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25] wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27] wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}] wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}] wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36] wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36] wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48] wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37] wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10] wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31] wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}] wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17] assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49] assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50] assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26] assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25] assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: package constellation.channel import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.util._ import constellation.noc.{HasNoCParams} class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams { val io = IO(new Bundle { val in = Input(new Channel(cParam)) }) val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B })) for (i <- 0 until cParam.srcSpeedup) { val flit = io.in.flit(i) when (flit.valid) { when (flit.bits.head) { in_flight(flit.bits.virt_channel_id) := true.B assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken") } when (flit.bits.tail) { in_flight(flit.bits.virt_channel_id) := false.B } } val possibleFlows = cParam.possibleFlows when (flit.valid && flit.bits.head) { cParam match { case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) => assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR) } } } } File Types.scala: package constellation.routing import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Parameters} import constellation.noc.{HasNoCParams} import constellation.channel.{Flit} /** A representation for 1 specific virtual channel in wormhole routing * * @param src the source node * @param vc ID for the virtual channel * @param dst the destination node * @param n_vc the number of virtual channels */ // BEGIN: ChannelRoutingInfo case class ChannelRoutingInfo( src: Int, dst: Int, vc: Int, n_vc: Int ) { // END: ChannelRoutingInfo require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this") require (!(src == -1 && dst == -1), s"Illegal $this") require (vc < n_vc, s"Illegal $this") val isIngress = src == -1 val isEgress = dst == -1 } /** Represents the properties of a packet that are relevant for routing * ingressId and egressId uniquely identify a flow, but vnet and dst are used here * to simplify the implementation of routingrelations * * @param ingressId packet's source ingress point * @param egressId packet's destination egress point * @param vNet virtual subnetwork identifier * @param dst packet's destination node ID */ // BEGIN: FlowRoutingInfo case class FlowRoutingInfo( ingressId: Int, egressId: Int, vNetId: Int, ingressNode: Int, ingressNodeId: Int, egressNode: Int, egressNodeId: Int, fifo: Boolean ) { // END: FlowRoutingInfo def isFlow(f: FlowRoutingBundle): Bool = { (f.ingress_node === ingressNode.U && f.egress_node === egressNode.U && f.ingress_node_id === ingressNodeId.U && f.egress_node_id === egressNodeId.U) } def asLiteral(b: FlowRoutingBundle): BigInt = { Seq( (vNetId , b.vnet_id), (ingressNode , b.ingress_node), (ingressNodeId , b.ingress_node_id), (egressNode , b.egress_node), (egressNodeId , b.egress_node_id) ).foldLeft(0)((l, t) => { (l << t._2.getWidth) | t._1 }) } } class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams { // Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination // This simplifies the routing tables val vnet_id = UInt(log2Ceil(nVirtualNetworks).W) val ingress_node = UInt(log2Ceil(nNodes).W) val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W) val egress_node = UInt(log2Ceil(nNodes).W) val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W) }
module NoCMonitor_65( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow || routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }
module InputUnit_10( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_2_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first | last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first | last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB || !io.status.bits.blockB) assert (!io.status.bits.nestC || !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe || !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid || io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid || io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty || request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) | Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid || meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U || !(request.opcode === PutFullData || request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r || p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c || m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read || clean release can lead to this state eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client eviction(S_TIP_D, true) // MMIO write || dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done | probe_bit probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst || last_probe w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst || last_probe w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U) w_pprobeack := w_pprobeack || set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U || io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f || p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read || clean release can lead to this state bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client bypass(S_TIP_D, true) // MMIO write || dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid || (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT || new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") }
module MSHR( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:57:20] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _req_clientBit_T = request_source[5:3]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 3'h2; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire req_clientBit = _req_clientBit_T_3; // @[Parameters.scala:54:67, :56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:56:48] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _probe_bit_T = io_sinkc_bits_source_0[5:3]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 3'h2; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire probe_bit = _probe_bit_T_3; // @[Parameters.scala:54:67, :56:48] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:56:48] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _new_clientBit_T = new_request_source[5:3]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 3'h2; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire new_clientBit = _new_clientBit_T_3; // @[Parameters.scala:54:67, :56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /** These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of *ResetSynchronizerPrimitiveShiftReg, * intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }
module AsyncResetSynchronizerShiftReg_w1_d3_i0_41( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_85 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1025:0] _c_sizes_set_T_1 = 1026'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [383:0] c_opcodes_set = 384'h0; // @[Monitor.scala:740:34] wire [383:0] c_sizes_set = 384'h0; // @[Monitor.scala:741:34] wire [95:0] c_set = 96'h0; // @[Monitor.scala:738:34] wire [95:0] c_set_wo_ready = 96'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits[6:5] != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [6:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [6:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [6:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [6:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [6:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [6:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [6:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [6:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [6:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [6:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1[6:5] != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [95:0] inflight; // @[Monitor.scala:614:27] reg [383:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [383:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [95:0] a_set; // @[Monitor.scala:626:34] wire [95:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [383:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [383:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [383:0] _a_opcode_lookup_T_6 = {380'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [383:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [383:0] _a_size_lookup_T_6 = {380'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [383:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[95:0] : 96'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[95:0] : 96'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[383:0] : 384'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1025:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[383:0] : 384'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [95:0] d_clr; // @[Monitor.scala:664:34] wire [95:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [383:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [383:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[95:0] : 96'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[95:0] : 96'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[383:0] : 384'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[383:0] : 384'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [383:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [95:0] inflight_1; // @[Monitor.scala:726:35] wire [95:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [383:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [383:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [383:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [383:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [383:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [383:0] _c_opcode_lookup_T_6 = {380'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [383:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[383:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [383:0] _c_size_lookup_T_6 = {380'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [383:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [95:0] d_clr_1; // @[Monitor.scala:774:34] wire [95:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [383:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [383:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[95:0] : 96'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[95:0] : 96'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[383:0] : 384'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[383:0] : 384'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [95:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [383:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [383:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [383:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire || io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) || !io.outCol.fire) assert(!(state === 1.U) || !io.inRow.fire) }
module PE_241( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File btb.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomBTBParams( nSets: Int = 128, nWays: Int = 2, offsetSz: Int = 13, extendedNSets: Int = 128 ) class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets override val nWays = params.nWays val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1 val offsetSz = params.offsetSz val extendedNSets = params.extendedNSets require(isPow2(nSets)) require(isPow2(extendedNSets) || extendedNSets == 0) require(extendedNSets <= nSets) require(extendedNSets >= 1) class BTBEntry extends Bundle { val offset = SInt(offsetSz.W) val extended = Bool() } val btbEntrySz = offsetSz + 1 class BTBMeta extends Bundle { val is_br = Bool() val tag = UInt(tagSz.W) } val btbMetaSz = tagSz + 1 class BTBPredictMeta extends Bundle { val write_way = UInt(log2Ceil(nWays).W) } val s1_meta = Wire(new BTBPredictMeta) val f3_meta = RegNext(RegNext(s1_meta)) io.f3_meta := f3_meta.asUInt override val metaSz = s1_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) } val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) } val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W)) val mems = (((0 until nWays) map ({w:Int => Seq( (f"btb_meta_way$w", nSets, bankWidth * btbMetaSz), (f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended))) val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) }) val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) }) val s1_req_rebtb = ebtb.read(s0_idx, s0_valid) val s1_req_tag = s1_idx >> log2Ceil(nSets) val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W)))) val s1_is_br = Wire(Vec(bankWidth, Bool())) val s1_is_jal = Wire(Vec(bankWidth, Bool())) val s1_hit_ohs = VecInit((0 until bankWidth) map { i => VecInit((0 until nWays) map { w => s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0) }) }) val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) } val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) } for (w <- 0 until bankWidth) { val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w) val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w) s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w) s1_resp(w).bits := Mux( entry_btb.extended, s1_req_rebtb, (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt) s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br io.resp.f2(w) := io.resp_in(0).f2(w) io.resp.f3(w) := io.resp_in(0).f3(w) when (RegNext(s1_hits(w))) { io.resp.f2(w).predicted_pc := RegNext(s1_resp(w)) io.resp.f2(w).is_br := RegNext(s1_is_br(w)) io.resp.f2(w).is_jal := RegNext(s1_is_jal(w)) when (RegNext(s1_is_jal(w))) { io.resp.f2(w).taken := true.B } } when (RegNext(RegNext(s1_hits(w)))) { io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc) io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br) io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal) when (RegNext(RegNext(s1_is_jal(w)))) { io.resp.f3(w).taken := true.B } } } val alloc_way = if (nWays > 1) { val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0)) val l = log2Ceil(nWays) val nChunks = (r_metas.getWidth + l - 1) / l val chunks = (0 until nChunks) map { i => r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l) } chunks.reduce(_^_) } else { 0.U } s1_meta.write_way := Mux(s1_hits.reduce(_||_), PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)), alloc_way) val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta) val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt val new_offset_value = (s1_update.bits.target.asSInt - (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt) val offset_is_extended = (new_offset_value > max_offset_value || new_offset_value < min_offset_value) val s1_update_wbtb_data = Wire(new BTBEntry) s1_update_wbtb_data.extended := offset_is_extended s1_update_wbtb_data.offset := new_offset_value val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) & Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update)) val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) & (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) | (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts) ) ) val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta)) for (w <- 0 until bankWidth) { s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets)) s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w) } for (w <- 0 until nWays) { when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) { btb(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }), VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wbtb_mask).asBools ) meta(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }), VecInit(s1_update_wmeta_data.map(_.asUInt))), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmeta_mask).asBools ) } } when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) { ebtb.write(s1_update_idx, s1_update.bits.target) } }
module ebtb_2( // @[btb.scala:67:29] input [6:0] R0_addr, input R0_en, input R0_clk, output [39:0] R0_data, input [6:0] W0_addr, input W0_en, input W0_clk, input [39:0] W0_data ); ebtb_ext ebtb_ext ( // @[btb.scala:67:29] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[btb.scala:67:29] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /** Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. */ class ClientMetadata extends Bundle { /** Actual state information stored in this bundle */ val state = UInt(ClientStates.width.W) /** Metadata equality */ def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /** Is the block's data present in this cache */ def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /** Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) */ private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /** Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). */ private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd || param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /** Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). */ def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /** Does a secondary miss on the block require another Acquire message */ def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /** Metadata change on a returned Grant */ def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /** Determine what state to go to based on Probe param */ private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /** Translate cache control cmds into Probe param */ private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /** Factories for ClientMetadata, including on reset */ object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File dcache.scala: //****************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v4.common._ import boom.v4.exu.BrUpdateInfo import boom.v4.util._ class BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new WritebackReq(edge.bundle))) val meta_read = Decoupled(new L1MetaReadReq) val resp = Output(Bool()) val idx = Output(Valid(UInt())) val data_req = Decoupled(new L1DataReadReq) val data_resp = Input(UInt(encRowBits.W)) val mem_grant = Input(Bool()) val release = Decoupled(new TLBundleC(edge.bundle)) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) }) val req = Reg(new WritebackReq(edge.bundle)) val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5) val state = RegInit(s_invalid) val r1_data_req_fired = RegInit(false.B) val r2_data_req_fired = RegInit(false.B) val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W)) val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W)) val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release) val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W))) val acked = RegInit(false.B) io.idx.valid := state =/= s_invalid io.idx.bits := req.idx io.release.valid := false.B io.release.bits := DontCare io.req.ready := false.B io.meta_read.valid := false.B io.meta_read.bits := DontCare io.data_req.valid := false.B io.data_req.bits := DontCare io.resp := false.B io.lsu_release.valid := false.B io.lsu_release.bits := DontCare val r_address = Cat(req.tag, req.idx) << blockOffBits val id = cfg.nMSHRs val probeResponse = edge.ProbeAck( fromSource = req.source, toAddress = r_address, lgSize = lgCacheBlockBytes.U, reportPermissions = req.param, data = wb_buffer(data_req_cnt)) val voluntaryRelease = edge.Release( fromSource = id.U, toAddress = r_address, lgSize = lgCacheBlockBytes.U, shrinkPermissions = req.param, data = wb_buffer(data_req_cnt))._2 when (state === s_invalid) { io.req.ready := true.B when (io.req.fire) { state := s_fill_buffer data_req_cnt := 0.U req := io.req.bits acked := false.B } } .elsewhen (state === s_fill_buffer) { io.meta_read.valid := data_req_cnt < refillCycles.U io.meta_read.bits.idx := req.idx io.meta_read.bits.tag := req.tag io.data_req.valid := data_req_cnt < refillCycles.U io.data_req.bits.way_en := req.way_en io.data_req.bits.addr := (if(refillCycles > 1) Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0)) else req.idx) << rowOffBits r1_data_req_fired := false.B r1_data_req_cnt := 0.U r2_data_req_fired := r1_data_req_fired r2_data_req_cnt := r1_data_req_cnt when (io.data_req.fire && io.meta_read.fire) { r1_data_req_fired := true.B r1_data_req_cnt := data_req_cnt data_req_cnt := data_req_cnt + 1.U } when (r2_data_req_fired) { wb_buffer(r2_data_req_cnt) := io.data_resp when (r2_data_req_cnt === (refillCycles-1).U) { io.resp := true.B state := s_lsu_release data_req_cnt := 0.U } } } .elsewhen (state === s_lsu_release) { io.lsu_release.valid := true.B io.lsu_release.bits := probeResponse when (io.lsu_release.fire) { state := s_active } } .elsewhen (state === s_active) { io.release.valid := data_req_cnt < refillCycles.U io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse) when (io.mem_grant) { acked := true.B } when (io.release.fire) { data_req_cnt := data_req_cnt + 1.U } when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) { state := Mux(req.voluntary, s_grant, s_invalid) } } .elsewhen (state === s_grant) { when (io.mem_grant) { acked := true.B } when (acked) { state := s_invalid } } } class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Decoupled(new TLBundleB(edge.bundle))) val rep = Decoupled(new TLBundleC(edge.bundle)) val meta_read = Decoupled(new L1MetaReadReq) val meta_write = Decoupled(new L1MetaWriteReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val way_en = Input(UInt(nWays.W)) val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed? val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own? val block_state = Input(new ClientMetadata()) val lsu_release = Decoupled(new TLBundleC(edge.bundle)) val state = Output(Valid(UInt(coreMaxAddrBits.W))) }) val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: s_meta_write_resp :: Nil) = Enum(11) val state = RegInit(s_invalid) val req = Reg(new TLBundleB(edge.bundle)) val req_idx = req.address(idxMSB, idxLSB) val req_tag = req.address >> untagBits val way_en = Reg(UInt()) val tag_matches = way_en.orR val old_coh = Reg(new ClientMetadata) val miss_coh = ClientMetadata.onReset val reply_coh = Mux(tag_matches, old_coh, miss_coh) val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param) io.state.valid := state =/= s_invalid io.state.bits := req.address io.req.ready := state === s_invalid io.rep.valid := state === s_release io.rep.bits := edge.ProbeAck(req, report_param) assert(!io.rep.valid || !edge.hasData(io.rep.bits), "ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it") io.meta_read.valid := state === s_meta_read io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := ~(0.U(nWays.W)) io.meta_write.valid := state === s_meta_write io.meta_write.bits.way_en := way_en io.meta_write.bits.idx := req_idx io.meta_write.bits.tag := req_tag io.meta_write.bits.data.tag := req_tag io.meta_write.bits.data.coh := new_coh io.wb_req.valid := state === s_writeback_req io.wb_req.bits.source := req.source io.wb_req.bits.idx := req_idx io.wb_req.bits.tag := req_tag io.wb_req.bits.param := report_param io.wb_req.bits.way_en := way_en io.wb_req.bits.voluntary := false.B io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp) io.lsu_release.valid := state === s_lsu_release io.lsu_release.bits := edge.ProbeAck(req, report_param) // state === s_invalid when (state === s_invalid) { when (io.req.fire) { state := s_meta_read req := io.req.bits } } .elsewhen (state === s_meta_read) { when (io.meta_read.fire) { state := s_meta_resp } } .elsewhen (state === s_meta_resp) { // we need to wait one cycle for the metadata to be read from the array state := s_mshr_req } .elsewhen (state === s_mshr_req) { old_coh := io.block_state way_en := io.way_en // if the read didn't go through, we need to retry state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read) } .elsewhen (state === s_mshr_resp) { state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release) } .elsewhen (state === s_lsu_release) { when (io.lsu_release.fire) { state := s_release } } .elsewhen (state === s_release) { when (io.rep.ready) { state := Mux(tag_matches, s_meta_write, s_invalid) } } .elsewhen (state === s_writeback_req) { when (io.wb_req.fire) { state := s_writeback_resp } } .elsewhen (state === s_writeback_resp) { // wait for the writeback request to finish before updating the metadata when (io.wb_req.ready) { state := s_meta_write } } .elsewhen (state === s_meta_write) { when (io.meta_write.fire) { state := s_meta_write_resp } } .elsewhen (state === s_meta_write_resp) { state := s_invalid } } class BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(lsuWidth, new L1MetaReadReq) } class BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) { val req = Vec(lsuWidth, new L1DataReadReq) val valid = Vec(lsuWidth, Bool()) } abstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters { val io = IO(new BoomBundle { val read = Input(Vec(lsuWidth, Valid(new L1DataReadReq))) val write = Input(Valid(new L1DataWriteReq)) val resp = Output(Vec(lsuWidth, Vec(nWays, Bits(encRowBits.W)))) val s1_nacks = Output(Vec(lsuWidth, Bool())) }) def pipeMap[T <: Data](f: Int => T) = VecInit((0 until lsuWidth).map(f)) } class BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val waddr = io.write.bits.addr >> rowOffBits for (j <- 0 until lsuWidth) { val raddr = io.read(j).bits.addr >> rowOffBits for (w <- 0 until nWays) { val array = DescribedSRAM( name = s"array_${w}_${j}", desc = "Non-blocking DCache Data Array", size = nSets * refillCycles, data = Vec(rowWords, Bits(encDataBits.W)) ) when (io.write.bits.way_en(w) && io.write.valid) { val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))) array.write(waddr, data, io.write.bits.wmask.asBools) } if (dcacheSinglePorted) io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt) else io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).valid).asUInt) } io.s1_nacks(j) := false.B } } class BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray { val nBanks = boomParams.numDCacheBanks val bankSize = nSets * refillCycles / nBanks require (nBanks >= lsuWidth) require (bankSize > 0) val bankBits = log2Ceil(nBanks) val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes) val bidxBits = log2Ceil(bankSize) val bidxOffBits = bankOffBits + bankBits //---------------------------------------------------------------------------------------------------- val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U) val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0))) val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0) val s0_read_valids = VecInit(io.read.map(_.valid)) val s0_bank_conflicts = pipeMap(w => { ((s0_rbanks(w) === s0_wbank) && io.write.valid && dcacheSinglePorted.B) || (0 until w).foldLeft(false.B)((c,i) => c || io.read(i).valid && s0_rbanks(i) === s0_rbanks(w)) }) val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c} val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)})) val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools //---------------------------------------------------------------------------------------------------- val s1_rbanks = RegNext(s0_rbanks) val s1_ridxs = RegNext(s0_ridxs) val s1_read_valids = RegNext(s0_read_valids) val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j => if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i) else if (j == i) true.B else false.B)))) val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i) else if (j == i) true.B else false.B)) val s1_nacks = pipeMap(w => s1_read_valids(w) && (!RegNext(s0_do_bank_read(w)) || (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR) ) val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks)) //---------------------------------------------------------------------------------------------------- val s2_bank_selection = RegNext(s1_bank_selection) io.s1_nacks := s1_nacks val data_arrays = Seq.tabulate(nBanks) { b => DescribedSRAM( name = s"array_${b}", desc = "Boom DCache data array", size = bankSize, data = Vec(nWays * rowWords, Bits(encDataBits.W)) ) } val s2_bank_reads = Reg(Vec(nBanks, Vec(nWays, Bits(encRowBits.W)))) for (b <- 0 until nBanks) { val array = data_arrays(b) val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs) val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en)) val write_en = s0_bank_write_gnt(b) val write_mask = Cat(Seq.tabulate(nWays) { w => Mux(io.write.bits.way_en(w), io.write.bits.wmask, 0.U(rowWords.W)) }.reverse).asBools val read_en = WireInit(s0_bank_read_gnts(b).reduce(_||_)) s2_bank_reads(b) := (if (dcacheSinglePorted) { assert(!(read_en && write_en)) array.read(ridx, !write_en && read_en) } else { array.read(ridx, read_en) }).asTypeOf(Vec(nWays, Bits(encRowBits.W))) when (write_en) { val data = Wire(Vec(nWays * rowWords, Bits(encDataBits.W))) for (w <- 0 until nWays) { for (i <- 0 until rowWords) { data(w*rowWords+i) := io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i) } } array.write(s0_widx, data, write_mask) } } for (w <- 0 until nWays) { for (i <- 0 until lsuWidth) { io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i))(w) } } } /** * Top level class wrapping a non-blocking dcache. * * @param hartid hardware thread for the cache */ class BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule { private val tileParams = p(TileKey) protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache", sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO", sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs), requestFifo = true)) val node = TLClientNode(Seq(TLMasterPortParameters.v1( cacheClientParameters ++ mmioClientParameters, minLatency = 1))) lazy val module = new BoomNonBlockingDCacheModule(this) def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) { val errors = new DCacheErrors val lsu = Flipped(new LSUDMemIO) } class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters with HasBoomCoreParameters { implicit val edge = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new BoomDCacheBundle) io.errors := DontCare private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}") } def widthMap[T <: Data](f: Int => T) = VecInit((0 until lsuWidth).map(f)) val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6) val wb = Module(new BoomWritebackUnit) val prober = Module(new BoomProbeUnit) val mshrs = Module(new BoomMSHRFile) mshrs.io.clear_all := io.lsu.force_order mshrs.io.brupdate := io.lsu.brupdate mshrs.io.exception := io.lsu.exception mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx mshrs.io.rob_head_idx := io.lsu.rob_head_idx // tags def onReset = L1Metadata(0.U, ClientMetadata.onReset) val meta = Seq.fill(lsuWidth) { Module(new L1MetadataArray(onReset _)) } val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2)) // 0 goes to MSHR refills, 1 goes to prober val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6)) // 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read, // 4 goes to pipeline, 5 goes to prefetcher metaReadArb.io.in := DontCare for (w <- 0 until lsuWidth) { meta(w).io.write.valid := metaWriteArb.io.out.fire meta(w).io.write.bits := metaWriteArb.io.out.bits meta(w).io.read.valid := metaReadArb.io.out.valid meta(w).io.read.bits := metaReadArb.io.out.bits.req(w) } metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_||_) metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_||_) // data val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray) val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2)) // 0 goes to pipeline, 1 goes to MSHR refills val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3)) // 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline dataReadArb.io.in := DontCare for (w <- 0 until lsuWidth) { data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid data.io.read(w).bits := dataReadArb.io.out.bits.req(w) } dataReadArb.io.out.ready := true.B data.io.write.valid := dataWriteArb.io.out.fire data.io.write.bits := dataWriteArb.io.out.bits dataWriteArb.io.out.ready := true.B val singlePortedDCacheWrite = data.io.write.valid && dcacheSinglePorted.B // ------------ // New requests // In a 1-wide LSU, load/store wakeups and MSHR resps contend for same port, so // we should block incoming requests when the MSHR trying to respond val block_incoming_reqs = (lsuWidth == 1).B && mshrs.io.resp.valid io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready && !block_incoming_reqs metaReadArb.io.in(4).valid := io.lsu.req.valid && !block_incoming_reqs dataReadArb.io.in(2).valid := io.lsu.req.valid && !block_incoming_reqs for (w <- 0 until lsuWidth) { // Tag read for new requests metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits metaReadArb.io.in(4).bits.req(w).way_en := DontCare metaReadArb.io.in(4).bits.req(w).tag := DontCare // Data read for new requests dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W) } // ------------ // MSHR Replays val replay_req = Wire(Vec(lsuWidth, new BoomDCacheReq)) replay_req := DontCare replay_req(0).uop := mshrs.io.replay.bits.uop replay_req(0).addr := mshrs.io.replay.bits.addr replay_req(0).data := mshrs.io.replay.bits.data replay_req(0).is_hella := mshrs.io.replay.bits.is_hella // Don't let replays get nacked due to conflict with dcache write mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready && !singlePortedDCacheWrite // Tag read for MSHR replays // We don't actually need to read the metadata, for replays we already know our way metaReadArb.io.in(0).valid := mshrs.io.replay.valid && !singlePortedDCacheWrite metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits metaReadArb.io.in(0).bits.req(0).way_en := DontCare metaReadArb.io.in(0).bits.req(0).tag := DontCare // Data read for MSHR replays dataReadArb.io.in(0).valid := mshrs.io.replay.valid && !singlePortedDCacheWrite dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B) // ----------- // MSHR Meta read val mshr_read_req = Wire(Vec(lsuWidth, new BoomDCacheReq)) mshr_read_req := DontCare mshr_read_req(0).uop := NullMicroOp mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits mshr_read_req(0).data := DontCare mshr_read_req(0).is_hella := false.B metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready // ----------- // Write-backs val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire val wb_req = Wire(Vec(lsuWidth, new BoomDCacheReq)) wb_req := DontCare wb_req(0).uop := NullMicroOp wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr) wb_req(0).data := DontCare wb_req(0).is_hella := false.B // Couple the two decoupled interfaces of the WBUnit's meta_read and data_read // Can't launch data read if possibility of conflict w. write // Tag read for write-back metaReadArb.io.in(2).valid := wb.io.meta_read.valid && !singlePortedDCacheWrite metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready && !singlePortedDCacheWrite // Data read for write-back dataReadArb.io.in(1).valid := wb.io.data_req.valid && !singlePortedDCacheWrite dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B) wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready && !singlePortedDCacheWrite assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire)) // ------- // Prober val prober_fire = prober.io.meta_read.fire val prober_req = Wire(Vec(lsuWidth, new BoomDCacheReq)) prober_req := DontCare prober_req(0).uop := NullMicroOp prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits prober_req(0).data := DontCare prober_req(0).is_hella := false.B // Tag read for prober metaReadArb.io.in(1).valid := prober.io.meta_read.valid metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits prober.io.meta_read.ready := metaReadArb.io.in(1).ready // Prober does not need to read data array // ------- // Prefetcher val prefetch_fire = mshrs.io.prefetch.fire val prefetch_req = Wire(Vec(lsuWidth, new BoomDCacheReq)) prefetch_req := DontCare prefetch_req(0) := mshrs.io.prefetch.bits // Tag read for prefetch metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits metaReadArb.io.in(5).bits.req(0).way_en := DontCare metaReadArb.io.in(5).bits.req(0).tag := DontCare mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready // Prefetch does not need to read data array val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)), Mux(mshrs.io.replay.fire || wb_fire || prober_fire || prefetch_fire || mshrs.io.meta_read.fire, VecInit(1.U(lsuWidth.W).asBools), VecInit(0.U(lsuWidth.W).asBools))) val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)), Mux(wb_fire , wb_req, Mux(prober_fire , prober_req, Mux(prefetch_fire , prefetch_req, Mux(mshrs.io.meta_read.fire, mshr_read_req , replay_req))))) val s0_type = Mux(io.lsu.req.fire , t_lsu, Mux(wb_fire , t_wb, Mux(prober_fire , t_probe, Mux(prefetch_fire , t_prefetch, Mux(mshrs.io.meta_read.fire, t_mshr_meta_read , t_replay))))) // Does this request need to send a response or nack val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid, VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(lsuWidth.W), 0.U(lsuWidth.W)).asBools)) val s1_req = RegNext(s0_req) for (w <- 0 until lsuWidth) s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop) val s2_store_failed = Wire(Bool()) val s1_valid = widthMap(w => RegNext(s0_valid(w) && !IsKilledByBranch(io.lsu.brupdate, false.B, s0_req(w).uop) && !(io.lsu.exception && s0_req(w).uop.uses_ldq) && !(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq), init=false.B)) for (w <- 0 until lsuWidth) assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid))) val s1_addr = s1_req.map(_.addr) val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready) val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack) val s1_type = RegNext(s0_type) val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en) val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en) // tag check def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f)) val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt) val s1_tag_match_way = widthMap(i => Mux(s1_type === t_replay, s1_replay_way_en, Mux(s1_type === t_wb, s1_wb_way_en, Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en, wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt)))) val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid) for (w <- 0 until lsuWidth) { io.lsu.s1_nack_advisory(w) := data.io.s1_nacks(w) } val s2_req = RegNext(s1_req) val s2_type = RegNext(s1_type) val s2_valid = widthMap(w => RegNext(s1_valid(w) && !io.lsu.s1_kill(w) && !IsKilledByBranch(io.lsu.brupdate, false.B, s1_req(w).uop) && !(io.lsu.exception && s1_req(w).uop.uses_ldq) && !(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq))) for (w <- 0 until lsuWidth) s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop) val s2_tag_match_way = RegNext(s1_tag_match_way) val s2_tag_match = s2_tag_match_way.map(_.orR) val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh)))) val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1) val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3) val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) || s2_type.isOneOf(t_replay, t_wb)) val s2_nack = Wire(Vec(lsuWidth, Bool())) assert(!(s2_type === t_replay && !s2_hit(0)), "Replays should always hit") assert(!(s2_type === t_wb && !s2_hit(0)), "Writeback should always see data hit") val s2_wb_idx_matches = RegNext(s1_wb_idx_matches) // lr/sc val debug_sc_fail_addr = RegInit(0.U) val debug_sc_fail_cnt = RegInit(0.U(8.W)) val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W)) val lrsc_valid = lrsc_count > lrscBackoff.U val lrsc_addr = Reg(UInt()) val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) || s2_type === t_replay) val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) || s2_type === t_replay) val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits)) val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0) when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U } when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) || (s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) { when (s2_lr) { lrsc_count := (lrscCycles - 1).U lrsc_addr := s2_req(0).addr >> blockOffBits } when (lrsc_count > 0.U) { lrsc_count := 0.U } } for (w <- 0 until lsuWidth) { when (s2_valid(w) && s2_type === t_lsu && !s2_hit(w) && !(s2_has_permission(w) && s2_tag_match(w)) && s2_lrsc_addr_match(w) && !s2_nack(w)) { lrsc_count := 0.U } } when (s2_valid(0)) { when (s2_req(0).addr === debug_sc_fail_addr) { when (s2_sc_fail) { debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U } .elsewhen (s2_sc) { debug_sc_fail_cnt := 0.U } } .otherwise { when (s2_sc_fail) { debug_sc_fail_addr := s2_req(0).addr debug_sc_fail_cnt := 1.U } } } assert(debug_sc_fail_cnt < 100.U, "L1DCache failed too many SCs in a row") val s2_data = Wire(Vec(lsuWidth, Vec(nWays, UInt(encRowBits.W)))) for (i <- 0 until lsuWidth) { for (w <- 0 until nWays) { s2_data(i)(w) := data.io.resp(i)(w) } } val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w))) val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWords*wordBytes)-1, log2Up(wordBytes))) // replacement policy val replacer = cacheParams.replacement val s1_replaced_way_en = UIntToOH(replacer.way) val s2_replaced_way_en = UIntToOH(RegNext(replacer.way)) val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq)) // nack because of incoming probe val s2_nack_hit = RegNext(VecInit(s1_nack)) // Nack when we hit something currently being evicted val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w)) // MSHRs not ready for request val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready) // Bank conflict on data arrays val s2_nack_data = widthMap(w => s2_valid(w) && RegNext(data.io.s1_nacks(w))) // Can't allocate MSHR for same set currently being written back val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w)) s2_nack := widthMap(w => (s2_nack_miss(w) || s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w) || s2_nack_wb(w)) && s2_type =/= t_replay) assert(!(s2_nack_data.reduce(_||_) && s2_type.isOneOf(t_replay, t_wb))) val s2_send_resp = widthMap(w => ( RegNext(s1_send_resp_or_nack(w)) && (!(s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w)) || s2_type === t_replay) && s2_hit(w) && isRead(s2_req(w).uop.mem_cmd) )) val s2_send_store_ack = widthMap(w => ( RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) && isWrite(s2_req(w).uop.mem_cmd) && (s2_hit(w) || mshrs.io.req(w).fire))) val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w))) for (w <- 0 until lsuWidth) assert(!(s2_send_resp(w) && s2_send_nack(w))) // hits always send a response // If MSHR is not available, LSU has to replay this request later // If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq // Miss handling for (w <- 0 until lsuWidth) { mshrs.io.req(w).valid := s2_valid(w) && !s2_hit(w) && !s2_nack_hit(w) && !s2_nack_victim(w) && !s2_nack_data(w) && !s2_nack_wb(w) && s2_type.isOneOf(t_lsu, t_prefetch) && !(io.lsu.exception && s2_req(w).uop.uses_ldq) && (isPrefetch(s2_req(w).uop.mem_cmd) || isRead(s2_req(w).uop.mem_cmd) || isWrite(s2_req(w).uop.mem_cmd)) assert(!(mshrs.io.req(w).valid && s2_type === t_replay), "Replays should not need to go back into MSHRs") mshrs.io.req(w).bits := DontCare mshrs.io.req(w).bits.uop := s2_req(w).uop mshrs.io.req(w).bits.addr := s2_req(w).addr mshrs.io.req(w).bits.tag_match := s2_tag_match(w) mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w)) mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en) mshrs.io.req(w).bits.data := s2_req(w).data mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w) } mshrs.io.meta_resp.valid := !s2_nack_hit(0) || prober.io.mshr_wb_rdy mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp)) when (mshrs.io.req.map(_.fire).reduce(_||_)) { replacer.miss } tl_out.a <> mshrs.io.mem_acquire // probes and releases prober.io.req.valid := tl_out.b.valid && !lrsc_valid tl_out.b.ready := prober.io.req.ready && !lrsc_valid prober.io.req.bits := tl_out.b.bits prober.io.way_en := s2_tag_match_way(0) prober.io.block_state := s2_hit_state(0) metaWriteArb.io.in(1) <> prober.io.meta_write prober.io.mshr_rdy := mshrs.io.probe_rdy prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid mshrs.io.prober_state := prober.io.state // refills when (tl_out.d.bits.source === cfg.nMSHRs.U) { // This should be ReleaseAck tl_out.d.ready := true.B mshrs.io.mem_grant.valid := false.B mshrs.io.mem_grant.bits := DontCare } .otherwise { // This should be GrantData mshrs.io.mem_grant <> tl_out.d } dataWriteArb.io.in(1) <> mshrs.io.refill metaWriteArb.io.in(0) <> mshrs.io.meta_write tl_out.e <> mshrs.io.mem_finish // writebacks val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2)) // 0 goes to prober, 1 goes to MSHR evictions wbArb.io.in(0) <> prober.io.wb_req wbArb.io.in(1) <> mshrs.io.wb_req wb.io.req <> wbArb.io.out wb.io.data_resp := s2_data_muxed(0) mshrs.io.wb_resp := wb.io.resp wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2)) io.lsu.release <> lsu_release_arb.io.out lsu_release_arb.io.in(0) <> wb.io.lsu_release lsu_release_arb.io.in(1) <> prober.io.lsu_release TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep) io.lsu.perf.release := edge.done(tl_out.c) io.lsu.perf.acquire := edge.done(tl_out.a) // load data gen val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W))) val s2_data_word = Wire(Vec(lsuWidth, UInt())) val loadgen = (0 until lsuWidth).map { w => new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr, s2_data_word(w), s2_sc && (w == 0).B, wordBytes) } // Mux between cache responses and uncache responses for (w <- 0 until lsuWidth) { io.lsu.resp(w).valid := s2_valid(w) && s2_send_resp(w) io.lsu.resp(w).bits.uop := s2_req(w).uop io.lsu.resp(w).bits.data := loadgen(w).data | s2_sc_fail io.lsu.resp(w).bits.is_hella := s2_req(w).is_hella io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) io.lsu.nack(w).bits := s2_req(w) assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu)) io.lsu.store_ack(w).valid := s2_valid(w) && s2_send_store_ack(w) && (w == 0).B io.lsu.store_ack(w).bits := s2_req(w) } io.lsu.ll_resp <> mshrs.io.resp // Store/amo hits val s3_req = Wire(new BoomDCacheReq) s3_req := RegNext(s2_req(0)) val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(0) && s2_nack(0))) val s3_data_word = RegNext(s2_data_word(0)) for (w <- 1 until lsuWidth) { assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) && !s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))), "Store must go through 0th pipe in L1D") } // For bypassing val s4_req = RegNext(s3_req) val s4_valid = RegNext(s3_valid) val s5_req = RegNext(s4_req) val s5_valid = RegNext(s4_valid) val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits))) val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits))) val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits))) // Store -> Load bypassing for (w <- 0 until lsuWidth) { s2_data_word(w) := Mux(s3_bypass(w), s3_req.data, Mux(s4_bypass(w), s4_req.data, Mux(s5_bypass(w), s5_req.data, s2_data_word_prebypass(w)))) } val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := new StoreGen(s3_req.uop.mem_size, s3_req.addr, 0.U, xLen/8).mask amoalu.io.cmd := s3_req.uop.mem_cmd amoalu.io.lhs := s3_data_word amoalu.io.rhs := RegNext(s2_req(0).data) s3_req.data := amoalu.io.out val s3_way = RegNext(s2_tag_match_way(0)) dataWriteArb.io.in(0).valid := s3_valid dataWriteArb.io.in(0).bits.addr := s3_req.addr dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb)) dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data) dataWriteArb.io.in(0).bits.way_en := s3_way io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_||_) && !s2_valid.reduce(_||_) } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways * (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) | wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /** @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree */ def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File consts.scala: //****************************************************************************** // Copyright (c) 2011 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Constants //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.common.constants import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import freechips.rocketchip.rocket.RVCExpander /** * Mixin for scalar operation constants */ trait ScalarOpConstants { val X = BitPat("b?") val Y = BitPat("b1") val N = BitPat("b0") //************************************ // Extra Constants // Which branch predictor predicted us val BSRC_SZ = 3 val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred val BSRC_4 = 3.U(BSRC_SZ.W) // 4-cycle branch pred val BSRC_C = 4.U(BSRC_SZ.W) // core branch resolution //************************************ // Control Signals // CFI types val CFI_SZ = 3 val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction val CFI_BR = 1.U(CFI_SZ.W) // Branch val CFI_JAL = 2.U(CFI_SZ.W) // JAL val CFI_JALR = 3.U(CFI_SZ.W) // JALR // PC Select Signal val PC_PLUS4 = 0.U(2.W) // PC + 4 val PC_BRJMP = 1.U(2.W) // brjmp_target val PC_JALR = 2.U(2.W) // jump_reg_target // Branch Type val B_N = 0.U(4.W) // Next val B_NE = 1.U(4.W) // Branch on NotEqual val B_EQ = 2.U(4.W) // Branch on Equal val B_GE = 3.U(4.W) // Branch on Greater/Equal val B_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned val B_LT = 5.U(4.W) // Branch on Less Than val B_LTU = 6.U(4.W) // Branch on Less Than Unsigned val B_J = 7.U(4.W) // Jump val B_JR = 8.U(4.W) // Jump Register // RS1 Operand Select Signal val OP1_RS1 = 0.U(2.W) // Register Source #1 val OP1_ZERO= 1.U(2.W) val OP1_PC = 2.U(2.W) val OP1_RS1SHL = 3.U(2.W) val OP1_X = BitPat("b??") // RS2 Operand Select Signal val OP2_RS2 = 0.U(3.W) // Register Source #2 val OP2_IMM = 1.U(3.W) // immediate val OP2_ZERO= 2.U(3.W) // constant 0 val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4) val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1 val OP2_RS2OH = 5.U(3.W) val OP2_IMMOH = 6.U(3.W) val OP2_X = BitPat("b???") // Register File Write Enable Signal val REN_0 = false.B val REN_1 = true.B // Is 32b Word or 64b Doubldword? val SZ_DW = 1 val DW_X = true.B // Bool(xLen==64) val DW_32 = false.B val DW_64 = true.B val DW_XPR = true.B // Bool(xLen==64) // Memory Enable Signal val MEN_0 = false.B val MEN_1 = true.B val MEN_X = false.B // Immediate Extend Select val IS_I = 0.U(3.W) // I-Type (LD,ALU) val IS_S = 1.U(3.W) // S-Type (ST) val IS_B = 2.U(3.W) // SB-Type (BR) val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC) val IS_J = 4.U(3.W) // UJ-Type (J/JAL) val IS_SH = 5.U(3.W) // short-type (sign extend from pimm to get imm) val IS_N = 6.U(3.W) // No immediate (zeros immediate) val IS_F3 = 7.U(3.W) // funct3 // Decode Stage Control Signals val RT_FIX = 0.U(2.W) val RT_FLT = 1.U(2.W) val RT_X = 2.U(2.W) // not-a-register (prs1 = lrs1 special case) val RT_ZERO = 3.U(2.W) // IQT type val IQ_SZ = 4 val IQ_MEM = 0 val IQ_UNQ = 1 val IQ_ALU = 2 val IQ_FP = 3 // Functional unit select // bit mask, since a given execution pipeline may support multiple functional units val FC_SZ = 10 val FC_ALU = 0 val FC_AGEN = 1 val FC_DGEN = 2 val FC_MUL = 3 val FC_DIV = 4 val FC_CSR = 5 val FC_FPU = 6 val FC_FDV = 7 val FC_I2F = 8 val FC_F2I = 9 def NullMicroOp(implicit p: Parameters) = 0.U.asTypeOf(new boom.v4.common.MicroOp) } /** * Mixin for RISCV constants */ trait RISCVConstants { // abstract out instruction decode magic numbers val RD_MSB = 11 val RD_LSB = 7 val RS1_MSB = 19 val RS1_LSB = 15 val RS2_MSB = 24 val RS2_LSB = 20 val RS3_MSB = 31 val RS3_LSB = 27 val CSR_ADDR_MSB = 31 val CSR_ADDR_LSB = 20 val CSR_ADDR_SZ = 12 // location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.) val SHAMT_5_BIT = 25 val LONGEST_IMM_SZ = 20 val X0 = 0.U val RA = 1.U // return address register // memory consistency model // The C/C++ atomics MCM requires that two loads to the same address maintain program order. // The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior). val MCM_ORDER_DEPENDENT_LOADS = true val jal_opc = (0x6f).U val jalr_opc = (0x67).U def GetUop(inst: UInt): UInt = inst(6,0) def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB) def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB) def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = { val rvc_exp = Module(new RVCExpander) rvc_exp.io.in := inst Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst) } // Note: Accepts only EXPANDED rvc instructions def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) ((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = { val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) ((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt } // Note: Accepts only EXPANDED rvc instructions def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = { val bdecode = Module(new boom.v4.exu.BranchDecode) bdecode.io.inst := inst bdecode.io.pc := 0.U bdecode.io.out.cfi_type } } /** * Mixin for exception cause constants */ trait ExcCauseConstants { // a memory disambigious misspeculation occurred val MINI_EXCEPTION_MEM_ORDERING = 16.U val MINI_EXCEPTION_CSR_REPLAY = 17.U require (!freechips.rocketchip.rocket.Causes.all.contains(16)) require (!freechips.rocketchip.rocket.Causes.all.contains(17)) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_||_).init assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_||_) || winner.reduce(_||_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_*) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. */ class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /** This tests that the lowest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /** This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize*8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) | Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and || logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out | ~wmask & io.lhs io.out_unmasked := out }
module BoomNonBlockingDCache( // @[dcache.scala:438:7] input clock, // @[dcache.scala:438:7] input reset, // @[dcache.scala:438:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [15:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output io_lsu_req_ready, // @[dcache.scala:444:14] input io_lsu_req_valid, // @[dcache.scala:444:14] input io_lsu_req_bits_0_valid, // @[dcache.scala:444:14] input [31:0] io_lsu_req_bits_0_bits_uop_inst, // @[dcache.scala:444:14] input [31:0] io_lsu_req_bits_0_bits_uop_debug_inst, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_rvc, // @[dcache.scala:444:14] input [39:0] io_lsu_req_bits_0_bits_uop_debug_pc, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iq_type_0, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iq_type_1, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iq_type_2, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iq_type_3, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_0, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_1, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_2, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_3, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_4, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_5, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_6, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_7, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_8, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fu_code_9, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iw_issued, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_dis_col_sel, // @[dcache.scala:444:14] input [15:0] io_lsu_req_bits_0_bits_uop_br_mask, // @[dcache.scala:444:14] input [3:0] io_lsu_req_bits_0_bits_uop_br_tag, // @[dcache.scala:444:14] input [3:0] io_lsu_req_bits_0_bits_uop_br_type, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_sfb, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_fence, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_fencei, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_sfence, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_amo, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_eret, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_rocc, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_mov, // @[dcache.scala:444:14] input [4:0] io_lsu_req_bits_0_bits_uop_ftq_idx, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_edge_inst, // @[dcache.scala:444:14] input [5:0] io_lsu_req_bits_0_bits_uop_pc_lob, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_taken, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_imm_rename, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_imm_sel, // @[dcache.scala:444:14] input [4:0] io_lsu_req_bits_0_bits_uop_pimm, // @[dcache.scala:444:14] input [19:0] io_lsu_req_bits_0_bits_uop_imm_packed, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_op1_sel, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_op2_sel, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14] input [6:0] io_lsu_req_bits_0_bits_uop_rob_idx, // @[dcache.scala:444:14] input [4:0] io_lsu_req_bits_0_bits_uop_ldq_idx, // @[dcache.scala:444:14] input [4:0] io_lsu_req_bits_0_bits_uop_stq_idx, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx, // @[dcache.scala:444:14] input [6:0] io_lsu_req_bits_0_bits_uop_pdst, // @[dcache.scala:444:14] input [6:0] io_lsu_req_bits_0_bits_uop_prs1, // @[dcache.scala:444:14] input [6:0] io_lsu_req_bits_0_bits_uop_prs2, // @[dcache.scala:444:14] input [6:0] io_lsu_req_bits_0_bits_uop_prs3, // @[dcache.scala:444:14] input [4:0] io_lsu_req_bits_0_bits_uop_ppred, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_prs1_busy, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_prs2_busy, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_prs3_busy, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_ppred_busy, // @[dcache.scala:444:14] input [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_exception, // @[dcache.scala:444:14] input [63:0] io_lsu_req_bits_0_bits_uop_exc_cause, // @[dcache.scala:444:14] input [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_mem_size, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_mem_signed, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_uses_ldq, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_uses_stq, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_is_unique, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_flush_on_commit, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_csr_cmd, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14] input [5:0] io_lsu_req_bits_0_bits_uop_ldst, // @[dcache.scala:444:14] input [5:0] io_lsu_req_bits_0_bits_uop_lrs1, // @[dcache.scala:444:14] input [5:0] io_lsu_req_bits_0_bits_uop_lrs2, // @[dcache.scala:444:14] input [5:0] io_lsu_req_bits_0_bits_uop_lrs3, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_frs3_en, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fcn_dw, // @[dcache.scala:444:14] input [4:0] io_lsu_req_bits_0_bits_uop_fcn_op, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_fp_val, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_fp_rm, // @[dcache.scala:444:14] input [1:0] io_lsu_req_bits_0_bits_uop_fp_typ, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_bp_debug_if, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_debug_fsrc, // @[dcache.scala:444:14] input [2:0] io_lsu_req_bits_0_bits_uop_debug_tsrc, // @[dcache.scala:444:14] input [39:0] io_lsu_req_bits_0_bits_addr, // @[dcache.scala:444:14] input [63:0] io_lsu_req_bits_0_bits_data, // @[dcache.scala:444:14] input io_lsu_req_bits_0_bits_is_hella, // @[dcache.scala:444:14] input io_lsu_s1_kill_0, // @[dcache.scala:444:14] output io_lsu_resp_0_valid, // @[dcache.scala:444:14] output [31:0] io_lsu_resp_0_bits_uop_inst, // @[dcache.scala:444:14] output [31:0] io_lsu_resp_0_bits_uop_debug_inst, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_rvc, // @[dcache.scala:444:14] output [39:0] io_lsu_resp_0_bits_uop_debug_pc, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iq_type_0, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iq_type_1, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iq_type_2, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iq_type_3, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_0, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_1, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_2, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_3, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_4, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_5, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_6, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_7, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_8, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fu_code_9, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iw_issued, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_dis_col_sel, // @[dcache.scala:444:14] output [15:0] io_lsu_resp_0_bits_uop_br_mask, // @[dcache.scala:444:14] output [3:0] io_lsu_resp_0_bits_uop_br_tag, // @[dcache.scala:444:14] output [3:0] io_lsu_resp_0_bits_uop_br_type, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_sfb, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_fence, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_fencei, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_sfence, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_amo, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_eret, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_rocc, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_mov, // @[dcache.scala:444:14] output [4:0] io_lsu_resp_0_bits_uop_ftq_idx, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_edge_inst, // @[dcache.scala:444:14] output [5:0] io_lsu_resp_0_bits_uop_pc_lob, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_taken, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_imm_rename, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_imm_sel, // @[dcache.scala:444:14] output [4:0] io_lsu_resp_0_bits_uop_pimm, // @[dcache.scala:444:14] output [19:0] io_lsu_resp_0_bits_uop_imm_packed, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_op1_sel, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_op2_sel, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14] output [6:0] io_lsu_resp_0_bits_uop_rob_idx, // @[dcache.scala:444:14] output [4:0] io_lsu_resp_0_bits_uop_ldq_idx, // @[dcache.scala:444:14] output [4:0] io_lsu_resp_0_bits_uop_stq_idx, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_rxq_idx, // @[dcache.scala:444:14] output [6:0] io_lsu_resp_0_bits_uop_pdst, // @[dcache.scala:444:14] output [6:0] io_lsu_resp_0_bits_uop_prs1, // @[dcache.scala:444:14] output [6:0] io_lsu_resp_0_bits_uop_prs2, // @[dcache.scala:444:14] output [6:0] io_lsu_resp_0_bits_uop_prs3, // @[dcache.scala:444:14] output [4:0] io_lsu_resp_0_bits_uop_ppred, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_prs1_busy, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_prs2_busy, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_prs3_busy, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_ppred_busy, // @[dcache.scala:444:14] output [6:0] io_lsu_resp_0_bits_uop_stale_pdst, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_exception, // @[dcache.scala:444:14] output [63:0] io_lsu_resp_0_bits_uop_exc_cause, // @[dcache.scala:444:14] output [4:0] io_lsu_resp_0_bits_uop_mem_cmd, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_mem_size, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_mem_signed, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_uses_ldq, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_uses_stq, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_is_unique, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_flush_on_commit, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_csr_cmd, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14] output [5:0] io_lsu_resp_0_bits_uop_ldst, // @[dcache.scala:444:14] output [5:0] io_lsu_resp_0_bits_uop_lrs1, // @[dcache.scala:444:14] output [5:0] io_lsu_resp_0_bits_uop_lrs2, // @[dcache.scala:444:14] output [5:0] io_lsu_resp_0_bits_uop_lrs3, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_dst_rtype, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_frs3_en, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fcn_dw, // @[dcache.scala:444:14] output [4:0] io_lsu_resp_0_bits_uop_fcn_op, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_fp_val, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_fp_rm, // @[dcache.scala:444:14] output [1:0] io_lsu_resp_0_bits_uop_fp_typ, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_bp_debug_if, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_debug_fsrc, // @[dcache.scala:444:14] output [2:0] io_lsu_resp_0_bits_uop_debug_tsrc, // @[dcache.scala:444:14] output [63:0] io_lsu_resp_0_bits_data, // @[dcache.scala:444:14] output io_lsu_resp_0_bits_is_hella, // @[dcache.scala:444:14] output io_lsu_store_ack_0_valid, // @[dcache.scala:444:14] output [31:0] io_lsu_store_ack_0_bits_uop_inst, // @[dcache.scala:444:14] output [31:0] io_lsu_store_ack_0_bits_uop_debug_inst, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_rvc, // @[dcache.scala:444:14] output [39:0] io_lsu_store_ack_0_bits_uop_debug_pc, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iq_type_0, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iq_type_1, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iq_type_2, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iq_type_3, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_0, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_1, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_2, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_3, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_4, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_5, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_6, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_7, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_8, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fu_code_9, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iw_issued, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_dis_col_sel, // @[dcache.scala:444:14] output [15:0] io_lsu_store_ack_0_bits_uop_br_mask, // @[dcache.scala:444:14] output [3:0] io_lsu_store_ack_0_bits_uop_br_tag, // @[dcache.scala:444:14] output [3:0] io_lsu_store_ack_0_bits_uop_br_type, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_sfb, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_fence, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_fencei, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_sfence, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_amo, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_eret, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_rocc, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_mov, // @[dcache.scala:444:14] output [4:0] io_lsu_store_ack_0_bits_uop_ftq_idx, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_edge_inst, // @[dcache.scala:444:14] output [5:0] io_lsu_store_ack_0_bits_uop_pc_lob, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_taken, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_imm_rename, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_imm_sel, // @[dcache.scala:444:14] output [4:0] io_lsu_store_ack_0_bits_uop_pimm, // @[dcache.scala:444:14] output [19:0] io_lsu_store_ack_0_bits_uop_imm_packed, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_op1_sel, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_op2_sel, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14] output [6:0] io_lsu_store_ack_0_bits_uop_rob_idx, // @[dcache.scala:444:14] output [4:0] io_lsu_store_ack_0_bits_uop_ldq_idx, // @[dcache.scala:444:14] output [4:0] io_lsu_store_ack_0_bits_uop_stq_idx, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_rxq_idx, // @[dcache.scala:444:14] output [6:0] io_lsu_store_ack_0_bits_uop_pdst, // @[dcache.scala:444:14] output [6:0] io_lsu_store_ack_0_bits_uop_prs1, // @[dcache.scala:444:14] output [6:0] io_lsu_store_ack_0_bits_uop_prs2, // @[dcache.scala:444:14] output [6:0] io_lsu_store_ack_0_bits_uop_prs3, // @[dcache.scala:444:14] output [4:0] io_lsu_store_ack_0_bits_uop_ppred, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_prs1_busy, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_prs2_busy, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_prs3_busy, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_ppred_busy, // @[dcache.scala:444:14] output [6:0] io_lsu_store_ack_0_bits_uop_stale_pdst, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_exception, // @[dcache.scala:444:14] output [63:0] io_lsu_store_ack_0_bits_uop_exc_cause, // @[dcache.scala:444:14] output [4:0] io_lsu_store_ack_0_bits_uop_mem_cmd, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_mem_size, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_mem_signed, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_uses_ldq, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_uses_stq, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_is_unique, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_flush_on_commit, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_csr_cmd, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14] output [5:0] io_lsu_store_ack_0_bits_uop_ldst, // @[dcache.scala:444:14] output [5:0] io_lsu_store_ack_0_bits_uop_lrs1, // @[dcache.scala:444:14] output [5:0] io_lsu_store_ack_0_bits_uop_lrs2, // @[dcache.scala:444:14] output [5:0] io_lsu_store_ack_0_bits_uop_lrs3, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_dst_rtype, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_lrs1_rtype, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_lrs2_rtype, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_frs3_en, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fcn_dw, // @[dcache.scala:444:14] output [4:0] io_lsu_store_ack_0_bits_uop_fcn_op, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_fp_val, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_fp_rm, // @[dcache.scala:444:14] output [1:0] io_lsu_store_ack_0_bits_uop_fp_typ, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_bp_debug_if, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_debug_fsrc, // @[dcache.scala:444:14] output [2:0] io_lsu_store_ack_0_bits_uop_debug_tsrc, // @[dcache.scala:444:14] output [39:0] io_lsu_store_ack_0_bits_addr, // @[dcache.scala:444:14] output [63:0] io_lsu_store_ack_0_bits_data, // @[dcache.scala:444:14] output io_lsu_store_ack_0_bits_is_hella, // @[dcache.scala:444:14] output io_lsu_nack_0_valid, // @[dcache.scala:444:14] output [31:0] io_lsu_nack_0_bits_uop_inst, // @[dcache.scala:444:14] output [31:0] io_lsu_nack_0_bits_uop_debug_inst, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_rvc, // @[dcache.scala:444:14] output [39:0] io_lsu_nack_0_bits_uop_debug_pc, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iq_type_0, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iq_type_1, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iq_type_2, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iq_type_3, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_0, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_1, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_2, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_3, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_4, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_5, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_6, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_7, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_8, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fu_code_9, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iw_issued, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_dis_col_sel, // @[dcache.scala:444:14] output [15:0] io_lsu_nack_0_bits_uop_br_mask, // @[dcache.scala:444:14] output [3:0] io_lsu_nack_0_bits_uop_br_tag, // @[dcache.scala:444:14] output [3:0] io_lsu_nack_0_bits_uop_br_type, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_sfb, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_fence, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_fencei, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_sfence, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_amo, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_eret, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_rocc, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_mov, // @[dcache.scala:444:14] output [4:0] io_lsu_nack_0_bits_uop_ftq_idx, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_edge_inst, // @[dcache.scala:444:14] output [5:0] io_lsu_nack_0_bits_uop_pc_lob, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_taken, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_imm_rename, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_imm_sel, // @[dcache.scala:444:14] output [4:0] io_lsu_nack_0_bits_uop_pimm, // @[dcache.scala:444:14] output [19:0] io_lsu_nack_0_bits_uop_imm_packed, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_op1_sel, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_op2_sel, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14] output [6:0] io_lsu_nack_0_bits_uop_rob_idx, // @[dcache.scala:444:14] output [4:0] io_lsu_nack_0_bits_uop_ldq_idx, // @[dcache.scala:444:14] output [4:0] io_lsu_nack_0_bits_uop_stq_idx, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_rxq_idx, // @[dcache.scala:444:14] output [6:0] io_lsu_nack_0_bits_uop_pdst, // @[dcache.scala:444:14] output [6:0] io_lsu_nack_0_bits_uop_prs1, // @[dcache.scala:444:14] output [6:0] io_lsu_nack_0_bits_uop_prs2, // @[dcache.scala:444:14] output [6:0] io_lsu_nack_0_bits_uop_prs3, // @[dcache.scala:444:14] output [4:0] io_lsu_nack_0_bits_uop_ppred, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_prs1_busy, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_prs2_busy, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_prs3_busy, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_ppred_busy, // @[dcache.scala:444:14] output [6:0] io_lsu_nack_0_bits_uop_stale_pdst, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_exception, // @[dcache.scala:444:14] output [63:0] io_lsu_nack_0_bits_uop_exc_cause, // @[dcache.scala:444:14] output [4:0] io_lsu_nack_0_bits_uop_mem_cmd, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_mem_size, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_mem_signed, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_uses_ldq, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_uses_stq, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_is_unique, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_flush_on_commit, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_csr_cmd, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14] output [5:0] io_lsu_nack_0_bits_uop_ldst, // @[dcache.scala:444:14] output [5:0] io_lsu_nack_0_bits_uop_lrs1, // @[dcache.scala:444:14] output [5:0] io_lsu_nack_0_bits_uop_lrs2, // @[dcache.scala:444:14] output [5:0] io_lsu_nack_0_bits_uop_lrs3, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_dst_rtype, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_frs3_en, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fcn_dw, // @[dcache.scala:444:14] output [4:0] io_lsu_nack_0_bits_uop_fcn_op, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_fp_val, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_fp_rm, // @[dcache.scala:444:14] output [1:0] io_lsu_nack_0_bits_uop_fp_typ, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_bp_debug_if, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_debug_fsrc, // @[dcache.scala:444:14] output [2:0] io_lsu_nack_0_bits_uop_debug_tsrc, // @[dcache.scala:444:14] output [39:0] io_lsu_nack_0_bits_addr, // @[dcache.scala:444:14] output [63:0] io_lsu_nack_0_bits_data, // @[dcache.scala:444:14] output io_lsu_nack_0_bits_is_hella, // @[dcache.scala:444:14] input io_lsu_ll_resp_ready, // @[dcache.scala:444:14] output io_lsu_ll_resp_valid, // @[dcache.scala:444:14] output [31:0] io_lsu_ll_resp_bits_uop_inst, // @[dcache.scala:444:14] output [31:0] io_lsu_ll_resp_bits_uop_debug_inst, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_rvc, // @[dcache.scala:444:14] output [39:0] io_lsu_ll_resp_bits_uop_debug_pc, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iq_type_0, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iq_type_1, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iq_type_2, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iq_type_3, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_0, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_1, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_2, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_3, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_4, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_5, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_6, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_7, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_8, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fu_code_9, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iw_issued, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iw_issued_partial_agen, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_iw_p1_speculative_child, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_iw_p2_speculative_child, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_dis_col_sel, // @[dcache.scala:444:14] output [15:0] io_lsu_ll_resp_bits_uop_br_mask, // @[dcache.scala:444:14] output [3:0] io_lsu_ll_resp_bits_uop_br_tag, // @[dcache.scala:444:14] output [3:0] io_lsu_ll_resp_bits_uop_br_type, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_sfb, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_fence, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_fencei, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_sfence, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_amo, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_eret, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_sys_pc2epc, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_rocc, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_mov, // @[dcache.scala:444:14] output [4:0] io_lsu_ll_resp_bits_uop_ftq_idx, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_edge_inst, // @[dcache.scala:444:14] output [5:0] io_lsu_ll_resp_bits_uop_pc_lob, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_taken, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_imm_rename, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_imm_sel, // @[dcache.scala:444:14] output [4:0] io_lsu_ll_resp_bits_uop_pimm, // @[dcache.scala:444:14] output [19:0] io_lsu_ll_resp_bits_uop_imm_packed, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_op1_sel, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_op2_sel, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_ldst, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_wen, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_ren1, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_ren2, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_ren3, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_swap12, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_swap23, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_fromint, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_toint, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_fma, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_div, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_wflags, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_ctrl_vec, // @[dcache.scala:444:14] output [6:0] io_lsu_ll_resp_bits_uop_rob_idx, // @[dcache.scala:444:14] output [4:0] io_lsu_ll_resp_bits_uop_ldq_idx, // @[dcache.scala:444:14] output [4:0] io_lsu_ll_resp_bits_uop_stq_idx, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_rxq_idx, // @[dcache.scala:444:14] output [6:0] io_lsu_ll_resp_bits_uop_pdst, // @[dcache.scala:444:14] output [6:0] io_lsu_ll_resp_bits_uop_prs1, // @[dcache.scala:444:14] output [6:0] io_lsu_ll_resp_bits_uop_prs2, // @[dcache.scala:444:14] output [6:0] io_lsu_ll_resp_bits_uop_prs3, // @[dcache.scala:444:14] output [4:0] io_lsu_ll_resp_bits_uop_ppred, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_prs1_busy, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_prs2_busy, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_prs3_busy, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_ppred_busy, // @[dcache.scala:444:14] output [6:0] io_lsu_ll_resp_bits_uop_stale_pdst, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_exception, // @[dcache.scala:444:14] output [63:0] io_lsu_ll_resp_bits_uop_exc_cause, // @[dcache.scala:444:14] output [4:0] io_lsu_ll_resp_bits_uop_mem_cmd, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_mem_size, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_mem_signed, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_uses_ldq, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_uses_stq, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_is_unique, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_flush_on_commit, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_csr_cmd, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_ldst_is_rs1, // @[dcache.scala:444:14] output [5:0] io_lsu_ll_resp_bits_uop_ldst, // @[dcache.scala:444:14] output [5:0] io_lsu_ll_resp_bits_uop_lrs1, // @[dcache.scala:444:14] output [5:0] io_lsu_ll_resp_bits_uop_lrs2, // @[dcache.scala:444:14] output [5:0] io_lsu_ll_resp_bits_uop_lrs3, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_dst_rtype, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_lrs1_rtype, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_lrs2_rtype, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_frs3_en, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fcn_dw, // @[dcache.scala:444:14] output [4:0] io_lsu_ll_resp_bits_uop_fcn_op, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_fp_val, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_fp_rm, // @[dcache.scala:444:14] output [1:0] io_lsu_ll_resp_bits_uop_fp_typ, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_xcpt_pf_if, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_xcpt_ae_if, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_xcpt_ma_if, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_bp_debug_if, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_uop_bp_xcpt_if, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_debug_fsrc, // @[dcache.scala:444:14] output [2:0] io_lsu_ll_resp_bits_uop_debug_tsrc, // @[dcache.scala:444:14] output [63:0] io_lsu_ll_resp_bits_data, // @[dcache.scala:444:14] output io_lsu_ll_resp_bits_is_hella, // @[dcache.scala:444:14] input [15:0] io_lsu_brupdate_b1_resolve_mask, // @[dcache.scala:444:14] input [15:0] io_lsu_brupdate_b1_mispredict_mask, // @[dcache.scala:444:14] input [31:0] io_lsu_brupdate_b2_uop_inst, // @[dcache.scala:444:14] input [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_rvc, // @[dcache.scala:444:14] input [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iq_type_0, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iq_type_1, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iq_type_2, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iq_type_3, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_0, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_1, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_2, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_3, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_4, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_5, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_6, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_7, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_8, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fu_code_9, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iw_issued, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iw_issued_partial_agen, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iw_issued_partial_dgen, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_iw_p1_speculative_child, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_iw_p2_speculative_child, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iw_p1_bypass_hint, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iw_p2_bypass_hint, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_iw_p3_bypass_hint, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_dis_col_sel, // @[dcache.scala:444:14] input [15:0] io_lsu_brupdate_b2_uop_br_mask, // @[dcache.scala:444:14] input [3:0] io_lsu_brupdate_b2_uop_br_tag, // @[dcache.scala:444:14] input [3:0] io_lsu_brupdate_b2_uop_br_type, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_sfb, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_fence, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_fencei, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_sfence, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_amo, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_eret, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_rocc, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_mov, // @[dcache.scala:444:14] input [4:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_edge_inst, // @[dcache.scala:444:14] input [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_taken, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_imm_rename, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_imm_sel, // @[dcache.scala:444:14] input [4:0] io_lsu_brupdate_b2_uop_pimm, // @[dcache.scala:444:14] input [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_op1_sel, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_op2_sel, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_ldst, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_wen, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_ren1, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_ren2, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_ren3, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_swap12, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_swap23, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_fromint, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_toint, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_fma, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_div, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_sqrt, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_wflags, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_ctrl_vec, // @[dcache.scala:444:14] input [6:0] io_lsu_brupdate_b2_uop_rob_idx, // @[dcache.scala:444:14] input [4:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[dcache.scala:444:14] input [4:0] io_lsu_brupdate_b2_uop_stq_idx, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[dcache.scala:444:14] input [6:0] io_lsu_brupdate_b2_uop_pdst, // @[dcache.scala:444:14] input [6:0] io_lsu_brupdate_b2_uop_prs1, // @[dcache.scala:444:14] input [6:0] io_lsu_brupdate_b2_uop_prs2, // @[dcache.scala:444:14] input [6:0] io_lsu_brupdate_b2_uop_prs3, // @[dcache.scala:444:14] input [4:0] io_lsu_brupdate_b2_uop_ppred, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_prs1_busy, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_prs2_busy, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_prs3_busy, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_ppred_busy, // @[dcache.scala:444:14] input [6:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_exception, // @[dcache.scala:444:14] input [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[dcache.scala:444:14] input [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_mem_signed, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_uses_ldq, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_uses_stq, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_is_unique, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_flush_on_commit, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_csr_cmd, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[dcache.scala:444:14] input [5:0] io_lsu_brupdate_b2_uop_ldst, // @[dcache.scala:444:14] input [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[dcache.scala:444:14] input [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[dcache.scala:444:14] input [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_frs3_en, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fcn_dw, // @[dcache.scala:444:14] input [4:0] io_lsu_brupdate_b2_uop_fcn_op, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_fp_val, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_fp_rm, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_uop_fp_typ, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_bp_debug_if, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_mispredict, // @[dcache.scala:444:14] input io_lsu_brupdate_b2_taken, // @[dcache.scala:444:14] input [2:0] io_lsu_brupdate_b2_cfi_type, // @[dcache.scala:444:14] input [1:0] io_lsu_brupdate_b2_pc_sel, // @[dcache.scala:444:14] input [39:0] io_lsu_brupdate_b2_jalr_target, // @[dcache.scala:444:14] input [20:0] io_lsu_brupdate_b2_target_offset, // @[dcache.scala:444:14] input io_lsu_exception, // @[dcache.scala:444:14] input [6:0] io_lsu_rob_pnr_idx, // @[dcache.scala:444:14] input [6:0] io_lsu_rob_head_idx, // @[dcache.scala:444:14] input io_lsu_release_ready, // @[dcache.scala:444:14] output io_lsu_release_valid, // @[dcache.scala:444:14] output [2:0] io_lsu_release_bits_opcode, // @[dcache.scala:444:14] output [2:0] io_lsu_release_bits_param, // @[dcache.scala:444:14] output [3:0] io_lsu_release_bits_size, // @[dcache.scala:444:14] output [2:0] io_lsu_release_bits_source, // @[dcache.scala:444:14] output [31:0] io_lsu_release_bits_address, // @[dcache.scala:444:14] output [127:0] io_lsu_release_bits_data, // @[dcache.scala:444:14] input io_lsu_force_order, // @[dcache.scala:444:14] output io_lsu_ordered, // @[dcache.scala:444:14] output io_lsu_perf_acquire, // @[dcache.scala:444:14] output io_lsu_perf_release // @[dcache.scala:444:14] ); wire [1:0] s3_req_uop_mem_size; // @[dcache.scala:895:22] wire [1:0] _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73] wire [1:0] _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73] wire _mshrs_io_replay_ready_T; // @[dcache.scala:534:58] wire _lsu_release_arb_io_in_0_ready; // @[dcache.scala:857:31] wire _lsu_release_arb_io_in_1_ready; // @[dcache.scala:857:31] wire _wbArb_io_in_0_ready; // @[dcache.scala:848:21] wire _wbArb_io_in_1_ready; // @[dcache.scala:848:21] wire _wbArb_io_out_valid; // @[dcache.scala:848:21] wire [19:0] _wbArb_io_out_bits_tag; // @[dcache.scala:848:21] wire [5:0] _wbArb_io_out_bits_idx; // @[dcache.scala:848:21] wire [2:0] _wbArb_io_out_bits_source; // @[dcache.scala:848:21] wire [2:0] _wbArb_io_out_bits_param; // @[dcache.scala:848:21] wire [7:0] _wbArb_io_out_bits_way_en; // @[dcache.scala:848:21] wire _wbArb_io_out_bits_voluntary; // @[dcache.scala:848:21] wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22] wire _dataReadArb_io_in_1_ready; // @[dcache.scala:490:27] wire _dataReadArb_io_in_2_ready; // @[dcache.scala:490:27] wire _dataReadArb_io_out_valid; // @[dcache.scala:490:27] wire [7:0] _dataReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:490:27] wire [11:0] _dataReadArb_io_out_bits_req_0_addr; // @[dcache.scala:490:27] wire _dataReadArb_io_out_bits_valid_0; // @[dcache.scala:490:27] wire _dataWriteArb_io_in_1_ready; // @[dcache.scala:488:28] wire [7:0] _dataWriteArb_io_out_bits_way_en; // @[dcache.scala:488:28] wire [11:0] _dataWriteArb_io_out_bits_addr; // @[dcache.scala:488:28] wire [1:0] _dataWriteArb_io_out_bits_wmask; // @[dcache.scala:488:28] wire [127:0] _dataWriteArb_io_out_bits_data; // @[dcache.scala:488:28] wire _metaReadArb_io_in_1_ready; // @[dcache.scala:472:27] wire _metaReadArb_io_in_2_ready; // @[dcache.scala:472:27] wire _metaReadArb_io_in_3_ready; // @[dcache.scala:472:27] wire _metaReadArb_io_in_4_ready; // @[dcache.scala:472:27] wire _metaReadArb_io_in_5_ready; // @[dcache.scala:472:27] wire _metaReadArb_io_out_valid; // @[dcache.scala:472:27] wire [5:0] _metaReadArb_io_out_bits_req_0_idx; // @[dcache.scala:472:27] wire [7:0] _metaReadArb_io_out_bits_req_0_way_en; // @[dcache.scala:472:27] wire [19:0] _metaReadArb_io_out_bits_req_0_tag; // @[dcache.scala:472:27] wire _metaWriteArb_io_in_0_ready; // @[dcache.scala:470:28] wire _metaWriteArb_io_in_1_ready; // @[dcache.scala:470:28] wire _metaWriteArb_io_out_valid; // @[dcache.scala:470:28] wire [5:0] _metaWriteArb_io_out_bits_idx; // @[dcache.scala:470:28] wire [7:0] _metaWriteArb_io_out_bits_way_en; // @[dcache.scala:470:28] wire [19:0] _metaWriteArb_io_out_bits_tag; // @[dcache.scala:470:28] wire [1:0] _metaWriteArb_io_out_bits_data_coh_state; // @[dcache.scala:470:28] wire [19:0] _metaWriteArb_io_out_bits_data_tag; // @[dcache.scala:470:28] wire _meta_0_io_read_ready; // @[dcache.scala:469:41] wire _meta_0_io_write_ready; // @[dcache.scala:469:41] wire [1:0] _meta_0_io_resp_0_coh_state; // @[dcache.scala:469:41] wire [19:0] _meta_0_io_resp_0_tag; // @[dcache.scala:469:41] wire [1:0] _meta_0_io_resp_1_coh_state; // @[dcache.scala:469:41] wire [19:0] _meta_0_io_resp_1_tag; // @[dcache.scala:469:41] wire [1:0] _meta_0_io_resp_2_coh_state; // @[dcache.scala:469:41] wire [19:0] _meta_0_io_resp_2_tag; // @[dcache.scala:469:41] wire [1:0] _meta_0_io_resp_3_coh_state; // @[dcache.scala:469:41] wire [19:0] _meta_0_io_resp_3_tag; // @[dcache.scala:469:41] wire [1:0] _meta_0_io_resp_4_coh_state; // @[dcache.scala:469:41] wire [19:0] _meta_0_io_resp_4_tag; // @[dcache.scala:469:41] wire [1:0] _meta_0_io_resp_5_coh_state; // @[dcache.scala:469:41] wire [19:0] _meta_0_io_resp_5_tag; // @[dcache.scala:469:41] wire [1:0] _meta_0_io_resp_6_coh_state; // @[dcache.scala:469:41] wire [19:0] _meta_0_io_resp_6_tag; // @[dcache.scala:469:41] wire [1:0] _meta_0_io_resp_7_coh_state; // @[dcache.scala:469:41] wire [19:0] _meta_0_io_resp_7_tag; // @[dcache.scala:469:41] wire _mshrs_io_req_0_ready; // @[dcache.scala:460:21] wire _mshrs_io_resp_valid; // @[dcache.scala:460:21] wire _mshrs_io_secondary_miss_0; // @[dcache.scala:460:21] wire _mshrs_io_block_hit_0; // @[dcache.scala:460:21] wire _mshrs_io_mem_grant_ready; // @[dcache.scala:460:21] wire _mshrs_io_refill_valid; // @[dcache.scala:460:21] wire [7:0] _mshrs_io_refill_bits_way_en; // @[dcache.scala:460:21] wire [11:0] _mshrs_io_refill_bits_addr; // @[dcache.scala:460:21] wire [127:0] _mshrs_io_refill_bits_data; // @[dcache.scala:460:21] wire _mshrs_io_meta_write_valid; // @[dcache.scala:460:21] wire [5:0] _mshrs_io_meta_write_bits_idx; // @[dcache.scala:460:21] wire [7:0] _mshrs_io_meta_write_bits_way_en; // @[dcache.scala:460:21] wire [19:0] _mshrs_io_meta_write_bits_tag; // @[dcache.scala:460:21] wire [1:0] _mshrs_io_meta_write_bits_data_coh_state; // @[dcache.scala:460:21] wire [19:0] _mshrs_io_meta_write_bits_data_tag; // @[dcache.scala:460:21] wire _mshrs_io_meta_read_valid; // @[dcache.scala:460:21] wire [5:0] _mshrs_io_meta_read_bits_idx; // @[dcache.scala:460:21] wire [7:0] _mshrs_io_meta_read_bits_way_en; // @[dcache.scala:460:21] wire [19:0] _mshrs_io_meta_read_bits_tag; // @[dcache.scala:460:21] wire _mshrs_io_replay_valid; // @[dcache.scala:460:21] wire [4:0] _mshrs_io_replay_bits_uop_mem_cmd; // @[dcache.scala:460:21] wire [39:0] _mshrs_io_replay_bits_addr; // @[dcache.scala:460:21] wire [7:0] _mshrs_io_replay_bits_way_en; // @[dcache.scala:460:21] wire _mshrs_io_wb_req_valid; // @[dcache.scala:460:21] wire [19:0] _mshrs_io_wb_req_bits_tag; // @[dcache.scala:460:21] wire [5:0] _mshrs_io_wb_req_bits_idx; // @[dcache.scala:460:21] wire [2:0] _mshrs_io_wb_req_bits_source; // @[dcache.scala:460:21] wire [2:0] _mshrs_io_wb_req_bits_param; // @[dcache.scala:460:21] wire [7:0] _mshrs_io_wb_req_bits_way_en; // @[dcache.scala:460:21] wire _mshrs_io_fence_rdy; // @[dcache.scala:460:21] wire _mshrs_io_probe_rdy; // @[dcache.scala:460:21] wire _prober_io_req_ready; // @[dcache.scala:459:22] wire _prober_io_rep_valid; // @[dcache.scala:459:22] wire [2:0] _prober_io_rep_bits_param; // @[dcache.scala:459:22] wire [3:0] _prober_io_rep_bits_size; // @[dcache.scala:459:22] wire [2:0] _prober_io_rep_bits_source; // @[dcache.scala:459:22] wire [31:0] _prober_io_rep_bits_address; // @[dcache.scala:459:22] wire _prober_io_meta_read_valid; // @[dcache.scala:459:22] wire [5:0] _prober_io_meta_read_bits_idx; // @[dcache.scala:459:22] wire [19:0] _prober_io_meta_read_bits_tag; // @[dcache.scala:459:22] wire _prober_io_meta_write_valid; // @[dcache.scala:459:22] wire [5:0] _prober_io_meta_write_bits_idx; // @[dcache.scala:459:22] wire [7:0] _prober_io_meta_write_bits_way_en; // @[dcache.scala:459:22] wire [19:0] _prober_io_meta_write_bits_tag; // @[dcache.scala:459:22] wire [1:0] _prober_io_meta_write_bits_data_coh_state; // @[dcache.scala:459:22] wire [19:0] _prober_io_meta_write_bits_data_tag; // @[dcache.scala:459:22] wire _prober_io_wb_req_valid; // @[dcache.scala:459:22] wire [19:0] _prober_io_wb_req_bits_tag; // @[dcache.scala:459:22] wire [5:0] _prober_io_wb_req_bits_idx; // @[dcache.scala:459:22] wire [2:0] _prober_io_wb_req_bits_source; // @[dcache.scala:459:22] wire [2:0] _prober_io_wb_req_bits_param; // @[dcache.scala:459:22] wire [7:0] _prober_io_wb_req_bits_way_en; // @[dcache.scala:459:22] wire _prober_io_mshr_wb_rdy; // @[dcache.scala:459:22] wire _prober_io_lsu_release_valid; // @[dcache.scala:459:22] wire [2:0] _prober_io_lsu_release_bits_param; // @[dcache.scala:459:22] wire [3:0] _prober_io_lsu_release_bits_size; // @[dcache.scala:459:22] wire [2:0] _prober_io_lsu_release_bits_source; // @[dcache.scala:459:22] wire [31:0] _prober_io_lsu_release_bits_address; // @[dcache.scala:459:22] wire _prober_io_state_valid; // @[dcache.scala:459:22] wire [39:0] _prober_io_state_bits; // @[dcache.scala:459:22] wire _wb_io_req_ready; // @[dcache.scala:458:18] wire _wb_io_meta_read_valid; // @[dcache.scala:458:18] wire [5:0] _wb_io_meta_read_bits_idx; // @[dcache.scala:458:18] wire [19:0] _wb_io_meta_read_bits_tag; // @[dcache.scala:458:18] wire _wb_io_resp; // @[dcache.scala:458:18] wire _wb_io_idx_valid; // @[dcache.scala:458:18] wire [5:0] _wb_io_idx_bits; // @[dcache.scala:458:18] wire _wb_io_data_req_valid; // @[dcache.scala:458:18] wire [7:0] _wb_io_data_req_bits_way_en; // @[dcache.scala:458:18] wire [11:0] _wb_io_data_req_bits_addr; // @[dcache.scala:458:18] wire _wb_io_release_valid; // @[dcache.scala:458:18] wire [2:0] _wb_io_release_bits_opcode; // @[dcache.scala:458:18] wire [2:0] _wb_io_release_bits_param; // @[dcache.scala:458:18] wire [2:0] _wb_io_release_bits_source; // @[dcache.scala:458:18] wire [31:0] _wb_io_release_bits_address; // @[dcache.scala:458:18] wire [127:0] _wb_io_release_bits_data; // @[dcache.scala:458:18] wire _wb_io_lsu_release_valid; // @[dcache.scala:458:18] wire [2:0] _wb_io_lsu_release_bits_param; // @[dcache.scala:458:18] wire [2:0] _wb_io_lsu_release_bits_source; // @[dcache.scala:458:18] wire [31:0] _wb_io_lsu_release_bits_address; // @[dcache.scala:458:18] wire [127:0] _wb_io_lsu_release_bits_data; // @[dcache.scala:458:18] wire auto_out_a_ready_0 = auto_out_a_ready; // @[dcache.scala:438:7] wire auto_out_b_valid_0 = auto_out_b_valid; // @[dcache.scala:438:7] wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[dcache.scala:438:7] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[dcache.scala:438:7] wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[dcache.scala:438:7] wire [2:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[dcache.scala:438:7] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[dcache.scala:438:7] wire [15:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[dcache.scala:438:7] wire [127:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[dcache.scala:438:7] wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[dcache.scala:438:7] wire auto_out_c_ready_0 = auto_out_c_ready; // @[dcache.scala:438:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[dcache.scala:438:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[dcache.scala:438:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[dcache.scala:438:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[dcache.scala:438:7] wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[dcache.scala:438:7] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[dcache.scala:438:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[dcache.scala:438:7] wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[dcache.scala:438:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[dcache.scala:438:7] wire auto_out_e_ready_0 = auto_out_e_ready; // @[dcache.scala:438:7] wire io_lsu_req_valid_0 = io_lsu_req_valid; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_valid_0 = io_lsu_req_bits_0_valid; // @[dcache.scala:438:7] wire [31:0] io_lsu_req_bits_0_bits_uop_inst_0 = io_lsu_req_bits_0_bits_uop_inst; // @[dcache.scala:438:7] wire [31:0] io_lsu_req_bits_0_bits_uop_debug_inst_0 = io_lsu_req_bits_0_bits_uop_debug_inst; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_rvc_0 = io_lsu_req_bits_0_bits_uop_is_rvc; // @[dcache.scala:438:7] wire [39:0] io_lsu_req_bits_0_bits_uop_debug_pc_0 = io_lsu_req_bits_0_bits_uop_debug_pc; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iq_type_0_0 = io_lsu_req_bits_0_bits_uop_iq_type_0; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iq_type_1_0 = io_lsu_req_bits_0_bits_uop_iq_type_1; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iq_type_2_0 = io_lsu_req_bits_0_bits_uop_iq_type_2; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iq_type_3_0 = io_lsu_req_bits_0_bits_uop_iq_type_3; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_0_0 = io_lsu_req_bits_0_bits_uop_fu_code_0; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_1_0 = io_lsu_req_bits_0_bits_uop_fu_code_1; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_2_0 = io_lsu_req_bits_0_bits_uop_fu_code_2; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_3_0 = io_lsu_req_bits_0_bits_uop_fu_code_3; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_4_0 = io_lsu_req_bits_0_bits_uop_fu_code_4; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_5_0 = io_lsu_req_bits_0_bits_uop_fu_code_5; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_6_0 = io_lsu_req_bits_0_bits_uop_fu_code_6; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_7_0 = io_lsu_req_bits_0_bits_uop_fu_code_7; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_8_0 = io_lsu_req_bits_0_bits_uop_fu_code_8; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fu_code_9_0 = io_lsu_req_bits_0_bits_uop_fu_code_9; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iw_issued_0 = io_lsu_req_bits_0_bits_uop_iw_issued; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_dis_col_sel_0 = io_lsu_req_bits_0_bits_uop_dis_col_sel; // @[dcache.scala:438:7] wire [15:0] io_lsu_req_bits_0_bits_uop_br_mask_0 = io_lsu_req_bits_0_bits_uop_br_mask; // @[dcache.scala:438:7] wire [3:0] io_lsu_req_bits_0_bits_uop_br_tag_0 = io_lsu_req_bits_0_bits_uop_br_tag; // @[dcache.scala:438:7] wire [3:0] io_lsu_req_bits_0_bits_uop_br_type_0 = io_lsu_req_bits_0_bits_uop_br_type; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_sfb_0 = io_lsu_req_bits_0_bits_uop_is_sfb; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_fence_0 = io_lsu_req_bits_0_bits_uop_is_fence; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_fencei_0 = io_lsu_req_bits_0_bits_uop_is_fencei; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_sfence_0 = io_lsu_req_bits_0_bits_uop_is_sfence; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_amo_0 = io_lsu_req_bits_0_bits_uop_is_amo; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_eret_0 = io_lsu_req_bits_0_bits_uop_is_eret; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0 = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_rocc_0 = io_lsu_req_bits_0_bits_uop_is_rocc; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_mov_0 = io_lsu_req_bits_0_bits_uop_is_mov; // @[dcache.scala:438:7] wire [4:0] io_lsu_req_bits_0_bits_uop_ftq_idx_0 = io_lsu_req_bits_0_bits_uop_ftq_idx; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_edge_inst_0 = io_lsu_req_bits_0_bits_uop_edge_inst; // @[dcache.scala:438:7] wire [5:0] io_lsu_req_bits_0_bits_uop_pc_lob_0 = io_lsu_req_bits_0_bits_uop_pc_lob; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_taken_0 = io_lsu_req_bits_0_bits_uop_taken; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_imm_rename_0 = io_lsu_req_bits_0_bits_uop_imm_rename; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_imm_sel_0 = io_lsu_req_bits_0_bits_uop_imm_sel; // @[dcache.scala:438:7] wire [4:0] io_lsu_req_bits_0_bits_uop_pimm_0 = io_lsu_req_bits_0_bits_uop_pimm; // @[dcache.scala:438:7] wire [19:0] io_lsu_req_bits_0_bits_uop_imm_packed_0 = io_lsu_req_bits_0_bits_uop_imm_packed; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_op1_sel_0 = io_lsu_req_bits_0_bits_uop_op1_sel; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_op2_sel_0 = io_lsu_req_bits_0_bits_uop_op2_sel; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_wen_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_wen; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_toint_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_toint; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_fma_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_fma; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_div_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_div; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_ctrl_vec_0 = io_lsu_req_bits_0_bits_uop_fp_ctrl_vec; // @[dcache.scala:438:7] wire [6:0] io_lsu_req_bits_0_bits_uop_rob_idx_0 = io_lsu_req_bits_0_bits_uop_rob_idx; // @[dcache.scala:438:7] wire [4:0] io_lsu_req_bits_0_bits_uop_ldq_idx_0 = io_lsu_req_bits_0_bits_uop_ldq_idx; // @[dcache.scala:438:7] wire [4:0] io_lsu_req_bits_0_bits_uop_stq_idx_0 = io_lsu_req_bits_0_bits_uop_stq_idx; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_rxq_idx_0 = io_lsu_req_bits_0_bits_uop_rxq_idx; // @[dcache.scala:438:7] wire [6:0] io_lsu_req_bits_0_bits_uop_pdst_0 = io_lsu_req_bits_0_bits_uop_pdst; // @[dcache.scala:438:7] wire [6:0] io_lsu_req_bits_0_bits_uop_prs1_0 = io_lsu_req_bits_0_bits_uop_prs1; // @[dcache.scala:438:7] wire [6:0] io_lsu_req_bits_0_bits_uop_prs2_0 = io_lsu_req_bits_0_bits_uop_prs2; // @[dcache.scala:438:7] wire [6:0] io_lsu_req_bits_0_bits_uop_prs3_0 = io_lsu_req_bits_0_bits_uop_prs3; // @[dcache.scala:438:7] wire [4:0] io_lsu_req_bits_0_bits_uop_ppred_0 = io_lsu_req_bits_0_bits_uop_ppred; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_prs1_busy_0 = io_lsu_req_bits_0_bits_uop_prs1_busy; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_prs2_busy_0 = io_lsu_req_bits_0_bits_uop_prs2_busy; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_prs3_busy_0 = io_lsu_req_bits_0_bits_uop_prs3_busy; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_ppred_busy_0 = io_lsu_req_bits_0_bits_uop_ppred_busy; // @[dcache.scala:438:7] wire [6:0] io_lsu_req_bits_0_bits_uop_stale_pdst_0 = io_lsu_req_bits_0_bits_uop_stale_pdst; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_exception_0 = io_lsu_req_bits_0_bits_uop_exception; // @[dcache.scala:438:7] wire [63:0] io_lsu_req_bits_0_bits_uop_exc_cause_0 = io_lsu_req_bits_0_bits_uop_exc_cause; // @[dcache.scala:438:7] wire [4:0] io_lsu_req_bits_0_bits_uop_mem_cmd_0 = io_lsu_req_bits_0_bits_uop_mem_cmd; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_mem_size_0 = io_lsu_req_bits_0_bits_uop_mem_size; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_mem_signed_0 = io_lsu_req_bits_0_bits_uop_mem_signed; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_uses_ldq_0 = io_lsu_req_bits_0_bits_uop_uses_ldq; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_uses_stq_0 = io_lsu_req_bits_0_bits_uop_uses_stq; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_is_unique_0 = io_lsu_req_bits_0_bits_uop_is_unique; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_flush_on_commit_0 = io_lsu_req_bits_0_bits_uop_flush_on_commit; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_csr_cmd_0 = io_lsu_req_bits_0_bits_uop_csr_cmd; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1; // @[dcache.scala:438:7] wire [5:0] io_lsu_req_bits_0_bits_uop_ldst_0 = io_lsu_req_bits_0_bits_uop_ldst; // @[dcache.scala:438:7] wire [5:0] io_lsu_req_bits_0_bits_uop_lrs1_0 = io_lsu_req_bits_0_bits_uop_lrs1; // @[dcache.scala:438:7] wire [5:0] io_lsu_req_bits_0_bits_uop_lrs2_0 = io_lsu_req_bits_0_bits_uop_lrs2; // @[dcache.scala:438:7] wire [5:0] io_lsu_req_bits_0_bits_uop_lrs3_0 = io_lsu_req_bits_0_bits_uop_lrs3; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_dst_rtype_0 = io_lsu_req_bits_0_bits_uop_dst_rtype; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_lrs1_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs1_rtype; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_lrs2_rtype_0 = io_lsu_req_bits_0_bits_uop_lrs2_rtype; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_frs3_en_0 = io_lsu_req_bits_0_bits_uop_frs3_en; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fcn_dw_0 = io_lsu_req_bits_0_bits_uop_fcn_dw; // @[dcache.scala:438:7] wire [4:0] io_lsu_req_bits_0_bits_uop_fcn_op_0 = io_lsu_req_bits_0_bits_uop_fcn_op; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_fp_val_0 = io_lsu_req_bits_0_bits_uop_fp_val; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_fp_rm_0 = io_lsu_req_bits_0_bits_uop_fp_rm; // @[dcache.scala:438:7] wire [1:0] io_lsu_req_bits_0_bits_uop_fp_typ_0 = io_lsu_req_bits_0_bits_uop_fp_typ; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_pf_if; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ae_if; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0 = io_lsu_req_bits_0_bits_uop_xcpt_ma_if; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_bp_debug_if_0 = io_lsu_req_bits_0_bits_uop_bp_debug_if; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0 = io_lsu_req_bits_0_bits_uop_bp_xcpt_if; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_debug_fsrc_0 = io_lsu_req_bits_0_bits_uop_debug_fsrc; // @[dcache.scala:438:7] wire [2:0] io_lsu_req_bits_0_bits_uop_debug_tsrc_0 = io_lsu_req_bits_0_bits_uop_debug_tsrc; // @[dcache.scala:438:7] wire [39:0] io_lsu_req_bits_0_bits_addr_0 = io_lsu_req_bits_0_bits_addr; // @[dcache.scala:438:7] wire [63:0] io_lsu_req_bits_0_bits_data_0 = io_lsu_req_bits_0_bits_data; // @[dcache.scala:438:7] wire io_lsu_req_bits_0_bits_is_hella_0 = io_lsu_req_bits_0_bits_is_hella; // @[dcache.scala:438:7] wire io_lsu_s1_kill_0_0 = io_lsu_s1_kill_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_ready_0 = io_lsu_ll_resp_ready; // @[dcache.scala:438:7] wire [15:0] io_lsu_brupdate_b1_resolve_mask_0 = io_lsu_brupdate_b1_resolve_mask; // @[dcache.scala:438:7] wire [15:0] io_lsu_brupdate_b1_mispredict_mask_0 = io_lsu_brupdate_b1_mispredict_mask; // @[dcache.scala:438:7] wire [31:0] io_lsu_brupdate_b2_uop_inst_0 = io_lsu_brupdate_b2_uop_inst; // @[dcache.scala:438:7] wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0 = io_lsu_brupdate_b2_uop_debug_inst; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_rvc_0 = io_lsu_brupdate_b2_uop_is_rvc; // @[dcache.scala:438:7] wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0 = io_lsu_brupdate_b2_uop_debug_pc; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iq_type_0_0 = io_lsu_brupdate_b2_uop_iq_type_0; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iq_type_1_0 = io_lsu_brupdate_b2_uop_iq_type_1; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iq_type_2_0 = io_lsu_brupdate_b2_uop_iq_type_2; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iq_type_3_0 = io_lsu_brupdate_b2_uop_iq_type_3; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_0_0 = io_lsu_brupdate_b2_uop_fu_code_0; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_1_0 = io_lsu_brupdate_b2_uop_fu_code_1; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_2_0 = io_lsu_brupdate_b2_uop_fu_code_2; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_3_0 = io_lsu_brupdate_b2_uop_fu_code_3; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_4_0 = io_lsu_brupdate_b2_uop_fu_code_4; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_5_0 = io_lsu_brupdate_b2_uop_fu_code_5; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_6_0 = io_lsu_brupdate_b2_uop_fu_code_6; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_7_0 = io_lsu_brupdate_b2_uop_fu_code_7; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_8_0 = io_lsu_brupdate_b2_uop_fu_code_8; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fu_code_9_0 = io_lsu_brupdate_b2_uop_fu_code_9; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iw_issued_0 = io_lsu_brupdate_b2_uop_iw_issued; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iw_issued_partial_agen_0 = io_lsu_brupdate_b2_uop_iw_issued_partial_agen; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_lsu_brupdate_b2_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_iw_p1_speculative_child_0 = io_lsu_brupdate_b2_uop_iw_p1_speculative_child; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_iw_p2_speculative_child_0 = io_lsu_brupdate_b2_uop_iw_p2_speculative_child; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_lsu_brupdate_b2_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_lsu_brupdate_b2_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_lsu_brupdate_b2_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_dis_col_sel_0 = io_lsu_brupdate_b2_uop_dis_col_sel; // @[dcache.scala:438:7] wire [15:0] io_lsu_brupdate_b2_uop_br_mask_0 = io_lsu_brupdate_b2_uop_br_mask; // @[dcache.scala:438:7] wire [3:0] io_lsu_brupdate_b2_uop_br_tag_0 = io_lsu_brupdate_b2_uop_br_tag; // @[dcache.scala:438:7] wire [3:0] io_lsu_brupdate_b2_uop_br_type_0 = io_lsu_brupdate_b2_uop_br_type; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_sfb_0 = io_lsu_brupdate_b2_uop_is_sfb; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_fence_0 = io_lsu_brupdate_b2_uop_is_fence; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_fencei_0 = io_lsu_brupdate_b2_uop_is_fencei; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_sfence_0 = io_lsu_brupdate_b2_uop_is_sfence; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_amo_0 = io_lsu_brupdate_b2_uop_is_amo; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_eret_0 = io_lsu_brupdate_b2_uop_is_eret; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_rocc_0 = io_lsu_brupdate_b2_uop_is_rocc; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_mov_0 = io_lsu_brupdate_b2_uop_is_mov; // @[dcache.scala:438:7] wire [4:0] io_lsu_brupdate_b2_uop_ftq_idx_0 = io_lsu_brupdate_b2_uop_ftq_idx; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_edge_inst_0 = io_lsu_brupdate_b2_uop_edge_inst; // @[dcache.scala:438:7] wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0 = io_lsu_brupdate_b2_uop_pc_lob; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_taken_0 = io_lsu_brupdate_b2_uop_taken; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_imm_rename_0 = io_lsu_brupdate_b2_uop_imm_rename; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_imm_sel_0 = io_lsu_brupdate_b2_uop_imm_sel; // @[dcache.scala:438:7] wire [4:0] io_lsu_brupdate_b2_uop_pimm_0 = io_lsu_brupdate_b2_uop_pimm; // @[dcache.scala:438:7] wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0 = io_lsu_brupdate_b2_uop_imm_packed; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_op1_sel_0 = io_lsu_brupdate_b2_uop_op1_sel; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_op2_sel_0 = io_lsu_brupdate_b2_uop_op2_sel; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ldst_0 = io_lsu_brupdate_b2_uop_fp_ctrl_ldst; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_wen_0 = io_lsu_brupdate_b2_uop_fp_ctrl_wen; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren1_0 = io_lsu_brupdate_b2_uop_fp_ctrl_ren1; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren2_0 = io_lsu_brupdate_b2_uop_fp_ctrl_ren2; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren3_0 = io_lsu_brupdate_b2_uop_fp_ctrl_ren3; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_swap12_0 = io_lsu_brupdate_b2_uop_fp_ctrl_swap12; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_swap23_0 = io_lsu_brupdate_b2_uop_fp_ctrl_swap23; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fromint_0 = io_lsu_brupdate_b2_uop_fp_ctrl_fromint; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_toint_0 = io_lsu_brupdate_b2_uop_fp_ctrl_toint; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fma_0 = io_lsu_brupdate_b2_uop_fp_ctrl_fma; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_div_0 = io_lsu_brupdate_b2_uop_fp_ctrl_div; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_lsu_brupdate_b2_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_wflags_0 = io_lsu_brupdate_b2_uop_fp_ctrl_wflags; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_vec_0 = io_lsu_brupdate_b2_uop_fp_ctrl_vec; // @[dcache.scala:438:7] wire [6:0] io_lsu_brupdate_b2_uop_rob_idx_0 = io_lsu_brupdate_b2_uop_rob_idx; // @[dcache.scala:438:7] wire [4:0] io_lsu_brupdate_b2_uop_ldq_idx_0 = io_lsu_brupdate_b2_uop_ldq_idx; // @[dcache.scala:438:7] wire [4:0] io_lsu_brupdate_b2_uop_stq_idx_0 = io_lsu_brupdate_b2_uop_stq_idx; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0 = io_lsu_brupdate_b2_uop_rxq_idx; // @[dcache.scala:438:7] wire [6:0] io_lsu_brupdate_b2_uop_pdst_0 = io_lsu_brupdate_b2_uop_pdst; // @[dcache.scala:438:7] wire [6:0] io_lsu_brupdate_b2_uop_prs1_0 = io_lsu_brupdate_b2_uop_prs1; // @[dcache.scala:438:7] wire [6:0] io_lsu_brupdate_b2_uop_prs2_0 = io_lsu_brupdate_b2_uop_prs2; // @[dcache.scala:438:7] wire [6:0] io_lsu_brupdate_b2_uop_prs3_0 = io_lsu_brupdate_b2_uop_prs3; // @[dcache.scala:438:7] wire [4:0] io_lsu_brupdate_b2_uop_ppred_0 = io_lsu_brupdate_b2_uop_ppred; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_prs1_busy_0 = io_lsu_brupdate_b2_uop_prs1_busy; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_prs2_busy_0 = io_lsu_brupdate_b2_uop_prs2_busy; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_prs3_busy_0 = io_lsu_brupdate_b2_uop_prs3_busy; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_ppred_busy_0 = io_lsu_brupdate_b2_uop_ppred_busy; // @[dcache.scala:438:7] wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst_0 = io_lsu_brupdate_b2_uop_stale_pdst; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_exception_0 = io_lsu_brupdate_b2_uop_exception; // @[dcache.scala:438:7] wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0 = io_lsu_brupdate_b2_uop_exc_cause; // @[dcache.scala:438:7] wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0 = io_lsu_brupdate_b2_uop_mem_cmd; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0 = io_lsu_brupdate_b2_uop_mem_size; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_mem_signed_0 = io_lsu_brupdate_b2_uop_mem_signed; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_uses_ldq_0 = io_lsu_brupdate_b2_uop_uses_ldq; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_uses_stq_0 = io_lsu_brupdate_b2_uop_uses_stq; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_is_unique_0 = io_lsu_brupdate_b2_uop_is_unique; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_flush_on_commit_0 = io_lsu_brupdate_b2_uop_flush_on_commit; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_csr_cmd_0 = io_lsu_brupdate_b2_uop_csr_cmd; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[dcache.scala:438:7] wire [5:0] io_lsu_brupdate_b2_uop_ldst_0 = io_lsu_brupdate_b2_uop_ldst; // @[dcache.scala:438:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0 = io_lsu_brupdate_b2_uop_lrs1; // @[dcache.scala:438:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0 = io_lsu_brupdate_b2_uop_lrs2; // @[dcache.scala:438:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0 = io_lsu_brupdate_b2_uop_lrs3; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0 = io_lsu_brupdate_b2_uop_dst_rtype; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0 = io_lsu_brupdate_b2_uop_lrs1_rtype; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0 = io_lsu_brupdate_b2_uop_lrs2_rtype; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_frs3_en_0 = io_lsu_brupdate_b2_uop_frs3_en; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fcn_dw_0 = io_lsu_brupdate_b2_uop_fcn_dw; // @[dcache.scala:438:7] wire [4:0] io_lsu_brupdate_b2_uop_fcn_op_0 = io_lsu_brupdate_b2_uop_fcn_op; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_fp_val_0 = io_lsu_brupdate_b2_uop_fp_val; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_fp_rm_0 = io_lsu_brupdate_b2_uop_fp_rm; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_typ_0 = io_lsu_brupdate_b2_uop_fp_typ; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_bp_debug_if_0 = io_lsu_brupdate_b2_uop_bp_debug_if; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_debug_fsrc_0 = io_lsu_brupdate_b2_uop_debug_fsrc; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_uop_debug_tsrc_0 = io_lsu_brupdate_b2_uop_debug_tsrc; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_mispredict_0 = io_lsu_brupdate_b2_mispredict; // @[dcache.scala:438:7] wire io_lsu_brupdate_b2_taken_0 = io_lsu_brupdate_b2_taken; // @[dcache.scala:438:7] wire [2:0] io_lsu_brupdate_b2_cfi_type_0 = io_lsu_brupdate_b2_cfi_type; // @[dcache.scala:438:7] wire [1:0] io_lsu_brupdate_b2_pc_sel_0 = io_lsu_brupdate_b2_pc_sel; // @[dcache.scala:438:7] wire [39:0] io_lsu_brupdate_b2_jalr_target_0 = io_lsu_brupdate_b2_jalr_target; // @[dcache.scala:438:7] wire [20:0] io_lsu_brupdate_b2_target_offset_0 = io_lsu_brupdate_b2_target_offset; // @[dcache.scala:438:7] wire io_lsu_exception_0 = io_lsu_exception; // @[dcache.scala:438:7] wire [6:0] io_lsu_rob_pnr_idx_0 = io_lsu_rob_pnr_idx; // @[dcache.scala:438:7] wire [6:0] io_lsu_rob_head_idx_0 = io_lsu_rob_head_idx; // @[dcache.scala:438:7] wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:438:7] wire io_lsu_force_order_0 = io_lsu_force_order; // @[dcache.scala:438:7] wire auto_out_a_bits_corrupt = 1'h0; // @[dcache.scala:438:7] wire auto_out_c_bits_corrupt = 1'h0; // @[dcache.scala:438:7] wire io_errors_bus_valid = 1'h0; // @[dcache.scala:438:7] wire io_lsu_s1_nack_advisory_0 = 1'h0; // @[dcache.scala:438:7] wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:438:7] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire singlePortedDCacheWrite = 1'h0; // @[dcache.scala:503:53] wire mshr_read_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iq_type_0 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iq_type_1 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iq_type_2 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iq_type_3 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_0 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_1 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_2 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_3 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_4 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_5 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_6 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_7 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_8 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fu_code_9 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iw_issued = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iw_issued_partial_agen = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iw_issued_partial_dgen = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iw_p1_bypass_hint = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iw_p2_bypass_hint = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_iw_p3_bypass_hint = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_fence = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_sfence = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_amo = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_eret = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_rocc = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_mov = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_taken = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_imm_rename = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_ldst = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_wen = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_ren1 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_ren2 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_ren3 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_swap12 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_swap23 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_fromint = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_toint = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_fastpipe = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_fma = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_div = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_sqrt = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_wflags = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_ctrl_vec = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_exception = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_is_unique = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fcn_dw = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_fp_val = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:549:27] wire mshr_read_req_0_is_hella = 1'h0; // @[dcache.scala:549:27] wire _mshr_read_req_0_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _mshr_read_req_0_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire wb_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iq_type_0 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iq_type_1 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iq_type_2 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iq_type_3 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_0 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_1 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_2 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_3 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_4 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_5 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_6 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_7 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_8 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fu_code_9 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iw_issued = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iw_issued_partial_agen = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iw_issued_partial_dgen = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iw_p1_bypass_hint = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iw_p2_bypass_hint = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_iw_p3_bypass_hint = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_fence = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_sfence = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_amo = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_eret = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_rocc = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_mov = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_taken = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_imm_rename = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_ldst = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_wen = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_ren1 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_ren2 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_ren3 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_swap12 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_swap23 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_fromint = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_toint = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_fastpipe = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_fma = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_div = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_sqrt = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_wflags = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_ctrl_vec = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_exception = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_is_unique = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fcn_dw = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_fp_val = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:564:20] wire wb_req_0_is_hella = 1'h0; // @[dcache.scala:564:20] wire _wb_req_0_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _wb_req_0_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire prober_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iq_type_0 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iq_type_1 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iq_type_2 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iq_type_3 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_0 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_1 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_2 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_3 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_4 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_5 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_6 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_7 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_8 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fu_code_9 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iw_issued = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iw_issued_partial_agen = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iw_issued_partial_dgen = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iw_p1_bypass_hint = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iw_p2_bypass_hint = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_iw_p3_bypass_hint = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_fence = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_sfence = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_amo = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_eret = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_rocc = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_mov = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_taken = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_imm_rename = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_ldst = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_wen = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_ren1 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_ren2 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_ren3 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_swap12 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_swap23 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_fromint = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_toint = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_fastpipe = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_fma = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_div = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_sqrt = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_wflags = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_ctrl_vec = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_exception = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_is_unique = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fcn_dw = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_fp_val = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:586:26] wire prober_req_0_is_hella = 1'h0; // @[dcache.scala:586:26] wire _prober_req_0_uop_WIRE_is_rvc = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iq_type_0 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iq_type_1 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iq_type_2 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iq_type_3 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_0 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_1 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_2 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_3 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_4 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_5 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_6 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_7 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_8 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fu_code_9 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iw_issued = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_sfb = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_fence = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_fencei = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_sfence = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_amo = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_eret = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_sys_pc2epc = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_rocc = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_mov = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_edge_inst = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_taken = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_imm_rename = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_wen = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_toint = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_fma = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_div = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_ctrl_vec = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_prs1_busy = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_prs2_busy = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_prs3_busy = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_ppred_busy = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_exception = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_mem_signed = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_uses_ldq = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_uses_stq = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_is_unique = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_flush_on_commit = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_ldst_is_rs1 = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_frs3_en = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fcn_dw = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_fp_val = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_xcpt_pf_if = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_xcpt_ae_if = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_xcpt_ma_if = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_bp_debug_if = 1'h0; // @[consts.scala:141:57] wire _prober_req_0_uop_WIRE_bp_xcpt_if = 1'h0; // @[consts.scala:141:57] wire prefetch_fire = 1'h0; // @[Decoupled.scala:51:35] wire prefetch_req_0_uop_is_rvc = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iq_type_0 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iq_type_1 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iq_type_2 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iq_type_3 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_0 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_1 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_2 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_3 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_4 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_5 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_6 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_7 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_8 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fu_code_9 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iw_issued = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iw_issued_partial_agen = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iw_issued_partial_dgen = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iw_p1_bypass_hint = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iw_p2_bypass_hint = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_iw_p3_bypass_hint = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_sfb = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_fence = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_fencei = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_sfence = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_amo = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_eret = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_sys_pc2epc = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_rocc = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_mov = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_edge_inst = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_taken = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_imm_rename = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_ldst = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_wen = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_ren1 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_ren2 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_ren3 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_swap12 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_swap23 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_fromint = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_toint = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_fastpipe = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_fma = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_div = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_sqrt = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_wflags = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_ctrl_vec = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_prs1_busy = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_prs2_busy = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_prs3_busy = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_ppred_busy = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_exception = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_mem_signed = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_uses_ldq = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_uses_stq = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_is_unique = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_flush_on_commit = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_ldst_is_rs1 = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_frs3_en = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fcn_dw = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_fp_val = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_xcpt_pf_if = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_xcpt_ae_if = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_xcpt_ma_if = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_bp_debug_if = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_uop_bp_xcpt_if = 1'h0; // @[dcache.scala:601:27] wire prefetch_req_0_is_hella = 1'h0; // @[dcache.scala:601:27] wire _s0_valid_WIRE_2_0 = 1'h0; // @[dcache.scala:614:82] wire _s2_has_permission_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _s2_has_permission_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _s2_has_permission_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _s2_has_permission_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _s2_has_permission_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_new_hit_state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _s2_new_hit_state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _s2_new_hit_state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _s2_new_hit_state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _s2_new_hit_state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_nack_data_T = 1'h0; // @[dcache.scala:766:50] wire s2_nack_data_0 = 1'h0; // @[dcache.scala:454:49] wire opdata_1 = 1'h0; // @[Edges.scala:102:36] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _nodeOut_c_bits_WIRE_corrupt = 1'h0; // @[Mux.scala:30:73] wire _nodeOut_c_bits_T = 1'h0; // @[Mux.scala:30:73] wire _nodeOut_c_bits_T_1 = 1'h0; // @[Mux.scala:30:73] wire _nodeOut_c_bits_T_2 = 1'h0; // @[Mux.scala:30:73] wire _nodeOut_c_bits_WIRE_1 = 1'h0; // @[Mux.scala:30:73] wire io_lsu_resp_0_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_lsu_resp_0_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire _mshrs_io_replay_ready_T_1 = 1'h1; // @[dcache.scala:534:91] wire _metaReadArb_io_in_0_valid_T = 1'h1; // @[dcache.scala:537:71] wire _dataReadArb_io_in_0_valid_T = 1'h1; // @[dcache.scala:542:71] wire _metaReadArb_io_in_2_valid_T = 1'h1; // @[dcache.scala:573:65] wire _wb_io_meta_read_ready_T_1 = 1'h1; // @[dcache.scala:575:88] wire _dataReadArb_io_in_1_valid_T = 1'h1; // @[dcache.scala:577:64] wire _wb_io_data_req_ready_T_1 = 1'h1; // @[dcache.scala:580:88] wire _s0_valid_WIRE_1_0 = 1'h1; // @[dcache.scala:614:48] wire _mshrs_io_req_0_valid_T_6 = 1'h1; // @[dcache.scala:795:29] wire [31:0] io_errors_bus_bits = 32'h0; // @[dcache.scala:438:7] wire [31:0] mshr_read_req_0_uop_inst = 32'h0; // @[dcache.scala:549:27] wire [31:0] mshr_read_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:549:27] wire [31:0] _mshr_read_req_0_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _mshr_read_req_0_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] wb_req_0_uop_inst = 32'h0; // @[dcache.scala:564:20] wire [31:0] wb_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:564:20] wire [31:0] _wb_req_0_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _wb_req_0_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] prober_req_0_uop_inst = 32'h0; // @[dcache.scala:586:26] wire [31:0] prober_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:586:26] wire [31:0] _prober_req_0_uop_WIRE_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] _prober_req_0_uop_WIRE_debug_inst = 32'h0; // @[consts.scala:141:57] wire [31:0] prefetch_req_0_uop_inst = 32'h0; // @[dcache.scala:601:27] wire [31:0] prefetch_req_0_uop_debug_inst = 32'h0; // @[dcache.scala:601:27] wire [127:0] _nodeOut_c_bits_T_4 = 128'h0; // @[Mux.scala:30:73] wire [7:0] maskedBeats_1 = 8'h0; // @[Arbiter.scala:82:69] wire [7:0] decode = 8'h3; // @[Edges.scala:220:59] wire [11:0] _decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [3:0] _s2_has_permission_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _s2_new_hit_state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _s2_has_permission_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _s2_new_hit_state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _s2_has_permission_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _s2_new_hit_state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _s2_has_permission_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _s2_new_hit_state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _s2_has_permission_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _s2_new_hit_state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] mshr_read_req_0_uop_br_tag = 4'h0; // @[dcache.scala:549:27] wire [3:0] mshr_read_req_0_uop_br_type = 4'h0; // @[dcache.scala:549:27] wire [3:0] _mshr_read_req_0_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _mshr_read_req_0_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] wb_req_0_uop_br_tag = 4'h0; // @[dcache.scala:564:20] wire [3:0] wb_req_0_uop_br_type = 4'h0; // @[dcache.scala:564:20] wire [3:0] _wb_req_0_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _wb_req_0_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] prober_req_0_uop_br_tag = 4'h0; // @[dcache.scala:586:26] wire [3:0] prober_req_0_uop_br_type = 4'h0; // @[dcache.scala:586:26] wire [3:0] _prober_req_0_uop_WIRE_br_tag = 4'h0; // @[consts.scala:141:57] wire [3:0] _prober_req_0_uop_WIRE_br_type = 4'h0; // @[consts.scala:141:57] wire [3:0] prefetch_req_0_uop_br_tag = 4'h0; // @[dcache.scala:601:27] wire [3:0] prefetch_req_0_uop_br_type = 4'h0; // @[dcache.scala:601:27] wire [3:0] _s2_has_permission_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _s2_new_hit_state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [1:0] mshr_read_req_0_uop_op1_sel = 2'h0; // @[dcache.scala:549:27] wire [1:0] mshr_read_req_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[dcache.scala:549:27] wire [1:0] mshr_read_req_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[dcache.scala:549:27] wire [1:0] mshr_read_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:549:27] wire [1:0] mshr_read_req_0_uop_mem_size = 2'h0; // @[dcache.scala:549:27] wire [1:0] mshr_read_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:549:27] wire [1:0] mshr_read_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:549:27] wire [1:0] mshr_read_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:549:27] wire [1:0] mshr_read_req_0_uop_fp_typ = 2'h0; // @[dcache.scala:549:27] wire [1:0] _mshr_read_req_0_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _mshr_read_req_0_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _mshr_read_req_0_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _mshr_read_req_0_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _mshr_read_req_0_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _mshr_read_req_0_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _mshr_read_req_0_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _mshr_read_req_0_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _mshr_read_req_0_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] wb_req_0_uop_op1_sel = 2'h0; // @[dcache.scala:564:20] wire [1:0] wb_req_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[dcache.scala:564:20] wire [1:0] wb_req_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[dcache.scala:564:20] wire [1:0] wb_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:564:20] wire [1:0] wb_req_0_uop_mem_size = 2'h0; // @[dcache.scala:564:20] wire [1:0] wb_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:564:20] wire [1:0] wb_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:564:20] wire [1:0] wb_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:564:20] wire [1:0] wb_req_0_uop_fp_typ = 2'h0; // @[dcache.scala:564:20] wire [1:0] _wb_req_0_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _wb_req_0_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _wb_req_0_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _wb_req_0_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _wb_req_0_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _wb_req_0_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _wb_req_0_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _wb_req_0_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _wb_req_0_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] prober_req_0_uop_op1_sel = 2'h0; // @[dcache.scala:586:26] wire [1:0] prober_req_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[dcache.scala:586:26] wire [1:0] prober_req_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[dcache.scala:586:26] wire [1:0] prober_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:586:26] wire [1:0] prober_req_0_uop_mem_size = 2'h0; // @[dcache.scala:586:26] wire [1:0] prober_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:586:26] wire [1:0] prober_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:586:26] wire [1:0] prober_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:586:26] wire [1:0] prober_req_0_uop_fp_typ = 2'h0; // @[dcache.scala:586:26] wire [1:0] _prober_req_0_uop_WIRE_op1_sel = 2'h0; // @[consts.scala:141:57] wire [1:0] _prober_req_0_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[consts.scala:141:57] wire [1:0] _prober_req_0_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[consts.scala:141:57] wire [1:0] _prober_req_0_uop_WIRE_rxq_idx = 2'h0; // @[consts.scala:141:57] wire [1:0] _prober_req_0_uop_WIRE_mem_size = 2'h0; // @[consts.scala:141:57] wire [1:0] _prober_req_0_uop_WIRE_dst_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _prober_req_0_uop_WIRE_lrs1_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _prober_req_0_uop_WIRE_lrs2_rtype = 2'h0; // @[consts.scala:141:57] wire [1:0] _prober_req_0_uop_WIRE_fp_typ = 2'h0; // @[consts.scala:141:57] wire [1:0] prefetch_req_0_uop_op1_sel = 2'h0; // @[dcache.scala:601:27] wire [1:0] prefetch_req_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[dcache.scala:601:27] wire [1:0] prefetch_req_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[dcache.scala:601:27] wire [1:0] prefetch_req_0_uop_rxq_idx = 2'h0; // @[dcache.scala:601:27] wire [1:0] prefetch_req_0_uop_mem_size = 2'h0; // @[dcache.scala:601:27] wire [1:0] prefetch_req_0_uop_dst_rtype = 2'h0; // @[dcache.scala:601:27] wire [1:0] prefetch_req_0_uop_lrs1_rtype = 2'h0; // @[dcache.scala:601:27] wire [1:0] prefetch_req_0_uop_lrs2_rtype = 2'h0; // @[dcache.scala:601:27] wire [1:0] prefetch_req_0_uop_fp_typ = 2'h0; // @[dcache.scala:601:27] wire [1:0] _s2_has_permission_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _s2_has_permission_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _s2_has_permission_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _s2_has_permission_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _s2_new_hit_state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _s2_new_hit_state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _s2_new_hit_state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _s2_new_hit_state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [3:0] _s2_has_permission_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _s2_new_hit_state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _s2_has_permission_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _s2_new_hit_state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _s2_has_permission_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _s2_new_hit_state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _s2_has_permission_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _s2_new_hit_state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _s2_has_permission_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _s2_new_hit_state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _s2_has_permission_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _s2_new_hit_state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [33:0] _metaReadArb_io_in_5_bits_req_0_idx_T = 34'h0; // @[dcache.scala:606:74] wire [63:0] mshr_read_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:549:27] wire [63:0] mshr_read_req_0_data = 64'h0; // @[dcache.scala:549:27] wire [63:0] _mshr_read_req_0_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [63:0] wb_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:564:20] wire [63:0] wb_req_0_data = 64'h0; // @[dcache.scala:564:20] wire [63:0] _wb_req_0_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [63:0] prober_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:586:26] wire [63:0] prober_req_0_data = 64'h0; // @[dcache.scala:586:26] wire [63:0] _prober_req_0_uop_WIRE_exc_cause = 64'h0; // @[consts.scala:141:57] wire [63:0] prefetch_req_0_uop_exc_cause = 64'h0; // @[dcache.scala:601:27] wire [63:0] prefetch_req_0_data = 64'h0; // @[dcache.scala:601:27] wire [39:0] mshr_read_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:549:27] wire [39:0] _mshr_read_req_0_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [39:0] wb_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:564:20] wire [39:0] _wb_req_0_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [39:0] prober_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:586:26] wire [39:0] _prober_req_0_uop_WIRE_debug_pc = 40'h0; // @[consts.scala:141:57] wire [39:0] prefetch_req_0_uop_debug_pc = 40'h0; // @[dcache.scala:601:27] wire [39:0] prefetch_req_0_addr = 40'h0; // @[dcache.scala:601:27] wire [2:0] mshr_read_req_0_uop_iw_p1_speculative_child = 3'h0; // @[dcache.scala:549:27] wire [2:0] mshr_read_req_0_uop_iw_p2_speculative_child = 3'h0; // @[dcache.scala:549:27] wire [2:0] mshr_read_req_0_uop_dis_col_sel = 3'h0; // @[dcache.scala:549:27] wire [2:0] mshr_read_req_0_uop_imm_sel = 3'h0; // @[dcache.scala:549:27] wire [2:0] mshr_read_req_0_uop_op2_sel = 3'h0; // @[dcache.scala:549:27] wire [2:0] mshr_read_req_0_uop_csr_cmd = 3'h0; // @[dcache.scala:549:27] wire [2:0] mshr_read_req_0_uop_fp_rm = 3'h0; // @[dcache.scala:549:27] wire [2:0] mshr_read_req_0_uop_debug_fsrc = 3'h0; // @[dcache.scala:549:27] wire [2:0] mshr_read_req_0_uop_debug_tsrc = 3'h0; // @[dcache.scala:549:27] wire [2:0] _mshr_read_req_0_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _mshr_read_req_0_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _mshr_read_req_0_uop_WIRE_dis_col_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _mshr_read_req_0_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _mshr_read_req_0_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _mshr_read_req_0_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _mshr_read_req_0_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _mshr_read_req_0_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _mshr_read_req_0_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] wb_req_0_uop_iw_p1_speculative_child = 3'h0; // @[dcache.scala:564:20] wire [2:0] wb_req_0_uop_iw_p2_speculative_child = 3'h0; // @[dcache.scala:564:20] wire [2:0] wb_req_0_uop_dis_col_sel = 3'h0; // @[dcache.scala:564:20] wire [2:0] wb_req_0_uop_imm_sel = 3'h0; // @[dcache.scala:564:20] wire [2:0] wb_req_0_uop_op2_sel = 3'h0; // @[dcache.scala:564:20] wire [2:0] wb_req_0_uop_csr_cmd = 3'h0; // @[dcache.scala:564:20] wire [2:0] wb_req_0_uop_fp_rm = 3'h0; // @[dcache.scala:564:20] wire [2:0] wb_req_0_uop_debug_fsrc = 3'h0; // @[dcache.scala:564:20] wire [2:0] wb_req_0_uop_debug_tsrc = 3'h0; // @[dcache.scala:564:20] wire [2:0] _wb_req_0_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _wb_req_0_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _wb_req_0_uop_WIRE_dis_col_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _wb_req_0_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _wb_req_0_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _wb_req_0_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _wb_req_0_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _wb_req_0_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _wb_req_0_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] prober_req_0_uop_iw_p1_speculative_child = 3'h0; // @[dcache.scala:586:26] wire [2:0] prober_req_0_uop_iw_p2_speculative_child = 3'h0; // @[dcache.scala:586:26] wire [2:0] prober_req_0_uop_dis_col_sel = 3'h0; // @[dcache.scala:586:26] wire [2:0] prober_req_0_uop_imm_sel = 3'h0; // @[dcache.scala:586:26] wire [2:0] prober_req_0_uop_op2_sel = 3'h0; // @[dcache.scala:586:26] wire [2:0] prober_req_0_uop_csr_cmd = 3'h0; // @[dcache.scala:586:26] wire [2:0] prober_req_0_uop_fp_rm = 3'h0; // @[dcache.scala:586:26] wire [2:0] prober_req_0_uop_debug_fsrc = 3'h0; // @[dcache.scala:586:26] wire [2:0] prober_req_0_uop_debug_tsrc = 3'h0; // @[dcache.scala:586:26] wire [2:0] _prober_req_0_uop_WIRE_iw_p1_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _prober_req_0_uop_WIRE_iw_p2_speculative_child = 3'h0; // @[consts.scala:141:57] wire [2:0] _prober_req_0_uop_WIRE_dis_col_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _prober_req_0_uop_WIRE_imm_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _prober_req_0_uop_WIRE_op2_sel = 3'h0; // @[consts.scala:141:57] wire [2:0] _prober_req_0_uop_WIRE_csr_cmd = 3'h0; // @[consts.scala:141:57] wire [2:0] _prober_req_0_uop_WIRE_fp_rm = 3'h0; // @[consts.scala:141:57] wire [2:0] _prober_req_0_uop_WIRE_debug_fsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] _prober_req_0_uop_WIRE_debug_tsrc = 3'h0; // @[consts.scala:141:57] wire [2:0] prefetch_req_0_uop_iw_p1_speculative_child = 3'h0; // @[dcache.scala:601:27] wire [2:0] prefetch_req_0_uop_iw_p2_speculative_child = 3'h0; // @[dcache.scala:601:27] wire [2:0] prefetch_req_0_uop_dis_col_sel = 3'h0; // @[dcache.scala:601:27] wire [2:0] prefetch_req_0_uop_imm_sel = 3'h0; // @[dcache.scala:601:27] wire [2:0] prefetch_req_0_uop_op2_sel = 3'h0; // @[dcache.scala:601:27] wire [2:0] prefetch_req_0_uop_csr_cmd = 3'h0; // @[dcache.scala:601:27] wire [2:0] prefetch_req_0_uop_fp_rm = 3'h0; // @[dcache.scala:601:27] wire [2:0] prefetch_req_0_uop_debug_fsrc = 3'h0; // @[dcache.scala:601:27] wire [2:0] prefetch_req_0_uop_debug_tsrc = 3'h0; // @[dcache.scala:601:27] wire [4:0] mshr_read_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:549:27] wire [4:0] mshr_read_req_0_uop_pimm = 5'h0; // @[dcache.scala:549:27] wire [4:0] mshr_read_req_0_uop_ldq_idx = 5'h0; // @[dcache.scala:549:27] wire [4:0] mshr_read_req_0_uop_stq_idx = 5'h0; // @[dcache.scala:549:27] wire [4:0] mshr_read_req_0_uop_ppred = 5'h0; // @[dcache.scala:549:27] wire [4:0] mshr_read_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:549:27] wire [4:0] mshr_read_req_0_uop_fcn_op = 5'h0; // @[dcache.scala:549:27] wire [4:0] _mshr_read_req_0_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _mshr_read_req_0_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _mshr_read_req_0_uop_WIRE_ldq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _mshr_read_req_0_uop_WIRE_stq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _mshr_read_req_0_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _mshr_read_req_0_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _mshr_read_req_0_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] wb_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:564:20] wire [4:0] wb_req_0_uop_pimm = 5'h0; // @[dcache.scala:564:20] wire [4:0] wb_req_0_uop_ldq_idx = 5'h0; // @[dcache.scala:564:20] wire [4:0] wb_req_0_uop_stq_idx = 5'h0; // @[dcache.scala:564:20] wire [4:0] wb_req_0_uop_ppred = 5'h0; // @[dcache.scala:564:20] wire [4:0] wb_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:564:20] wire [4:0] wb_req_0_uop_fcn_op = 5'h0; // @[dcache.scala:564:20] wire [4:0] _wb_req_0_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _wb_req_0_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _wb_req_0_uop_WIRE_ldq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _wb_req_0_uop_WIRE_stq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _wb_req_0_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _wb_req_0_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _wb_req_0_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] prober_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:586:26] wire [4:0] prober_req_0_uop_pimm = 5'h0; // @[dcache.scala:586:26] wire [4:0] prober_req_0_uop_ldq_idx = 5'h0; // @[dcache.scala:586:26] wire [4:0] prober_req_0_uop_stq_idx = 5'h0; // @[dcache.scala:586:26] wire [4:0] prober_req_0_uop_ppred = 5'h0; // @[dcache.scala:586:26] wire [4:0] prober_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:586:26] wire [4:0] prober_req_0_uop_fcn_op = 5'h0; // @[dcache.scala:586:26] wire [4:0] _prober_req_0_uop_WIRE_ftq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _prober_req_0_uop_WIRE_pimm = 5'h0; // @[consts.scala:141:57] wire [4:0] _prober_req_0_uop_WIRE_ldq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _prober_req_0_uop_WIRE_stq_idx = 5'h0; // @[consts.scala:141:57] wire [4:0] _prober_req_0_uop_WIRE_ppred = 5'h0; // @[consts.scala:141:57] wire [4:0] _prober_req_0_uop_WIRE_mem_cmd = 5'h0; // @[consts.scala:141:57] wire [4:0] _prober_req_0_uop_WIRE_fcn_op = 5'h0; // @[consts.scala:141:57] wire [4:0] prefetch_req_0_uop_ftq_idx = 5'h0; // @[dcache.scala:601:27] wire [4:0] prefetch_req_0_uop_pimm = 5'h0; // @[dcache.scala:601:27] wire [4:0] prefetch_req_0_uop_ldq_idx = 5'h0; // @[dcache.scala:601:27] wire [4:0] prefetch_req_0_uop_stq_idx = 5'h0; // @[dcache.scala:601:27] wire [4:0] prefetch_req_0_uop_ppred = 5'h0; // @[dcache.scala:601:27] wire [4:0] prefetch_req_0_uop_mem_cmd = 5'h0; // @[dcache.scala:601:27] wire [4:0] prefetch_req_0_uop_fcn_op = 5'h0; // @[dcache.scala:601:27] wire [5:0] mshr_read_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:549:27] wire [5:0] mshr_read_req_0_uop_ldst = 6'h0; // @[dcache.scala:549:27] wire [5:0] mshr_read_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:549:27] wire [5:0] mshr_read_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:549:27] wire [5:0] mshr_read_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:549:27] wire [5:0] _mshr_read_req_0_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _mshr_read_req_0_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _mshr_read_req_0_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _mshr_read_req_0_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _mshr_read_req_0_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [5:0] wb_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:564:20] wire [5:0] wb_req_0_uop_ldst = 6'h0; // @[dcache.scala:564:20] wire [5:0] wb_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:564:20] wire [5:0] wb_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:564:20] wire [5:0] wb_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:564:20] wire [5:0] _wb_req_0_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _wb_req_0_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _wb_req_0_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _wb_req_0_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _wb_req_0_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [5:0] prober_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:586:26] wire [5:0] prober_req_0_uop_ldst = 6'h0; // @[dcache.scala:586:26] wire [5:0] prober_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:586:26] wire [5:0] prober_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:586:26] wire [5:0] prober_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:586:26] wire [5:0] _prober_req_0_uop_WIRE_pc_lob = 6'h0; // @[consts.scala:141:57] wire [5:0] _prober_req_0_uop_WIRE_ldst = 6'h0; // @[consts.scala:141:57] wire [5:0] _prober_req_0_uop_WIRE_lrs1 = 6'h0; // @[consts.scala:141:57] wire [5:0] _prober_req_0_uop_WIRE_lrs2 = 6'h0; // @[consts.scala:141:57] wire [5:0] _prober_req_0_uop_WIRE_lrs3 = 6'h0; // @[consts.scala:141:57] wire [5:0] prefetch_req_0_uop_pc_lob = 6'h0; // @[dcache.scala:601:27] wire [5:0] prefetch_req_0_uop_ldst = 6'h0; // @[dcache.scala:601:27] wire [5:0] prefetch_req_0_uop_lrs1 = 6'h0; // @[dcache.scala:601:27] wire [5:0] prefetch_req_0_uop_lrs2 = 6'h0; // @[dcache.scala:601:27] wire [5:0] prefetch_req_0_uop_lrs3 = 6'h0; // @[dcache.scala:601:27] wire [6:0] mshr_read_req_0_uop_rob_idx = 7'h0; // @[dcache.scala:549:27] wire [6:0] mshr_read_req_0_uop_pdst = 7'h0; // @[dcache.scala:549:27] wire [6:0] mshr_read_req_0_uop_prs1 = 7'h0; // @[dcache.scala:549:27] wire [6:0] mshr_read_req_0_uop_prs2 = 7'h0; // @[dcache.scala:549:27] wire [6:0] mshr_read_req_0_uop_prs3 = 7'h0; // @[dcache.scala:549:27] wire [6:0] mshr_read_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:549:27] wire [6:0] _mshr_read_req_0_uop_WIRE_rob_idx = 7'h0; // @[consts.scala:141:57] wire [6:0] _mshr_read_req_0_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _mshr_read_req_0_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _mshr_read_req_0_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _mshr_read_req_0_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _mshr_read_req_0_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] wb_req_0_uop_rob_idx = 7'h0; // @[dcache.scala:564:20] wire [6:0] wb_req_0_uop_pdst = 7'h0; // @[dcache.scala:564:20] wire [6:0] wb_req_0_uop_prs1 = 7'h0; // @[dcache.scala:564:20] wire [6:0] wb_req_0_uop_prs2 = 7'h0; // @[dcache.scala:564:20] wire [6:0] wb_req_0_uop_prs3 = 7'h0; // @[dcache.scala:564:20] wire [6:0] wb_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:564:20] wire [6:0] _wb_req_0_uop_WIRE_rob_idx = 7'h0; // @[consts.scala:141:57] wire [6:0] _wb_req_0_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _wb_req_0_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _wb_req_0_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _wb_req_0_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _wb_req_0_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] prober_req_0_uop_rob_idx = 7'h0; // @[dcache.scala:586:26] wire [6:0] prober_req_0_uop_pdst = 7'h0; // @[dcache.scala:586:26] wire [6:0] prober_req_0_uop_prs1 = 7'h0; // @[dcache.scala:586:26] wire [6:0] prober_req_0_uop_prs2 = 7'h0; // @[dcache.scala:586:26] wire [6:0] prober_req_0_uop_prs3 = 7'h0; // @[dcache.scala:586:26] wire [6:0] prober_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:586:26] wire [6:0] _prober_req_0_uop_WIRE_rob_idx = 7'h0; // @[consts.scala:141:57] wire [6:0] _prober_req_0_uop_WIRE_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] _prober_req_0_uop_WIRE_prs1 = 7'h0; // @[consts.scala:141:57] wire [6:0] _prober_req_0_uop_WIRE_prs2 = 7'h0; // @[consts.scala:141:57] wire [6:0] _prober_req_0_uop_WIRE_prs3 = 7'h0; // @[consts.scala:141:57] wire [6:0] _prober_req_0_uop_WIRE_stale_pdst = 7'h0; // @[consts.scala:141:57] wire [6:0] prefetch_req_0_uop_rob_idx = 7'h0; // @[dcache.scala:601:27] wire [6:0] prefetch_req_0_uop_pdst = 7'h0; // @[dcache.scala:601:27] wire [6:0] prefetch_req_0_uop_prs1 = 7'h0; // @[dcache.scala:601:27] wire [6:0] prefetch_req_0_uop_prs2 = 7'h0; // @[dcache.scala:601:27] wire [6:0] prefetch_req_0_uop_prs3 = 7'h0; // @[dcache.scala:601:27] wire [6:0] prefetch_req_0_uop_stale_pdst = 7'h0; // @[dcache.scala:601:27] wire [19:0] mshr_read_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:549:27] wire [19:0] _mshr_read_req_0_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [19:0] wb_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:564:20] wire [19:0] _wb_req_0_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [19:0] prober_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:586:26] wire [19:0] _prober_req_0_uop_WIRE_imm_packed = 20'h0; // @[consts.scala:141:57] wire [19:0] prefetch_req_0_uop_imm_packed = 20'h0; // @[dcache.scala:601:27] wire [15:0] mshr_read_req_0_uop_br_mask = 16'h0; // @[dcache.scala:549:27] wire [15:0] _mshr_read_req_0_uop_WIRE_br_mask = 16'h0; // @[consts.scala:141:57] wire [15:0] wb_req_0_uop_br_mask = 16'h0; // @[dcache.scala:564:20] wire [15:0] _wb_req_0_uop_WIRE_br_mask = 16'h0; // @[consts.scala:141:57] wire [15:0] prober_req_0_uop_br_mask = 16'h0; // @[dcache.scala:586:26] wire [15:0] _prober_req_0_uop_WIRE_br_mask = 16'h0; // @[consts.scala:141:57] wire [15:0] prefetch_req_0_uop_br_mask = 16'h0; // @[dcache.scala:601:27] wire [7:0] _dataReadArb_io_in_2_bits_req_0_way_en_T = 8'hFF; // @[dcache.scala:522:48] wire [1:0] _s2_has_permission_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _s2_has_permission_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _s2_has_permission_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _s2_has_permission_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _s2_new_hit_state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _s2_new_hit_state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _s2_new_hit_state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _s2_new_hit_state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _s2_has_permission_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _s2_has_permission_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _s2_has_permission_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _s2_has_permission_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _s2_new_hit_state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _s2_new_hit_state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _s2_new_hit_state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _s2_new_hit_state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire nodeOut_a_ready = auto_out_a_ready_0; // @[MixedNode.scala:542:17] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[MixedNode.scala:542:17] wire [15:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[MixedNode.scala:542:17] wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[MixedNode.scala:542:17] wire nodeOut_c_ready = auto_out_c_ready_0; // @[MixedNode.scala:542:17] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17] wire nodeOut_e_ready = auto_out_e_ready_0; // @[MixedNode.scala:542:17] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire _io_lsu_req_ready_T_2; // @[dcache.scala:511:80] wire _s0_valid_WIRE_0 = io_lsu_req_bits_0_valid_0; // @[dcache.scala:438:7, :612:46] wire [31:0] _s0_req_WIRE_0_uop_inst = io_lsu_req_bits_0_bits_uop_inst_0; // @[dcache.scala:438:7, :615:56] wire [31:0] _s0_req_WIRE_0_uop_debug_inst = io_lsu_req_bits_0_bits_uop_debug_inst_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_rvc = io_lsu_req_bits_0_bits_uop_is_rvc_0; // @[dcache.scala:438:7, :615:56] wire [39:0] _s0_req_WIRE_0_uop_debug_pc = io_lsu_req_bits_0_bits_uop_debug_pc_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iq_type_0 = io_lsu_req_bits_0_bits_uop_iq_type_0_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iq_type_1 = io_lsu_req_bits_0_bits_uop_iq_type_1_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iq_type_2 = io_lsu_req_bits_0_bits_uop_iq_type_2_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iq_type_3 = io_lsu_req_bits_0_bits_uop_iq_type_3_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_0 = io_lsu_req_bits_0_bits_uop_fu_code_0_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_1 = io_lsu_req_bits_0_bits_uop_fu_code_1_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_2 = io_lsu_req_bits_0_bits_uop_fu_code_2_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_3 = io_lsu_req_bits_0_bits_uop_fu_code_3_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_4 = io_lsu_req_bits_0_bits_uop_fu_code_4_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_5 = io_lsu_req_bits_0_bits_uop_fu_code_5_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_6 = io_lsu_req_bits_0_bits_uop_fu_code_6_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_7 = io_lsu_req_bits_0_bits_uop_fu_code_7_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_8 = io_lsu_req_bits_0_bits_uop_fu_code_8_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fu_code_9 = io_lsu_req_bits_0_bits_uop_fu_code_9_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iw_issued = io_lsu_req_bits_0_bits_uop_iw_issued_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iw_issued_partial_agen = io_lsu_req_bits_0_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iw_issued_partial_dgen = io_lsu_req_bits_0_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_iw_p1_speculative_child = io_lsu_req_bits_0_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_iw_p2_speculative_child = io_lsu_req_bits_0_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iw_p1_bypass_hint = io_lsu_req_bits_0_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iw_p2_bypass_hint = io_lsu_req_bits_0_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_iw_p3_bypass_hint = io_lsu_req_bits_0_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_dis_col_sel = io_lsu_req_bits_0_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7, :615:56] wire [15:0] _s0_req_WIRE_0_uop_br_mask = io_lsu_req_bits_0_bits_uop_br_mask_0; // @[dcache.scala:438:7, :615:56] wire [3:0] _s0_req_WIRE_0_uop_br_tag = io_lsu_req_bits_0_bits_uop_br_tag_0; // @[dcache.scala:438:7, :615:56] wire [3:0] _s0_req_WIRE_0_uop_br_type = io_lsu_req_bits_0_bits_uop_br_type_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_sfb = io_lsu_req_bits_0_bits_uop_is_sfb_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_fence = io_lsu_req_bits_0_bits_uop_is_fence_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_fencei = io_lsu_req_bits_0_bits_uop_is_fencei_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_sfence = io_lsu_req_bits_0_bits_uop_is_sfence_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_amo = io_lsu_req_bits_0_bits_uop_is_amo_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_eret = io_lsu_req_bits_0_bits_uop_is_eret_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_sys_pc2epc = io_lsu_req_bits_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_rocc = io_lsu_req_bits_0_bits_uop_is_rocc_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_mov = io_lsu_req_bits_0_bits_uop_is_mov_0; // @[dcache.scala:438:7, :615:56] wire [4:0] _s0_req_WIRE_0_uop_ftq_idx = io_lsu_req_bits_0_bits_uop_ftq_idx_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_edge_inst = io_lsu_req_bits_0_bits_uop_edge_inst_0; // @[dcache.scala:438:7, :615:56] wire [5:0] _s0_req_WIRE_0_uop_pc_lob = io_lsu_req_bits_0_bits_uop_pc_lob_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_taken = io_lsu_req_bits_0_bits_uop_taken_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_imm_rename = io_lsu_req_bits_0_bits_uop_imm_rename_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_imm_sel = io_lsu_req_bits_0_bits_uop_imm_sel_0; // @[dcache.scala:438:7, :615:56] wire [4:0] _s0_req_WIRE_0_uop_pimm = io_lsu_req_bits_0_bits_uop_pimm_0; // @[dcache.scala:438:7, :615:56] wire [19:0] _s0_req_WIRE_0_uop_imm_packed = io_lsu_req_bits_0_bits_uop_imm_packed_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_op1_sel = io_lsu_req_bits_0_bits_uop_op1_sel_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_op2_sel = io_lsu_req_bits_0_bits_uop_op2_sel_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_ldst = io_lsu_req_bits_0_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_wen = io_lsu_req_bits_0_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_ren1 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_ren2 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_ren3 = io_lsu_req_bits_0_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_swap12 = io_lsu_req_bits_0_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_swap23 = io_lsu_req_bits_0_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_fp_ctrl_typeTagIn = io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_fp_ctrl_typeTagOut = io_lsu_req_bits_0_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_fromint = io_lsu_req_bits_0_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_toint = io_lsu_req_bits_0_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_fastpipe = io_lsu_req_bits_0_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_fma = io_lsu_req_bits_0_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_div = io_lsu_req_bits_0_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_sqrt = io_lsu_req_bits_0_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_wflags = io_lsu_req_bits_0_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_ctrl_vec = io_lsu_req_bits_0_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7, :615:56] wire [6:0] _s0_req_WIRE_0_uop_rob_idx = io_lsu_req_bits_0_bits_uop_rob_idx_0; // @[dcache.scala:438:7, :615:56] wire [4:0] _s0_req_WIRE_0_uop_ldq_idx = io_lsu_req_bits_0_bits_uop_ldq_idx_0; // @[dcache.scala:438:7, :615:56] wire [4:0] _s0_req_WIRE_0_uop_stq_idx = io_lsu_req_bits_0_bits_uop_stq_idx_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_rxq_idx = io_lsu_req_bits_0_bits_uop_rxq_idx_0; // @[dcache.scala:438:7, :615:56] wire [6:0] _s0_req_WIRE_0_uop_pdst = io_lsu_req_bits_0_bits_uop_pdst_0; // @[dcache.scala:438:7, :615:56] wire [6:0] _s0_req_WIRE_0_uop_prs1 = io_lsu_req_bits_0_bits_uop_prs1_0; // @[dcache.scala:438:7, :615:56] wire [6:0] _s0_req_WIRE_0_uop_prs2 = io_lsu_req_bits_0_bits_uop_prs2_0; // @[dcache.scala:438:7, :615:56] wire [6:0] _s0_req_WIRE_0_uop_prs3 = io_lsu_req_bits_0_bits_uop_prs3_0; // @[dcache.scala:438:7, :615:56] wire [4:0] _s0_req_WIRE_0_uop_ppred = io_lsu_req_bits_0_bits_uop_ppred_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_prs1_busy = io_lsu_req_bits_0_bits_uop_prs1_busy_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_prs2_busy = io_lsu_req_bits_0_bits_uop_prs2_busy_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_prs3_busy = io_lsu_req_bits_0_bits_uop_prs3_busy_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_ppred_busy = io_lsu_req_bits_0_bits_uop_ppred_busy_0; // @[dcache.scala:438:7, :615:56] wire [6:0] _s0_req_WIRE_0_uop_stale_pdst = io_lsu_req_bits_0_bits_uop_stale_pdst_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_exception = io_lsu_req_bits_0_bits_uop_exception_0; // @[dcache.scala:438:7, :615:56] wire [63:0] _s0_req_WIRE_0_uop_exc_cause = io_lsu_req_bits_0_bits_uop_exc_cause_0; // @[dcache.scala:438:7, :615:56] wire [4:0] _s0_req_WIRE_0_uop_mem_cmd = io_lsu_req_bits_0_bits_uop_mem_cmd_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_mem_size = io_lsu_req_bits_0_bits_uop_mem_size_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_mem_signed = io_lsu_req_bits_0_bits_uop_mem_signed_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_uses_ldq = io_lsu_req_bits_0_bits_uop_uses_ldq_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_uses_stq = io_lsu_req_bits_0_bits_uop_uses_stq_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_is_unique = io_lsu_req_bits_0_bits_uop_is_unique_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_flush_on_commit = io_lsu_req_bits_0_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_csr_cmd = io_lsu_req_bits_0_bits_uop_csr_cmd_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_ldst_is_rs1 = io_lsu_req_bits_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7, :615:56] wire [5:0] _s0_req_WIRE_0_uop_ldst = io_lsu_req_bits_0_bits_uop_ldst_0; // @[dcache.scala:438:7, :615:56] wire [5:0] _s0_req_WIRE_0_uop_lrs1 = io_lsu_req_bits_0_bits_uop_lrs1_0; // @[dcache.scala:438:7, :615:56] wire [5:0] _s0_req_WIRE_0_uop_lrs2 = io_lsu_req_bits_0_bits_uop_lrs2_0; // @[dcache.scala:438:7, :615:56] wire [5:0] _s0_req_WIRE_0_uop_lrs3 = io_lsu_req_bits_0_bits_uop_lrs3_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_dst_rtype = io_lsu_req_bits_0_bits_uop_dst_rtype_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_lrs1_rtype = io_lsu_req_bits_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_lrs2_rtype = io_lsu_req_bits_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_frs3_en = io_lsu_req_bits_0_bits_uop_frs3_en_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fcn_dw = io_lsu_req_bits_0_bits_uop_fcn_dw_0; // @[dcache.scala:438:7, :615:56] wire [4:0] _s0_req_WIRE_0_uop_fcn_op = io_lsu_req_bits_0_bits_uop_fcn_op_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_fp_val = io_lsu_req_bits_0_bits_uop_fp_val_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_fp_rm = io_lsu_req_bits_0_bits_uop_fp_rm_0; // @[dcache.scala:438:7, :615:56] wire [1:0] _s0_req_WIRE_0_uop_fp_typ = io_lsu_req_bits_0_bits_uop_fp_typ_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_xcpt_pf_if = io_lsu_req_bits_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_xcpt_ae_if = io_lsu_req_bits_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_xcpt_ma_if = io_lsu_req_bits_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_bp_debug_if = io_lsu_req_bits_0_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_uop_bp_xcpt_if = io_lsu_req_bits_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_debug_fsrc = io_lsu_req_bits_0_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7, :615:56] wire [2:0] _s0_req_WIRE_0_uop_debug_tsrc = io_lsu_req_bits_0_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7, :615:56] wire [39:0] _s0_req_WIRE_0_addr = io_lsu_req_bits_0_bits_addr_0; // @[dcache.scala:438:7, :615:56] wire [63:0] _s0_req_WIRE_0_data = io_lsu_req_bits_0_bits_data_0; // @[dcache.scala:438:7, :615:56] wire _s0_req_WIRE_0_is_hella = io_lsu_req_bits_0_bits_is_hella_0; // @[dcache.scala:438:7, :615:56] wire _io_lsu_resp_0_valid_T; // @[dcache.scala:877:41] wire [63:0] _io_lsu_resp_0_bits_data_T_24; // @[dcache.scala:879:49] wire _io_lsu_store_ack_0_valid_T_1; // @[dcache.scala:888:70] wire _io_lsu_nack_0_valid_T; // @[dcache.scala:884:41] wire _io_lsu_ordered_T_3; // @[dcache.scala:941:66] wire io_lsu_perf_acquire_done; // @[Edges.scala:233:22] wire io_lsu_perf_release_done; // @[Edges.scala:233:22] wire [2:0] auto_out_a_bits_opcode_0; // @[dcache.scala:438:7] wire [2:0] auto_out_a_bits_param_0; // @[dcache.scala:438:7] wire [3:0] auto_out_a_bits_size_0; // @[dcache.scala:438:7] wire [2:0] auto_out_a_bits_source_0; // @[dcache.scala:438:7] wire [31:0] auto_out_a_bits_address_0; // @[dcache.scala:438:7] wire [15:0] auto_out_a_bits_mask_0; // @[dcache.scala:438:7] wire [127:0] auto_out_a_bits_data_0; // @[dcache.scala:438:7] wire auto_out_a_valid_0; // @[dcache.scala:438:7] wire auto_out_b_ready_0; // @[dcache.scala:438:7] wire [2:0] auto_out_c_bits_opcode_0; // @[dcache.scala:438:7] wire [2:0] auto_out_c_bits_param_0; // @[dcache.scala:438:7] wire [3:0] auto_out_c_bits_size_0; // @[dcache.scala:438:7] wire [2:0] auto_out_c_bits_source_0; // @[dcache.scala:438:7] wire [31:0] auto_out_c_bits_address_0; // @[dcache.scala:438:7] wire [127:0] auto_out_c_bits_data_0; // @[dcache.scala:438:7] wire auto_out_c_valid_0; // @[dcache.scala:438:7] wire auto_out_d_ready_0; // @[dcache.scala:438:7] wire [3:0] auto_out_e_bits_sink_0; // @[dcache.scala:438:7] wire auto_out_e_valid_0; // @[dcache.scala:438:7] wire io_lsu_req_ready_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iq_type_0_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iq_type_1_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iq_type_2_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iq_type_3_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_0_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_1_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_2_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_3_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_4_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_5_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_6_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_7_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_8_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fu_code_9_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_resp_0_bits_uop_inst_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_resp_0_bits_uop_debug_inst_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_rvc_0; // @[dcache.scala:438:7] wire [39:0] io_lsu_resp_0_bits_uop_debug_pc_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iw_issued_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7] wire [15:0] io_lsu_resp_0_bits_uop_br_mask_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_resp_0_bits_uop_br_tag_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_resp_0_bits_uop_br_type_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_sfb_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_fence_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_fencei_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_sfence_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_amo_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_eret_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_rocc_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_mov_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_resp_0_bits_uop_ftq_idx_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_edge_inst_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_resp_0_bits_uop_pc_lob_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_taken_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_imm_rename_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_imm_sel_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_resp_0_bits_uop_pimm_0; // @[dcache.scala:438:7] wire [19:0] io_lsu_resp_0_bits_uop_imm_packed_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_op1_sel_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_op2_sel_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_resp_0_bits_uop_rob_idx_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_resp_0_bits_uop_ldq_idx_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_resp_0_bits_uop_stq_idx_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_rxq_idx_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_resp_0_bits_uop_pdst_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_resp_0_bits_uop_prs1_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_resp_0_bits_uop_prs2_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_resp_0_bits_uop_prs3_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_resp_0_bits_uop_ppred_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_prs1_busy_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_prs2_busy_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_prs3_busy_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_ppred_busy_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_resp_0_bits_uop_stale_pdst_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_exception_0; // @[dcache.scala:438:7] wire [63:0] io_lsu_resp_0_bits_uop_exc_cause_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_resp_0_bits_uop_mem_cmd_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_mem_size_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_mem_signed_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_uses_ldq_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_uses_stq_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_is_unique_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_csr_cmd_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_resp_0_bits_uop_ldst_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_resp_0_bits_uop_lrs1_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_resp_0_bits_uop_lrs2_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_resp_0_bits_uop_lrs3_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_dst_rtype_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_frs3_en_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fcn_dw_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_resp_0_bits_uop_fcn_op_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_fp_val_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_fp_rm_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_resp_0_bits_uop_fp_typ_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_resp_0_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7] wire [63:0] io_lsu_resp_0_bits_data_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_bits_is_hella_0; // @[dcache.scala:438:7] wire io_lsu_resp_0_valid_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iq_type_0_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iq_type_1_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iq_type_2_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iq_type_3_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_0_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_1_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_2_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_3_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_4_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_5_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_6_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_7_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_8_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fu_code_9_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_store_ack_0_bits_uop_inst_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_store_ack_0_bits_uop_debug_inst_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_rvc_0; // @[dcache.scala:438:7] wire [39:0] io_lsu_store_ack_0_bits_uop_debug_pc_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iw_issued_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7] wire [15:0] io_lsu_store_ack_0_bits_uop_br_mask_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_store_ack_0_bits_uop_br_tag_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_store_ack_0_bits_uop_br_type_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_sfb_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_fence_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_fencei_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_sfence_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_amo_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_eret_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_rocc_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_mov_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_store_ack_0_bits_uop_ftq_idx_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_edge_inst_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_store_ack_0_bits_uop_pc_lob_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_taken_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_imm_rename_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_imm_sel_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_store_ack_0_bits_uop_pimm_0; // @[dcache.scala:438:7] wire [19:0] io_lsu_store_ack_0_bits_uop_imm_packed_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_op1_sel_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_op2_sel_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_store_ack_0_bits_uop_rob_idx_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_store_ack_0_bits_uop_ldq_idx_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_store_ack_0_bits_uop_stq_idx_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_rxq_idx_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_store_ack_0_bits_uop_pdst_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_store_ack_0_bits_uop_prs1_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_store_ack_0_bits_uop_prs2_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_store_ack_0_bits_uop_prs3_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_store_ack_0_bits_uop_ppred_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_prs1_busy_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_prs2_busy_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_prs3_busy_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_ppred_busy_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_store_ack_0_bits_uop_stale_pdst_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_exception_0; // @[dcache.scala:438:7] wire [63:0] io_lsu_store_ack_0_bits_uop_exc_cause_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_store_ack_0_bits_uop_mem_cmd_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_mem_size_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_mem_signed_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_uses_ldq_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_uses_stq_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_is_unique_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_csr_cmd_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_store_ack_0_bits_uop_ldst_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_store_ack_0_bits_uop_lrs1_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_store_ack_0_bits_uop_lrs2_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_store_ack_0_bits_uop_lrs3_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_dst_rtype_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_frs3_en_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fcn_dw_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_store_ack_0_bits_uop_fcn_op_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_fp_val_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_fp_rm_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_store_ack_0_bits_uop_fp_typ_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_store_ack_0_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7] wire [39:0] io_lsu_store_ack_0_bits_addr_0; // @[dcache.scala:438:7] wire [63:0] io_lsu_store_ack_0_bits_data_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_bits_is_hella_0; // @[dcache.scala:438:7] wire io_lsu_store_ack_0_valid_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iq_type_0_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iq_type_1_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iq_type_2_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iq_type_3_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_0_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_1_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_2_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_3_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_4_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_5_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_6_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_7_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_8_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fu_code_9_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_nack_0_bits_uop_inst_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_nack_0_bits_uop_debug_inst_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_rvc_0; // @[dcache.scala:438:7] wire [39:0] io_lsu_nack_0_bits_uop_debug_pc_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iw_issued_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7] wire [15:0] io_lsu_nack_0_bits_uop_br_mask_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_nack_0_bits_uop_br_tag_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_nack_0_bits_uop_br_type_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_sfb_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_fence_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_fencei_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_sfence_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_amo_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_eret_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_rocc_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_mov_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_nack_0_bits_uop_ftq_idx_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_edge_inst_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_nack_0_bits_uop_pc_lob_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_taken_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_imm_rename_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_imm_sel_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_nack_0_bits_uop_pimm_0; // @[dcache.scala:438:7] wire [19:0] io_lsu_nack_0_bits_uop_imm_packed_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_op1_sel_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_op2_sel_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_nack_0_bits_uop_rob_idx_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_nack_0_bits_uop_ldq_idx_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_nack_0_bits_uop_stq_idx_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_rxq_idx_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_nack_0_bits_uop_pdst_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_nack_0_bits_uop_prs1_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_nack_0_bits_uop_prs2_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_nack_0_bits_uop_prs3_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_nack_0_bits_uop_ppred_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_prs1_busy_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_prs2_busy_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_prs3_busy_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_ppred_busy_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_nack_0_bits_uop_stale_pdst_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_exception_0; // @[dcache.scala:438:7] wire [63:0] io_lsu_nack_0_bits_uop_exc_cause_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_nack_0_bits_uop_mem_cmd_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_mem_size_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_mem_signed_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_uses_ldq_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_uses_stq_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_is_unique_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_csr_cmd_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_nack_0_bits_uop_ldst_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_nack_0_bits_uop_lrs1_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_nack_0_bits_uop_lrs2_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_nack_0_bits_uop_lrs3_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_dst_rtype_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_frs3_en_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fcn_dw_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_nack_0_bits_uop_fcn_op_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_fp_val_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_fp_rm_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_nack_0_bits_uop_fp_typ_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_nack_0_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7] wire [39:0] io_lsu_nack_0_bits_addr_0; // @[dcache.scala:438:7] wire [63:0] io_lsu_nack_0_bits_data_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_bits_is_hella_0; // @[dcache.scala:438:7] wire io_lsu_nack_0_valid_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iq_type_0_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iq_type_1_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iq_type_2_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iq_type_3_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_0_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_1_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_2_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_3_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_4_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_5_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_6_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_7_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_8_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fu_code_9_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_ldst_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_wen_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_ren1_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_ren2_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_ren3_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_swap12_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_swap23_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_fromint_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_toint_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_fastpipe_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_fma_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_div_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_sqrt_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_wflags_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_ctrl_vec_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_ll_resp_bits_uop_inst_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_ll_resp_bits_uop_debug_inst_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_rvc_0; // @[dcache.scala:438:7] wire [39:0] io_lsu_ll_resp_bits_uop_debug_pc_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iw_issued_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iw_issued_partial_agen_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iw_issued_partial_dgen_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_iw_p1_speculative_child_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_iw_p2_speculative_child_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iw_p1_bypass_hint_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iw_p2_bypass_hint_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_iw_p3_bypass_hint_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_dis_col_sel_0; // @[dcache.scala:438:7] wire [15:0] io_lsu_ll_resp_bits_uop_br_mask_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_ll_resp_bits_uop_br_tag_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_ll_resp_bits_uop_br_type_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_sfb_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_fence_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_fencei_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_sfence_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_amo_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_eret_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_sys_pc2epc_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_rocc_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_mov_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_ll_resp_bits_uop_ftq_idx_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_edge_inst_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_ll_resp_bits_uop_pc_lob_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_taken_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_imm_rename_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_imm_sel_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_ll_resp_bits_uop_pimm_0; // @[dcache.scala:438:7] wire [19:0] io_lsu_ll_resp_bits_uop_imm_packed_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_op1_sel_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_op2_sel_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_ll_resp_bits_uop_rob_idx_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_ll_resp_bits_uop_ldq_idx_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_ll_resp_bits_uop_stq_idx_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_rxq_idx_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_ll_resp_bits_uop_pdst_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_ll_resp_bits_uop_prs1_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_ll_resp_bits_uop_prs2_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_ll_resp_bits_uop_prs3_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_ll_resp_bits_uop_ppred_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_prs1_busy_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_prs2_busy_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_prs3_busy_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_ppred_busy_0; // @[dcache.scala:438:7] wire [6:0] io_lsu_ll_resp_bits_uop_stale_pdst_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_exception_0; // @[dcache.scala:438:7] wire [63:0] io_lsu_ll_resp_bits_uop_exc_cause_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_ll_resp_bits_uop_mem_cmd_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_mem_size_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_mem_signed_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_uses_ldq_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_uses_stq_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_is_unique_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_flush_on_commit_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_csr_cmd_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_ldst_is_rs1_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_ll_resp_bits_uop_ldst_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_ll_resp_bits_uop_lrs1_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_ll_resp_bits_uop_lrs2_0; // @[dcache.scala:438:7] wire [5:0] io_lsu_ll_resp_bits_uop_lrs3_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_dst_rtype_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_lrs1_rtype_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_lrs2_rtype_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_frs3_en_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fcn_dw_0; // @[dcache.scala:438:7] wire [4:0] io_lsu_ll_resp_bits_uop_fcn_op_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_fp_val_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_fp_rm_0; // @[dcache.scala:438:7] wire [1:0] io_lsu_ll_resp_bits_uop_fp_typ_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_xcpt_pf_if_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_xcpt_ae_if_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_xcpt_ma_if_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_bp_debug_if_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_uop_bp_xcpt_if_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_debug_fsrc_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_ll_resp_bits_uop_debug_tsrc_0; // @[dcache.scala:438:7] wire [63:0] io_lsu_ll_resp_bits_data_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_bits_is_hella_0; // @[dcache.scala:438:7] wire io_lsu_ll_resp_valid_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_release_bits_opcode_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:438:7] wire [3:0] io_lsu_release_bits_size_0; // @[dcache.scala:438:7] wire [2:0] io_lsu_release_bits_source_0; // @[dcache.scala:438:7] wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:438:7] wire [127:0] io_lsu_release_bits_data_0; // @[dcache.scala:438:7] wire io_lsu_release_valid_0; // @[dcache.scala:438:7] wire io_lsu_perf_acquire_0; // @[dcache.scala:438:7] wire io_lsu_perf_release_0; // @[dcache.scala:438:7] wire io_lsu_ordered_0; // @[dcache.scala:438:7] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[MixedNode.scala:542:17] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire _nodeOut_b_ready_T_1; // @[dcache.scala:822:48] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[MixedNode.scala:542:17] wire _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire [2:0] _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [127:0] _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[MixedNode.scala:542:17] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[MixedNode.scala:542:17] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[MixedNode.scala:542:17] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire _meta_0_io_write_valid_T = _meta_0_io_write_ready & _metaWriteArb_io_out_valid; // @[Decoupled.scala:51:35] wire _data_io_read_0_valid_T = _dataReadArb_io_out_bits_valid_0 & _dataReadArb_io_out_valid; // @[dcache.scala:490:27, :495:63] wire block_incoming_reqs; // @[dcache.scala:510:47] wire _io_lsu_req_ready_T = _metaReadArb_io_in_4_ready & _dataReadArb_io_in_2_ready; // @[dcache.scala:472:27, :490:27, :511:50] wire _io_lsu_req_ready_T_1 = ~block_incoming_reqs; // @[dcache.scala:510:47, :511:83] assign _io_lsu_req_ready_T_2 = _io_lsu_req_ready_T & _io_lsu_req_ready_T_1; // @[dcache.scala:511:{50,80,83}] assign io_lsu_req_ready_0 = _io_lsu_req_ready_T_2; // @[dcache.scala:438:7, :511:80] wire _metaReadArb_io_in_4_valid_T = ~block_incoming_reqs; // @[dcache.scala:510:47, :511:83, :512:53] wire _metaReadArb_io_in_4_valid_T_1 = io_lsu_req_valid_0 & _metaReadArb_io_in_4_valid_T; // @[dcache.scala:438:7, :512:{50,53}] wire _dataReadArb_io_in_2_valid_T = ~block_incoming_reqs; // @[dcache.scala:510:47, :511:83, :513:53] wire _dataReadArb_io_in_2_valid_T_1 = io_lsu_req_valid_0 & _dataReadArb_io_in_2_valid_T; // @[dcache.scala:438:7, :513:{50,53}] wire [33:0] _metaReadArb_io_in_4_bits_req_0_idx_T = io_lsu_req_bits_0_bits_addr_0[39:6]; // @[dcache.scala:438:7, :516:77] wire replay_req_0_uop_iq_type_0; // @[dcache.scala:527:24] wire replay_req_0_uop_iq_type_1; // @[dcache.scala:527:24] wire replay_req_0_uop_iq_type_2; // @[dcache.scala:527:24] wire replay_req_0_uop_iq_type_3; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_0; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_1; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_2; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_3; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_4; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_5; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_6; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_7; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_8; // @[dcache.scala:527:24] wire replay_req_0_uop_fu_code_9; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_wen; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_toint; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_fma; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_div; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_ctrl_vec; // @[dcache.scala:527:24] wire [31:0] replay_req_0_uop_inst; // @[dcache.scala:527:24] wire [31:0] replay_req_0_uop_debug_inst; // @[dcache.scala:527:24] wire replay_req_0_uop_is_rvc; // @[dcache.scala:527:24] wire [39:0] replay_req_0_uop_debug_pc; // @[dcache.scala:527:24] wire replay_req_0_uop_iw_issued; // @[dcache.scala:527:24] wire replay_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:527:24] wire replay_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:527:24] wire replay_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:527:24] wire replay_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:527:24] wire replay_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_dis_col_sel; // @[dcache.scala:527:24] wire [15:0] replay_req_0_uop_br_mask; // @[dcache.scala:527:24] wire [3:0] replay_req_0_uop_br_tag; // @[dcache.scala:527:24] wire [3:0] replay_req_0_uop_br_type; // @[dcache.scala:527:24] wire replay_req_0_uop_is_sfb; // @[dcache.scala:527:24] wire replay_req_0_uop_is_fence; // @[dcache.scala:527:24] wire replay_req_0_uop_is_fencei; // @[dcache.scala:527:24] wire replay_req_0_uop_is_sfence; // @[dcache.scala:527:24] wire replay_req_0_uop_is_amo; // @[dcache.scala:527:24] wire replay_req_0_uop_is_eret; // @[dcache.scala:527:24] wire replay_req_0_uop_is_sys_pc2epc; // @[dcache.scala:527:24] wire replay_req_0_uop_is_rocc; // @[dcache.scala:527:24] wire replay_req_0_uop_is_mov; // @[dcache.scala:527:24] wire [4:0] replay_req_0_uop_ftq_idx; // @[dcache.scala:527:24] wire replay_req_0_uop_edge_inst; // @[dcache.scala:527:24] wire [5:0] replay_req_0_uop_pc_lob; // @[dcache.scala:527:24] wire replay_req_0_uop_taken; // @[dcache.scala:527:24] wire replay_req_0_uop_imm_rename; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_imm_sel; // @[dcache.scala:527:24] wire [4:0] replay_req_0_uop_pimm; // @[dcache.scala:527:24] wire [19:0] replay_req_0_uop_imm_packed; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_op1_sel; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_op2_sel; // @[dcache.scala:527:24] wire [6:0] replay_req_0_uop_rob_idx; // @[dcache.scala:527:24] wire [4:0] replay_req_0_uop_ldq_idx; // @[dcache.scala:527:24] wire [4:0] replay_req_0_uop_stq_idx; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_rxq_idx; // @[dcache.scala:527:24] wire [6:0] replay_req_0_uop_pdst; // @[dcache.scala:527:24] wire [6:0] replay_req_0_uop_prs1; // @[dcache.scala:527:24] wire [6:0] replay_req_0_uop_prs2; // @[dcache.scala:527:24] wire [6:0] replay_req_0_uop_prs3; // @[dcache.scala:527:24] wire [4:0] replay_req_0_uop_ppred; // @[dcache.scala:527:24] wire replay_req_0_uop_prs1_busy; // @[dcache.scala:527:24] wire replay_req_0_uop_prs2_busy; // @[dcache.scala:527:24] wire replay_req_0_uop_prs3_busy; // @[dcache.scala:527:24] wire replay_req_0_uop_ppred_busy; // @[dcache.scala:527:24] wire [6:0] replay_req_0_uop_stale_pdst; // @[dcache.scala:527:24] wire replay_req_0_uop_exception; // @[dcache.scala:527:24] wire [63:0] replay_req_0_uop_exc_cause; // @[dcache.scala:527:24] wire [4:0] replay_req_0_uop_mem_cmd; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_mem_size; // @[dcache.scala:527:24] wire replay_req_0_uop_mem_signed; // @[dcache.scala:527:24] wire replay_req_0_uop_uses_ldq; // @[dcache.scala:527:24] wire replay_req_0_uop_uses_stq; // @[dcache.scala:527:24] wire replay_req_0_uop_is_unique; // @[dcache.scala:527:24] wire replay_req_0_uop_flush_on_commit; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_csr_cmd; // @[dcache.scala:527:24] wire replay_req_0_uop_ldst_is_rs1; // @[dcache.scala:527:24] wire [5:0] replay_req_0_uop_ldst; // @[dcache.scala:527:24] wire [5:0] replay_req_0_uop_lrs1; // @[dcache.scala:527:24] wire [5:0] replay_req_0_uop_lrs2; // @[dcache.scala:527:24] wire [5:0] replay_req_0_uop_lrs3; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_dst_rtype; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_lrs1_rtype; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_lrs2_rtype; // @[dcache.scala:527:24] wire replay_req_0_uop_frs3_en; // @[dcache.scala:527:24] wire replay_req_0_uop_fcn_dw; // @[dcache.scala:527:24] wire [4:0] replay_req_0_uop_fcn_op; // @[dcache.scala:527:24] wire replay_req_0_uop_fp_val; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_fp_rm; // @[dcache.scala:527:24] wire [1:0] replay_req_0_uop_fp_typ; // @[dcache.scala:527:24] wire replay_req_0_uop_xcpt_pf_if; // @[dcache.scala:527:24] wire replay_req_0_uop_xcpt_ae_if; // @[dcache.scala:527:24] wire replay_req_0_uop_xcpt_ma_if; // @[dcache.scala:527:24] wire replay_req_0_uop_bp_debug_if; // @[dcache.scala:527:24] wire replay_req_0_uop_bp_xcpt_if; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_debug_fsrc; // @[dcache.scala:527:24] wire [2:0] replay_req_0_uop_debug_tsrc; // @[dcache.scala:527:24] wire [39:0] replay_req_0_addr; // @[dcache.scala:527:24] wire [63:0] replay_req_0_data; // @[dcache.scala:527:24] wire replay_req_0_is_hella; // @[dcache.scala:527:24] wire _mshrs_io_replay_ready_T_2 = _mshrs_io_replay_ready_T; // @[dcache.scala:534:{58,88}] wire [33:0] _metaReadArb_io_in_0_bits_req_0_idx_T = _mshrs_io_replay_bits_addr[39:6]; // @[dcache.scala:460:21, :538:72] wire [39:0] mshr_read_req_0_addr; // @[dcache.scala:549:27] wire [25:0] _mshr_read_req_0_addr_T = {_mshrs_io_meta_read_bits_tag, _mshrs_io_meta_read_bits_idx}; // @[dcache.scala:460:21, :552:35] wire [31:0] _mshr_read_req_0_addr_T_1 = {_mshr_read_req_0_addr_T, 6'h0}; // @[dcache.scala:552:{35,94}] assign mshr_read_req_0_addr = {8'h0, _mshr_read_req_0_addr_T_1}; // @[dcache.scala:549:27, :552:{29,94}] wire _wb_io_meta_read_ready_T_2; // @[dcache.scala:575:85] wire _wb_fire_T = _wb_io_meta_read_ready_T_2 & _wb_io_meta_read_valid; // @[Decoupled.scala:51:35] wire _wb_io_data_req_ready_T_2; // @[dcache.scala:580:85] wire _wb_fire_T_1 = _wb_io_data_req_ready_T_2 & _wb_io_data_req_valid; // @[Decoupled.scala:51:35] wire wb_fire = _wb_fire_T & _wb_fire_T_1; // @[Decoupled.scala:51:35] wire [39:0] wb_req_0_addr; // @[dcache.scala:564:20] wire [31:0] _wb_req_0_addr_T = {_wb_io_meta_read_bits_tag, _wb_io_data_req_bits_addr}; // @[dcache.scala:458:18, :567:28] assign wb_req_0_addr = {8'h0, _wb_req_0_addr_T}; // @[dcache.scala:564:20, :567:{22,28}] wire _GEN = _metaReadArb_io_in_2_ready & _dataReadArb_io_in_1_ready; // @[dcache.scala:472:27, :490:27, :575:55] wire _wb_io_meta_read_ready_T; // @[dcache.scala:575:55] assign _wb_io_meta_read_ready_T = _GEN; // @[dcache.scala:575:55] wire _wb_io_data_req_ready_T; // @[dcache.scala:580:55] assign _wb_io_data_req_ready_T = _GEN; // @[dcache.scala:575:55, :580:55] assign _wb_io_meta_read_ready_T_2 = _wb_io_meta_read_ready_T; // @[dcache.scala:575:{55,85}] assign _wb_io_data_req_ready_T_2 = _wb_io_data_req_ready_T; // @[dcache.scala:580:{55,85}] wire prober_fire = _metaReadArb_io_in_1_ready & _prober_io_meta_read_valid; // @[Decoupled.scala:51:35] wire [39:0] prober_req_0_addr; // @[dcache.scala:586:26] wire [25:0] _prober_req_0_addr_T = {_prober_io_meta_read_bits_tag, _prober_io_meta_read_bits_idx}; // @[dcache.scala:459:22, :589:32] wire [31:0] _prober_req_0_addr_T_1 = {_prober_req_0_addr_T, 6'h0}; // @[dcache.scala:589:{32,93}] assign prober_req_0_addr = {8'h0, _prober_req_0_addr_T_1}; // @[dcache.scala:586:26, :589:{26,93}] wire _T_7 = io_lsu_req_ready_0 & io_lsu_req_valid_0; // @[Decoupled.scala:51:35] wire _s0_valid_T; // @[Decoupled.scala:51:35] assign _s0_valid_T = _T_7; // @[Decoupled.scala:51:35] wire _s0_req_T; // @[Decoupled.scala:51:35] assign _s0_req_T = _T_7; // @[Decoupled.scala:51:35] wire _s0_type_T; // @[Decoupled.scala:51:35] assign _s0_type_T = _T_7; // @[Decoupled.scala:51:35] wire _s0_send_resp_or_nack_T; // @[Decoupled.scala:51:35] assign _s0_send_resp_or_nack_T = _T_7; // @[Decoupled.scala:51:35] wire _s1_valid_T_8; // @[Decoupled.scala:51:35] assign _s1_valid_T_8 = _T_7; // @[Decoupled.scala:51:35] wire _GEN_0 = _mshrs_io_replay_ready_T_2 & _mshrs_io_replay_valid; // @[Decoupled.scala:51:35] wire _s0_valid_T_1; // @[Decoupled.scala:51:35] assign _s0_valid_T_1 = _GEN_0; // @[Decoupled.scala:51:35] wire _s0_send_resp_or_nack_T_1; // @[Decoupled.scala:51:35] assign _s0_send_resp_or_nack_T_1 = _GEN_0; // @[Decoupled.scala:51:35] wire _s0_valid_T_2 = _s0_valid_T_1 | wb_fire; // @[Decoupled.scala:51:35] wire _s0_valid_T_3 = _s0_valid_T_2 | prober_fire; // @[Decoupled.scala:51:35] wire _s0_valid_T_4 = _s0_valid_T_3; // @[dcache.scala:613:{54,69}] wire _GEN_1 = _metaReadArb_io_in_3_ready & _mshrs_io_meta_read_valid; // @[Decoupled.scala:51:35] wire _s0_valid_T_5; // @[Decoupled.scala:51:35] assign _s0_valid_T_5 = _GEN_1; // @[Decoupled.scala:51:35] wire _s0_req_T_1; // @[Decoupled.scala:51:35] assign _s0_req_T_1 = _GEN_1; // @[Decoupled.scala:51:35] wire _s0_type_T_1; // @[Decoupled.scala:51:35] assign _s0_type_T_1 = _GEN_1; // @[Decoupled.scala:51:35] wire _s0_valid_T_6 = _s0_valid_T_4 | _s0_valid_T_5; // @[Decoupled.scala:51:35] wire _s0_valid_T_7_0 = _s0_valid_T_6; // @[dcache.scala:613:{21,86}] wire s0_valid_0 = _s0_valid_T ? _s0_valid_WIRE_0 : _s0_valid_T_7_0; // @[Decoupled.scala:51:35] wire [31:0] _s0_req_T_2_0_uop_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_inst; // @[Decoupled.scala:51:35] wire [31:0] _s0_req_T_2_0_uop_debug_inst = _s0_req_T_1 ? 32'h0 : replay_req_0_uop_debug_inst; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_rvc = ~_s0_req_T_1 & replay_req_0_uop_is_rvc; // @[Decoupled.scala:51:35] wire [39:0] _s0_req_T_2_0_uop_debug_pc = _s0_req_T_1 ? 40'h0 : replay_req_0_uop_debug_pc; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iq_type_0 = ~_s0_req_T_1 & replay_req_0_uop_iq_type_0; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iq_type_1 = ~_s0_req_T_1 & replay_req_0_uop_iq_type_1; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iq_type_2 = ~_s0_req_T_1 & replay_req_0_uop_iq_type_2; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iq_type_3 = ~_s0_req_T_1 & replay_req_0_uop_iq_type_3; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_0 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_0; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_1 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_1; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_2 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_2; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_3 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_3; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_4 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_4; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_5 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_5; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_6 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_6; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_7 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_7; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_8 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_8; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fu_code_9 = ~_s0_req_T_1 & replay_req_0_uop_fu_code_9; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iw_issued = ~_s0_req_T_1 & replay_req_0_uop_iw_issued; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iw_issued_partial_agen = ~_s0_req_T_1 & replay_req_0_uop_iw_issued_partial_agen; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iw_issued_partial_dgen = ~_s0_req_T_1 & replay_req_0_uop_iw_issued_partial_dgen; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_iw_p1_speculative_child = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_iw_p1_speculative_child; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_iw_p2_speculative_child = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_iw_p2_speculative_child; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iw_p1_bypass_hint = ~_s0_req_T_1 & replay_req_0_uop_iw_p1_bypass_hint; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iw_p2_bypass_hint = ~_s0_req_T_1 & replay_req_0_uop_iw_p2_bypass_hint; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_iw_p3_bypass_hint = ~_s0_req_T_1 & replay_req_0_uop_iw_p3_bypass_hint; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_dis_col_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_dis_col_sel; // @[Decoupled.scala:51:35] wire [15:0] _s0_req_T_2_0_uop_br_mask = _s0_req_T_1 ? 16'h0 : replay_req_0_uop_br_mask; // @[Decoupled.scala:51:35] wire [3:0] _s0_req_T_2_0_uop_br_tag = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_br_tag; // @[Decoupled.scala:51:35] wire [3:0] _s0_req_T_2_0_uop_br_type = _s0_req_T_1 ? 4'h0 : replay_req_0_uop_br_type; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_sfb = ~_s0_req_T_1 & replay_req_0_uop_is_sfb; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_fence = ~_s0_req_T_1 & replay_req_0_uop_is_fence; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_fencei = ~_s0_req_T_1 & replay_req_0_uop_is_fencei; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_sfence = ~_s0_req_T_1 & replay_req_0_uop_is_sfence; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_amo = ~_s0_req_T_1 & replay_req_0_uop_is_amo; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_eret = ~_s0_req_T_1 & replay_req_0_uop_is_eret; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_sys_pc2epc = ~_s0_req_T_1 & replay_req_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_rocc = ~_s0_req_T_1 & replay_req_0_uop_is_rocc; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_mov = ~_s0_req_T_1 & replay_req_0_uop_is_mov; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_2_0_uop_ftq_idx = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ftq_idx; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_edge_inst = ~_s0_req_T_1 & replay_req_0_uop_edge_inst; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_2_0_uop_pc_lob = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_pc_lob; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_taken = ~_s0_req_T_1 & replay_req_0_uop_taken; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_imm_rename = ~_s0_req_T_1 & replay_req_0_uop_imm_rename; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_imm_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_imm_sel; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_2_0_uop_pimm = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_pimm; // @[Decoupled.scala:51:35] wire [19:0] _s0_req_T_2_0_uop_imm_packed = _s0_req_T_1 ? 20'h0 : replay_req_0_uop_imm_packed; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_op1_sel = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_op1_sel; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_op2_sel = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_op2_sel; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_ldst = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_ldst; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_wen = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_wen; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_ren1 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_ren1; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_ren2 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_ren2; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_ren3 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_ren3; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_swap12 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_swap12; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_swap23 = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_swap23; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_fp_ctrl_typeTagIn = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_fp_ctrl_typeTagIn; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_fp_ctrl_typeTagOut = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_fp_ctrl_typeTagOut; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_fromint = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_fromint; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_toint = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_toint; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_fastpipe = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_fastpipe; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_fma = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_fma; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_div = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_div; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_sqrt = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_sqrt; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_wflags = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_wflags; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_ctrl_vec = ~_s0_req_T_1 & replay_req_0_uop_fp_ctrl_vec; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_2_0_uop_rob_idx = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_rob_idx; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_2_0_uop_ldq_idx = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ldq_idx; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_2_0_uop_stq_idx = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_stq_idx; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_rxq_idx = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_rxq_idx; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_2_0_uop_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_pdst; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_2_0_uop_prs1 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs1; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_2_0_uop_prs2 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs2; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_2_0_uop_prs3 = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_prs3; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_2_0_uop_ppred = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_ppred; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_prs1_busy = ~_s0_req_T_1 & replay_req_0_uop_prs1_busy; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_prs2_busy = ~_s0_req_T_1 & replay_req_0_uop_prs2_busy; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_prs3_busy = ~_s0_req_T_1 & replay_req_0_uop_prs3_busy; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_ppred_busy = ~_s0_req_T_1 & replay_req_0_uop_ppred_busy; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_2_0_uop_stale_pdst = _s0_req_T_1 ? 7'h0 : replay_req_0_uop_stale_pdst; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_exception = ~_s0_req_T_1 & replay_req_0_uop_exception; // @[Decoupled.scala:51:35] wire [63:0] _s0_req_T_2_0_uop_exc_cause = _s0_req_T_1 ? 64'h0 : replay_req_0_uop_exc_cause; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_2_0_uop_mem_cmd = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_mem_cmd; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_mem_size = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_mem_size; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_mem_signed = ~_s0_req_T_1 & replay_req_0_uop_mem_signed; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_uses_ldq = ~_s0_req_T_1 & replay_req_0_uop_uses_ldq; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_uses_stq = ~_s0_req_T_1 & replay_req_0_uop_uses_stq; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_is_unique = ~_s0_req_T_1 & replay_req_0_uop_is_unique; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_flush_on_commit = ~_s0_req_T_1 & replay_req_0_uop_flush_on_commit; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_csr_cmd = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_csr_cmd; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_ldst_is_rs1 = ~_s0_req_T_1 & replay_req_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_2_0_uop_ldst = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_ldst; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_2_0_uop_lrs1 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs1; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_2_0_uop_lrs2 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs2; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_2_0_uop_lrs3 = _s0_req_T_1 ? 6'h0 : replay_req_0_uop_lrs3; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_dst_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_dst_rtype; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_lrs1_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_lrs2_rtype = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_frs3_en = ~_s0_req_T_1 & replay_req_0_uop_frs3_en; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fcn_dw = ~_s0_req_T_1 & replay_req_0_uop_fcn_dw; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_2_0_uop_fcn_op = _s0_req_T_1 ? 5'h0 : replay_req_0_uop_fcn_op; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_fp_val = ~_s0_req_T_1 & replay_req_0_uop_fp_val; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_fp_rm = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_fp_rm; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_2_0_uop_fp_typ = _s0_req_T_1 ? 2'h0 : replay_req_0_uop_fp_typ; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_xcpt_pf_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_xcpt_ae_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_xcpt_ma_if = ~_s0_req_T_1 & replay_req_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_bp_debug_if = ~_s0_req_T_1 & replay_req_0_uop_bp_debug_if; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_uop_bp_xcpt_if = ~_s0_req_T_1 & replay_req_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_debug_fsrc = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_debug_fsrc; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_2_0_uop_debug_tsrc = _s0_req_T_1 ? 3'h0 : replay_req_0_uop_debug_tsrc; // @[Decoupled.scala:51:35] wire [39:0] _s0_req_T_2_0_addr = _s0_req_T_1 ? mshr_read_req_0_addr : replay_req_0_addr; // @[Decoupled.scala:51:35] wire [63:0] _s0_req_T_2_0_data = _s0_req_T_1 ? 64'h0 : replay_req_0_data; // @[Decoupled.scala:51:35] wire _s0_req_T_2_0_is_hella = ~_s0_req_T_1 & replay_req_0_is_hella; // @[Decoupled.scala:51:35] wire [31:0] _s0_req_T_3_0_uop_inst = _s0_req_T_2_0_uop_inst; // @[dcache.scala:618:21, :619:21] wire [31:0] _s0_req_T_3_0_uop_debug_inst = _s0_req_T_2_0_uop_debug_inst; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_rvc = _s0_req_T_2_0_uop_is_rvc; // @[dcache.scala:618:21, :619:21] wire [39:0] _s0_req_T_3_0_uop_debug_pc = _s0_req_T_2_0_uop_debug_pc; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iq_type_0 = _s0_req_T_2_0_uop_iq_type_0; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iq_type_1 = _s0_req_T_2_0_uop_iq_type_1; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iq_type_2 = _s0_req_T_2_0_uop_iq_type_2; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iq_type_3 = _s0_req_T_2_0_uop_iq_type_3; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_0 = _s0_req_T_2_0_uop_fu_code_0; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_1 = _s0_req_T_2_0_uop_fu_code_1; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_2 = _s0_req_T_2_0_uop_fu_code_2; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_3 = _s0_req_T_2_0_uop_fu_code_3; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_4 = _s0_req_T_2_0_uop_fu_code_4; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_5 = _s0_req_T_2_0_uop_fu_code_5; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_6 = _s0_req_T_2_0_uop_fu_code_6; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_7 = _s0_req_T_2_0_uop_fu_code_7; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_8 = _s0_req_T_2_0_uop_fu_code_8; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fu_code_9 = _s0_req_T_2_0_uop_fu_code_9; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iw_issued = _s0_req_T_2_0_uop_iw_issued; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iw_issued_partial_agen = _s0_req_T_2_0_uop_iw_issued_partial_agen; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iw_issued_partial_dgen = _s0_req_T_2_0_uop_iw_issued_partial_dgen; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_iw_p1_speculative_child = _s0_req_T_2_0_uop_iw_p1_speculative_child; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_iw_p2_speculative_child = _s0_req_T_2_0_uop_iw_p2_speculative_child; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iw_p1_bypass_hint = _s0_req_T_2_0_uop_iw_p1_bypass_hint; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iw_p2_bypass_hint = _s0_req_T_2_0_uop_iw_p2_bypass_hint; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_iw_p3_bypass_hint = _s0_req_T_2_0_uop_iw_p3_bypass_hint; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_dis_col_sel = _s0_req_T_2_0_uop_dis_col_sel; // @[dcache.scala:618:21, :619:21] wire [15:0] _s0_req_T_3_0_uop_br_mask = _s0_req_T_2_0_uop_br_mask; // @[dcache.scala:618:21, :619:21] wire [3:0] _s0_req_T_3_0_uop_br_tag = _s0_req_T_2_0_uop_br_tag; // @[dcache.scala:618:21, :619:21] wire [3:0] _s0_req_T_3_0_uop_br_type = _s0_req_T_2_0_uop_br_type; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_sfb = _s0_req_T_2_0_uop_is_sfb; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_fence = _s0_req_T_2_0_uop_is_fence; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_fencei = _s0_req_T_2_0_uop_is_fencei; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_sfence = _s0_req_T_2_0_uop_is_sfence; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_amo = _s0_req_T_2_0_uop_is_amo; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_eret = _s0_req_T_2_0_uop_is_eret; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_sys_pc2epc = _s0_req_T_2_0_uop_is_sys_pc2epc; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_rocc = _s0_req_T_2_0_uop_is_rocc; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_mov = _s0_req_T_2_0_uop_is_mov; // @[dcache.scala:618:21, :619:21] wire [4:0] _s0_req_T_3_0_uop_ftq_idx = _s0_req_T_2_0_uop_ftq_idx; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_edge_inst = _s0_req_T_2_0_uop_edge_inst; // @[dcache.scala:618:21, :619:21] wire [5:0] _s0_req_T_3_0_uop_pc_lob = _s0_req_T_2_0_uop_pc_lob; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_taken = _s0_req_T_2_0_uop_taken; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_imm_rename = _s0_req_T_2_0_uop_imm_rename; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_imm_sel = _s0_req_T_2_0_uop_imm_sel; // @[dcache.scala:618:21, :619:21] wire [4:0] _s0_req_T_3_0_uop_pimm = _s0_req_T_2_0_uop_pimm; // @[dcache.scala:618:21, :619:21] wire [19:0] _s0_req_T_3_0_uop_imm_packed = _s0_req_T_2_0_uop_imm_packed; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_op1_sel = _s0_req_T_2_0_uop_op1_sel; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_op2_sel = _s0_req_T_2_0_uop_op2_sel; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_ldst = _s0_req_T_2_0_uop_fp_ctrl_ldst; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_wen = _s0_req_T_2_0_uop_fp_ctrl_wen; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_ren1 = _s0_req_T_2_0_uop_fp_ctrl_ren1; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_ren2 = _s0_req_T_2_0_uop_fp_ctrl_ren2; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_ren3 = _s0_req_T_2_0_uop_fp_ctrl_ren3; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_swap12 = _s0_req_T_2_0_uop_fp_ctrl_swap12; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_swap23 = _s0_req_T_2_0_uop_fp_ctrl_swap23; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_fp_ctrl_typeTagIn = _s0_req_T_2_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_fp_ctrl_typeTagOut = _s0_req_T_2_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_fromint = _s0_req_T_2_0_uop_fp_ctrl_fromint; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_toint = _s0_req_T_2_0_uop_fp_ctrl_toint; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_fastpipe = _s0_req_T_2_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_fma = _s0_req_T_2_0_uop_fp_ctrl_fma; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_div = _s0_req_T_2_0_uop_fp_ctrl_div; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_sqrt = _s0_req_T_2_0_uop_fp_ctrl_sqrt; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_wflags = _s0_req_T_2_0_uop_fp_ctrl_wflags; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_ctrl_vec = _s0_req_T_2_0_uop_fp_ctrl_vec; // @[dcache.scala:618:21, :619:21] wire [6:0] _s0_req_T_3_0_uop_rob_idx = _s0_req_T_2_0_uop_rob_idx; // @[dcache.scala:618:21, :619:21] wire [4:0] _s0_req_T_3_0_uop_ldq_idx = _s0_req_T_2_0_uop_ldq_idx; // @[dcache.scala:618:21, :619:21] wire [4:0] _s0_req_T_3_0_uop_stq_idx = _s0_req_T_2_0_uop_stq_idx; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_rxq_idx = _s0_req_T_2_0_uop_rxq_idx; // @[dcache.scala:618:21, :619:21] wire [6:0] _s0_req_T_3_0_uop_pdst = _s0_req_T_2_0_uop_pdst; // @[dcache.scala:618:21, :619:21] wire [6:0] _s0_req_T_3_0_uop_prs1 = _s0_req_T_2_0_uop_prs1; // @[dcache.scala:618:21, :619:21] wire [6:0] _s0_req_T_3_0_uop_prs2 = _s0_req_T_2_0_uop_prs2; // @[dcache.scala:618:21, :619:21] wire [6:0] _s0_req_T_3_0_uop_prs3 = _s0_req_T_2_0_uop_prs3; // @[dcache.scala:618:21, :619:21] wire [4:0] _s0_req_T_3_0_uop_ppred = _s0_req_T_2_0_uop_ppred; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_prs1_busy = _s0_req_T_2_0_uop_prs1_busy; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_prs2_busy = _s0_req_T_2_0_uop_prs2_busy; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_prs3_busy = _s0_req_T_2_0_uop_prs3_busy; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_ppred_busy = _s0_req_T_2_0_uop_ppred_busy; // @[dcache.scala:618:21, :619:21] wire [6:0] _s0_req_T_3_0_uop_stale_pdst = _s0_req_T_2_0_uop_stale_pdst; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_exception = _s0_req_T_2_0_uop_exception; // @[dcache.scala:618:21, :619:21] wire [63:0] _s0_req_T_3_0_uop_exc_cause = _s0_req_T_2_0_uop_exc_cause; // @[dcache.scala:618:21, :619:21] wire [4:0] _s0_req_T_3_0_uop_mem_cmd = _s0_req_T_2_0_uop_mem_cmd; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_mem_size = _s0_req_T_2_0_uop_mem_size; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_mem_signed = _s0_req_T_2_0_uop_mem_signed; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_uses_ldq = _s0_req_T_2_0_uop_uses_ldq; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_uses_stq = _s0_req_T_2_0_uop_uses_stq; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_is_unique = _s0_req_T_2_0_uop_is_unique; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_flush_on_commit = _s0_req_T_2_0_uop_flush_on_commit; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_csr_cmd = _s0_req_T_2_0_uop_csr_cmd; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_ldst_is_rs1 = _s0_req_T_2_0_uop_ldst_is_rs1; // @[dcache.scala:618:21, :619:21] wire [5:0] _s0_req_T_3_0_uop_ldst = _s0_req_T_2_0_uop_ldst; // @[dcache.scala:618:21, :619:21] wire [5:0] _s0_req_T_3_0_uop_lrs1 = _s0_req_T_2_0_uop_lrs1; // @[dcache.scala:618:21, :619:21] wire [5:0] _s0_req_T_3_0_uop_lrs2 = _s0_req_T_2_0_uop_lrs2; // @[dcache.scala:618:21, :619:21] wire [5:0] _s0_req_T_3_0_uop_lrs3 = _s0_req_T_2_0_uop_lrs3; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_dst_rtype = _s0_req_T_2_0_uop_dst_rtype; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_lrs1_rtype = _s0_req_T_2_0_uop_lrs1_rtype; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_lrs2_rtype = _s0_req_T_2_0_uop_lrs2_rtype; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_frs3_en = _s0_req_T_2_0_uop_frs3_en; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fcn_dw = _s0_req_T_2_0_uop_fcn_dw; // @[dcache.scala:618:21, :619:21] wire [4:0] _s0_req_T_3_0_uop_fcn_op = _s0_req_T_2_0_uop_fcn_op; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_fp_val = _s0_req_T_2_0_uop_fp_val; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_fp_rm = _s0_req_T_2_0_uop_fp_rm; // @[dcache.scala:618:21, :619:21] wire [1:0] _s0_req_T_3_0_uop_fp_typ = _s0_req_T_2_0_uop_fp_typ; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_xcpt_pf_if = _s0_req_T_2_0_uop_xcpt_pf_if; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_xcpt_ae_if = _s0_req_T_2_0_uop_xcpt_ae_if; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_xcpt_ma_if = _s0_req_T_2_0_uop_xcpt_ma_if; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_bp_debug_if = _s0_req_T_2_0_uop_bp_debug_if; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_uop_bp_xcpt_if = _s0_req_T_2_0_uop_bp_xcpt_if; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_debug_fsrc = _s0_req_T_2_0_uop_debug_fsrc; // @[dcache.scala:618:21, :619:21] wire [2:0] _s0_req_T_3_0_uop_debug_tsrc = _s0_req_T_2_0_uop_debug_tsrc; // @[dcache.scala:618:21, :619:21] wire [39:0] _s0_req_T_3_0_addr = _s0_req_T_2_0_addr; // @[dcache.scala:618:21, :619:21] wire [63:0] _s0_req_T_3_0_data = _s0_req_T_2_0_data; // @[dcache.scala:618:21, :619:21] wire _s0_req_T_3_0_is_hella = _s0_req_T_2_0_is_hella; // @[dcache.scala:618:21, :619:21] wire [31:0] _s0_req_T_4_0_uop_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_inst; // @[Decoupled.scala:51:35] wire [31:0] _s0_req_T_4_0_uop_debug_inst = prober_fire ? 32'h0 : _s0_req_T_3_0_uop_debug_inst; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_rvc = ~prober_fire & _s0_req_T_3_0_uop_is_rvc; // @[Decoupled.scala:51:35] wire [39:0] _s0_req_T_4_0_uop_debug_pc = prober_fire ? 40'h0 : _s0_req_T_3_0_uop_debug_pc; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iq_type_0 = ~prober_fire & _s0_req_T_3_0_uop_iq_type_0; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iq_type_1 = ~prober_fire & _s0_req_T_3_0_uop_iq_type_1; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iq_type_2 = ~prober_fire & _s0_req_T_3_0_uop_iq_type_2; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iq_type_3 = ~prober_fire & _s0_req_T_3_0_uop_iq_type_3; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_0 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_0; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_1 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_1; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_2 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_2; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_3 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_3; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_4 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_4; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_5 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_5; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_6 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_6; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_7 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_7; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_8 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_8; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fu_code_9 = ~prober_fire & _s0_req_T_3_0_uop_fu_code_9; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iw_issued = ~prober_fire & _s0_req_T_3_0_uop_iw_issued; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iw_issued_partial_agen = ~prober_fire & _s0_req_T_3_0_uop_iw_issued_partial_agen; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iw_issued_partial_dgen = ~prober_fire & _s0_req_T_3_0_uop_iw_issued_partial_dgen; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_iw_p1_speculative_child = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_iw_p1_speculative_child; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_iw_p2_speculative_child = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_iw_p2_speculative_child; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iw_p1_bypass_hint = ~prober_fire & _s0_req_T_3_0_uop_iw_p1_bypass_hint; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iw_p2_bypass_hint = ~prober_fire & _s0_req_T_3_0_uop_iw_p2_bypass_hint; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_iw_p3_bypass_hint = ~prober_fire & _s0_req_T_3_0_uop_iw_p3_bypass_hint; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_dis_col_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_dis_col_sel; // @[Decoupled.scala:51:35] wire [15:0] _s0_req_T_4_0_uop_br_mask = prober_fire ? 16'h0 : _s0_req_T_3_0_uop_br_mask; // @[Decoupled.scala:51:35] wire [3:0] _s0_req_T_4_0_uop_br_tag = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_br_tag; // @[Decoupled.scala:51:35] wire [3:0] _s0_req_T_4_0_uop_br_type = prober_fire ? 4'h0 : _s0_req_T_3_0_uop_br_type; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_sfb = ~prober_fire & _s0_req_T_3_0_uop_is_sfb; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_fence = ~prober_fire & _s0_req_T_3_0_uop_is_fence; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_fencei = ~prober_fire & _s0_req_T_3_0_uop_is_fencei; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_sfence = ~prober_fire & _s0_req_T_3_0_uop_is_sfence; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_amo = ~prober_fire & _s0_req_T_3_0_uop_is_amo; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_eret = ~prober_fire & _s0_req_T_3_0_uop_is_eret; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_sys_pc2epc = ~prober_fire & _s0_req_T_3_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_rocc = ~prober_fire & _s0_req_T_3_0_uop_is_rocc; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_mov = ~prober_fire & _s0_req_T_3_0_uop_is_mov; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_4_0_uop_ftq_idx = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ftq_idx; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_edge_inst = ~prober_fire & _s0_req_T_3_0_uop_edge_inst; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_4_0_uop_pc_lob = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_pc_lob; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_taken = ~prober_fire & _s0_req_T_3_0_uop_taken; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_imm_rename = ~prober_fire & _s0_req_T_3_0_uop_imm_rename; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_imm_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_imm_sel; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_4_0_uop_pimm = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_pimm; // @[Decoupled.scala:51:35] wire [19:0] _s0_req_T_4_0_uop_imm_packed = prober_fire ? 20'h0 : _s0_req_T_3_0_uop_imm_packed; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_op1_sel = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_op1_sel; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_op2_sel = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_op2_sel; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_ldst = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_ldst; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_wen = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_wen; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_ren1 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_ren1; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_ren2 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_ren2; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_ren3 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_ren3; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_swap12 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_swap12; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_swap23 = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_swap23; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_fp_ctrl_typeTagIn = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_fp_ctrl_typeTagIn; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_fp_ctrl_typeTagOut = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_fp_ctrl_typeTagOut; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_fromint = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_fromint; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_toint = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_toint; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_fastpipe = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_fastpipe; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_fma = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_fma; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_div = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_div; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_sqrt = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_sqrt; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_wflags = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_wflags; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_ctrl_vec = ~prober_fire & _s0_req_T_3_0_uop_fp_ctrl_vec; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_4_0_uop_rob_idx = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_rob_idx; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_4_0_uop_ldq_idx = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ldq_idx; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_4_0_uop_stq_idx = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_stq_idx; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_rxq_idx = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_rxq_idx; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_4_0_uop_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_pdst; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_4_0_uop_prs1 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs1; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_4_0_uop_prs2 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs2; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_4_0_uop_prs3 = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_prs3; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_4_0_uop_ppred = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_ppred; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_prs1_busy = ~prober_fire & _s0_req_T_3_0_uop_prs1_busy; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_prs2_busy = ~prober_fire & _s0_req_T_3_0_uop_prs2_busy; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_prs3_busy = ~prober_fire & _s0_req_T_3_0_uop_prs3_busy; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_ppred_busy = ~prober_fire & _s0_req_T_3_0_uop_ppred_busy; // @[Decoupled.scala:51:35] wire [6:0] _s0_req_T_4_0_uop_stale_pdst = prober_fire ? 7'h0 : _s0_req_T_3_0_uop_stale_pdst; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_exception = ~prober_fire & _s0_req_T_3_0_uop_exception; // @[Decoupled.scala:51:35] wire [63:0] _s0_req_T_4_0_uop_exc_cause = prober_fire ? 64'h0 : _s0_req_T_3_0_uop_exc_cause; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_4_0_uop_mem_cmd = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_mem_cmd; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_mem_size = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_mem_size; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_mem_signed = ~prober_fire & _s0_req_T_3_0_uop_mem_signed; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_uses_ldq = ~prober_fire & _s0_req_T_3_0_uop_uses_ldq; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_uses_stq = ~prober_fire & _s0_req_T_3_0_uop_uses_stq; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_is_unique = ~prober_fire & _s0_req_T_3_0_uop_is_unique; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_flush_on_commit = ~prober_fire & _s0_req_T_3_0_uop_flush_on_commit; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_csr_cmd = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_csr_cmd; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_ldst_is_rs1 = ~prober_fire & _s0_req_T_3_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_4_0_uop_ldst = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_ldst; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_4_0_uop_lrs1 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs1; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_4_0_uop_lrs2 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs2; // @[Decoupled.scala:51:35] wire [5:0] _s0_req_T_4_0_uop_lrs3 = prober_fire ? 6'h0 : _s0_req_T_3_0_uop_lrs3; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_dst_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_dst_rtype; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_lrs1_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_lrs2_rtype = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_frs3_en = ~prober_fire & _s0_req_T_3_0_uop_frs3_en; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fcn_dw = ~prober_fire & _s0_req_T_3_0_uop_fcn_dw; // @[Decoupled.scala:51:35] wire [4:0] _s0_req_T_4_0_uop_fcn_op = prober_fire ? 5'h0 : _s0_req_T_3_0_uop_fcn_op; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_fp_val = ~prober_fire & _s0_req_T_3_0_uop_fp_val; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_fp_rm = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_fp_rm; // @[Decoupled.scala:51:35] wire [1:0] _s0_req_T_4_0_uop_fp_typ = prober_fire ? 2'h0 : _s0_req_T_3_0_uop_fp_typ; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_xcpt_pf_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_xcpt_ae_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_xcpt_ma_if = ~prober_fire & _s0_req_T_3_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_bp_debug_if = ~prober_fire & _s0_req_T_3_0_uop_bp_debug_if; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_uop_bp_xcpt_if = ~prober_fire & _s0_req_T_3_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_debug_fsrc = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_debug_fsrc; // @[Decoupled.scala:51:35] wire [2:0] _s0_req_T_4_0_uop_debug_tsrc = prober_fire ? 3'h0 : _s0_req_T_3_0_uop_debug_tsrc; // @[Decoupled.scala:51:35] wire [39:0] _s0_req_T_4_0_addr = prober_fire ? prober_req_0_addr : _s0_req_T_3_0_addr; // @[Decoupled.scala:51:35] wire [63:0] _s0_req_T_4_0_data = prober_fire ? 64'h0 : _s0_req_T_3_0_data; // @[Decoupled.scala:51:35] wire _s0_req_T_4_0_is_hella = ~prober_fire & _s0_req_T_3_0_is_hella; // @[Decoupled.scala:51:35] wire [31:0] _s0_req_T_5_0_uop_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_inst; // @[dcache.scala:563:38, :616:21, :617:21] wire [31:0] _s0_req_T_5_0_uop_debug_inst = wb_fire ? 32'h0 : _s0_req_T_4_0_uop_debug_inst; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_rvc = ~wb_fire & _s0_req_T_4_0_uop_is_rvc; // @[dcache.scala:563:38, :616:21, :617:21] wire [39:0] _s0_req_T_5_0_uop_debug_pc = wb_fire ? 40'h0 : _s0_req_T_4_0_uop_debug_pc; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iq_type_0 = ~wb_fire & _s0_req_T_4_0_uop_iq_type_0; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iq_type_1 = ~wb_fire & _s0_req_T_4_0_uop_iq_type_1; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iq_type_2 = ~wb_fire & _s0_req_T_4_0_uop_iq_type_2; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iq_type_3 = ~wb_fire & _s0_req_T_4_0_uop_iq_type_3; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_0 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_0; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_1 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_1; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_2 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_2; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_3 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_3; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_4 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_4; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_5 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_5; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_6 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_6; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_7 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_7; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_8 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_8; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fu_code_9 = ~wb_fire & _s0_req_T_4_0_uop_fu_code_9; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iw_issued = ~wb_fire & _s0_req_T_4_0_uop_iw_issued; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iw_issued_partial_agen = ~wb_fire & _s0_req_T_4_0_uop_iw_issued_partial_agen; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iw_issued_partial_dgen = ~wb_fire & _s0_req_T_4_0_uop_iw_issued_partial_dgen; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_iw_p1_speculative_child = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_iw_p1_speculative_child; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_iw_p2_speculative_child = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_iw_p2_speculative_child; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iw_p1_bypass_hint = ~wb_fire & _s0_req_T_4_0_uop_iw_p1_bypass_hint; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iw_p2_bypass_hint = ~wb_fire & _s0_req_T_4_0_uop_iw_p2_bypass_hint; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_iw_p3_bypass_hint = ~wb_fire & _s0_req_T_4_0_uop_iw_p3_bypass_hint; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_dis_col_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_dis_col_sel; // @[dcache.scala:563:38, :616:21, :617:21] wire [15:0] _s0_req_T_5_0_uop_br_mask = wb_fire ? 16'h0 : _s0_req_T_4_0_uop_br_mask; // @[dcache.scala:563:38, :616:21, :617:21] wire [3:0] _s0_req_T_5_0_uop_br_tag = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_br_tag; // @[dcache.scala:563:38, :616:21, :617:21] wire [3:0] _s0_req_T_5_0_uop_br_type = wb_fire ? 4'h0 : _s0_req_T_4_0_uop_br_type; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_sfb = ~wb_fire & _s0_req_T_4_0_uop_is_sfb; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_fence = ~wb_fire & _s0_req_T_4_0_uop_is_fence; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_fencei = ~wb_fire & _s0_req_T_4_0_uop_is_fencei; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_sfence = ~wb_fire & _s0_req_T_4_0_uop_is_sfence; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_amo = ~wb_fire & _s0_req_T_4_0_uop_is_amo; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_eret = ~wb_fire & _s0_req_T_4_0_uop_is_eret; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_sys_pc2epc = ~wb_fire & _s0_req_T_4_0_uop_is_sys_pc2epc; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_rocc = ~wb_fire & _s0_req_T_4_0_uop_is_rocc; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_mov = ~wb_fire & _s0_req_T_4_0_uop_is_mov; // @[dcache.scala:563:38, :616:21, :617:21] wire [4:0] _s0_req_T_5_0_uop_ftq_idx = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ftq_idx; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_edge_inst = ~wb_fire & _s0_req_T_4_0_uop_edge_inst; // @[dcache.scala:563:38, :616:21, :617:21] wire [5:0] _s0_req_T_5_0_uop_pc_lob = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_pc_lob; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_taken = ~wb_fire & _s0_req_T_4_0_uop_taken; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_imm_rename = ~wb_fire & _s0_req_T_4_0_uop_imm_rename; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_imm_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_imm_sel; // @[dcache.scala:563:38, :616:21, :617:21] wire [4:0] _s0_req_T_5_0_uop_pimm = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_pimm; // @[dcache.scala:563:38, :616:21, :617:21] wire [19:0] _s0_req_T_5_0_uop_imm_packed = wb_fire ? 20'h0 : _s0_req_T_4_0_uop_imm_packed; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_op1_sel = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_op1_sel; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_op2_sel = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_op2_sel; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_ldst = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_ldst; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_wen = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_wen; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_ren1 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_ren1; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_ren2 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_ren2; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_ren3 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_ren3; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_swap12 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_swap12; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_swap23 = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_swap23; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_fp_ctrl_typeTagIn = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_fp_ctrl_typeTagOut = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_fromint = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_fromint; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_toint = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_toint; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_fastpipe = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_fma = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_fma; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_div = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_div; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_sqrt = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_sqrt; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_wflags = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_wflags; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_ctrl_vec = ~wb_fire & _s0_req_T_4_0_uop_fp_ctrl_vec; // @[dcache.scala:563:38, :616:21, :617:21] wire [6:0] _s0_req_T_5_0_uop_rob_idx = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_rob_idx; // @[dcache.scala:563:38, :616:21, :617:21] wire [4:0] _s0_req_T_5_0_uop_ldq_idx = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ldq_idx; // @[dcache.scala:563:38, :616:21, :617:21] wire [4:0] _s0_req_T_5_0_uop_stq_idx = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_stq_idx; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_rxq_idx = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_rxq_idx; // @[dcache.scala:563:38, :616:21, :617:21] wire [6:0] _s0_req_T_5_0_uop_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_pdst; // @[dcache.scala:563:38, :616:21, :617:21] wire [6:0] _s0_req_T_5_0_uop_prs1 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs1; // @[dcache.scala:563:38, :616:21, :617:21] wire [6:0] _s0_req_T_5_0_uop_prs2 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs2; // @[dcache.scala:563:38, :616:21, :617:21] wire [6:0] _s0_req_T_5_0_uop_prs3 = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_prs3; // @[dcache.scala:563:38, :616:21, :617:21] wire [4:0] _s0_req_T_5_0_uop_ppred = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_ppred; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_prs1_busy = ~wb_fire & _s0_req_T_4_0_uop_prs1_busy; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_prs2_busy = ~wb_fire & _s0_req_T_4_0_uop_prs2_busy; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_prs3_busy = ~wb_fire & _s0_req_T_4_0_uop_prs3_busy; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_ppred_busy = ~wb_fire & _s0_req_T_4_0_uop_ppred_busy; // @[dcache.scala:563:38, :616:21, :617:21] wire [6:0] _s0_req_T_5_0_uop_stale_pdst = wb_fire ? 7'h0 : _s0_req_T_4_0_uop_stale_pdst; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_exception = ~wb_fire & _s0_req_T_4_0_uop_exception; // @[dcache.scala:563:38, :616:21, :617:21] wire [63:0] _s0_req_T_5_0_uop_exc_cause = wb_fire ? 64'h0 : _s0_req_T_4_0_uop_exc_cause; // @[dcache.scala:563:38, :616:21, :617:21] wire [4:0] _s0_req_T_5_0_uop_mem_cmd = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_mem_cmd; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_mem_size = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_mem_size; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_mem_signed = ~wb_fire & _s0_req_T_4_0_uop_mem_signed; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_uses_ldq = ~wb_fire & _s0_req_T_4_0_uop_uses_ldq; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_uses_stq = ~wb_fire & _s0_req_T_4_0_uop_uses_stq; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_is_unique = ~wb_fire & _s0_req_T_4_0_uop_is_unique; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_flush_on_commit = ~wb_fire & _s0_req_T_4_0_uop_flush_on_commit; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_csr_cmd = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_csr_cmd; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_ldst_is_rs1 = ~wb_fire & _s0_req_T_4_0_uop_ldst_is_rs1; // @[dcache.scala:563:38, :616:21, :617:21] wire [5:0] _s0_req_T_5_0_uop_ldst = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_ldst; // @[dcache.scala:563:38, :616:21, :617:21] wire [5:0] _s0_req_T_5_0_uop_lrs1 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs1; // @[dcache.scala:563:38, :616:21, :617:21] wire [5:0] _s0_req_T_5_0_uop_lrs2 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs2; // @[dcache.scala:563:38, :616:21, :617:21] wire [5:0] _s0_req_T_5_0_uop_lrs3 = wb_fire ? 6'h0 : _s0_req_T_4_0_uop_lrs3; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_dst_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_dst_rtype; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_lrs1_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs1_rtype; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_lrs2_rtype = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_lrs2_rtype; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_frs3_en = ~wb_fire & _s0_req_T_4_0_uop_frs3_en; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fcn_dw = ~wb_fire & _s0_req_T_4_0_uop_fcn_dw; // @[dcache.scala:563:38, :616:21, :617:21] wire [4:0] _s0_req_T_5_0_uop_fcn_op = wb_fire ? 5'h0 : _s0_req_T_4_0_uop_fcn_op; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_fp_val = ~wb_fire & _s0_req_T_4_0_uop_fp_val; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_fp_rm = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_fp_rm; // @[dcache.scala:563:38, :616:21, :617:21] wire [1:0] _s0_req_T_5_0_uop_fp_typ = wb_fire ? 2'h0 : _s0_req_T_4_0_uop_fp_typ; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_xcpt_pf_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_pf_if; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_xcpt_ae_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ae_if; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_xcpt_ma_if = ~wb_fire & _s0_req_T_4_0_uop_xcpt_ma_if; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_bp_debug_if = ~wb_fire & _s0_req_T_4_0_uop_bp_debug_if; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_uop_bp_xcpt_if = ~wb_fire & _s0_req_T_4_0_uop_bp_xcpt_if; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_debug_fsrc = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_debug_fsrc; // @[dcache.scala:563:38, :616:21, :617:21] wire [2:0] _s0_req_T_5_0_uop_debug_tsrc = wb_fire ? 3'h0 : _s0_req_T_4_0_uop_debug_tsrc; // @[dcache.scala:563:38, :616:21, :617:21] wire [39:0] _s0_req_T_5_0_addr = wb_fire ? wb_req_0_addr : _s0_req_T_4_0_addr; // @[dcache.scala:563:38, :564:20, :616:21, :617:21] wire [63:0] _s0_req_T_5_0_data = wb_fire ? 64'h0 : _s0_req_T_4_0_data; // @[dcache.scala:563:38, :616:21, :617:21] wire _s0_req_T_5_0_is_hella = ~wb_fire & _s0_req_T_4_0_is_hella; // @[dcache.scala:563:38, :616:21, :617:21] wire [31:0] s0_req_0_uop_inst = _s0_req_T ? _s0_req_WIRE_0_uop_inst : _s0_req_T_5_0_uop_inst; // @[Decoupled.scala:51:35] wire [31:0] s0_req_0_uop_debug_inst = _s0_req_T ? _s0_req_WIRE_0_uop_debug_inst : _s0_req_T_5_0_uop_debug_inst; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_rvc = _s0_req_T ? _s0_req_WIRE_0_uop_is_rvc : _s0_req_T_5_0_uop_is_rvc; // @[Decoupled.scala:51:35] wire [39:0] s0_req_0_uop_debug_pc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_pc : _s0_req_T_5_0_uop_debug_pc; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iq_type_0 = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type_0 : _s0_req_T_5_0_uop_iq_type_0; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iq_type_1 = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type_1 : _s0_req_T_5_0_uop_iq_type_1; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iq_type_2 = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type_2 : _s0_req_T_5_0_uop_iq_type_2; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iq_type_3 = _s0_req_T ? _s0_req_WIRE_0_uop_iq_type_3 : _s0_req_T_5_0_uop_iq_type_3; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_0 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_0 : _s0_req_T_5_0_uop_fu_code_0; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_1 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_1 : _s0_req_T_5_0_uop_fu_code_1; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_2 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_2 : _s0_req_T_5_0_uop_fu_code_2; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_3 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_3 : _s0_req_T_5_0_uop_fu_code_3; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_4 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_4 : _s0_req_T_5_0_uop_fu_code_4; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_5 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_5 : _s0_req_T_5_0_uop_fu_code_5; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_6 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_6 : _s0_req_T_5_0_uop_fu_code_6; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_7 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_7 : _s0_req_T_5_0_uop_fu_code_7; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_8 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_8 : _s0_req_T_5_0_uop_fu_code_8; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fu_code_9 = _s0_req_T ? _s0_req_WIRE_0_uop_fu_code_9 : _s0_req_T_5_0_uop_fu_code_9; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iw_issued = _s0_req_T ? _s0_req_WIRE_0_uop_iw_issued : _s0_req_T_5_0_uop_iw_issued; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iw_issued_partial_agen = _s0_req_T ? _s0_req_WIRE_0_uop_iw_issued_partial_agen : _s0_req_T_5_0_uop_iw_issued_partial_agen; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iw_issued_partial_dgen = _s0_req_T ? _s0_req_WIRE_0_uop_iw_issued_partial_dgen : _s0_req_T_5_0_uop_iw_issued_partial_dgen; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_iw_p1_speculative_child = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p1_speculative_child : _s0_req_T_5_0_uop_iw_p1_speculative_child; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_iw_p2_speculative_child = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p2_speculative_child : _s0_req_T_5_0_uop_iw_p2_speculative_child; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iw_p1_bypass_hint = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p1_bypass_hint : _s0_req_T_5_0_uop_iw_p1_bypass_hint; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iw_p2_bypass_hint = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p2_bypass_hint : _s0_req_T_5_0_uop_iw_p2_bypass_hint; // @[Decoupled.scala:51:35] wire s0_req_0_uop_iw_p3_bypass_hint = _s0_req_T ? _s0_req_WIRE_0_uop_iw_p3_bypass_hint : _s0_req_T_5_0_uop_iw_p3_bypass_hint; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_dis_col_sel = _s0_req_T ? _s0_req_WIRE_0_uop_dis_col_sel : _s0_req_T_5_0_uop_dis_col_sel; // @[Decoupled.scala:51:35] wire [15:0] s0_req_0_uop_br_mask = _s0_req_T ? _s0_req_WIRE_0_uop_br_mask : _s0_req_T_5_0_uop_br_mask; // @[Decoupled.scala:51:35] wire [3:0] s0_req_0_uop_br_tag = _s0_req_T ? _s0_req_WIRE_0_uop_br_tag : _s0_req_T_5_0_uop_br_tag; // @[Decoupled.scala:51:35] wire [3:0] s0_req_0_uop_br_type = _s0_req_T ? _s0_req_WIRE_0_uop_br_type : _s0_req_T_5_0_uop_br_type; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_sfb = _s0_req_T ? _s0_req_WIRE_0_uop_is_sfb : _s0_req_T_5_0_uop_is_sfb; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_fence = _s0_req_T ? _s0_req_WIRE_0_uop_is_fence : _s0_req_T_5_0_uop_is_fence; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_fencei = _s0_req_T ? _s0_req_WIRE_0_uop_is_fencei : _s0_req_T_5_0_uop_is_fencei; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_sfence = _s0_req_T ? _s0_req_WIRE_0_uop_is_sfence : _s0_req_T_5_0_uop_is_sfence; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_amo = _s0_req_T ? _s0_req_WIRE_0_uop_is_amo : _s0_req_T_5_0_uop_is_amo; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_eret = _s0_req_T ? _s0_req_WIRE_0_uop_is_eret : _s0_req_T_5_0_uop_is_eret; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_sys_pc2epc = _s0_req_T ? _s0_req_WIRE_0_uop_is_sys_pc2epc : _s0_req_T_5_0_uop_is_sys_pc2epc; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_rocc = _s0_req_T ? _s0_req_WIRE_0_uop_is_rocc : _s0_req_T_5_0_uop_is_rocc; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_mov = _s0_req_T ? _s0_req_WIRE_0_uop_is_mov : _s0_req_T_5_0_uop_is_mov; // @[Decoupled.scala:51:35] wire [4:0] s0_req_0_uop_ftq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ftq_idx : _s0_req_T_5_0_uop_ftq_idx; // @[Decoupled.scala:51:35] wire s0_req_0_uop_edge_inst = _s0_req_T ? _s0_req_WIRE_0_uop_edge_inst : _s0_req_T_5_0_uop_edge_inst; // @[Decoupled.scala:51:35] wire [5:0] s0_req_0_uop_pc_lob = _s0_req_T ? _s0_req_WIRE_0_uop_pc_lob : _s0_req_T_5_0_uop_pc_lob; // @[Decoupled.scala:51:35] wire s0_req_0_uop_taken = _s0_req_T ? _s0_req_WIRE_0_uop_taken : _s0_req_T_5_0_uop_taken; // @[Decoupled.scala:51:35] wire s0_req_0_uop_imm_rename = _s0_req_T ? _s0_req_WIRE_0_uop_imm_rename : _s0_req_T_5_0_uop_imm_rename; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_imm_sel = _s0_req_T ? _s0_req_WIRE_0_uop_imm_sel : _s0_req_T_5_0_uop_imm_sel; // @[Decoupled.scala:51:35] wire [4:0] s0_req_0_uop_pimm = _s0_req_T ? _s0_req_WIRE_0_uop_pimm : _s0_req_T_5_0_uop_pimm; // @[Decoupled.scala:51:35] wire [19:0] s0_req_0_uop_imm_packed = _s0_req_T ? _s0_req_WIRE_0_uop_imm_packed : _s0_req_T_5_0_uop_imm_packed; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_op1_sel = _s0_req_T ? _s0_req_WIRE_0_uop_op1_sel : _s0_req_T_5_0_uop_op1_sel; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_op2_sel = _s0_req_T ? _s0_req_WIRE_0_uop_op2_sel : _s0_req_T_5_0_uop_op2_sel; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_ldst = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_ldst : _s0_req_T_5_0_uop_fp_ctrl_ldst; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_wen = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_wen : _s0_req_T_5_0_uop_fp_ctrl_wen; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_ren1 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_ren1 : _s0_req_T_5_0_uop_fp_ctrl_ren1; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_ren2 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_ren2 : _s0_req_T_5_0_uop_fp_ctrl_ren2; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_ren3 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_ren3 : _s0_req_T_5_0_uop_fp_ctrl_ren3; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_swap12 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_swap12 : _s0_req_T_5_0_uop_fp_ctrl_swap12; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_swap23 = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_swap23 : _s0_req_T_5_0_uop_fp_ctrl_swap23; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_fp_ctrl_typeTagIn = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_typeTagIn : _s0_req_T_5_0_uop_fp_ctrl_typeTagIn; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_fp_ctrl_typeTagOut = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_typeTagOut : _s0_req_T_5_0_uop_fp_ctrl_typeTagOut; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_fromint = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_fromint : _s0_req_T_5_0_uop_fp_ctrl_fromint; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_toint = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_toint : _s0_req_T_5_0_uop_fp_ctrl_toint; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_fastpipe = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_fastpipe : _s0_req_T_5_0_uop_fp_ctrl_fastpipe; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_fma = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_fma : _s0_req_T_5_0_uop_fp_ctrl_fma; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_div = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_div : _s0_req_T_5_0_uop_fp_ctrl_div; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_sqrt = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_sqrt : _s0_req_T_5_0_uop_fp_ctrl_sqrt; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_wflags = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_wflags : _s0_req_T_5_0_uop_fp_ctrl_wflags; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_ctrl_vec = _s0_req_T ? _s0_req_WIRE_0_uop_fp_ctrl_vec : _s0_req_T_5_0_uop_fp_ctrl_vec; // @[Decoupled.scala:51:35] wire [6:0] s0_req_0_uop_rob_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rob_idx : _s0_req_T_5_0_uop_rob_idx; // @[Decoupled.scala:51:35] wire [4:0] s0_req_0_uop_ldq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_ldq_idx : _s0_req_T_5_0_uop_ldq_idx; // @[Decoupled.scala:51:35] wire [4:0] s0_req_0_uop_stq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_stq_idx : _s0_req_T_5_0_uop_stq_idx; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_rxq_idx = _s0_req_T ? _s0_req_WIRE_0_uop_rxq_idx : _s0_req_T_5_0_uop_rxq_idx; // @[Decoupled.scala:51:35] wire [6:0] s0_req_0_uop_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_pdst : _s0_req_T_5_0_uop_pdst; // @[Decoupled.scala:51:35] wire [6:0] s0_req_0_uop_prs1 = _s0_req_T ? _s0_req_WIRE_0_uop_prs1 : _s0_req_T_5_0_uop_prs1; // @[Decoupled.scala:51:35] wire [6:0] s0_req_0_uop_prs2 = _s0_req_T ? _s0_req_WIRE_0_uop_prs2 : _s0_req_T_5_0_uop_prs2; // @[Decoupled.scala:51:35] wire [6:0] s0_req_0_uop_prs3 = _s0_req_T ? _s0_req_WIRE_0_uop_prs3 : _s0_req_T_5_0_uop_prs3; // @[Decoupled.scala:51:35] wire [4:0] s0_req_0_uop_ppred = _s0_req_T ? _s0_req_WIRE_0_uop_ppred : _s0_req_T_5_0_uop_ppred; // @[Decoupled.scala:51:35] wire s0_req_0_uop_prs1_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs1_busy : _s0_req_T_5_0_uop_prs1_busy; // @[Decoupled.scala:51:35] wire s0_req_0_uop_prs2_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs2_busy : _s0_req_T_5_0_uop_prs2_busy; // @[Decoupled.scala:51:35] wire s0_req_0_uop_prs3_busy = _s0_req_T ? _s0_req_WIRE_0_uop_prs3_busy : _s0_req_T_5_0_uop_prs3_busy; // @[Decoupled.scala:51:35] wire s0_req_0_uop_ppred_busy = _s0_req_T ? _s0_req_WIRE_0_uop_ppred_busy : _s0_req_T_5_0_uop_ppred_busy; // @[Decoupled.scala:51:35] wire [6:0] s0_req_0_uop_stale_pdst = _s0_req_T ? _s0_req_WIRE_0_uop_stale_pdst : _s0_req_T_5_0_uop_stale_pdst; // @[Decoupled.scala:51:35] wire s0_req_0_uop_exception = _s0_req_T ? _s0_req_WIRE_0_uop_exception : _s0_req_T_5_0_uop_exception; // @[Decoupled.scala:51:35] wire [63:0] s0_req_0_uop_exc_cause = _s0_req_T ? _s0_req_WIRE_0_uop_exc_cause : _s0_req_T_5_0_uop_exc_cause; // @[Decoupled.scala:51:35] wire [4:0] s0_req_0_uop_mem_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_mem_cmd : _s0_req_T_5_0_uop_mem_cmd; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_mem_size = _s0_req_T ? _s0_req_WIRE_0_uop_mem_size : _s0_req_T_5_0_uop_mem_size; // @[Decoupled.scala:51:35] wire s0_req_0_uop_mem_signed = _s0_req_T ? _s0_req_WIRE_0_uop_mem_signed : _s0_req_T_5_0_uop_mem_signed; // @[Decoupled.scala:51:35] wire s0_req_0_uop_uses_ldq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_ldq : _s0_req_T_5_0_uop_uses_ldq; // @[Decoupled.scala:51:35] wire s0_req_0_uop_uses_stq = _s0_req_T ? _s0_req_WIRE_0_uop_uses_stq : _s0_req_T_5_0_uop_uses_stq; // @[Decoupled.scala:51:35] wire s0_req_0_uop_is_unique = _s0_req_T ? _s0_req_WIRE_0_uop_is_unique : _s0_req_T_5_0_uop_is_unique; // @[Decoupled.scala:51:35] wire s0_req_0_uop_flush_on_commit = _s0_req_T ? _s0_req_WIRE_0_uop_flush_on_commit : _s0_req_T_5_0_uop_flush_on_commit; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_csr_cmd = _s0_req_T ? _s0_req_WIRE_0_uop_csr_cmd : _s0_req_T_5_0_uop_csr_cmd; // @[Decoupled.scala:51:35] wire s0_req_0_uop_ldst_is_rs1 = _s0_req_T ? _s0_req_WIRE_0_uop_ldst_is_rs1 : _s0_req_T_5_0_uop_ldst_is_rs1; // @[Decoupled.scala:51:35] wire [5:0] s0_req_0_uop_ldst = _s0_req_T ? _s0_req_WIRE_0_uop_ldst : _s0_req_T_5_0_uop_ldst; // @[Decoupled.scala:51:35] wire [5:0] s0_req_0_uop_lrs1 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1 : _s0_req_T_5_0_uop_lrs1; // @[Decoupled.scala:51:35] wire [5:0] s0_req_0_uop_lrs2 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2 : _s0_req_T_5_0_uop_lrs2; // @[Decoupled.scala:51:35] wire [5:0] s0_req_0_uop_lrs3 = _s0_req_T ? _s0_req_WIRE_0_uop_lrs3 : _s0_req_T_5_0_uop_lrs3; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_dst_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_dst_rtype : _s0_req_T_5_0_uop_dst_rtype; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_lrs1_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs1_rtype : _s0_req_T_5_0_uop_lrs1_rtype; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_lrs2_rtype = _s0_req_T ? _s0_req_WIRE_0_uop_lrs2_rtype : _s0_req_T_5_0_uop_lrs2_rtype; // @[Decoupled.scala:51:35] wire s0_req_0_uop_frs3_en = _s0_req_T ? _s0_req_WIRE_0_uop_frs3_en : _s0_req_T_5_0_uop_frs3_en; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fcn_dw = _s0_req_T ? _s0_req_WIRE_0_uop_fcn_dw : _s0_req_T_5_0_uop_fcn_dw; // @[Decoupled.scala:51:35] wire [4:0] s0_req_0_uop_fcn_op = _s0_req_T ? _s0_req_WIRE_0_uop_fcn_op : _s0_req_T_5_0_uop_fcn_op; // @[Decoupled.scala:51:35] wire s0_req_0_uop_fp_val = _s0_req_T ? _s0_req_WIRE_0_uop_fp_val : _s0_req_T_5_0_uop_fp_val; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_fp_rm = _s0_req_T ? _s0_req_WIRE_0_uop_fp_rm : _s0_req_T_5_0_uop_fp_rm; // @[Decoupled.scala:51:35] wire [1:0] s0_req_0_uop_fp_typ = _s0_req_T ? _s0_req_WIRE_0_uop_fp_typ : _s0_req_T_5_0_uop_fp_typ; // @[Decoupled.scala:51:35] wire s0_req_0_uop_xcpt_pf_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_pf_if : _s0_req_T_5_0_uop_xcpt_pf_if; // @[Decoupled.scala:51:35] wire s0_req_0_uop_xcpt_ae_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ae_if : _s0_req_T_5_0_uop_xcpt_ae_if; // @[Decoupled.scala:51:35] wire s0_req_0_uop_xcpt_ma_if = _s0_req_T ? _s0_req_WIRE_0_uop_xcpt_ma_if : _s0_req_T_5_0_uop_xcpt_ma_if; // @[Decoupled.scala:51:35] wire s0_req_0_uop_bp_debug_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_debug_if : _s0_req_T_5_0_uop_bp_debug_if; // @[Decoupled.scala:51:35] wire s0_req_0_uop_bp_xcpt_if = _s0_req_T ? _s0_req_WIRE_0_uop_bp_xcpt_if : _s0_req_T_5_0_uop_bp_xcpt_if; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_debug_fsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_fsrc : _s0_req_T_5_0_uop_debug_fsrc; // @[Decoupled.scala:51:35] wire [2:0] s0_req_0_uop_debug_tsrc = _s0_req_T ? _s0_req_WIRE_0_uop_debug_tsrc : _s0_req_T_5_0_uop_debug_tsrc; // @[Decoupled.scala:51:35] wire [39:0] s0_req_0_addr = _s0_req_T ? _s0_req_WIRE_0_addr : _s0_req_T_5_0_addr; // @[Decoupled.scala:51:35] wire [63:0] s0_req_0_data = _s0_req_T ? _s0_req_WIRE_0_data : _s0_req_T_5_0_data; // @[Decoupled.scala:51:35] wire s0_req_0_is_hella = _s0_req_T ? _s0_req_WIRE_0_is_hella : _s0_req_T_5_0_is_hella; // @[Decoupled.scala:51:35] wire [2:0] _s0_type_T_2 = _s0_type_T_1 ? 3'h3 : 3'h0; // @[Decoupled.scala:51:35] wire [2:0] _s0_type_T_3 = _s0_type_T_2; // @[dcache.scala:624:21, :625:21] wire [2:0] _s0_type_T_4 = prober_fire ? 3'h1 : _s0_type_T_3; // @[Decoupled.scala:51:35] wire [2:0] _s0_type_T_5 = wb_fire ? 3'h2 : _s0_type_T_4; // @[dcache.scala:563:38, :622:21, :623:21] wire [2:0] s0_type = _s0_type_T ? 3'h4 : _s0_type_T_5; // @[Decoupled.scala:51:35] wire _s0_send_resp_or_nack_T_2 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_3 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_4 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_5 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_6 = _s0_send_resp_or_nack_T_2 | _s0_send_resp_or_nack_T_3; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_7 = _s0_send_resp_or_nack_T_6 | _s0_send_resp_or_nack_T_4; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_8 = _s0_send_resp_or_nack_T_7 | _s0_send_resp_or_nack_T_5; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_9 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_10 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_11 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_12 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_13 = _s0_send_resp_or_nack_T_9 | _s0_send_resp_or_nack_T_10; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_14 = _s0_send_resp_or_nack_T_13 | _s0_send_resp_or_nack_T_11; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_15 = _s0_send_resp_or_nack_T_14 | _s0_send_resp_or_nack_T_12; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_16 = _mshrs_io_replay_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_17 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_18 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_19 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_20 = _mshrs_io_replay_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _s0_send_resp_or_nack_T_21 = _s0_send_resp_or_nack_T_16 | _s0_send_resp_or_nack_T_17; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_22 = _s0_send_resp_or_nack_T_21 | _s0_send_resp_or_nack_T_18; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_23 = _s0_send_resp_or_nack_T_22 | _s0_send_resp_or_nack_T_19; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_24 = _s0_send_resp_or_nack_T_23 | _s0_send_resp_or_nack_T_20; // @[package.scala:16:47, :81:59] wire _s0_send_resp_or_nack_T_25 = _s0_send_resp_or_nack_T_15 | _s0_send_resp_or_nack_T_24; // @[package.scala:81:59] wire _s0_send_resp_or_nack_T_26 = _s0_send_resp_or_nack_T_8 | _s0_send_resp_or_nack_T_25; // @[package.scala:81:59] wire _s0_send_resp_or_nack_T_27 = _s0_send_resp_or_nack_T_1 & _s0_send_resp_or_nack_T_26; // @[Decoupled.scala:51:35] wire _s0_send_resp_or_nack_T_28 = _s0_send_resp_or_nack_T_27; // @[dcache.scala:630:{16,38}] wire _s0_send_resp_or_nack_T_29 = _s0_send_resp_or_nack_T_28; // @[dcache.scala:630:{16,117}] wire _s0_send_resp_or_nack_WIRE_0 = _s0_send_resp_or_nack_T_29; // @[dcache.scala:630:{12,117}] wire s0_send_resp_or_nack_0 = _s0_send_resp_or_nack_T ? s0_valid_0 : _s0_send_resp_or_nack_WIRE_0; // @[Decoupled.scala:51:35] reg [31:0] s1_req_0_uop_inst; // @[dcache.scala:633:32] reg [31:0] s1_req_0_uop_debug_inst; // @[dcache.scala:633:32] reg s1_req_0_uop_is_rvc; // @[dcache.scala:633:32] reg [39:0] s1_req_0_uop_debug_pc; // @[dcache.scala:633:32] reg s1_req_0_uop_iq_type_0; // @[dcache.scala:633:32] reg s1_req_0_uop_iq_type_1; // @[dcache.scala:633:32] reg s1_req_0_uop_iq_type_2; // @[dcache.scala:633:32] reg s1_req_0_uop_iq_type_3; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_0; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_1; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_2; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_3; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_4; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_5; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_6; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_7; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_8; // @[dcache.scala:633:32] reg s1_req_0_uop_fu_code_9; // @[dcache.scala:633:32] reg s1_req_0_uop_iw_issued; // @[dcache.scala:633:32] reg s1_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:633:32] reg s1_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:633:32] reg s1_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:633:32] reg s1_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:633:32] reg s1_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_dis_col_sel; // @[dcache.scala:633:32] reg [15:0] s1_req_0_uop_br_mask; // @[dcache.scala:633:32] reg [3:0] s1_req_0_uop_br_tag; // @[dcache.scala:633:32] reg [3:0] s1_req_0_uop_br_type; // @[dcache.scala:633:32] reg s1_req_0_uop_is_sfb; // @[dcache.scala:633:32] reg s1_req_0_uop_is_fence; // @[dcache.scala:633:32] reg s1_req_0_uop_is_fencei; // @[dcache.scala:633:32] reg s1_req_0_uop_is_sfence; // @[dcache.scala:633:32] reg s1_req_0_uop_is_amo; // @[dcache.scala:633:32] reg s1_req_0_uop_is_eret; // @[dcache.scala:633:32] reg s1_req_0_uop_is_sys_pc2epc; // @[dcache.scala:633:32] reg s1_req_0_uop_is_rocc; // @[dcache.scala:633:32] reg s1_req_0_uop_is_mov; // @[dcache.scala:633:32] reg [4:0] s1_req_0_uop_ftq_idx; // @[dcache.scala:633:32] reg s1_req_0_uop_edge_inst; // @[dcache.scala:633:32] reg [5:0] s1_req_0_uop_pc_lob; // @[dcache.scala:633:32] reg s1_req_0_uop_taken; // @[dcache.scala:633:32] reg s1_req_0_uop_imm_rename; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_imm_sel; // @[dcache.scala:633:32] reg [4:0] s1_req_0_uop_pimm; // @[dcache.scala:633:32] reg [19:0] s1_req_0_uop_imm_packed; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_op1_sel; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_op2_sel; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_wen; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_toint; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_fma; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_div; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_ctrl_vec; // @[dcache.scala:633:32] reg [6:0] s1_req_0_uop_rob_idx; // @[dcache.scala:633:32] reg [4:0] s1_req_0_uop_ldq_idx; // @[dcache.scala:633:32] reg [4:0] s1_req_0_uop_stq_idx; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_rxq_idx; // @[dcache.scala:633:32] reg [6:0] s1_req_0_uop_pdst; // @[dcache.scala:633:32] reg [6:0] s1_req_0_uop_prs1; // @[dcache.scala:633:32] reg [6:0] s1_req_0_uop_prs2; // @[dcache.scala:633:32] reg [6:0] s1_req_0_uop_prs3; // @[dcache.scala:633:32] reg [4:0] s1_req_0_uop_ppred; // @[dcache.scala:633:32] reg s1_req_0_uop_prs1_busy; // @[dcache.scala:633:32] reg s1_req_0_uop_prs2_busy; // @[dcache.scala:633:32] reg s1_req_0_uop_prs3_busy; // @[dcache.scala:633:32] reg s1_req_0_uop_ppred_busy; // @[dcache.scala:633:32] reg [6:0] s1_req_0_uop_stale_pdst; // @[dcache.scala:633:32] reg s1_req_0_uop_exception; // @[dcache.scala:633:32] reg [63:0] s1_req_0_uop_exc_cause; // @[dcache.scala:633:32] reg [4:0] s1_req_0_uop_mem_cmd; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_mem_size; // @[dcache.scala:633:32] reg s1_req_0_uop_mem_signed; // @[dcache.scala:633:32] reg s1_req_0_uop_uses_ldq; // @[dcache.scala:633:32] reg s1_req_0_uop_uses_stq; // @[dcache.scala:633:32] reg s1_req_0_uop_is_unique; // @[dcache.scala:633:32] reg s1_req_0_uop_flush_on_commit; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_csr_cmd; // @[dcache.scala:633:32] reg s1_req_0_uop_ldst_is_rs1; // @[dcache.scala:633:32] reg [5:0] s1_req_0_uop_ldst; // @[dcache.scala:633:32] reg [5:0] s1_req_0_uop_lrs1; // @[dcache.scala:633:32] reg [5:0] s1_req_0_uop_lrs2; // @[dcache.scala:633:32] reg [5:0] s1_req_0_uop_lrs3; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_dst_rtype; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_lrs1_rtype; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_lrs2_rtype; // @[dcache.scala:633:32] reg s1_req_0_uop_frs3_en; // @[dcache.scala:633:32] reg s1_req_0_uop_fcn_dw; // @[dcache.scala:633:32] reg [4:0] s1_req_0_uop_fcn_op; // @[dcache.scala:633:32] reg s1_req_0_uop_fp_val; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_fp_rm; // @[dcache.scala:633:32] reg [1:0] s1_req_0_uop_fp_typ; // @[dcache.scala:633:32] reg s1_req_0_uop_xcpt_pf_if; // @[dcache.scala:633:32] reg s1_req_0_uop_xcpt_ae_if; // @[dcache.scala:633:32] reg s1_req_0_uop_xcpt_ma_if; // @[dcache.scala:633:32] reg s1_req_0_uop_bp_debug_if; // @[dcache.scala:633:32] reg s1_req_0_uop_bp_xcpt_if; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_debug_fsrc; // @[dcache.scala:633:32] reg [2:0] s1_req_0_uop_debug_tsrc; // @[dcache.scala:633:32] reg [39:0] s1_req_0_addr; // @[dcache.scala:633:32] reg [63:0] s1_req_0_data; // @[dcache.scala:633:32] reg s1_req_0_is_hella; // @[dcache.scala:633:32] wire [15:0] _s1_req_0_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] wire [15:0] _s1_req_0_uop_br_mask_T_1 = s0_req_0_uop_br_mask & _s1_req_0_uop_br_mask_T; // @[util.scala:93:{25,27}] wire _s2_store_failed_T_2; // @[dcache.scala:787:67] wire s2_store_failed; // @[dcache.scala:636:29] wire [15:0] _s1_valid_T = io_lsu_brupdate_b1_mispredict_mask_0 & s0_req_0_uop_br_mask; // @[util.scala:126:51] wire _s1_valid_T_1 = |_s1_valid_T; // @[util.scala:126:{51,59}] wire _s1_valid_T_2 = _s1_valid_T_1; // @[util.scala:61:61, :126:59] wire _s1_valid_T_3 = ~_s1_valid_T_2; // @[util.scala:61:61] wire _s1_valid_T_4 = s0_valid_0 & _s1_valid_T_3; // @[dcache.scala:612:21, :638:74, :639:26] wire _s1_valid_T_5 = io_lsu_exception_0 & s0_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :615:21, :640:45] wire _s1_valid_T_6 = ~_s1_valid_T_5; // @[dcache.scala:640:{26,45}] wire _s1_valid_T_7 = _s1_valid_T_4 & _s1_valid_T_6; // @[dcache.scala:638:74, :639:85, :640:26] wire _s1_valid_T_9 = s2_store_failed & _s1_valid_T_8; // @[Decoupled.scala:51:35] wire _s1_valid_T_10 = _s1_valid_T_9 & s0_req_0_uop_uses_stq; // @[dcache.scala:615:21, :641:{44,63}] wire _s1_valid_T_11 = ~_s1_valid_T_10; // @[dcache.scala:641:{26,63}] wire _s1_valid_T_12 = _s1_valid_T_7 & _s1_valid_T_11; // @[dcache.scala:639:85, :640:74, :641:26] reg s1_valid_REG; // @[dcache.scala:638:25] wire s1_valid_0 = s1_valid_REG; // @[dcache.scala:454:49, :638:25] reg REG; // @[dcache.scala:645:43] reg REG_1; // @[dcache.scala:645:72] wire [5:0] _s1_nack_T = s1_req_0_addr[11:6]; // @[dcache.scala:633:32, :647:43] wire [5:0] _s1_wb_idx_matches_T = s1_req_0_addr[11:6]; // @[dcache.scala:633:32, :647:43, :664:52] wire _s1_nack_T_1 = _s1_nack_T == _prober_io_meta_write_bits_idx; // @[dcache.scala:459:22, :647:{43,59}] wire _s1_nack_T_2 = ~_prober_io_req_ready; // @[dcache.scala:459:22, :647:96] wire s1_nack_0 = _s1_nack_T_1 & _s1_nack_T_2; // @[dcache.scala:647:{59,93,96}] wire _s2_nack_hit_WIRE_0 = s1_nack_0; // @[dcache.scala:647:93, :760:39] reg s1_send_resp_or_nack_0; // @[dcache.scala:648:37] reg [2:0] s1_type; // @[dcache.scala:649:32] reg [7:0] s1_mshr_meta_read_way_en; // @[dcache.scala:651:41] reg [7:0] s1_replay_way_en; // @[dcache.scala:652:41] reg [7:0] s1_wb_way_en; // @[dcache.scala:653:41] wire [27:0] _s1_tag_eq_way_T = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95] wire [27:0] _s1_tag_eq_way_T_2 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95] wire [27:0] _s1_tag_eq_way_T_4 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95] wire [27:0] _s1_tag_eq_way_T_6 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95] wire [27:0] _s1_tag_eq_way_T_8 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95] wire [27:0] _s1_tag_eq_way_T_10 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95] wire [27:0] _s1_tag_eq_way_T_12 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95] wire [27:0] _s1_tag_eq_way_T_14 = s1_req_0_addr[39:12]; // @[dcache.scala:633:32, :657:95] wire _s1_tag_eq_way_T_1 = {8'h0, _meta_0_io_resp_0_tag} == _s1_tag_eq_way_T; // @[dcache.scala:469:41, :657:{79,95}] wire _s1_tag_eq_way_WIRE_0 = _s1_tag_eq_way_T_1; // @[dcache.scala:656:47, :657:79] wire _s1_tag_eq_way_T_3 = {8'h0, _meta_0_io_resp_1_tag} == _s1_tag_eq_way_T_2; // @[dcache.scala:469:41, :657:{79,95}] wire _s1_tag_eq_way_WIRE_1 = _s1_tag_eq_way_T_3; // @[dcache.scala:656:47, :657:79] wire _s1_tag_eq_way_T_5 = {8'h0, _meta_0_io_resp_2_tag} == _s1_tag_eq_way_T_4; // @[dcache.scala:469:41, :657:{79,95}] wire _s1_tag_eq_way_WIRE_2 = _s1_tag_eq_way_T_5; // @[dcache.scala:656:47, :657:79] wire _s1_tag_eq_way_T_7 = {8'h0, _meta_0_io_resp_3_tag} == _s1_tag_eq_way_T_6; // @[dcache.scala:469:41, :657:{79,95}] wire _s1_tag_eq_way_WIRE_3 = _s1_tag_eq_way_T_7; // @[dcache.scala:656:47, :657:79] wire _s1_tag_eq_way_T_9 = {8'h0, _meta_0_io_resp_4_tag} == _s1_tag_eq_way_T_8; // @[dcache.scala:469:41, :657:{79,95}] wire _s1_tag_eq_way_WIRE_4 = _s1_tag_eq_way_T_9; // @[dcache.scala:656:47, :657:79] wire _s1_tag_eq_way_T_11 = {8'h0, _meta_0_io_resp_5_tag} == _s1_tag_eq_way_T_10; // @[dcache.scala:469:41, :657:{79,95}] wire _s1_tag_eq_way_WIRE_5 = _s1_tag_eq_way_T_11; // @[dcache.scala:656:47, :657:79] wire _s1_tag_eq_way_T_13 = {8'h0, _meta_0_io_resp_6_tag} == _s1_tag_eq_way_T_12; // @[dcache.scala:469:41, :657:{79,95}] wire _s1_tag_eq_way_WIRE_6 = _s1_tag_eq_way_T_13; // @[dcache.scala:656:47, :657:79] wire _s1_tag_eq_way_T_15 = {8'h0, _meta_0_io_resp_7_tag} == _s1_tag_eq_way_T_14; // @[dcache.scala:469:41, :657:{79,95}] wire _s1_tag_eq_way_WIRE_7 = _s1_tag_eq_way_T_15; // @[dcache.scala:656:47, :657:79] wire [1:0] s1_tag_eq_way_lo_lo = {_s1_tag_eq_way_WIRE_1, _s1_tag_eq_way_WIRE_0}; // @[dcache.scala:656:47, :657:110] wire [1:0] s1_tag_eq_way_lo_hi = {_s1_tag_eq_way_WIRE_3, _s1_tag_eq_way_WIRE_2}; // @[dcache.scala:656:47, :657:110] wire [3:0] s1_tag_eq_way_lo = {s1_tag_eq_way_lo_hi, s1_tag_eq_way_lo_lo}; // @[dcache.scala:657:110] wire [1:0] s1_tag_eq_way_hi_lo = {_s1_tag_eq_way_WIRE_5, _s1_tag_eq_way_WIRE_4}; // @[dcache.scala:656:47, :657:110] wire [1:0] s1_tag_eq_way_hi_hi = {_s1_tag_eq_way_WIRE_7, _s1_tag_eq_way_WIRE_6}; // @[dcache.scala:656:47, :657:110] wire [3:0] s1_tag_eq_way_hi = {s1_tag_eq_way_hi_hi, s1_tag_eq_way_hi_lo}; // @[dcache.scala:657:110] wire [7:0] _s1_tag_eq_way_T_16 = {s1_tag_eq_way_hi, s1_tag_eq_way_lo}; // @[dcache.scala:657:110] wire [7:0] s1_tag_eq_way_0 = _s1_tag_eq_way_T_16; // @[dcache.scala:454:49, :657:110] wire _s1_tag_match_way_T = s1_type == 3'h0; // @[dcache.scala:649:32, :659:38] wire _s1_tag_match_way_T_1 = s1_type == 3'h2; // @[dcache.scala:649:32, :660:38] wire _s1_tag_match_way_T_2 = s1_type == 3'h3; // @[dcache.scala:649:32, :661:38] wire _s1_tag_match_way_T_3 = s1_tag_eq_way_0[0]; // @[dcache.scala:454:49, :662:63] wire _s1_tag_match_way_T_4 = |_meta_0_io_resp_0_coh_state; // @[Metadata.scala:50:45] wire _s1_tag_match_way_T_5 = _s1_tag_match_way_T_3 & _s1_tag_match_way_T_4; // @[Metadata.scala:50:45] wire _s1_tag_match_way_WIRE_0 = _s1_tag_match_way_T_5; // @[dcache.scala:656:47, :662:67] wire _s1_tag_match_way_T_6 = s1_tag_eq_way_0[1]; // @[dcache.scala:454:49, :662:63] wire _s1_tag_match_way_T_7 = |_meta_0_io_resp_1_coh_state; // @[Metadata.scala:50:45] wire _s1_tag_match_way_T_8 = _s1_tag_match_way_T_6 & _s1_tag_match_way_T_7; // @[Metadata.scala:50:45] wire _s1_tag_match_way_WIRE_1 = _s1_tag_match_way_T_8; // @[dcache.scala:656:47, :662:67] wire _s1_tag_match_way_T_9 = s1_tag_eq_way_0[2]; // @[dcache.scala:454:49, :662:63] wire _s1_tag_match_way_T_10 = |_meta_0_io_resp_2_coh_state; // @[Metadata.scala:50:45] wire _s1_tag_match_way_T_11 = _s1_tag_match_way_T_9 & _s1_tag_match_way_T_10; // @[Metadata.scala:50:45] wire _s1_tag_match_way_WIRE_2 = _s1_tag_match_way_T_11; // @[dcache.scala:656:47, :662:67] wire _s1_tag_match_way_T_12 = s1_tag_eq_way_0[3]; // @[dcache.scala:454:49, :662:63] wire _s1_tag_match_way_T_13 = |_meta_0_io_resp_3_coh_state; // @[Metadata.scala:50:45] wire _s1_tag_match_way_T_14 = _s1_tag_match_way_T_12 & _s1_tag_match_way_T_13; // @[Metadata.scala:50:45] wire _s1_tag_match_way_WIRE_3 = _s1_tag_match_way_T_14; // @[dcache.scala:656:47, :662:67] wire _s1_tag_match_way_T_15 = s1_tag_eq_way_0[4]; // @[dcache.scala:454:49, :662:63] wire _s1_tag_match_way_T_16 = |_meta_0_io_resp_4_coh_state; // @[Metadata.scala:50:45] wire _s1_tag_match_way_T_17 = _s1_tag_match_way_T_15 & _s1_tag_match_way_T_16; // @[Metadata.scala:50:45] wire _s1_tag_match_way_WIRE_4 = _s1_tag_match_way_T_17; // @[dcache.scala:656:47, :662:67] wire _s1_tag_match_way_T_18 = s1_tag_eq_way_0[5]; // @[dcache.scala:454:49, :662:63] wire _s1_tag_match_way_T_19 = |_meta_0_io_resp_5_coh_state; // @[Metadata.scala:50:45] wire _s1_tag_match_way_T_20 = _s1_tag_match_way_T_18 & _s1_tag_match_way_T_19; // @[Metadata.scala:50:45] wire _s1_tag_match_way_WIRE_5 = _s1_tag_match_way_T_20; // @[dcache.scala:656:47, :662:67] wire _s1_tag_match_way_T_21 = s1_tag_eq_way_0[6]; // @[dcache.scala:454:49, :662:63] wire _s1_tag_match_way_T_22 = |_meta_0_io_resp_6_coh_state; // @[Metadata.scala:50:45] wire _s1_tag_match_way_T_23 = _s1_tag_match_way_T_21 & _s1_tag_match_way_T_22; // @[Metadata.scala:50:45] wire _s1_tag_match_way_WIRE_6 = _s1_tag_match_way_T_23; // @[dcache.scala:656:47, :662:67] wire _s1_tag_match_way_T_24 = s1_tag_eq_way_0[7]; // @[dcache.scala:454:49, :662:63] wire _s1_tag_match_way_T_25 = |_meta_0_io_resp_7_coh_state; // @[Metadata.scala:50:45] wire _s1_tag_match_way_T_26 = _s1_tag_match_way_T_24 & _s1_tag_match_way_T_25; // @[Metadata.scala:50:45] wire _s1_tag_match_way_WIRE_7 = _s1_tag_match_way_T_26; // @[dcache.scala:656:47, :662:67] wire [1:0] s1_tag_match_way_lo_lo = {_s1_tag_match_way_WIRE_1, _s1_tag_match_way_WIRE_0}; // @[dcache.scala:656:47, :662:104] wire [1:0] s1_tag_match_way_lo_hi = {_s1_tag_match_way_WIRE_3, _s1_tag_match_way_WIRE_2}; // @[dcache.scala:656:47, :662:104] wire [3:0] s1_tag_match_way_lo = {s1_tag_match_way_lo_hi, s1_tag_match_way_lo_lo}; // @[dcache.scala:662:104] wire [1:0] s1_tag_match_way_hi_lo = {_s1_tag_match_way_WIRE_5, _s1_tag_match_way_WIRE_4}; // @[dcache.scala:656:47, :662:104] wire [1:0] s1_tag_match_way_hi_hi = {_s1_tag_match_way_WIRE_7, _s1_tag_match_way_WIRE_6}; // @[dcache.scala:656:47, :662:104] wire [3:0] s1_tag_match_way_hi = {s1_tag_match_way_hi_hi, s1_tag_match_way_hi_lo}; // @[dcache.scala:662:104] wire [7:0] _s1_tag_match_way_T_27 = {s1_tag_match_way_hi, s1_tag_match_way_lo}; // @[dcache.scala:662:104] wire [7:0] _s1_tag_match_way_T_28 = _s1_tag_match_way_T_2 ? s1_mshr_meta_read_way_en : _s1_tag_match_way_T_27; // @[dcache.scala:651:41, :661:{29,38}, :662:104] wire [7:0] _s1_tag_match_way_T_29 = _s1_tag_match_way_T_1 ? s1_wb_way_en : _s1_tag_match_way_T_28; // @[dcache.scala:653:41, :660:{29,38}, :661:29] wire [7:0] _s1_tag_match_way_T_30 = _s1_tag_match_way_T ? s1_replay_way_en : _s1_tag_match_way_T_29; // @[dcache.scala:652:41, :659:{29,38}, :660:29] wire [7:0] s1_tag_match_way_0 = _s1_tag_match_way_T_30; // @[dcache.scala:454:49, :659:29] wire _s1_wb_idx_matches_T_1 = _s1_wb_idx_matches_T == _wb_io_idx_bits; // @[dcache.scala:458:18, :664:{52,79}] wire _s1_wb_idx_matches_T_2 = _s1_wb_idx_matches_T_1 & _wb_io_idx_valid; // @[dcache.scala:458:18, :664:{79,99}] wire s1_wb_idx_matches_0 = _s1_wb_idx_matches_T_2; // @[dcache.scala:454:49, :664:99] reg [31:0] s2_req_0_uop_inst; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_inst_0 = s2_req_0_uop_inst; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_inst_0 = s2_req_0_uop_inst; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_inst_0 = s2_req_0_uop_inst; // @[dcache.scala:438:7, :670:25] reg [31:0] s2_req_0_uop_debug_inst; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_debug_inst_0 = s2_req_0_uop_debug_inst; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_debug_inst_0 = s2_req_0_uop_debug_inst; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_debug_inst_0 = s2_req_0_uop_debug_inst; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_rvc; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_rvc_0 = s2_req_0_uop_is_rvc; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_rvc_0 = s2_req_0_uop_is_rvc; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_rvc_0 = s2_req_0_uop_is_rvc; // @[dcache.scala:438:7, :670:25] reg [39:0] s2_req_0_uop_debug_pc; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_debug_pc_0 = s2_req_0_uop_debug_pc; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_debug_pc_0 = s2_req_0_uop_debug_pc; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_debug_pc_0 = s2_req_0_uop_debug_pc; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iq_type_0; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iq_type_0_0 = s2_req_0_uop_iq_type_0; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iq_type_0_0 = s2_req_0_uop_iq_type_0; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iq_type_0_0 = s2_req_0_uop_iq_type_0; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iq_type_1; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iq_type_1_0 = s2_req_0_uop_iq_type_1; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iq_type_1_0 = s2_req_0_uop_iq_type_1; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iq_type_1_0 = s2_req_0_uop_iq_type_1; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iq_type_2; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iq_type_2_0 = s2_req_0_uop_iq_type_2; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iq_type_2_0 = s2_req_0_uop_iq_type_2; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iq_type_2_0 = s2_req_0_uop_iq_type_2; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iq_type_3; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iq_type_3_0 = s2_req_0_uop_iq_type_3; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iq_type_3_0 = s2_req_0_uop_iq_type_3; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iq_type_3_0 = s2_req_0_uop_iq_type_3; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_0; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_0_0 = s2_req_0_uop_fu_code_0; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_0_0 = s2_req_0_uop_fu_code_0; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_0_0 = s2_req_0_uop_fu_code_0; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_1; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_1_0 = s2_req_0_uop_fu_code_1; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_1_0 = s2_req_0_uop_fu_code_1; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_1_0 = s2_req_0_uop_fu_code_1; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_2; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_2_0 = s2_req_0_uop_fu_code_2; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_2_0 = s2_req_0_uop_fu_code_2; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_2_0 = s2_req_0_uop_fu_code_2; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_3; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_3_0 = s2_req_0_uop_fu_code_3; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_3_0 = s2_req_0_uop_fu_code_3; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_3_0 = s2_req_0_uop_fu_code_3; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_4; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_4_0 = s2_req_0_uop_fu_code_4; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_4_0 = s2_req_0_uop_fu_code_4; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_4_0 = s2_req_0_uop_fu_code_4; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_5; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_5_0 = s2_req_0_uop_fu_code_5; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_5_0 = s2_req_0_uop_fu_code_5; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_5_0 = s2_req_0_uop_fu_code_5; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_6; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_6_0 = s2_req_0_uop_fu_code_6; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_6_0 = s2_req_0_uop_fu_code_6; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_6_0 = s2_req_0_uop_fu_code_6; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_7; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_7_0 = s2_req_0_uop_fu_code_7; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_7_0 = s2_req_0_uop_fu_code_7; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_7_0 = s2_req_0_uop_fu_code_7; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_8; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_8_0 = s2_req_0_uop_fu_code_8; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_8_0 = s2_req_0_uop_fu_code_8; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_8_0 = s2_req_0_uop_fu_code_8; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fu_code_9; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fu_code_9_0 = s2_req_0_uop_fu_code_9; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fu_code_9_0 = s2_req_0_uop_fu_code_9; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fu_code_9_0 = s2_req_0_uop_fu_code_9; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iw_issued; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iw_issued_0 = s2_req_0_uop_iw_issued; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iw_issued_0 = s2_req_0_uop_iw_issued; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iw_issued_0 = s2_req_0_uop_iw_issued; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iw_issued_partial_agen_0 = s2_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iw_issued_partial_agen_0 = s2_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iw_issued_partial_agen_0 = s2_req_0_uop_iw_issued_partial_agen; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iw_issued_partial_dgen_0 = s2_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iw_issued_partial_dgen_0 = s2_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iw_issued_partial_dgen_0 = s2_req_0_uop_iw_issued_partial_dgen; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iw_p1_speculative_child_0 = s2_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iw_p1_speculative_child_0 = s2_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iw_p1_speculative_child_0 = s2_req_0_uop_iw_p1_speculative_child; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iw_p2_speculative_child_0 = s2_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iw_p2_speculative_child_0 = s2_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iw_p2_speculative_child_0 = s2_req_0_uop_iw_p2_speculative_child; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iw_p1_bypass_hint_0 = s2_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iw_p1_bypass_hint_0 = s2_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iw_p1_bypass_hint_0 = s2_req_0_uop_iw_p1_bypass_hint; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iw_p2_bypass_hint_0 = s2_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iw_p2_bypass_hint_0 = s2_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iw_p2_bypass_hint_0 = s2_req_0_uop_iw_p2_bypass_hint; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_iw_p3_bypass_hint_0 = s2_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_iw_p3_bypass_hint_0 = s2_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_iw_p3_bypass_hint_0 = s2_req_0_uop_iw_p3_bypass_hint; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_dis_col_sel; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_dis_col_sel_0 = s2_req_0_uop_dis_col_sel; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_dis_col_sel_0 = s2_req_0_uop_dis_col_sel; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_dis_col_sel_0 = s2_req_0_uop_dis_col_sel; // @[dcache.scala:438:7, :670:25] reg [15:0] s2_req_0_uop_br_mask; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_br_mask_0 = s2_req_0_uop_br_mask; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_br_mask_0 = s2_req_0_uop_br_mask; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_br_mask_0 = s2_req_0_uop_br_mask; // @[dcache.scala:438:7, :670:25] reg [3:0] s2_req_0_uop_br_tag; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_br_tag_0 = s2_req_0_uop_br_tag; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_br_tag_0 = s2_req_0_uop_br_tag; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_br_tag_0 = s2_req_0_uop_br_tag; // @[dcache.scala:438:7, :670:25] reg [3:0] s2_req_0_uop_br_type; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_br_type_0 = s2_req_0_uop_br_type; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_br_type_0 = s2_req_0_uop_br_type; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_br_type_0 = s2_req_0_uop_br_type; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_sfb; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_sfb_0 = s2_req_0_uop_is_sfb; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_sfb_0 = s2_req_0_uop_is_sfb; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_sfb_0 = s2_req_0_uop_is_sfb; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_fence; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_fence_0 = s2_req_0_uop_is_fence; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_fence_0 = s2_req_0_uop_is_fence; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_fence_0 = s2_req_0_uop_is_fence; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_fencei; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_fencei_0 = s2_req_0_uop_is_fencei; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_fencei_0 = s2_req_0_uop_is_fencei; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_fencei_0 = s2_req_0_uop_is_fencei; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_sfence; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_sfence_0 = s2_req_0_uop_is_sfence; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_sfence_0 = s2_req_0_uop_is_sfence; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_sfence_0 = s2_req_0_uop_is_sfence; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_amo; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_amo_0 = s2_req_0_uop_is_amo; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_amo_0 = s2_req_0_uop_is_amo; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_amo_0 = s2_req_0_uop_is_amo; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_eret; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_eret_0 = s2_req_0_uop_is_eret; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_eret_0 = s2_req_0_uop_is_eret; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_eret_0 = s2_req_0_uop_is_eret; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_sys_pc2epc_0 = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_sys_pc2epc_0 = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_sys_pc2epc_0 = s2_req_0_uop_is_sys_pc2epc; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_rocc; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_rocc_0 = s2_req_0_uop_is_rocc; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_rocc_0 = s2_req_0_uop_is_rocc; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_rocc_0 = s2_req_0_uop_is_rocc; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_mov; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_mov_0 = s2_req_0_uop_is_mov; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_mov_0 = s2_req_0_uop_is_mov; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_mov_0 = s2_req_0_uop_is_mov; // @[dcache.scala:438:7, :670:25] reg [4:0] s2_req_0_uop_ftq_idx; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_ftq_idx_0 = s2_req_0_uop_ftq_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_ftq_idx_0 = s2_req_0_uop_ftq_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_ftq_idx_0 = s2_req_0_uop_ftq_idx; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_edge_inst; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_edge_inst_0 = s2_req_0_uop_edge_inst; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_edge_inst_0 = s2_req_0_uop_edge_inst; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_edge_inst_0 = s2_req_0_uop_edge_inst; // @[dcache.scala:438:7, :670:25] reg [5:0] s2_req_0_uop_pc_lob; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_pc_lob_0 = s2_req_0_uop_pc_lob; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_pc_lob_0 = s2_req_0_uop_pc_lob; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_pc_lob_0 = s2_req_0_uop_pc_lob; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_taken; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_taken_0 = s2_req_0_uop_taken; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_taken_0 = s2_req_0_uop_taken; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_taken_0 = s2_req_0_uop_taken; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_imm_rename; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_imm_rename_0 = s2_req_0_uop_imm_rename; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_imm_rename_0 = s2_req_0_uop_imm_rename; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_imm_rename_0 = s2_req_0_uop_imm_rename; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_imm_sel; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_imm_sel_0 = s2_req_0_uop_imm_sel; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_imm_sel_0 = s2_req_0_uop_imm_sel; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_imm_sel_0 = s2_req_0_uop_imm_sel; // @[dcache.scala:438:7, :670:25] reg [4:0] s2_req_0_uop_pimm; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_pimm_0 = s2_req_0_uop_pimm; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_pimm_0 = s2_req_0_uop_pimm; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_pimm_0 = s2_req_0_uop_pimm; // @[dcache.scala:438:7, :670:25] reg [19:0] s2_req_0_uop_imm_packed; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_imm_packed_0 = s2_req_0_uop_imm_packed; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_imm_packed_0 = s2_req_0_uop_imm_packed; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_imm_packed_0 = s2_req_0_uop_imm_packed; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_op1_sel; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_op1_sel_0 = s2_req_0_uop_op1_sel; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_op1_sel_0 = s2_req_0_uop_op1_sel; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_op1_sel_0 = s2_req_0_uop_op1_sel; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_op2_sel; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_op2_sel_0 = s2_req_0_uop_op2_sel; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_op2_sel_0 = s2_req_0_uop_op2_sel; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_op2_sel_0 = s2_req_0_uop_op2_sel; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_ldst_0 = s2_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_ldst_0 = s2_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_ldst_0 = s2_req_0_uop_fp_ctrl_ldst; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_wen; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_wen_0 = s2_req_0_uop_fp_ctrl_wen; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_wen_0 = s2_req_0_uop_fp_ctrl_wen; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_wen_0 = s2_req_0_uop_fp_ctrl_wen; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_ren1_0 = s2_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_ren1_0 = s2_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_ren1_0 = s2_req_0_uop_fp_ctrl_ren1; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_ren2_0 = s2_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_ren2_0 = s2_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_ren2_0 = s2_req_0_uop_fp_ctrl_ren2; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_ren3_0 = s2_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_ren3_0 = s2_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_ren3_0 = s2_req_0_uop_fp_ctrl_ren3; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_swap12_0 = s2_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_swap12_0 = s2_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_swap12_0 = s2_req_0_uop_fp_ctrl_swap12; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_swap23_0 = s2_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_swap23_0 = s2_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_swap23_0 = s2_req_0_uop_fp_ctrl_swap23; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_typeTagIn_0 = s2_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagIn_0 = s2_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_typeTagIn_0 = s2_req_0_uop_fp_ctrl_typeTagIn; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_typeTagOut_0 = s2_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_typeTagOut_0 = s2_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_typeTagOut_0 = s2_req_0_uop_fp_ctrl_typeTagOut; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_fromint_0 = s2_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_fromint_0 = s2_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_fromint_0 = s2_req_0_uop_fp_ctrl_fromint; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_toint; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_toint_0 = s2_req_0_uop_fp_ctrl_toint; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_toint_0 = s2_req_0_uop_fp_ctrl_toint; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_toint_0 = s2_req_0_uop_fp_ctrl_toint; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_fastpipe_0 = s2_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_fastpipe_0 = s2_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_fastpipe_0 = s2_req_0_uop_fp_ctrl_fastpipe; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_fma; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_fma_0 = s2_req_0_uop_fp_ctrl_fma; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_fma_0 = s2_req_0_uop_fp_ctrl_fma; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_fma_0 = s2_req_0_uop_fp_ctrl_fma; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_div; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_div_0 = s2_req_0_uop_fp_ctrl_div; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_div_0 = s2_req_0_uop_fp_ctrl_div; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_div_0 = s2_req_0_uop_fp_ctrl_div; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_sqrt_0 = s2_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_sqrt_0 = s2_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_sqrt_0 = s2_req_0_uop_fp_ctrl_sqrt; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_wflags_0 = s2_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_wflags_0 = s2_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_wflags_0 = s2_req_0_uop_fp_ctrl_wflags; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_ctrl_vec; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_ctrl_vec_0 = s2_req_0_uop_fp_ctrl_vec; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_ctrl_vec_0 = s2_req_0_uop_fp_ctrl_vec; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_ctrl_vec_0 = s2_req_0_uop_fp_ctrl_vec; // @[dcache.scala:438:7, :670:25] reg [6:0] s2_req_0_uop_rob_idx; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_rob_idx_0 = s2_req_0_uop_rob_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_rob_idx_0 = s2_req_0_uop_rob_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_rob_idx_0 = s2_req_0_uop_rob_idx; // @[dcache.scala:438:7, :670:25] reg [4:0] s2_req_0_uop_ldq_idx; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_ldq_idx_0 = s2_req_0_uop_ldq_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_ldq_idx_0 = s2_req_0_uop_ldq_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_ldq_idx_0 = s2_req_0_uop_ldq_idx; // @[dcache.scala:438:7, :670:25] reg [4:0] s2_req_0_uop_stq_idx; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_stq_idx_0 = s2_req_0_uop_stq_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_stq_idx_0 = s2_req_0_uop_stq_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_stq_idx_0 = s2_req_0_uop_stq_idx; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_rxq_idx; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_rxq_idx_0 = s2_req_0_uop_rxq_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_rxq_idx_0 = s2_req_0_uop_rxq_idx; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_rxq_idx_0 = s2_req_0_uop_rxq_idx; // @[dcache.scala:438:7, :670:25] reg [6:0] s2_req_0_uop_pdst; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_pdst_0 = s2_req_0_uop_pdst; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_pdst_0 = s2_req_0_uop_pdst; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_pdst_0 = s2_req_0_uop_pdst; // @[dcache.scala:438:7, :670:25] reg [6:0] s2_req_0_uop_prs1; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_prs1_0 = s2_req_0_uop_prs1; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_prs1_0 = s2_req_0_uop_prs1; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_prs1_0 = s2_req_0_uop_prs1; // @[dcache.scala:438:7, :670:25] reg [6:0] s2_req_0_uop_prs2; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_prs2_0 = s2_req_0_uop_prs2; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_prs2_0 = s2_req_0_uop_prs2; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_prs2_0 = s2_req_0_uop_prs2; // @[dcache.scala:438:7, :670:25] reg [6:0] s2_req_0_uop_prs3; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_prs3_0 = s2_req_0_uop_prs3; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_prs3_0 = s2_req_0_uop_prs3; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_prs3_0 = s2_req_0_uop_prs3; // @[dcache.scala:438:7, :670:25] reg [4:0] s2_req_0_uop_ppred; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_ppred_0 = s2_req_0_uop_ppred; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_ppred_0 = s2_req_0_uop_ppred; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_ppred_0 = s2_req_0_uop_ppred; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_prs1_busy; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_prs1_busy_0 = s2_req_0_uop_prs1_busy; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_prs1_busy_0 = s2_req_0_uop_prs1_busy; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_prs1_busy_0 = s2_req_0_uop_prs1_busy; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_prs2_busy; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_prs2_busy_0 = s2_req_0_uop_prs2_busy; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_prs2_busy_0 = s2_req_0_uop_prs2_busy; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_prs2_busy_0 = s2_req_0_uop_prs2_busy; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_prs3_busy; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_prs3_busy_0 = s2_req_0_uop_prs3_busy; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_prs3_busy_0 = s2_req_0_uop_prs3_busy; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_prs3_busy_0 = s2_req_0_uop_prs3_busy; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_ppred_busy; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_ppred_busy_0 = s2_req_0_uop_ppred_busy; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_ppred_busy_0 = s2_req_0_uop_ppred_busy; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_ppred_busy_0 = s2_req_0_uop_ppred_busy; // @[dcache.scala:438:7, :670:25] reg [6:0] s2_req_0_uop_stale_pdst; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_stale_pdst_0 = s2_req_0_uop_stale_pdst; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_stale_pdst_0 = s2_req_0_uop_stale_pdst; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_stale_pdst_0 = s2_req_0_uop_stale_pdst; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_exception; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_exception_0 = s2_req_0_uop_exception; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_exception_0 = s2_req_0_uop_exception; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_exception_0 = s2_req_0_uop_exception; // @[dcache.scala:438:7, :670:25] reg [63:0] s2_req_0_uop_exc_cause; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_exc_cause_0 = s2_req_0_uop_exc_cause; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_exc_cause_0 = s2_req_0_uop_exc_cause; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_exc_cause_0 = s2_req_0_uop_exc_cause; // @[dcache.scala:438:7, :670:25] reg [4:0] s2_req_0_uop_mem_cmd; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_mem_cmd_0 = s2_req_0_uop_mem_cmd; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_mem_cmd_0 = s2_req_0_uop_mem_cmd; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_mem_cmd_0 = s2_req_0_uop_mem_cmd; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_mem_size; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_mem_size_0 = s2_req_0_uop_mem_size; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_mem_size_0 = s2_req_0_uop_mem_size; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_mem_size_0 = s2_req_0_uop_mem_size; // @[dcache.scala:438:7, :670:25] wire [1:0] size = s2_req_0_uop_mem_size; // @[AMOALU.scala:11:18] reg s2_req_0_uop_mem_signed; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_mem_signed_0 = s2_req_0_uop_mem_signed; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_mem_signed_0 = s2_req_0_uop_mem_signed; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_mem_signed_0 = s2_req_0_uop_mem_signed; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_uses_ldq; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_uses_ldq_0 = s2_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_uses_ldq_0 = s2_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_uses_ldq_0 = s2_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_uses_stq; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_uses_stq_0 = s2_req_0_uop_uses_stq; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_uses_stq_0 = s2_req_0_uop_uses_stq; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_uses_stq_0 = s2_req_0_uop_uses_stq; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_is_unique; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_is_unique_0 = s2_req_0_uop_is_unique; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_is_unique_0 = s2_req_0_uop_is_unique; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_is_unique_0 = s2_req_0_uop_is_unique; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_flush_on_commit; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_flush_on_commit_0 = s2_req_0_uop_flush_on_commit; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_flush_on_commit_0 = s2_req_0_uop_flush_on_commit; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_flush_on_commit_0 = s2_req_0_uop_flush_on_commit; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_csr_cmd; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_csr_cmd_0 = s2_req_0_uop_csr_cmd; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_csr_cmd_0 = s2_req_0_uop_csr_cmd; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_csr_cmd_0 = s2_req_0_uop_csr_cmd; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_ldst_is_rs1_0 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_ldst_is_rs1_0 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_ldst_is_rs1_0 = s2_req_0_uop_ldst_is_rs1; // @[dcache.scala:438:7, :670:25] reg [5:0] s2_req_0_uop_ldst; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_ldst_0 = s2_req_0_uop_ldst; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_ldst_0 = s2_req_0_uop_ldst; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_ldst_0 = s2_req_0_uop_ldst; // @[dcache.scala:438:7, :670:25] reg [5:0] s2_req_0_uop_lrs1; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_lrs1_0 = s2_req_0_uop_lrs1; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_lrs1_0 = s2_req_0_uop_lrs1; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_lrs1_0 = s2_req_0_uop_lrs1; // @[dcache.scala:438:7, :670:25] reg [5:0] s2_req_0_uop_lrs2; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_lrs2_0 = s2_req_0_uop_lrs2; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_lrs2_0 = s2_req_0_uop_lrs2; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_lrs2_0 = s2_req_0_uop_lrs2; // @[dcache.scala:438:7, :670:25] reg [5:0] s2_req_0_uop_lrs3; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_lrs3_0 = s2_req_0_uop_lrs3; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_lrs3_0 = s2_req_0_uop_lrs3; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_lrs3_0 = s2_req_0_uop_lrs3; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_dst_rtype; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_dst_rtype_0 = s2_req_0_uop_dst_rtype; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_dst_rtype_0 = s2_req_0_uop_dst_rtype; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_dst_rtype_0 = s2_req_0_uop_dst_rtype; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_lrs1_rtype; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_lrs1_rtype_0 = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_lrs1_rtype_0 = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_lrs1_rtype_0 = s2_req_0_uop_lrs1_rtype; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_lrs2_rtype; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_lrs2_rtype_0 = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_lrs2_rtype_0 = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_lrs2_rtype_0 = s2_req_0_uop_lrs2_rtype; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_frs3_en; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_frs3_en_0 = s2_req_0_uop_frs3_en; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_frs3_en_0 = s2_req_0_uop_frs3_en; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_frs3_en_0 = s2_req_0_uop_frs3_en; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fcn_dw; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fcn_dw_0 = s2_req_0_uop_fcn_dw; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fcn_dw_0 = s2_req_0_uop_fcn_dw; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fcn_dw_0 = s2_req_0_uop_fcn_dw; // @[dcache.scala:438:7, :670:25] reg [4:0] s2_req_0_uop_fcn_op; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fcn_op_0 = s2_req_0_uop_fcn_op; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fcn_op_0 = s2_req_0_uop_fcn_op; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fcn_op_0 = s2_req_0_uop_fcn_op; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_fp_val; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_val_0 = s2_req_0_uop_fp_val; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_val_0 = s2_req_0_uop_fp_val; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_val_0 = s2_req_0_uop_fp_val; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_fp_rm; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_rm_0 = s2_req_0_uop_fp_rm; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_rm_0 = s2_req_0_uop_fp_rm; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_rm_0 = s2_req_0_uop_fp_rm; // @[dcache.scala:438:7, :670:25] reg [1:0] s2_req_0_uop_fp_typ; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_fp_typ_0 = s2_req_0_uop_fp_typ; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_fp_typ_0 = s2_req_0_uop_fp_typ; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_fp_typ_0 = s2_req_0_uop_fp_typ; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_xcpt_pf_if_0 = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_xcpt_pf_if_0 = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_xcpt_pf_if_0 = s2_req_0_uop_xcpt_pf_if; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_xcpt_ae_if_0 = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_xcpt_ae_if_0 = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_xcpt_ae_if_0 = s2_req_0_uop_xcpt_ae_if; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_xcpt_ma_if_0 = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_xcpt_ma_if_0 = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_xcpt_ma_if_0 = s2_req_0_uop_xcpt_ma_if; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_bp_debug_if; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_bp_debug_if_0 = s2_req_0_uop_bp_debug_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_bp_debug_if_0 = s2_req_0_uop_bp_debug_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_bp_debug_if_0 = s2_req_0_uop_bp_debug_if; // @[dcache.scala:438:7, :670:25] reg s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_bp_xcpt_if_0 = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_bp_xcpt_if_0 = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_bp_xcpt_if_0 = s2_req_0_uop_bp_xcpt_if; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_debug_fsrc; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_debug_fsrc_0 = s2_req_0_uop_debug_fsrc; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_debug_fsrc_0 = s2_req_0_uop_debug_fsrc; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_debug_fsrc_0 = s2_req_0_uop_debug_fsrc; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_req_0_uop_debug_tsrc; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_uop_debug_tsrc_0 = s2_req_0_uop_debug_tsrc; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_uop_debug_tsrc_0 = s2_req_0_uop_debug_tsrc; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_uop_debug_tsrc_0 = s2_req_0_uop_debug_tsrc; // @[dcache.scala:438:7, :670:25] reg [39:0] s2_req_0_addr; // @[dcache.scala:670:25] assign io_lsu_store_ack_0_bits_addr_0 = s2_req_0_addr; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_addr_0 = s2_req_0_addr; // @[dcache.scala:438:7, :670:25] reg [63:0] s2_req_0_data; // @[dcache.scala:670:25] assign io_lsu_store_ack_0_bits_data_0 = s2_req_0_data; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_data_0 = s2_req_0_data; // @[dcache.scala:438:7, :670:25] reg s2_req_0_is_hella; // @[dcache.scala:670:25] assign io_lsu_resp_0_bits_is_hella_0 = s2_req_0_is_hella; // @[dcache.scala:438:7, :670:25] assign io_lsu_store_ack_0_bits_is_hella_0 = s2_req_0_is_hella; // @[dcache.scala:438:7, :670:25] assign io_lsu_nack_0_bits_is_hella_0 = s2_req_0_is_hella; // @[dcache.scala:438:7, :670:25] reg [2:0] s2_type; // @[dcache.scala:671:25] wire _s2_valid_T = ~io_lsu_s1_kill_0_0; // @[dcache.scala:438:7, :674:26] wire _s2_valid_T_1 = s1_valid_0 & _s2_valid_T; // @[dcache.scala:454:49, :673:39, :674:26] wire [15:0] _s2_valid_T_2 = io_lsu_brupdate_b1_mispredict_mask_0 & s1_req_0_uop_br_mask; // @[util.scala:126:51] wire _s2_valid_T_3 = |_s2_valid_T_2; // @[util.scala:126:{51,59}] wire _s2_valid_T_4 = _s2_valid_T_3; // @[util.scala:61:61, :126:59] wire _s2_valid_T_5 = ~_s2_valid_T_4; // @[util.scala:61:61] wire _s2_valid_T_6 = _s2_valid_T_1 & _s2_valid_T_5; // @[dcache.scala:673:39, :674:45, :675:26] wire _s2_valid_T_7 = io_lsu_exception_0 & s1_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :633:32, :676:45] wire _s2_valid_T_8 = ~_s2_valid_T_7; // @[dcache.scala:676:{26,45}] wire _s2_valid_T_9 = _s2_valid_T_6 & _s2_valid_T_8; // @[dcache.scala:674:45, :675:85, :676:26] wire _s2_valid_T_10 = s1_type == 3'h4; // @[dcache.scala:649:32, :677:56] wire _s2_valid_T_11 = s2_store_failed & _s2_valid_T_10; // @[dcache.scala:636:29, :677:{44,56}] wire _s2_valid_T_12 = _s2_valid_T_11 & s1_req_0_uop_uses_stq; // @[dcache.scala:633:32, :677:{44,67}] wire _s2_valid_T_13 = ~_s2_valid_T_12; // @[dcache.scala:677:{26,67}] wire _s2_valid_T_14 = _s2_valid_T_9 & _s2_valid_T_13; // @[dcache.scala:675:85, :676:72, :677:26] reg s2_valid_REG; // @[dcache.scala:673:26] wire s2_valid_0 = s2_valid_REG; // @[dcache.scala:454:49, :673:26] wire [15:0] _s2_req_0_uop_br_mask_T = ~io_lsu_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] wire [15:0] _s2_req_0_uop_br_mask_T_1 = s1_req_0_uop_br_mask & _s2_req_0_uop_br_mask_T; // @[util.scala:93:{25,27}] reg [7:0] s2_tag_match_way_0; // @[dcache.scala:681:33] wire s2_tag_match_0 = |s2_tag_match_way_0; // @[dcache.scala:681:33, :682:49] reg [1:0] s2_hit_state_REG_state; // @[dcache.scala:683:93] wire [1:0] _s2_hit_state_WIRE_0_state = s2_hit_state_REG_state; // @[dcache.scala:656:47, :683:93] reg [1:0] s2_hit_state_REG_1_state; // @[dcache.scala:683:93] wire [1:0] _s2_hit_state_WIRE_1_state_0 = s2_hit_state_REG_1_state; // @[dcache.scala:656:47, :683:93] reg [1:0] s2_hit_state_REG_2_state; // @[dcache.scala:683:93] wire [1:0] _s2_hit_state_WIRE_2_state = s2_hit_state_REG_2_state; // @[dcache.scala:656:47, :683:93] reg [1:0] s2_hit_state_REG_3_state; // @[dcache.scala:683:93] wire [1:0] _s2_hit_state_WIRE_3_state = s2_hit_state_REG_3_state; // @[dcache.scala:656:47, :683:93] reg [1:0] s2_hit_state_REG_4_state; // @[dcache.scala:683:93] wire [1:0] _s2_hit_state_WIRE_4_state = s2_hit_state_REG_4_state; // @[dcache.scala:656:47, :683:93] reg [1:0] s2_hit_state_REG_5_state; // @[dcache.scala:683:93] wire [1:0] _s2_hit_state_WIRE_5_state = s2_hit_state_REG_5_state; // @[dcache.scala:656:47, :683:93] reg [1:0] s2_hit_state_REG_6_state; // @[dcache.scala:683:93] wire [1:0] _s2_hit_state_WIRE_6_state = s2_hit_state_REG_6_state; // @[dcache.scala:656:47, :683:93] reg [1:0] s2_hit_state_REG_7_state; // @[dcache.scala:683:93] wire [1:0] _s2_hit_state_WIRE_7_state = s2_hit_state_REG_7_state; // @[dcache.scala:656:47, :683:93] wire _s2_hit_state_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36] wire _s2_data_muxed_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36] wire _mshrs_io_meta_resp_bits_T = s2_tag_match_way_0[0]; // @[Mux.scala:32:36] wire _s2_hit_state_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36] wire _s2_data_muxed_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36] wire _mshrs_io_meta_resp_bits_T_1 = s2_tag_match_way_0[1]; // @[Mux.scala:32:36] wire _s2_hit_state_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36] wire _s2_data_muxed_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36] wire _mshrs_io_meta_resp_bits_T_2 = s2_tag_match_way_0[2]; // @[Mux.scala:32:36] wire _s2_hit_state_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36] wire _s2_data_muxed_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36] wire _mshrs_io_meta_resp_bits_T_3 = s2_tag_match_way_0[3]; // @[Mux.scala:32:36] wire _s2_hit_state_T_4 = s2_tag_match_way_0[4]; // @[Mux.scala:32:36] wire _s2_data_muxed_T_4 = s2_tag_match_way_0[4]; // @[Mux.scala:32:36] wire _mshrs_io_meta_resp_bits_T_4 = s2_tag_match_way_0[4]; // @[Mux.scala:32:36] wire _s2_hit_state_T_5 = s2_tag_match_way_0[5]; // @[Mux.scala:32:36] wire _s2_data_muxed_T_5 = s2_tag_match_way_0[5]; // @[Mux.scala:32:36] wire _mshrs_io_meta_resp_bits_T_5 = s2_tag_match_way_0[5]; // @[Mux.scala:32:36] wire _s2_hit_state_T_6 = s2_tag_match_way_0[6]; // @[Mux.scala:32:36] wire _s2_data_muxed_T_6 = s2_tag_match_way_0[6]; // @[Mux.scala:32:36] wire _mshrs_io_meta_resp_bits_T_6 = s2_tag_match_way_0[6]; // @[Mux.scala:32:36] wire _s2_hit_state_T_7 = s2_tag_match_way_0[7]; // @[Mux.scala:32:36] wire _s2_data_muxed_T_7 = s2_tag_match_way_0[7]; // @[Mux.scala:32:36] wire _mshrs_io_meta_resp_bits_T_7 = s2_tag_match_way_0[7]; // @[Mux.scala:32:36] wire [1:0] _s2_hit_state_WIRE_2; // @[Mux.scala:30:73] wire [1:0] s2_hit_state_0_state = _s2_hit_state_WIRE_1_state; // @[Mux.scala:30:73] wire [1:0] _s2_hit_state_T_8 = _s2_hit_state_T ? _s2_hit_state_WIRE_0_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_hit_state_T_9 = _s2_hit_state_T_1 ? _s2_hit_state_WIRE_1_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_hit_state_T_10 = _s2_hit_state_T_2 ? _s2_hit_state_WIRE_2_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_hit_state_T_11 = _s2_hit_state_T_3 ? _s2_hit_state_WIRE_3_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_hit_state_T_12 = _s2_hit_state_T_4 ? _s2_hit_state_WIRE_4_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_hit_state_T_13 = _s2_hit_state_T_5 ? _s2_hit_state_WIRE_5_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_hit_state_T_14 = _s2_hit_state_T_6 ? _s2_hit_state_WIRE_6_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_hit_state_T_15 = _s2_hit_state_T_7 ? _s2_hit_state_WIRE_7_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_hit_state_T_16 = _s2_hit_state_T_8 | _s2_hit_state_T_9; // @[Mux.scala:30:73] wire [1:0] _s2_hit_state_T_17 = _s2_hit_state_T_16 | _s2_hit_state_T_10; // @[Mux.scala:30:73] wire [1:0] _s2_hit_state_T_18 = _s2_hit_state_T_17 | _s2_hit_state_T_11; // @[Mux.scala:30:73] wire [1:0] _s2_hit_state_T_19 = _s2_hit_state_T_18 | _s2_hit_state_T_12; // @[Mux.scala:30:73] wire [1:0] _s2_hit_state_T_20 = _s2_hit_state_T_19 | _s2_hit_state_T_13; // @[Mux.scala:30:73] wire [1:0] _s2_hit_state_T_21 = _s2_hit_state_T_20 | _s2_hit_state_T_14; // @[Mux.scala:30:73] wire [1:0] _s2_hit_state_T_22 = _s2_hit_state_T_21 | _s2_hit_state_T_15; // @[Mux.scala:30:73] assign _s2_hit_state_WIRE_2 = _s2_hit_state_T_22; // @[Mux.scala:30:73] assign _s2_hit_state_WIRE_1_state = _s2_hit_state_WIRE_2; // @[Mux.scala:30:73] wire [1:0] mshrs_io_req_0_bits_old_meta_meta_coh_state = s2_hit_state_0_state; // @[HellaCache.scala:305:20] wire _GEN_2 = s2_req_0_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _s2_has_permission_r_c_cat_T; // @[Consts.scala:90:32] assign _s2_has_permission_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32] wire _s2_has_permission_r_c_cat_T_23; // @[Consts.scala:90:32] assign _s2_has_permission_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32] wire _s2_new_hit_state_r_c_cat_T; // @[Consts.scala:90:32] assign _s2_new_hit_state_r_c_cat_T = _GEN_2; // @[Consts.scala:90:32] wire _s2_new_hit_state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _s2_new_hit_state_r_c_cat_T_23 = _GEN_2; // @[Consts.scala:90:32] wire _s2_send_store_ack_T_2; // @[Consts.scala:90:32] assign _s2_send_store_ack_T_2 = _GEN_2; // @[Consts.scala:90:32] wire _mshrs_io_req_0_valid_T_46; // @[Consts.scala:90:32] assign _mshrs_io_req_0_valid_T_46 = _GEN_2; // @[Consts.scala:90:32] wire _s3_valid_T_1; // @[Consts.scala:90:32] assign _s3_valid_T_1 = _GEN_2; // @[Consts.scala:90:32] wire _GEN_3 = s2_req_0_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:49] assign _s2_has_permission_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49] wire _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:49] assign _s2_has_permission_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49] wire _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _s2_new_hit_state_r_c_cat_T_1 = _GEN_3; // @[Consts.scala:90:49] wire _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _s2_new_hit_state_r_c_cat_T_24 = _GEN_3; // @[Consts.scala:90:49] wire _s2_send_store_ack_T_3; // @[Consts.scala:90:49] assign _s2_send_store_ack_T_3 = _GEN_3; // @[Consts.scala:90:49] wire _mshrs_io_req_0_valid_T_47; // @[Consts.scala:90:49] assign _mshrs_io_req_0_valid_T_47 = _GEN_3; // @[Consts.scala:90:49] wire _s3_valid_T_2; // @[Consts.scala:90:49] assign _s3_valid_T_2 = _GEN_3; // @[Consts.scala:90:49] wire _s2_has_permission_r_c_cat_T_2 = _s2_has_permission_r_c_cat_T | _s2_has_permission_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_4 = s2_req_0_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:66] assign _s2_has_permission_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66] wire _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:66] assign _s2_has_permission_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66] wire _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _s2_new_hit_state_r_c_cat_T_3 = _GEN_4; // @[Consts.scala:90:66] wire _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _s2_new_hit_state_r_c_cat_T_26 = _GEN_4; // @[Consts.scala:90:66] wire _s2_sc_T; // @[dcache.scala:702:37] assign _s2_sc_T = _GEN_4; // @[Consts.scala:90:66] wire _s2_send_resp_T_10; // @[package.scala:16:47] assign _s2_send_resp_T_10 = _GEN_4; // @[package.scala:16:47] wire _s2_send_store_ack_T_5; // @[Consts.scala:90:66] assign _s2_send_store_ack_T_5 = _GEN_4; // @[Consts.scala:90:66] wire _mshrs_io_req_0_valid_T_23; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_23 = _GEN_4; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_49; // @[Consts.scala:90:66] assign _mshrs_io_req_0_valid_T_49 = _GEN_4; // @[Consts.scala:90:66] wire _s3_valid_T_4; // @[Consts.scala:90:66] assign _s3_valid_T_4 = _GEN_4; // @[Consts.scala:90:66] wire _s2_has_permission_r_c_cat_T_4 = _s2_has_permission_r_c_cat_T_2 | _s2_has_permission_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_5 = s2_req_0_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_5; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_28; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_5; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_5 = _GEN_5; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_28; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_28 = _GEN_5; // @[package.scala:16:47] wire _s2_send_resp_T_14; // @[package.scala:16:47] assign _s2_send_resp_T_14 = _GEN_5; // @[package.scala:16:47] wire _s2_send_store_ack_T_7; // @[package.scala:16:47] assign _s2_send_store_ack_T_7 = _GEN_5; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_27; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_27 = _GEN_5; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_51; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_51 = _GEN_5; // @[package.scala:16:47] wire _s3_valid_T_6; // @[package.scala:16:47] assign _s3_valid_T_6 = _GEN_5; // @[package.scala:16:47] wire _GEN_6 = s2_req_0_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_6 = _GEN_6; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_29 = _GEN_6; // @[package.scala:16:47] wire _s2_send_resp_T_15; // @[package.scala:16:47] assign _s2_send_resp_T_15 = _GEN_6; // @[package.scala:16:47] wire _s2_send_store_ack_T_8; // @[package.scala:16:47] assign _s2_send_store_ack_T_8 = _GEN_6; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_28; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_28 = _GEN_6; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_52; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_52 = _GEN_6; // @[package.scala:16:47] wire _s3_valid_T_7; // @[package.scala:16:47] assign _s3_valid_T_7 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = s2_req_0_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_7 = _GEN_7; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_30 = _GEN_7; // @[package.scala:16:47] wire _s2_send_resp_T_16; // @[package.scala:16:47] assign _s2_send_resp_T_16 = _GEN_7; // @[package.scala:16:47] wire _s2_send_store_ack_T_9; // @[package.scala:16:47] assign _s2_send_store_ack_T_9 = _GEN_7; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_29; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_29 = _GEN_7; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_53; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_53 = _GEN_7; // @[package.scala:16:47] wire _s3_valid_T_8; // @[package.scala:16:47] assign _s3_valid_T_8 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = s2_req_0_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_8 = _GEN_8; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_31 = _GEN_8; // @[package.scala:16:47] wire _s2_send_resp_T_17; // @[package.scala:16:47] assign _s2_send_resp_T_17 = _GEN_8; // @[package.scala:16:47] wire _s2_send_store_ack_T_10; // @[package.scala:16:47] assign _s2_send_store_ack_T_10 = _GEN_8; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_30; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_30 = _GEN_8; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_54; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_54 = _GEN_8; // @[package.scala:16:47] wire _s3_valid_T_9; // @[package.scala:16:47] assign _s3_valid_T_9 = _GEN_8; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_9 = _s2_has_permission_r_c_cat_T_5 | _s2_has_permission_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_10 = _s2_has_permission_r_c_cat_T_9 | _s2_has_permission_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_11 = _s2_has_permission_r_c_cat_T_10 | _s2_has_permission_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_9 = s2_req_0_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_12; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_35; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_12; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_12 = _GEN_9; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_35; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_35 = _GEN_9; // @[package.scala:16:47] wire _s2_send_resp_T_21; // @[package.scala:16:47] assign _s2_send_resp_T_21 = _GEN_9; // @[package.scala:16:47] wire _s2_send_store_ack_T_14; // @[package.scala:16:47] assign _s2_send_store_ack_T_14 = _GEN_9; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_34; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_34 = _GEN_9; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_58; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_58 = _GEN_9; // @[package.scala:16:47] wire _s3_valid_T_13; // @[package.scala:16:47] assign _s3_valid_T_13 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = s2_req_0_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_13 = _GEN_10; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_36 = _GEN_10; // @[package.scala:16:47] wire _s2_send_resp_T_22; // @[package.scala:16:47] assign _s2_send_resp_T_22 = _GEN_10; // @[package.scala:16:47] wire _s2_send_store_ack_T_15; // @[package.scala:16:47] assign _s2_send_store_ack_T_15 = _GEN_10; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_35; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_35 = _GEN_10; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_59; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_59 = _GEN_10; // @[package.scala:16:47] wire _s3_valid_T_14; // @[package.scala:16:47] assign _s3_valid_T_14 = _GEN_10; // @[package.scala:16:47] wire _GEN_11 = s2_req_0_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_14 = _GEN_11; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_37 = _GEN_11; // @[package.scala:16:47] wire _s2_send_resp_T_23; // @[package.scala:16:47] assign _s2_send_resp_T_23 = _GEN_11; // @[package.scala:16:47] wire _s2_send_store_ack_T_16; // @[package.scala:16:47] assign _s2_send_store_ack_T_16 = _GEN_11; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_36; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_36 = _GEN_11; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_60; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_60 = _GEN_11; // @[package.scala:16:47] wire _s3_valid_T_15; // @[package.scala:16:47] assign _s3_valid_T_15 = _GEN_11; // @[package.scala:16:47] wire _GEN_12 = s2_req_0_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_15 = _GEN_12; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_38 = _GEN_12; // @[package.scala:16:47] wire _s2_send_resp_T_24; // @[package.scala:16:47] assign _s2_send_resp_T_24 = _GEN_12; // @[package.scala:16:47] wire _s2_send_store_ack_T_17; // @[package.scala:16:47] assign _s2_send_store_ack_T_17 = _GEN_12; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_37; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_37 = _GEN_12; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_61; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_61 = _GEN_12; // @[package.scala:16:47] wire _s3_valid_T_16; // @[package.scala:16:47] assign _s3_valid_T_16 = _GEN_12; // @[package.scala:16:47] wire _GEN_13 = s2_req_0_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47] assign _s2_has_permission_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_16 = _GEN_13; // @[package.scala:16:47] wire _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47] assign _s2_new_hit_state_r_c_cat_T_39 = _GEN_13; // @[package.scala:16:47] wire _s2_send_resp_T_25; // @[package.scala:16:47] assign _s2_send_resp_T_25 = _GEN_13; // @[package.scala:16:47] wire _s2_send_store_ack_T_18; // @[package.scala:16:47] assign _s2_send_store_ack_T_18 = _GEN_13; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_38; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_38 = _GEN_13; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_62; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_62 = _GEN_13; // @[package.scala:16:47] wire _s3_valid_T_17; // @[package.scala:16:47] assign _s3_valid_T_17 = _GEN_13; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_17 = _s2_has_permission_r_c_cat_T_12 | _s2_has_permission_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_18 = _s2_has_permission_r_c_cat_T_17 | _s2_has_permission_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_19 = _s2_has_permission_r_c_cat_T_18 | _s2_has_permission_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_20 = _s2_has_permission_r_c_cat_T_19 | _s2_has_permission_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_21 = _s2_has_permission_r_c_cat_T_11 | _s2_has_permission_r_c_cat_T_20; // @[package.scala:81:59] wire _s2_has_permission_r_c_cat_T_22 = _s2_has_permission_r_c_cat_T_4 | _s2_has_permission_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _s2_has_permission_r_c_cat_T_25 = _s2_has_permission_r_c_cat_T_23 | _s2_has_permission_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _s2_has_permission_r_c_cat_T_27 = _s2_has_permission_r_c_cat_T_25 | _s2_has_permission_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _s2_has_permission_r_c_cat_T_32 = _s2_has_permission_r_c_cat_T_28 | _s2_has_permission_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_33 = _s2_has_permission_r_c_cat_T_32 | _s2_has_permission_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_34 = _s2_has_permission_r_c_cat_T_33 | _s2_has_permission_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_40 = _s2_has_permission_r_c_cat_T_35 | _s2_has_permission_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_41 = _s2_has_permission_r_c_cat_T_40 | _s2_has_permission_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_42 = _s2_has_permission_r_c_cat_T_41 | _s2_has_permission_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_43 = _s2_has_permission_r_c_cat_T_42 | _s2_has_permission_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _s2_has_permission_r_c_cat_T_44 = _s2_has_permission_r_c_cat_T_34 | _s2_has_permission_r_c_cat_T_43; // @[package.scala:81:59] wire _s2_has_permission_r_c_cat_T_45 = _s2_has_permission_r_c_cat_T_27 | _s2_has_permission_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_14 = s2_req_0_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:91:54] assign _s2_has_permission_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54] wire _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _s2_new_hit_state_r_c_cat_T_46 = _GEN_14; // @[Consts.scala:91:54] wire _mshrs_io_req_0_valid_T_18; // @[Consts.scala:88:52] assign _mshrs_io_req_0_valid_T_18 = _GEN_14; // @[Consts.scala:88:52, :91:54] wire _s2_has_permission_r_c_cat_T_47 = _s2_has_permission_r_c_cat_T_45 | _s2_has_permission_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_15 = s2_req_0_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:71] assign _s2_has_permission_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71] wire _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _s2_new_hit_state_r_c_cat_T_48 = _GEN_15; // @[Consts.scala:91:71] wire _s2_lr_T; // @[dcache.scala:701:37] assign _s2_lr_T = _GEN_15; // @[Consts.scala:91:71] wire _s2_send_resp_T_9; // @[package.scala:16:47] assign _s2_send_resp_T_9 = _GEN_15; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_22; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_22 = _GEN_15; // @[package.scala:16:47] wire _s2_has_permission_r_c_cat_T_49 = _s2_has_permission_r_c_cat_T_47 | _s2_has_permission_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] s2_has_permission_r_c = {_s2_has_permission_r_c_cat_T_22, _s2_has_permission_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _s2_has_permission_r_T = {s2_has_permission_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19] wire _s2_has_permission_r_T_25 = _s2_has_permission_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _s2_has_permission_r_T_27 = {1'h0, _s2_has_permission_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_28 = _s2_has_permission_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _s2_has_permission_r_T_30 = _s2_has_permission_r_T_28 ? 2'h2 : _s2_has_permission_r_T_27; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_31 = _s2_has_permission_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _s2_has_permission_r_T_33 = _s2_has_permission_r_T_31 ? 2'h1 : _s2_has_permission_r_T_30; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_34 = _s2_has_permission_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _s2_has_permission_r_T_36 = _s2_has_permission_r_T_34 ? 2'h2 : _s2_has_permission_r_T_33; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_37 = _s2_has_permission_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _s2_has_permission_r_T_39 = _s2_has_permission_r_T_37 ? 2'h0 : _s2_has_permission_r_T_36; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_40 = _s2_has_permission_r_T == 4'hE; // @[Misc.scala:49:20] wire _s2_has_permission_r_T_41 = _s2_has_permission_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_has_permission_r_T_42 = _s2_has_permission_r_T_40 ? 2'h3 : _s2_has_permission_r_T_39; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_43 = &_s2_has_permission_r_T; // @[Misc.scala:49:20] wire _s2_has_permission_r_T_44 = _s2_has_permission_r_T_43 | _s2_has_permission_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_has_permission_r_T_45 = _s2_has_permission_r_T_43 ? 2'h3 : _s2_has_permission_r_T_42; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_46 = _s2_has_permission_r_T == 4'h6; // @[Misc.scala:49:20] wire _s2_has_permission_r_T_47 = _s2_has_permission_r_T_46 | _s2_has_permission_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_has_permission_r_T_48 = _s2_has_permission_r_T_46 ? 2'h2 : _s2_has_permission_r_T_45; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_49 = _s2_has_permission_r_T == 4'h7; // @[Misc.scala:49:20] wire _s2_has_permission_r_T_50 = _s2_has_permission_r_T_49 | _s2_has_permission_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_has_permission_r_T_51 = _s2_has_permission_r_T_49 ? 2'h3 : _s2_has_permission_r_T_48; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_52 = _s2_has_permission_r_T == 4'h1; // @[Misc.scala:49:20] wire _s2_has_permission_r_T_53 = _s2_has_permission_r_T_52 | _s2_has_permission_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_has_permission_r_T_54 = _s2_has_permission_r_T_52 ? 2'h1 : _s2_has_permission_r_T_51; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_55 = _s2_has_permission_r_T == 4'h2; // @[Misc.scala:49:20] wire _s2_has_permission_r_T_56 = _s2_has_permission_r_T_55 | _s2_has_permission_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_has_permission_r_T_57 = _s2_has_permission_r_T_55 ? 2'h2 : _s2_has_permission_r_T_54; // @[Misc.scala:35:36, :49:20] wire _s2_has_permission_r_T_58 = _s2_has_permission_r_T == 4'h3; // @[Misc.scala:49:20] wire s2_has_permission_r_1 = _s2_has_permission_r_T_58 | _s2_has_permission_r_T_56; // @[Misc.scala:35:9, :49:20] wire s2_has_permission_0 = s2_has_permission_r_1; // @[Misc.scala:35:9] wire [1:0] s2_has_permission_r_2 = _s2_has_permission_r_T_58 ? 2'h3 : _s2_has_permission_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_has_permission_meta_state = s2_has_permission_r_2; // @[Misc.scala:35:36] wire _s2_new_hit_state_r_c_cat_T_2 = _s2_new_hit_state_r_c_cat_T | _s2_new_hit_state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _s2_new_hit_state_r_c_cat_T_4 = _s2_new_hit_state_r_c_cat_T_2 | _s2_new_hit_state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _s2_new_hit_state_r_c_cat_T_9 = _s2_new_hit_state_r_c_cat_T_5 | _s2_new_hit_state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_10 = _s2_new_hit_state_r_c_cat_T_9 | _s2_new_hit_state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_11 = _s2_new_hit_state_r_c_cat_T_10 | _s2_new_hit_state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_17 = _s2_new_hit_state_r_c_cat_T_12 | _s2_new_hit_state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_18 = _s2_new_hit_state_r_c_cat_T_17 | _s2_new_hit_state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_19 = _s2_new_hit_state_r_c_cat_T_18 | _s2_new_hit_state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_20 = _s2_new_hit_state_r_c_cat_T_19 | _s2_new_hit_state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_21 = _s2_new_hit_state_r_c_cat_T_11 | _s2_new_hit_state_r_c_cat_T_20; // @[package.scala:81:59] wire _s2_new_hit_state_r_c_cat_T_22 = _s2_new_hit_state_r_c_cat_T_4 | _s2_new_hit_state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _s2_new_hit_state_r_c_cat_T_25 = _s2_new_hit_state_r_c_cat_T_23 | _s2_new_hit_state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _s2_new_hit_state_r_c_cat_T_27 = _s2_new_hit_state_r_c_cat_T_25 | _s2_new_hit_state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _s2_new_hit_state_r_c_cat_T_32 = _s2_new_hit_state_r_c_cat_T_28 | _s2_new_hit_state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_33 = _s2_new_hit_state_r_c_cat_T_32 | _s2_new_hit_state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_34 = _s2_new_hit_state_r_c_cat_T_33 | _s2_new_hit_state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_40 = _s2_new_hit_state_r_c_cat_T_35 | _s2_new_hit_state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_41 = _s2_new_hit_state_r_c_cat_T_40 | _s2_new_hit_state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_42 = _s2_new_hit_state_r_c_cat_T_41 | _s2_new_hit_state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_43 = _s2_new_hit_state_r_c_cat_T_42 | _s2_new_hit_state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _s2_new_hit_state_r_c_cat_T_44 = _s2_new_hit_state_r_c_cat_T_34 | _s2_new_hit_state_r_c_cat_T_43; // @[package.scala:81:59] wire _s2_new_hit_state_r_c_cat_T_45 = _s2_new_hit_state_r_c_cat_T_27 | _s2_new_hit_state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _s2_new_hit_state_r_c_cat_T_47 = _s2_new_hit_state_r_c_cat_T_45 | _s2_new_hit_state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _s2_new_hit_state_r_c_cat_T_49 = _s2_new_hit_state_r_c_cat_T_47 | _s2_new_hit_state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] s2_new_hit_state_r_c = {_s2_new_hit_state_r_c_cat_T_22, _s2_new_hit_state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _s2_new_hit_state_r_T = {s2_new_hit_state_r_c, s2_hit_state_0_state}; // @[Metadata.scala:29:18, :58:19] wire _s2_new_hit_state_r_T_25 = _s2_new_hit_state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _s2_new_hit_state_r_T_27 = {1'h0, _s2_new_hit_state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_28 = _s2_new_hit_state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _s2_new_hit_state_r_T_30 = _s2_new_hit_state_r_T_28 ? 2'h2 : _s2_new_hit_state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_31 = _s2_new_hit_state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _s2_new_hit_state_r_T_33 = _s2_new_hit_state_r_T_31 ? 2'h1 : _s2_new_hit_state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_34 = _s2_new_hit_state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _s2_new_hit_state_r_T_36 = _s2_new_hit_state_r_T_34 ? 2'h2 : _s2_new_hit_state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_37 = _s2_new_hit_state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _s2_new_hit_state_r_T_39 = _s2_new_hit_state_r_T_37 ? 2'h0 : _s2_new_hit_state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_40 = _s2_new_hit_state_r_T == 4'hE; // @[Misc.scala:49:20] wire _s2_new_hit_state_r_T_41 = _s2_new_hit_state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_new_hit_state_r_T_42 = _s2_new_hit_state_r_T_40 ? 2'h3 : _s2_new_hit_state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_43 = &_s2_new_hit_state_r_T; // @[Misc.scala:49:20] wire _s2_new_hit_state_r_T_44 = _s2_new_hit_state_r_T_43 | _s2_new_hit_state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_new_hit_state_r_T_45 = _s2_new_hit_state_r_T_43 ? 2'h3 : _s2_new_hit_state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_46 = _s2_new_hit_state_r_T == 4'h6; // @[Misc.scala:49:20] wire _s2_new_hit_state_r_T_47 = _s2_new_hit_state_r_T_46 | _s2_new_hit_state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_new_hit_state_r_T_48 = _s2_new_hit_state_r_T_46 ? 2'h2 : _s2_new_hit_state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_49 = _s2_new_hit_state_r_T == 4'h7; // @[Misc.scala:49:20] wire _s2_new_hit_state_r_T_50 = _s2_new_hit_state_r_T_49 | _s2_new_hit_state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_new_hit_state_r_T_51 = _s2_new_hit_state_r_T_49 ? 2'h3 : _s2_new_hit_state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_52 = _s2_new_hit_state_r_T == 4'h1; // @[Misc.scala:49:20] wire _s2_new_hit_state_r_T_53 = _s2_new_hit_state_r_T_52 | _s2_new_hit_state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_new_hit_state_r_T_54 = _s2_new_hit_state_r_T_52 ? 2'h1 : _s2_new_hit_state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_55 = _s2_new_hit_state_r_T == 4'h2; // @[Misc.scala:49:20] wire _s2_new_hit_state_r_T_56 = _s2_new_hit_state_r_T_55 | _s2_new_hit_state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _s2_new_hit_state_r_T_57 = _s2_new_hit_state_r_T_55 ? 2'h2 : _s2_new_hit_state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _s2_new_hit_state_r_T_58 = _s2_new_hit_state_r_T == 4'h3; // @[Misc.scala:49:20] wire s2_new_hit_state_r_1 = _s2_new_hit_state_r_T_58 | _s2_new_hit_state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] s2_new_hit_state_r_2 = _s2_new_hit_state_r_T_58 ? 2'h3 : _s2_new_hit_state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_new_hit_state_meta_state = s2_new_hit_state_r_2; // @[Misc.scala:35:36] wire [1:0] s2_new_hit_state_0_state = s2_new_hit_state_meta_state; // @[Metadata.scala:160:20] wire _s2_hit_T = s2_tag_match_0 & s2_has_permission_0; // @[dcache.scala:454:49, :682:49, :687:47] wire _s2_hit_T_1 = s2_hit_state_0_state == s2_new_hit_state_0_state; // @[Metadata.scala:46:46] wire _s2_hit_T_2 = _s2_hit_T & _s2_hit_T_1; // @[Metadata.scala:46:46] wire _s2_hit_T_3 = ~_mshrs_io_block_hit_0; // @[dcache.scala:460:21, :687:117] wire _s2_hit_T_4 = _s2_hit_T_2 & _s2_hit_T_3; // @[dcache.scala:687:{71,114,117}] wire _T_75 = s2_type == 3'h0; // @[package.scala:16:47] wire _s2_hit_T_5; // @[package.scala:16:47] assign _s2_hit_T_5 = _T_75; // @[package.scala:16:47] wire _s2_lr_T_2; // @[dcache.scala:701:83] assign _s2_lr_T_2 = _T_75; // @[package.scala:16:47] wire _s2_sc_T_2; // @[dcache.scala:702:83] assign _s2_sc_T_2 = _T_75; // @[package.scala:16:47] wire _s2_send_resp_T_3; // @[dcache.scala:774:77] assign _s2_send_resp_T_3 = _T_75; // @[package.scala:16:47] wire _s2_hit_T_6 = s2_type == 3'h2; // @[package.scala:16:47] wire _s2_hit_T_7 = _s2_hit_T_5 | _s2_hit_T_6; // @[package.scala:16:47, :81:59] wire _s2_hit_T_8 = _s2_hit_T_4 | _s2_hit_T_7; // @[package.scala:81:59] wire s2_hit_0 = _s2_hit_T_8; // @[dcache.scala:454:49, :687:141] wire s2_nack_0; // @[dcache.scala:688:21] reg s2_wb_idx_matches_0; // @[dcache.scala:692:34] reg [39:0] debug_sc_fail_addr; // @[dcache.scala:695:35] reg [7:0] debug_sc_fail_cnt; // @[dcache.scala:696:35] reg [6:0] lrsc_count; // @[dcache.scala:698:27] wire lrsc_valid = |(lrsc_count[6:2]); // @[dcache.scala:698:27, :699:31] reg [33:0] lrsc_addr; // @[dcache.scala:700:23] reg s2_lr_REG; // @[dcache.scala:701:59] wire _s2_lr_T_1 = ~s2_lr_REG; // @[dcache.scala:701:{51,59}] wire _s2_lr_T_3 = _s2_lr_T_1 | _s2_lr_T_2; // @[dcache.scala:701:{51,72,83}] wire s2_lr = _s2_lr_T & _s2_lr_T_3; // @[dcache.scala:701:{37,47,72}] reg s2_sc_REG; // @[dcache.scala:702:59] wire _s2_sc_T_1 = ~s2_sc_REG; // @[dcache.scala:702:{51,59}] wire _s2_sc_T_3 = _s2_sc_T_1 | _s2_sc_T_2; // @[dcache.scala:702:{51,72,83}] wire s2_sc = _s2_sc_T & _s2_sc_T_3; // @[dcache.scala:702:{37,47,72}] wire io_lsu_resp_0_bits_data_doZero_2 = s2_sc; // @[AMOALU.scala:43:31] wire [33:0] _s2_lrsc_addr_match_T = s2_req_0_addr[39:6]; // @[dcache.scala:670:25, :703:86] wire [33:0] _lrsc_addr_T = s2_req_0_addr[39:6]; // @[dcache.scala:670:25, :703:86, :710:35] wire _s2_lrsc_addr_match_T_1 = lrsc_addr == _s2_lrsc_addr_match_T; // @[dcache.scala:700:23, :703:{66,86}] wire _s2_lrsc_addr_match_T_2 = lrsc_valid & _s2_lrsc_addr_match_T_1; // @[dcache.scala:699:31, :703:{53,66}] wire s2_lrsc_addr_match_0 = _s2_lrsc_addr_match_T_2; // @[dcache.scala:454:49, :703:53] wire _s2_sc_fail_T = ~s2_lrsc_addr_match_0; // @[dcache.scala:454:49, :704:29] wire s2_sc_fail = s2_sc & _s2_sc_fail_T; // @[dcache.scala:702:47, :704:{26,29}] wire [7:0] _lrsc_count_T = {1'h0, lrsc_count} - 8'h1; // @[dcache.scala:698:27, :705:54] wire [6:0] _lrsc_count_T_1 = _lrsc_count_T[6:0]; // @[dcache.scala:705:54] wire _mshrs_io_req_0_valid_T_10 = s2_type == 3'h4; // @[package.scala:16:47] wire [8:0] _debug_sc_fail_cnt_T = {1'h0, debug_sc_fail_cnt} + 9'h1; // @[dcache.scala:696:35, :730:48] wire [7:0] _debug_sc_fail_cnt_T_1 = _debug_sc_fail_cnt_T[7:0]; // @[dcache.scala:730:48] wire [127:0] s2_data_0_0; // @[dcache.scala:743:21] wire [127:0] s2_data_0_1; // @[dcache.scala:743:21] wire [127:0] s2_data_0_2; // @[dcache.scala:743:21] wire [127:0] s2_data_0_3; // @[dcache.scala:743:21] wire [127:0] s2_data_0_4; // @[dcache.scala:743:21] wire [127:0] s2_data_0_5; // @[dcache.scala:743:21] wire [127:0] s2_data_0_6; // @[dcache.scala:743:21] wire [127:0] s2_data_0_7; // @[dcache.scala:743:21] wire [127:0] _s2_data_muxed_T_8 = _s2_data_muxed_T ? s2_data_0_0 : 128'h0; // @[Mux.scala:30:73, :32:36] wire [127:0] _s2_data_muxed_T_9 = _s2_data_muxed_T_1 ? s2_data_0_1 : 128'h0; // @[Mux.scala:30:73, :32:36] wire [127:0] _s2_data_muxed_T_10 = _s2_data_muxed_T_2 ? s2_data_0_2 : 128'h0; // @[Mux.scala:30:73, :32:36] wire [127:0] _s2_data_muxed_T_11 = _s2_data_muxed_T_3 ? s2_data_0_3 : 128'h0; // @[Mux.scala:30:73, :32:36] wire [127:0] _s2_data_muxed_T_12 = _s2_data_muxed_T_4 ? s2_data_0_4 : 128'h0; // @[Mux.scala:30:73, :32:36] wire [127:0] _s2_data_muxed_T_13 = _s2_data_muxed_T_5 ? s2_data_0_5 : 128'h0; // @[Mux.scala:30:73, :32:36] wire [127:0] _s2_data_muxed_T_14 = _s2_data_muxed_T_6 ? s2_data_0_6 : 128'h0; // @[Mux.scala:30:73, :32:36] wire [127:0] _s2_data_muxed_T_15 = _s2_data_muxed_T_7 ? s2_data_0_7 : 128'h0; // @[Mux.scala:30:73, :32:36] wire [127:0] _s2_data_muxed_T_16 = _s2_data_muxed_T_8 | _s2_data_muxed_T_9; // @[Mux.scala:30:73] wire [127:0] _s2_data_muxed_T_17 = _s2_data_muxed_T_16 | _s2_data_muxed_T_10; // @[Mux.scala:30:73] wire [127:0] _s2_data_muxed_T_18 = _s2_data_muxed_T_17 | _s2_data_muxed_T_11; // @[Mux.scala:30:73] wire [127:0] _s2_data_muxed_T_19 = _s2_data_muxed_T_18 | _s2_data_muxed_T_12; // @[Mux.scala:30:73] wire [127:0] _s2_data_muxed_T_20 = _s2_data_muxed_T_19 | _s2_data_muxed_T_13; // @[Mux.scala:30:73] wire [127:0] _s2_data_muxed_T_21 = _s2_data_muxed_T_20 | _s2_data_muxed_T_14; // @[Mux.scala:30:73] wire [127:0] _s2_data_muxed_T_22 = _s2_data_muxed_T_21 | _s2_data_muxed_T_15; // @[Mux.scala:30:73] wire [127:0] _s2_data_muxed_WIRE = _s2_data_muxed_T_22; // @[Mux.scala:30:73] wire [127:0] s2_data_muxed_0 = _s2_data_muxed_WIRE; // @[Mux.scala:30:73] wire _s2_word_idx_T = s2_req_0_addr[3]; // @[dcache.scala:670:25, :751:79] wire s2_word_idx_0 = _s2_word_idx_T; // @[dcache.scala:454:49, :751:79] wire replace; // @[Replacement.scala:37:29] wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17] wire [2:0] _s1_replaced_way_en_T = lfsr[2:0]; // @[PRNG.scala:95:17] wire [2:0] _s2_replaced_way_en_T = lfsr[2:0]; // @[PRNG.scala:95:17] wire [7:0] s1_replaced_way_en = 8'h1 << _s1_replaced_way_en_T; // @[OneHot.scala:58:35] reg [2:0] s2_replaced_way_en_REG; // @[dcache.scala:756:44] wire [7:0] s2_replaced_way_en = 8'h1 << s2_replaced_way_en_REG; // @[OneHot.scala:58:35] reg [1:0] s2_repl_meta_REG_coh_state; // @[dcache.scala:757:88] wire [1:0] _s2_repl_meta_WIRE_0_coh_state = s2_repl_meta_REG_coh_state; // @[dcache.scala:656:47, :757:88] reg [19:0] s2_repl_meta_REG_tag; // @[dcache.scala:757:88] wire [19:0] _s2_repl_meta_WIRE_0_tag = s2_repl_meta_REG_tag; // @[dcache.scala:656:47, :757:88] reg [1:0] s2_repl_meta_REG_1_coh_state; // @[dcache.scala:757:88] wire [1:0] _s2_repl_meta_WIRE_1_coh_state_0 = s2_repl_meta_REG_1_coh_state; // @[dcache.scala:656:47, :757:88] reg [19:0] s2_repl_meta_REG_1_tag; // @[dcache.scala:757:88] wire [19:0] _s2_repl_meta_WIRE_1_tag_0 = s2_repl_meta_REG_1_tag; // @[dcache.scala:656:47, :757:88] reg [1:0] s2_repl_meta_REG_2_coh_state; // @[dcache.scala:757:88] wire [1:0] _s2_repl_meta_WIRE_2_coh_state = s2_repl_meta_REG_2_coh_state; // @[dcache.scala:656:47, :757:88] reg [19:0] s2_repl_meta_REG_2_tag; // @[dcache.scala:757:88] wire [19:0] _s2_repl_meta_WIRE_2_tag = s2_repl_meta_REG_2_tag; // @[dcache.scala:656:47, :757:88] reg [1:0] s2_repl_meta_REG_3_coh_state; // @[dcache.scala:757:88] wire [1:0] _s2_repl_meta_WIRE_3_coh_state = s2_repl_meta_REG_3_coh_state; // @[dcache.scala:656:47, :757:88] reg [19:0] s2_repl_meta_REG_3_tag; // @[dcache.scala:757:88] wire [19:0] _s2_repl_meta_WIRE_3_tag = s2_repl_meta_REG_3_tag; // @[dcache.scala:656:47, :757:88] reg [1:0] s2_repl_meta_REG_4_coh_state; // @[dcache.scala:757:88] wire [1:0] _s2_repl_meta_WIRE_4_coh_state = s2_repl_meta_REG_4_coh_state; // @[dcache.scala:656:47, :757:88] reg [19:0] s2_repl_meta_REG_4_tag; // @[dcache.scala:757:88] wire [19:0] _s2_repl_meta_WIRE_4_tag = s2_repl_meta_REG_4_tag; // @[dcache.scala:656:47, :757:88] reg [1:0] s2_repl_meta_REG_5_coh_state; // @[dcache.scala:757:88] wire [1:0] _s2_repl_meta_WIRE_5_coh_state = s2_repl_meta_REG_5_coh_state; // @[dcache.scala:656:47, :757:88] reg [19:0] s2_repl_meta_REG_5_tag; // @[dcache.scala:757:88] wire [19:0] _s2_repl_meta_WIRE_5_tag = s2_repl_meta_REG_5_tag; // @[dcache.scala:656:47, :757:88] reg [1:0] s2_repl_meta_REG_6_coh_state; // @[dcache.scala:757:88] wire [1:0] _s2_repl_meta_WIRE_6_coh_state = s2_repl_meta_REG_6_coh_state; // @[dcache.scala:656:47, :757:88] reg [19:0] s2_repl_meta_REG_6_tag; // @[dcache.scala:757:88] wire [19:0] _s2_repl_meta_WIRE_6_tag = s2_repl_meta_REG_6_tag; // @[dcache.scala:656:47, :757:88] reg [1:0] s2_repl_meta_REG_7_coh_state; // @[dcache.scala:757:88] wire [1:0] _s2_repl_meta_WIRE_7_coh_state = s2_repl_meta_REG_7_coh_state; // @[dcache.scala:656:47, :757:88] reg [19:0] s2_repl_meta_REG_7_tag; // @[dcache.scala:757:88] wire [19:0] _s2_repl_meta_WIRE_7_tag = s2_repl_meta_REG_7_tag; // @[dcache.scala:656:47, :757:88] wire _s2_repl_meta_T = s2_replaced_way_en[0]; // @[OneHot.scala:58:35] wire _s2_repl_meta_T_1 = s2_replaced_way_en[1]; // @[OneHot.scala:58:35] wire _s2_repl_meta_T_2 = s2_replaced_way_en[2]; // @[OneHot.scala:58:35] wire _s2_repl_meta_T_3 = s2_replaced_way_en[3]; // @[OneHot.scala:58:35] wire _s2_repl_meta_T_4 = s2_replaced_way_en[4]; // @[OneHot.scala:58:35] wire _s2_repl_meta_T_5 = s2_replaced_way_en[5]; // @[OneHot.scala:58:35] wire _s2_repl_meta_T_6 = s2_replaced_way_en[6]; // @[OneHot.scala:58:35] wire _s2_repl_meta_T_7 = s2_replaced_way_en[7]; // @[OneHot.scala:58:35] wire [1:0] _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73] wire [1:0] s2_repl_meta_0_coh_state = _s2_repl_meta_WIRE_1_coh_state; // @[Mux.scala:30:73] wire [19:0] s2_repl_meta_0_tag = _s2_repl_meta_WIRE_1_tag; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_T_8 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_repl_meta_T_9 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_tag_0 : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_repl_meta_T_10 = _s2_repl_meta_T_2 ? _s2_repl_meta_WIRE_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_repl_meta_T_11 = _s2_repl_meta_T_3 ? _s2_repl_meta_WIRE_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_repl_meta_T_12 = _s2_repl_meta_T_4 ? _s2_repl_meta_WIRE_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_repl_meta_T_13 = _s2_repl_meta_T_5 ? _s2_repl_meta_WIRE_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_repl_meta_T_14 = _s2_repl_meta_T_6 ? _s2_repl_meta_WIRE_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_repl_meta_T_15 = _s2_repl_meta_T_7 ? _s2_repl_meta_WIRE_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_repl_meta_T_16 = _s2_repl_meta_T_8 | _s2_repl_meta_T_9; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_T_17 = _s2_repl_meta_T_16 | _s2_repl_meta_T_10; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_T_18 = _s2_repl_meta_T_17 | _s2_repl_meta_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_T_19 = _s2_repl_meta_T_18 | _s2_repl_meta_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_T_20 = _s2_repl_meta_T_19 | _s2_repl_meta_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_T_21 = _s2_repl_meta_T_20 | _s2_repl_meta_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_repl_meta_T_22 = _s2_repl_meta_T_21 | _s2_repl_meta_T_15; // @[Mux.scala:30:73] assign _s2_repl_meta_WIRE_2 = _s2_repl_meta_T_22; // @[Mux.scala:30:73] assign _s2_repl_meta_WIRE_1_tag = _s2_repl_meta_WIRE_2; // @[Mux.scala:30:73] wire [1:0] _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73] assign _s2_repl_meta_WIRE_1_coh_state = _s2_repl_meta_WIRE_3_state; // @[Mux.scala:30:73] wire [1:0] _s2_repl_meta_T_23 = _s2_repl_meta_T ? _s2_repl_meta_WIRE_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_repl_meta_T_24 = _s2_repl_meta_T_1 ? _s2_repl_meta_WIRE_1_coh_state_0 : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_repl_meta_T_25 = _s2_repl_meta_T_2 ? _s2_repl_meta_WIRE_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_repl_meta_T_26 = _s2_repl_meta_T_3 ? _s2_repl_meta_WIRE_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_repl_meta_T_27 = _s2_repl_meta_T_4 ? _s2_repl_meta_WIRE_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_repl_meta_T_28 = _s2_repl_meta_T_5 ? _s2_repl_meta_WIRE_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_repl_meta_T_29 = _s2_repl_meta_T_6 ? _s2_repl_meta_WIRE_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_repl_meta_T_30 = _s2_repl_meta_T_7 ? _s2_repl_meta_WIRE_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_repl_meta_T_31 = _s2_repl_meta_T_23 | _s2_repl_meta_T_24; // @[Mux.scala:30:73] wire [1:0] _s2_repl_meta_T_32 = _s2_repl_meta_T_31 | _s2_repl_meta_T_25; // @[Mux.scala:30:73] wire [1:0] _s2_repl_meta_T_33 = _s2_repl_meta_T_32 | _s2_repl_meta_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_repl_meta_T_34 = _s2_repl_meta_T_33 | _s2_repl_meta_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_repl_meta_T_35 = _s2_repl_meta_T_34 | _s2_repl_meta_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_repl_meta_T_36 = _s2_repl_meta_T_35 | _s2_repl_meta_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_repl_meta_T_37 = _s2_repl_meta_T_36 | _s2_repl_meta_T_30; // @[Mux.scala:30:73] assign _s2_repl_meta_WIRE_4 = _s2_repl_meta_T_37; // @[Mux.scala:30:73] assign _s2_repl_meta_WIRE_3_state = _s2_repl_meta_WIRE_4; // @[Mux.scala:30:73] wire [19:0] mshrs_io_req_0_bits_old_meta_meta_tag = s2_repl_meta_0_tag; // @[HellaCache.scala:305:20] reg s2_nack_hit_0; // @[dcache.scala:760:31] wire _GEN_16 = s2_valid_0 & s2_hit_0; // @[dcache.scala:454:49, :762:50] wire _s2_nack_victim_T; // @[dcache.scala:762:50] assign _s2_nack_victim_T = _GEN_16; // @[dcache.scala:762:50] wire _s3_valid_T; // @[dcache.scala:897:38] assign _s3_valid_T = _GEN_16; // @[dcache.scala:762:50, :897:38] wire _s2_nack_victim_T_1 = _s2_nack_victim_T & _mshrs_io_secondary_miss_0; // @[dcache.scala:460:21, :762:{50,64}] wire s2_nack_victim_0 = _s2_nack_victim_T_1; // @[dcache.scala:454:49, :762:64] wire _s2_nack_miss_T = ~s2_hit_0; // @[dcache.scala:454:49, :689:36, :764:53] wire _s2_nack_miss_T_1 = s2_valid_0 & _s2_nack_miss_T; // @[dcache.scala:454:49, :764:{50,53}] wire _s2_nack_miss_T_2 = ~_mshrs_io_req_0_ready; // @[dcache.scala:460:21, :764:67] wire _s2_nack_miss_T_3 = _s2_nack_miss_T_1 & _s2_nack_miss_T_2; // @[dcache.scala:764:{50,64,67}] wire s2_nack_miss_0 = _s2_nack_miss_T_3; // @[dcache.scala:454:49, :764:64] wire _s2_nack_wb_T = ~s2_hit_0; // @[dcache.scala:454:49, :689:36, :768:53] wire _s2_nack_wb_T_1 = s2_valid_0 & _s2_nack_wb_T; // @[dcache.scala:454:49, :768:{50,53}] wire _s2_nack_wb_T_2 = _s2_nack_wb_T_1 & s2_wb_idx_matches_0; // @[dcache.scala:692:34, :768:{50,64}] wire s2_nack_wb_0 = _s2_nack_wb_T_2; // @[dcache.scala:454:49, :768:64] assign s2_nack_0 = (s2_nack_miss_0 | s2_nack_hit_0 | s2_nack_victim_0 | s2_nack_wb_0) & (|s2_type); // @[dcache.scala:454:49, :671:25, :688:21, :760:31, :770:{55,73,113,131,142}] reg s2_send_resp_REG; // @[dcache.scala:773:12] wire _s2_send_resp_T = s2_nack_hit_0 | s2_nack_victim_0; // @[dcache.scala:454:49, :760:31, :774:25] wire _s2_send_resp_T_1 = _s2_send_resp_T; // @[dcache.scala:774:{25,46}] wire _s2_send_resp_T_2 = ~_s2_send_resp_T_1; // @[dcache.scala:774:{8,46}] wire _s2_send_resp_T_4 = _s2_send_resp_T_2 | _s2_send_resp_T_3; // @[dcache.scala:774:{8,66,77}] wire _s2_send_resp_T_5 = s2_send_resp_REG & _s2_send_resp_T_4; // @[dcache.scala:773:{12,38}, :774:66] wire _s2_send_resp_T_6 = _s2_send_resp_T_5 & s2_hit_0; // @[dcache.scala:454:49, :773:38, :774:91] wire _GEN_17 = s2_req_0_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _s2_send_resp_T_7; // @[package.scala:16:47] assign _s2_send_resp_T_7 = _GEN_17; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_20; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_20 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = s2_req_0_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _s2_send_resp_T_8; // @[package.scala:16:47] assign _s2_send_resp_T_8 = _GEN_18; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_21; // @[package.scala:16:47] assign _mshrs_io_req_0_valid_T_21 = _GEN_18; // @[package.scala:16:47] wire _s2_send_resp_T_11 = _s2_send_resp_T_7 | _s2_send_resp_T_8; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_12 = _s2_send_resp_T_11 | _s2_send_resp_T_9; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_13 = _s2_send_resp_T_12 | _s2_send_resp_T_10; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_18 = _s2_send_resp_T_14 | _s2_send_resp_T_15; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_19 = _s2_send_resp_T_18 | _s2_send_resp_T_16; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_20 = _s2_send_resp_T_19 | _s2_send_resp_T_17; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_26 = _s2_send_resp_T_21 | _s2_send_resp_T_22; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_27 = _s2_send_resp_T_26 | _s2_send_resp_T_23; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_28 = _s2_send_resp_T_27 | _s2_send_resp_T_24; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_29 = _s2_send_resp_T_28 | _s2_send_resp_T_25; // @[package.scala:16:47, :81:59] wire _s2_send_resp_T_30 = _s2_send_resp_T_20 | _s2_send_resp_T_29; // @[package.scala:81:59] wire _s2_send_resp_T_31 = _s2_send_resp_T_13 | _s2_send_resp_T_30; // @[package.scala:81:59] wire _s2_send_resp_T_32 = _s2_send_resp_T_6 & _s2_send_resp_T_31; // @[Consts.scala:89:68] wire s2_send_resp_0 = _s2_send_resp_T_32; // @[dcache.scala:454:49, :775:17] reg s2_send_store_ack_REG; // @[dcache.scala:778:12] wire _s2_send_store_ack_T = ~s2_nack_0; // @[dcache.scala:688:21, :706:60, :778:41] wire _s2_send_store_ack_T_1 = s2_send_store_ack_REG & _s2_send_store_ack_T; // @[dcache.scala:778:{12,38,41}] wire _s2_send_store_ack_T_4 = _s2_send_store_ack_T_2 | _s2_send_store_ack_T_3; // @[Consts.scala:90:{32,42,49}] wire _s2_send_store_ack_T_6 = _s2_send_store_ack_T_4 | _s2_send_store_ack_T_5; // @[Consts.scala:90:{42,59,66}] wire _s2_send_store_ack_T_11 = _s2_send_store_ack_T_7 | _s2_send_store_ack_T_8; // @[package.scala:16:47, :81:59] wire _s2_send_store_ack_T_12 = _s2_send_store_ack_T_11 | _s2_send_store_ack_T_9; // @[package.scala:16:47, :81:59] wire _s2_send_store_ack_T_13 = _s2_send_store_ack_T_12 | _s2_send_store_ack_T_10; // @[package.scala:16:47, :81:59] wire _s2_send_store_ack_T_19 = _s2_send_store_ack_T_14 | _s2_send_store_ack_T_15; // @[package.scala:16:47, :81:59] wire _s2_send_store_ack_T_20 = _s2_send_store_ack_T_19 | _s2_send_store_ack_T_16; // @[package.scala:16:47, :81:59] wire _s2_send_store_ack_T_21 = _s2_send_store_ack_T_20 | _s2_send_store_ack_T_17; // @[package.scala:16:47, :81:59] wire _s2_send_store_ack_T_22 = _s2_send_store_ack_T_21 | _s2_send_store_ack_T_18; // @[package.scala:16:47, :81:59] wire _s2_send_store_ack_T_23 = _s2_send_store_ack_T_13 | _s2_send_store_ack_T_22; // @[package.scala:81:59] wire _s2_send_store_ack_T_24 = _s2_send_store_ack_T_6 | _s2_send_store_ack_T_23; // @[Consts.scala:87:44, :90:{59,76}] wire _s2_send_store_ack_T_25 = _s2_send_store_ack_T_1 & _s2_send_store_ack_T_24; // @[Consts.scala:90:76] wire _mshrs_io_req_0_valid_T_70; // @[dcache.scala:798:77] wire _T_81 = _mshrs_io_req_0_ready & _mshrs_io_req_0_valid_T_70; // @[Decoupled.scala:51:35] assign replace = _T_81; // @[Decoupled.scala:51:35] wire _s2_send_store_ack_T_26; // @[Decoupled.scala:51:35] assign _s2_send_store_ack_T_26 = _T_81; // @[Decoupled.scala:51:35] wire _s2_send_store_ack_T_27 = s2_hit_0 | _s2_send_store_ack_T_26; // @[Decoupled.scala:51:35] wire _s2_send_store_ack_T_28 = _s2_send_store_ack_T_25 & _s2_send_store_ack_T_27; // @[dcache.scala:778:{53,87}, :779:18] wire s2_send_store_ack_0 = _s2_send_store_ack_T_28; // @[dcache.scala:454:49, :778:87] reg s2_send_nack_REG; // @[dcache.scala:780:44] wire _s2_send_nack_T = s2_send_nack_REG & s2_nack_0; // @[dcache.scala:688:21, :780:{44,70}] wire s2_send_nack_0 = _s2_send_nack_T; // @[dcache.scala:454:49, :780:70] wire _s2_store_failed_T = s2_valid_0 & s2_nack_0; // @[dcache.scala:454:49, :688:21, :787:34] wire _s2_store_failed_T_1 = _s2_store_failed_T & s2_send_nack_0; // @[dcache.scala:454:49, :787:{34,48}] assign _s2_store_failed_T_2 = _s2_store_failed_T_1 & s2_req_0_uop_uses_stq; // @[dcache.scala:670:25, :787:{48,67}] assign s2_store_failed = _s2_store_failed_T_2; // @[dcache.scala:636:29, :787:67] wire _mshrs_io_req_0_valid_T = ~s2_hit_0; // @[dcache.scala:454:49, :689:36, :792:29] wire _mshrs_io_req_0_valid_T_1 = s2_valid_0 & _mshrs_io_req_0_valid_T; // @[dcache.scala:454:49, :791:51, :792:29] wire _mshrs_io_req_0_valid_T_2 = ~s2_nack_hit_0; // @[dcache.scala:760:31, :793:29] wire _mshrs_io_req_0_valid_T_3 = _mshrs_io_req_0_valid_T_1 & _mshrs_io_req_0_valid_T_2; // @[dcache.scala:791:51, :792:51, :793:29] wire _mshrs_io_req_0_valid_T_4 = ~s2_nack_victim_0; // @[dcache.scala:454:49, :794:29] wire _mshrs_io_req_0_valid_T_5 = _mshrs_io_req_0_valid_T_3 & _mshrs_io_req_0_valid_T_4; // @[dcache.scala:792:51, :793:51, :794:29] wire _mshrs_io_req_0_valid_T_7 = _mshrs_io_req_0_valid_T_5; // @[dcache.scala:793:51, :794:51] wire _mshrs_io_req_0_valid_T_8 = ~s2_nack_wb_0; // @[dcache.scala:454:49, :796:29] wire _mshrs_io_req_0_valid_T_9 = _mshrs_io_req_0_valid_T_7 & _mshrs_io_req_0_valid_T_8; // @[dcache.scala:794:51, :795:51, :796:29] wire _mshrs_io_req_0_valid_T_11 = s2_type == 3'h5; // @[package.scala:16:47] wire _mshrs_io_req_0_valid_T_12 = _mshrs_io_req_0_valid_T_10 | _mshrs_io_req_0_valid_T_11; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_13 = _mshrs_io_req_0_valid_T_9 & _mshrs_io_req_0_valid_T_12; // @[package.scala:81:59] wire _mshrs_io_req_0_valid_T_14 = io_lsu_exception_0 & s2_req_0_uop_uses_ldq; // @[dcache.scala:438:7, :670:25, :798:48] wire _mshrs_io_req_0_valid_T_15 = ~_mshrs_io_req_0_valid_T_14; // @[dcache.scala:798:{29,48}] wire _mshrs_io_req_0_valid_T_16 = _mshrs_io_req_0_valid_T_13 & _mshrs_io_req_0_valid_T_15; // @[dcache.scala:796:51, :797:77, :798:29] wire _mshrs_io_req_0_valid_T_17 = s2_req_0_uop_mem_cmd == 5'h2; // @[Consts.scala:88:35] wire _mshrs_io_req_0_valid_T_19 = _mshrs_io_req_0_valid_T_17 | _mshrs_io_req_0_valid_T_18; // @[Consts.scala:88:{35,45,52}] wire _mshrs_io_req_0_valid_T_24 = _mshrs_io_req_0_valid_T_20 | _mshrs_io_req_0_valid_T_21; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_25 = _mshrs_io_req_0_valid_T_24 | _mshrs_io_req_0_valid_T_22; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_26 = _mshrs_io_req_0_valid_T_25 | _mshrs_io_req_0_valid_T_23; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_31 = _mshrs_io_req_0_valid_T_27 | _mshrs_io_req_0_valid_T_28; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_32 = _mshrs_io_req_0_valid_T_31 | _mshrs_io_req_0_valid_T_29; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_33 = _mshrs_io_req_0_valid_T_32 | _mshrs_io_req_0_valid_T_30; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_39 = _mshrs_io_req_0_valid_T_34 | _mshrs_io_req_0_valid_T_35; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_40 = _mshrs_io_req_0_valid_T_39 | _mshrs_io_req_0_valid_T_36; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_41 = _mshrs_io_req_0_valid_T_40 | _mshrs_io_req_0_valid_T_37; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_42 = _mshrs_io_req_0_valid_T_41 | _mshrs_io_req_0_valid_T_38; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_43 = _mshrs_io_req_0_valid_T_33 | _mshrs_io_req_0_valid_T_42; // @[package.scala:81:59] wire _mshrs_io_req_0_valid_T_44 = _mshrs_io_req_0_valid_T_26 | _mshrs_io_req_0_valid_T_43; // @[package.scala:81:59] wire _mshrs_io_req_0_valid_T_45 = _mshrs_io_req_0_valid_T_19 | _mshrs_io_req_0_valid_T_44; // @[Consts.scala:88:45, :89:68] wire _mshrs_io_req_0_valid_T_48 = _mshrs_io_req_0_valid_T_46 | _mshrs_io_req_0_valid_T_47; // @[Consts.scala:90:{32,42,49}] wire _mshrs_io_req_0_valid_T_50 = _mshrs_io_req_0_valid_T_48 | _mshrs_io_req_0_valid_T_49; // @[Consts.scala:90:{42,59,66}] wire _mshrs_io_req_0_valid_T_55 = _mshrs_io_req_0_valid_T_51 | _mshrs_io_req_0_valid_T_52; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_56 = _mshrs_io_req_0_valid_T_55 | _mshrs_io_req_0_valid_T_53; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_57 = _mshrs_io_req_0_valid_T_56 | _mshrs_io_req_0_valid_T_54; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_63 = _mshrs_io_req_0_valid_T_58 | _mshrs_io_req_0_valid_T_59; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_64 = _mshrs_io_req_0_valid_T_63 | _mshrs_io_req_0_valid_T_60; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_65 = _mshrs_io_req_0_valid_T_64 | _mshrs_io_req_0_valid_T_61; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_66 = _mshrs_io_req_0_valid_T_65 | _mshrs_io_req_0_valid_T_62; // @[package.scala:16:47, :81:59] wire _mshrs_io_req_0_valid_T_67 = _mshrs_io_req_0_valid_T_57 | _mshrs_io_req_0_valid_T_66; // @[package.scala:81:59] wire _mshrs_io_req_0_valid_T_68 = _mshrs_io_req_0_valid_T_50 | _mshrs_io_req_0_valid_T_67; // @[Consts.scala:87:44, :90:{59,76}] wire _mshrs_io_req_0_valid_T_69 = _mshrs_io_req_0_valid_T_45 | _mshrs_io_req_0_valid_T_68; // @[Consts.scala:90:76] assign _mshrs_io_req_0_valid_T_70 = _mshrs_io_req_0_valid_T_16 & _mshrs_io_req_0_valid_T_69; // @[dcache.scala:797:77, :798:77, :800:65] wire [1:0] _mshrs_io_req_0_bits_old_meta_T_coh_state = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_coh_state : s2_repl_meta_0_coh_state; // @[HellaCache.scala:305:20] wire [19:0] _mshrs_io_req_0_bits_old_meta_T_tag = s2_tag_match_0 ? mshrs_io_req_0_bits_old_meta_meta_tag : s2_repl_meta_0_tag; // @[HellaCache.scala:305:20] wire [7:0] _mshrs_io_req_0_bits_way_en_T = s2_tag_match_0 ? s2_tag_match_way_0 : s2_replaced_way_en; // @[OneHot.scala:58:35] wire _mshrs_io_req_is_probe_0_T = s2_type == 3'h1; // @[dcache.scala:671:25, :812:49] wire _mshrs_io_req_is_probe_0_T_1 = _mshrs_io_req_is_probe_0_T & s2_valid_0; // @[dcache.scala:454:49, :812:{49,61}] wire _mshrs_io_meta_resp_valid_T = ~s2_nack_hit_0; // @[dcache.scala:760:31, :793:29, :815:36] wire _mshrs_io_meta_resp_valid_T_1 = _mshrs_io_meta_resp_valid_T | _prober_io_mshr_wb_rdy; // @[dcache.scala:459:22, :815:{36,52}] reg [1:0] mshrs_io_meta_resp_bits_REG_0_coh_state; // @[dcache.scala:816:70] reg [19:0] mshrs_io_meta_resp_bits_REG_0_tag; // @[dcache.scala:816:70] reg [1:0] mshrs_io_meta_resp_bits_REG_1_coh_state; // @[dcache.scala:816:70] reg [19:0] mshrs_io_meta_resp_bits_REG_1_tag; // @[dcache.scala:816:70] reg [1:0] mshrs_io_meta_resp_bits_REG_2_coh_state; // @[dcache.scala:816:70] reg [19:0] mshrs_io_meta_resp_bits_REG_2_tag; // @[dcache.scala:816:70] reg [1:0] mshrs_io_meta_resp_bits_REG_3_coh_state; // @[dcache.scala:816:70] reg [19:0] mshrs_io_meta_resp_bits_REG_3_tag; // @[dcache.scala:816:70] reg [1:0] mshrs_io_meta_resp_bits_REG_4_coh_state; // @[dcache.scala:816:70] reg [19:0] mshrs_io_meta_resp_bits_REG_4_tag; // @[dcache.scala:816:70] reg [1:0] mshrs_io_meta_resp_bits_REG_5_coh_state; // @[dcache.scala:816:70] reg [19:0] mshrs_io_meta_resp_bits_REG_5_tag; // @[dcache.scala:816:70] reg [1:0] mshrs_io_meta_resp_bits_REG_6_coh_state; // @[dcache.scala:816:70] reg [19:0] mshrs_io_meta_resp_bits_REG_6_tag; // @[dcache.scala:816:70] reg [1:0] mshrs_io_meta_resp_bits_REG_7_coh_state; // @[dcache.scala:816:70] reg [19:0] mshrs_io_meta_resp_bits_REG_7_tag; // @[dcache.scala:816:70] wire [1:0] _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_T_8 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _mshrs_io_meta_resp_bits_T_9 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _mshrs_io_meta_resp_bits_T_10 = _mshrs_io_meta_resp_bits_T_2 ? mshrs_io_meta_resp_bits_REG_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _mshrs_io_meta_resp_bits_T_11 = _mshrs_io_meta_resp_bits_T_3 ? mshrs_io_meta_resp_bits_REG_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _mshrs_io_meta_resp_bits_T_12 = _mshrs_io_meta_resp_bits_T_4 ? mshrs_io_meta_resp_bits_REG_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _mshrs_io_meta_resp_bits_T_13 = _mshrs_io_meta_resp_bits_T_5 ? mshrs_io_meta_resp_bits_REG_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _mshrs_io_meta_resp_bits_T_14 = _mshrs_io_meta_resp_bits_T_6 ? mshrs_io_meta_resp_bits_REG_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _mshrs_io_meta_resp_bits_T_15 = _mshrs_io_meta_resp_bits_T_7 ? mshrs_io_meta_resp_bits_REG_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _mshrs_io_meta_resp_bits_T_16 = _mshrs_io_meta_resp_bits_T_8 | _mshrs_io_meta_resp_bits_T_9; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_T_17 = _mshrs_io_meta_resp_bits_T_16 | _mshrs_io_meta_resp_bits_T_10; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_T_18 = _mshrs_io_meta_resp_bits_T_17 | _mshrs_io_meta_resp_bits_T_11; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_T_19 = _mshrs_io_meta_resp_bits_T_18 | _mshrs_io_meta_resp_bits_T_12; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_T_20 = _mshrs_io_meta_resp_bits_T_19 | _mshrs_io_meta_resp_bits_T_13; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_T_21 = _mshrs_io_meta_resp_bits_T_20 | _mshrs_io_meta_resp_bits_T_14; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_T_22 = _mshrs_io_meta_resp_bits_T_21 | _mshrs_io_meta_resp_bits_T_15; // @[Mux.scala:30:73] assign _mshrs_io_meta_resp_bits_WIRE_1 = _mshrs_io_meta_resp_bits_T_22; // @[Mux.scala:30:73] wire [19:0] _mshrs_io_meta_resp_bits_WIRE_tag = _mshrs_io_meta_resp_bits_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_WIRE_coh_state = _mshrs_io_meta_resp_bits_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_T_23 = _mshrs_io_meta_resp_bits_T ? mshrs_io_meta_resp_bits_REG_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _mshrs_io_meta_resp_bits_T_24 = _mshrs_io_meta_resp_bits_T_1 ? mshrs_io_meta_resp_bits_REG_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _mshrs_io_meta_resp_bits_T_25 = _mshrs_io_meta_resp_bits_T_2 ? mshrs_io_meta_resp_bits_REG_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _mshrs_io_meta_resp_bits_T_26 = _mshrs_io_meta_resp_bits_T_3 ? mshrs_io_meta_resp_bits_REG_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _mshrs_io_meta_resp_bits_T_27 = _mshrs_io_meta_resp_bits_T_4 ? mshrs_io_meta_resp_bits_REG_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _mshrs_io_meta_resp_bits_T_28 = _mshrs_io_meta_resp_bits_T_5 ? mshrs_io_meta_resp_bits_REG_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _mshrs_io_meta_resp_bits_T_29 = _mshrs_io_meta_resp_bits_T_6 ? mshrs_io_meta_resp_bits_REG_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _mshrs_io_meta_resp_bits_T_30 = _mshrs_io_meta_resp_bits_T_7 ? mshrs_io_meta_resp_bits_REG_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _mshrs_io_meta_resp_bits_T_31 = _mshrs_io_meta_resp_bits_T_23 | _mshrs_io_meta_resp_bits_T_24; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_T_32 = _mshrs_io_meta_resp_bits_T_31 | _mshrs_io_meta_resp_bits_T_25; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_T_33 = _mshrs_io_meta_resp_bits_T_32 | _mshrs_io_meta_resp_bits_T_26; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_T_34 = _mshrs_io_meta_resp_bits_T_33 | _mshrs_io_meta_resp_bits_T_27; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_T_35 = _mshrs_io_meta_resp_bits_T_34 | _mshrs_io_meta_resp_bits_T_28; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_T_36 = _mshrs_io_meta_resp_bits_T_35 | _mshrs_io_meta_resp_bits_T_29; // @[Mux.scala:30:73] wire [1:0] _mshrs_io_meta_resp_bits_T_37 = _mshrs_io_meta_resp_bits_T_36 | _mshrs_io_meta_resp_bits_T_30; // @[Mux.scala:30:73] assign _mshrs_io_meta_resp_bits_WIRE_3 = _mshrs_io_meta_resp_bits_T_37; // @[Mux.scala:30:73] assign _mshrs_io_meta_resp_bits_WIRE_2_state = _mshrs_io_meta_resp_bits_WIRE_3; // @[Mux.scala:30:73] wire _prober_io_req_valid_T = ~lrsc_valid; // @[dcache.scala:699:31, :821:46] wire _prober_io_req_valid_T_1 = nodeOut_b_valid & _prober_io_req_valid_T; // @[MixedNode.scala:542:17] wire _nodeOut_b_ready_T = ~lrsc_valid; // @[dcache.scala:699:31, :821:46, :822:51] assign _nodeOut_b_ready_T_1 = _prober_io_req_ready & _nodeOut_b_ready_T; // @[dcache.scala:459:22, :822:{48,51}] assign nodeOut_b_ready = _nodeOut_b_ready_T_1; // @[MixedNode.scala:542:17] wire _prober_io_wb_rdy_T = _prober_io_meta_write_bits_idx != _wb_io_idx_bits; // @[dcache.scala:458:18, :459:22, :828:59] wire _prober_io_wb_rdy_T_1 = ~_wb_io_idx_valid; // @[dcache.scala:458:18, :828:82] wire _prober_io_wb_rdy_T_2 = _prober_io_wb_rdy_T | _prober_io_wb_rdy_T_1; // @[dcache.scala:828:{59,79,82}] wire _wb_io_mem_grant_T_1 = nodeOut_d_bits_source == 3'h4; // @[MixedNode.scala:542:17] assign nodeOut_d_ready = _wb_io_mem_grant_T_1 | _mshrs_io_mem_grant_ready; // @[MixedNode.scala:542:17] wire _wb_io_mem_grant_T = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire _wb_io_mem_grant_T_2 = _wb_io_mem_grant_T & _wb_io_mem_grant_T_1; // @[Decoupled.scala:51:35] wire opdata = _wb_io_release_bits_opcode[0]; // @[Edges.scala:102:36] wire [26:0] _decode_T_3 = 27'hFFF << _prober_io_rep_bits_size; // @[package.scala:243:71] wire [11:0] _decode_T_4 = _decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _decode_T_5 = ~_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] decode_1 = _decode_T_5[11:4]; // @[package.scala:243:46] reg [7:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_c_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {_prober_io_rep_valid, _wb_io_release_valid}; // @[Arbiter.scala:68:51] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & _wb_io_release_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & _prober_io_rep_valid; // @[Arbiter.scala:68:27, :71:69] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_c_valid_T = _wb_io_release_valid | _prober_io_rep_valid; // @[Arbiter.scala:79:31, :96:46] wire [7:0] maskedBeats_0 = winner_0 & opdata ? 8'h3 : 8'h0; // @[Edges.scala:102:36, :221:14] wire [7:0] initBeats = maskedBeats_0; // @[Arbiter.scala:82:69, :84:44] wire _GEN_19 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35] wire _beatsLeft_T; // @[Decoupled.scala:51:35] assign _beatsLeft_T = _GEN_19; // @[Decoupled.scala:51:35] wire _io_lsu_perf_release_T; // @[Decoupled.scala:51:35] assign _io_lsu_perf_release_T = _GEN_19; // @[Decoupled.scala:51:35] wire [8:0] _beatsLeft_T_1 = {1'h0, beatsLeft} - {8'h0, _beatsLeft_T}; // @[Decoupled.scala:51:35] wire [7:0] _beatsLeft_T_2 = _beatsLeft_T_1[7:0]; // @[Arbiter.scala:85:52] wire [7:0] _beatsLeft_T_3 = latch ? initBeats : _beatsLeft_T_2; // @[Arbiter.scala:62:24, :84:44, :85:{23,52}] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:27, :88:26, :89:25] wire allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala:61:28, :68:27, :88:26, :92:24] wire _wb_io_release_ready_T = nodeOut_c_ready & allowed_0; // @[Arbiter.scala:92:24, :94:31] wire _prober_io_rep_ready_T = nodeOut_c_ready & allowed_1; // @[Arbiter.scala:92:24, :94:31] wire _nodeOut_c_valid_T_1 = state_0 & _wb_io_release_valid; // @[Mux.scala:30:73] wire _nodeOut_c_valid_T_2 = state_1 & _prober_io_rep_valid; // @[Mux.scala:30:73] wire _nodeOut_c_valid_T_3 = _nodeOut_c_valid_T_1 | _nodeOut_c_valid_T_2; // @[Mux.scala:30:73] wire _nodeOut_c_valid_WIRE = _nodeOut_c_valid_T_3; // @[Mux.scala:30:73] assign _nodeOut_c_valid_T_4 = idle ? _nodeOut_c_valid_T : _nodeOut_c_valid_WIRE; // @[Mux.scala:30:73] assign nodeOut_c_valid = _nodeOut_c_valid_T_4; // @[Arbiter.scala:96:24] wire [2:0] _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73] assign nodeOut_c_bits_opcode = _nodeOut_c_bits_WIRE_opcode; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73] assign nodeOut_c_bits_param = _nodeOut_c_bits_WIRE_param; // @[Mux.scala:30:73] wire [3:0] _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73] assign nodeOut_c_bits_size = _nodeOut_c_bits_WIRE_size; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73] assign nodeOut_c_bits_source = _nodeOut_c_bits_WIRE_source; // @[Mux.scala:30:73] wire [31:0] _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73] assign nodeOut_c_bits_address = _nodeOut_c_bits_WIRE_address; // @[Mux.scala:30:73] wire [127:0] _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73] assign nodeOut_c_bits_data = _nodeOut_c_bits_WIRE_data; // @[Mux.scala:30:73] wire [127:0] _nodeOut_c_bits_T_3 = muxState_0 ? _wb_io_release_bits_data : 128'h0; // @[Mux.scala:30:73] wire [127:0] _nodeOut_c_bits_T_5 = _nodeOut_c_bits_T_3; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_2 = _nodeOut_c_bits_T_5; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_data = _nodeOut_c_bits_WIRE_2; // @[Mux.scala:30:73] wire [31:0] _nodeOut_c_bits_T_6 = muxState_0 ? _wb_io_release_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _nodeOut_c_bits_T_7 = muxState_1 ? _prober_io_rep_bits_address : 32'h0; // @[Mux.scala:30:73] wire [31:0] _nodeOut_c_bits_T_8 = _nodeOut_c_bits_T_6 | _nodeOut_c_bits_T_7; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_5 = _nodeOut_c_bits_T_8; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_address = _nodeOut_c_bits_WIRE_5; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_9 = muxState_0 ? _wb_io_release_bits_source : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_10 = muxState_1 ? _prober_io_rep_bits_source : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_11 = _nodeOut_c_bits_T_9 | _nodeOut_c_bits_T_10; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_6 = _nodeOut_c_bits_T_11; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_source = _nodeOut_c_bits_WIRE_6; // @[Mux.scala:30:73] wire [3:0] _nodeOut_c_bits_T_12 = muxState_0 ? 4'h6 : 4'h0; // @[Mux.scala:30:73] wire [3:0] _nodeOut_c_bits_T_13 = muxState_1 ? _prober_io_rep_bits_size : 4'h0; // @[Mux.scala:30:73] wire [3:0] _nodeOut_c_bits_T_14 = _nodeOut_c_bits_T_12 | _nodeOut_c_bits_T_13; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_7 = _nodeOut_c_bits_T_14; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_size = _nodeOut_c_bits_WIRE_7; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_15 = muxState_0 ? _wb_io_release_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_16 = muxState_1 ? _prober_io_rep_bits_param : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_17 = _nodeOut_c_bits_T_15 | _nodeOut_c_bits_T_16; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_8 = _nodeOut_c_bits_T_17; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_param = _nodeOut_c_bits_WIRE_8; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_18 = muxState_0 ? _wb_io_release_bits_opcode : 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_19 = {muxState_1, 2'h0}; // @[Mux.scala:30:73] wire [2:0] _nodeOut_c_bits_T_20 = _nodeOut_c_bits_T_18 | _nodeOut_c_bits_T_19; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_9 = _nodeOut_c_bits_T_20; // @[Mux.scala:30:73] assign _nodeOut_c_bits_WIRE_opcode = _nodeOut_c_bits_WIRE_9; // @[Mux.scala:30:73] wire [26:0] _io_lsu_perf_release_beats1_decode_T = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71] wire [11:0] _io_lsu_perf_release_beats1_decode_T_1 = _io_lsu_perf_release_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _io_lsu_perf_release_beats1_decode_T_2 = ~_io_lsu_perf_release_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] io_lsu_perf_release_beats1_decode = _io_lsu_perf_release_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire io_lsu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire [7:0] io_lsu_perf_release_beats1 = io_lsu_perf_release_beats1_opdata ? io_lsu_perf_release_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] io_lsu_perf_release_counter; // @[Edges.scala:229:27] wire [8:0] _io_lsu_perf_release_counter1_T = {1'h0, io_lsu_perf_release_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] io_lsu_perf_release_counter1 = _io_lsu_perf_release_counter1_T[7:0]; // @[Edges.scala:230:28] wire io_lsu_perf_release_first = io_lsu_perf_release_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _io_lsu_perf_release_last_T = io_lsu_perf_release_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _io_lsu_perf_release_last_T_1 = io_lsu_perf_release_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire io_lsu_perf_release_last = _io_lsu_perf_release_last_T | _io_lsu_perf_release_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_lsu_perf_release_done = io_lsu_perf_release_last & _io_lsu_perf_release_T; // @[Decoupled.scala:51:35] assign io_lsu_perf_release_0 = io_lsu_perf_release_done; // @[Edges.scala:233:22] wire [7:0] _io_lsu_perf_release_count_T = ~io_lsu_perf_release_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] io_lsu_perf_release_count = io_lsu_perf_release_beats1 & _io_lsu_perf_release_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _io_lsu_perf_release_counter_T = io_lsu_perf_release_first ? io_lsu_perf_release_beats1 : io_lsu_perf_release_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _io_lsu_perf_acquire_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35] wire [26:0] _io_lsu_perf_acquire_beats1_decode_T = 27'hFFF << nodeOut_a_bits_size; // @[package.scala:243:71] wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_1 = _io_lsu_perf_acquire_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _io_lsu_perf_acquire_beats1_decode_T_2 = ~_io_lsu_perf_acquire_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] io_lsu_perf_acquire_beats1_decode = _io_lsu_perf_acquire_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _io_lsu_perf_acquire_beats1_opdata_T = nodeOut_a_bits_opcode[2]; // @[Edges.scala:92:37] wire io_lsu_perf_acquire_beats1_opdata = ~_io_lsu_perf_acquire_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] io_lsu_perf_acquire_beats1 = io_lsu_perf_acquire_beats1_opdata ? io_lsu_perf_acquire_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] io_lsu_perf_acquire_counter; // @[Edges.scala:229:27] wire [8:0] _io_lsu_perf_acquire_counter1_T = {1'h0, io_lsu_perf_acquire_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] io_lsu_perf_acquire_counter1 = _io_lsu_perf_acquire_counter1_T[7:0]; // @[Edges.scala:230:28] wire io_lsu_perf_acquire_first = io_lsu_perf_acquire_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _io_lsu_perf_acquire_last_T = io_lsu_perf_acquire_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _io_lsu_perf_acquire_last_T_1 = io_lsu_perf_acquire_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire io_lsu_perf_acquire_last = _io_lsu_perf_acquire_last_T | _io_lsu_perf_acquire_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_lsu_perf_acquire_done = io_lsu_perf_acquire_last & _io_lsu_perf_acquire_T; // @[Decoupled.scala:51:35] assign io_lsu_perf_acquire_0 = io_lsu_perf_acquire_done; // @[Edges.scala:233:22] wire [7:0] _io_lsu_perf_acquire_count_T = ~io_lsu_perf_acquire_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] io_lsu_perf_acquire_count = io_lsu_perf_acquire_beats1 & _io_lsu_perf_acquire_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _io_lsu_perf_acquire_counter_T = io_lsu_perf_acquire_first ? io_lsu_perf_acquire_beats1 : io_lsu_perf_acquire_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [6:0] _s2_data_word_prebypass_T = {s2_word_idx_0, 6'h0}; // @[dcache.scala:454:49, :868:69] wire [127:0] _s2_data_word_prebypass_T_1 = s2_data_muxed_0 >> _s2_data_word_prebypass_T; // @[dcache.scala:454:49, :868:{63,69}] wire [127:0] s2_data_word_prebypass_0 = _s2_data_word_prebypass_T_1; // @[dcache.scala:454:49, :868:63] wire [127:0] _s2_data_word_0_T_2; // @[dcache.scala:919:27] wire [127:0] s2_data_word_0; // @[dcache.scala:869:26] wire [127:0] size_dat_padded = s2_data_word_0; // @[AMOALU.scala:13:27] assign _io_lsu_resp_0_valid_T = s2_valid_0 & s2_send_resp_0; // @[dcache.scala:454:49, :877:41] assign io_lsu_resp_0_valid_0 = _io_lsu_resp_0_valid_T; // @[dcache.scala:438:7, :877:41] wire _io_lsu_resp_0_bits_data_shifted_T = s2_req_0_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_lsu_resp_0_bits_data_shifted_T_1 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_lsu_resp_0_bits_data_T_5 = s2_data_word_0[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_lsu_resp_0_bits_data_shifted_T_2 = s2_data_word_0[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_lsu_resp_0_bits_data_shifted = _io_lsu_resp_0_bits_data_shifted_T ? _io_lsu_resp_0_bits_data_shifted_T_1 : _io_lsu_resp_0_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_lsu_resp_0_bits_data_zeroed = io_lsu_resp_0_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_lsu_resp_0_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_lsu_resp_0_bits_data_T_1 = _io_lsu_resp_0_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_lsu_resp_0_bits_data_T_2 = io_lsu_resp_0_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_lsu_resp_0_bits_data_T_3 = s2_req_0_uop_mem_signed & _io_lsu_resp_0_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_lsu_resp_0_bits_data_T_4 = {32{_io_lsu_resp_0_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_lsu_resp_0_bits_data_T_6 = _io_lsu_resp_0_bits_data_T_1 ? _io_lsu_resp_0_bits_data_T_4 : _io_lsu_resp_0_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_lsu_resp_0_bits_data_T_7 = {_io_lsu_resp_0_bits_data_T_6, io_lsu_resp_0_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_lsu_resp_0_bits_data_shifted_T_3 = s2_req_0_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_lsu_resp_0_bits_data_shifted_T_4 = _io_lsu_resp_0_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_lsu_resp_0_bits_data_shifted_T_5 = _io_lsu_resp_0_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_lsu_resp_0_bits_data_shifted_1 = _io_lsu_resp_0_bits_data_shifted_T_3 ? _io_lsu_resp_0_bits_data_shifted_T_4 : _io_lsu_resp_0_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_lsu_resp_0_bits_data_zeroed_1 = io_lsu_resp_0_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_lsu_resp_0_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_lsu_resp_0_bits_data_T_9 = _io_lsu_resp_0_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_lsu_resp_0_bits_data_T_10 = io_lsu_resp_0_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_lsu_resp_0_bits_data_T_11 = s2_req_0_uop_mem_signed & _io_lsu_resp_0_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_lsu_resp_0_bits_data_T_12 = {48{_io_lsu_resp_0_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_lsu_resp_0_bits_data_T_13 = _io_lsu_resp_0_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_lsu_resp_0_bits_data_T_14 = _io_lsu_resp_0_bits_data_T_9 ? _io_lsu_resp_0_bits_data_T_12 : _io_lsu_resp_0_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_lsu_resp_0_bits_data_T_15 = {_io_lsu_resp_0_bits_data_T_14, io_lsu_resp_0_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_lsu_resp_0_bits_data_shifted_T_6 = s2_req_0_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_lsu_resp_0_bits_data_shifted_T_7 = _io_lsu_resp_0_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_lsu_resp_0_bits_data_shifted_T_8 = _io_lsu_resp_0_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_lsu_resp_0_bits_data_shifted_2 = _io_lsu_resp_0_bits_data_shifted_T_6 ? _io_lsu_resp_0_bits_data_shifted_T_7 : _io_lsu_resp_0_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_lsu_resp_0_bits_data_zeroed_2 = io_lsu_resp_0_bits_data_doZero_2 ? 8'h0 : io_lsu_resp_0_bits_data_shifted_2; // @[AMOALU.scala:42:24, :43:31, :44:23] wire _io_lsu_resp_0_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_lsu_resp_0_bits_data_T_17 = _io_lsu_resp_0_bits_data_T_16 | io_lsu_resp_0_bits_data_doZero_2; // @[AMOALU.scala:43:31, :45:{26,34}] wire _io_lsu_resp_0_bits_data_T_18 = io_lsu_resp_0_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_lsu_resp_0_bits_data_T_19 = s2_req_0_uop_mem_signed & _io_lsu_resp_0_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_lsu_resp_0_bits_data_T_20 = {56{_io_lsu_resp_0_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_lsu_resp_0_bits_data_T_21 = _io_lsu_resp_0_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_lsu_resp_0_bits_data_T_22 = _io_lsu_resp_0_bits_data_T_17 ? _io_lsu_resp_0_bits_data_T_20 : _io_lsu_resp_0_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_lsu_resp_0_bits_data_T_23 = {_io_lsu_resp_0_bits_data_T_22, io_lsu_resp_0_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign _io_lsu_resp_0_bits_data_T_24 = {_io_lsu_resp_0_bits_data_T_23[63:1], _io_lsu_resp_0_bits_data_T_23[0] | s2_sc_fail}; // @[AMOALU.scala:45:16] assign io_lsu_resp_0_bits_data_0 = _io_lsu_resp_0_bits_data_T_24; // @[dcache.scala:438:7, :879:49] assign _io_lsu_nack_0_valid_T = s2_valid_0 & s2_send_nack_0; // @[dcache.scala:454:49, :884:41] assign io_lsu_nack_0_valid_0 = _io_lsu_nack_0_valid_T; // @[dcache.scala:438:7, :884:41]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }
module AsyncValidSync_163( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_177 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ListBuffer.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean) { val queueBits = log2Up(queues) val entryBits = log2Up(entries) } class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle { val index = UInt(params.queueBits.W) val data = Output(params.gen) } class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module { override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}" val io = IO(new Bundle { // push is visible on the same cycle; flow queues val push = Flipped(Decoupled(new ListBufferPush(params))) val valid = UInt(params.queues.W) val pop = Flipped(Valid(UInt(params.queueBits.W))) val data = Output(params.gen) }) val valid = RegInit(0.U(params.queues.W)) val head = Mem(params.queues, UInt(params.entryBits.W)) val tail = Mem(params.queues, UInt(params.entryBits.W)) val used = RegInit(0.U(params.entries.W)) val next = Mem(params.entries, UInt(params.entryBits.W)) val data = Mem(params.entries, params.gen) val freeOH = ~(leftOR(~used) << 1) & ~used val freeIdx = OHToUInt(freeOH) val valid_set = WireDefault(0.U(params.queues.W)) val valid_clr = WireDefault(0.U(params.queues.W)) val used_set = WireDefault(0.U(params.entries.W)) val used_clr = WireDefault(0.U(params.entries.W)) val push_tail = tail.read(io.push.bits.index) val push_valid = valid(io.push.bits.index) io.push.ready := !used.andR when (io.push.fire) { valid_set := UIntToOH(io.push.bits.index, params.queues) used_set := freeOH data.write(freeIdx, io.push.bits.data) when (push_valid) { next.write(push_tail, freeIdx) } .otherwise { head.write(io.push.bits.index, freeIdx) } tail.write(io.push.bits.index, freeIdx) } val pop_head = head.read(io.pop.bits) val pop_valid = valid(io.pop.bits) // Bypass push data to the peek port io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head))) io.valid := (if (!params.bypass) valid else (valid | valid_set)) // It is an error to pop something that is not valid assert (!io.pop.fire || (io.valid)(io.pop.bits)) when (io.pop.fire) { used_clr := UIntToOH(pop_head, params.entries) when (pop_head === tail.read(io.pop.bits)) { valid_clr := UIntToOH(io.pop.bits, params.queues) } head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head))) } // Empty bypass changes no state when ((!params.bypass).B || !io.pop.valid || pop_valid) { used := (used & ~used_clr) | used_set valid := (valid & ~valid_clr) | valid_set } }
module ListBuffer_QueuedRequest_q21_e33( // @[ListBuffer.scala:36:7] input clock, // @[ListBuffer.scala:36:7] input reset, // @[ListBuffer.scala:36:7] output io_push_ready, // @[ListBuffer.scala:39:14] input io_push_valid, // @[ListBuffer.scala:39:14] input [4:0] io_push_bits_index, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14] input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14] input io_push_bits_data_control, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14] input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14] input [8:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14] input [12:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14] input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14] output [20:0] io_valid, // @[ListBuffer.scala:39:14] input io_pop_valid, // @[ListBuffer.scala:39:14] input [4:0] io_pop_bits, // @[ListBuffer.scala:39:14] output io_data_prio_0, // @[ListBuffer.scala:39:14] output io_data_prio_1, // @[ListBuffer.scala:39:14] output io_data_prio_2, // @[ListBuffer.scala:39:14] output io_data_control, // @[ListBuffer.scala:39:14] output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14] output [2:0] io_data_param, // @[ListBuffer.scala:39:14] output [2:0] io_data_size, // @[ListBuffer.scala:39:14] output [8:0] io_data_source, // @[ListBuffer.scala:39:14] output [12:0] io_data_tag, // @[ListBuffer.scala:39:14] output [5:0] io_data_offset, // @[ListBuffer.scala:39:14] output [5:0] io_data_put // @[ListBuffer.scala:39:14] ); wire [46:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18] wire [5:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18] wire [5:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18] wire [5:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18] wire [5:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18] reg [20:0] valid; // @[ListBuffer.scala:47:22] reg [32:0] used; // @[ListBuffer.scala:50:22] wire [32:0] _freeOH_T_22 = ~used; // @[ListBuffer.scala:50:22, :54:25] wire [31:0] _freeOH_T_3 = _freeOH_T_22[31:0] | {_freeOH_T_22[30:0], 1'h0}; // @[package.scala:253:{43,53}] wire [31:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[29:0], 2'h0}; // @[package.scala:253:{43,53}] wire [31:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[27:0], 4'h0}; // @[package.scala:253:{43,53}] wire [31:0] _freeOH_T_12 = _freeOH_T_9 | {_freeOH_T_9[23:0], 8'h0}; // @[package.scala:253:{43,53}] wire [32:0] _GEN = {~(_freeOH_T_12 | {_freeOH_T_12[15:0], 16'h0}), 1'h1} & _freeOH_T_22; // @[package.scala:253:{43,53}] wire [14:0] _freeIdx_T_3 = _GEN[31:17] | _GEN[15:1]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [6:0] _freeIdx_T_5 = _freeIdx_T_3[14:8] | _freeIdx_T_3[6:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] _freeIdx_T_7 = _freeIdx_T_5[6:4] | _freeIdx_T_5[2:0]; // @[OneHot.scala:30:18, :31:18, :32:28] wire [5:0] freeIdx = {_GEN[32], |(_GEN[31:16]), |(_freeIdx_T_3[14:7]), |(_freeIdx_T_5[6:3]), |(_freeIdx_T_7[2:1]), _freeIdx_T_7[2] | _freeIdx_T_7[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire [20:0] _push_valid_T = valid >> io_push_bits_index; // @[ListBuffer.scala:47:22, :63:25] wire io_push_ready_0 = used != 33'h1FFFFFFFF; // @[ListBuffer.scala:50:22, :65:26] wire data_MPORT_en = io_push_ready_0 & io_push_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }
module OptimizationBarrier_TLBEntryData_301( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ :*=* _) .getOrElse(TLNameNode("no_buffer")) } } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module TLBuffer_a29d64s8k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [7:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_10 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a29d64s8k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a29d64s8k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RoundAnyRawFNToRecFN.scala: /*============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact) ) != 0) || (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) || (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) | doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit || anyRoundExtra val roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && roundPosBit) || (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig | roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 | Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even || roundingMode_near_maxMag) && unboundedRange_roundPosBit) || (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow || //*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //*** M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow || anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc || io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow || (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even || roundingMode_near_maxMag || roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero || common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) | Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) | Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) | Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) | Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut || io.in.isZero || common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) | Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }
module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_47(); // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22] wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28] wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14] wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16] wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73] wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13] wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23] wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23] wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66] wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43] wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22] wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32] wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22] wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38] endmodule
Generate the Verilog code corresponding to the following Chisel files. File functional-unit.scala: //****************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Functional Units //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // If regfile bypassing is disabled, then the functional unit must do its own // bypassing in here on the WB stage (i.e., bypassing the io.resp.data) // // TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass? package boom.v4.exu import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ import freechips.rocketchip.tile import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR} import freechips.rocketchip.rocket.ALU._ import boom.v4.common._ import boom.v4.ifu._ import boom.v4.util._ /** * Bundle for signals sent to the functional unit * * @param dataWidth width of the data sent to the functional unit */ class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val numOperands = 3 val rs1_data = UInt(dataWidth.W) val rs2_data = UInt(dataWidth.W) val rs3_data = UInt(dataWidth.W) // only used for FMA units val ftq_info = Vec(2, new FTQInfo) // Need this-pc and next-pc for JALR val pred_data = Bool() val imm_data = UInt(xLen.W) // only used for integer ALU and AGen units } class BrInfoBundle(implicit p: Parameters) extends BoomBundle { val ldq_idx = UInt(ldqAddrSz.W) val stq_idx = UInt(stqAddrSz.W) val rxq_idx = UInt(log2Ceil(numRxqEntries).W) } /** * Branch resolution information given from the branch unit */ class BrResolutionInfo(implicit p: Parameters) extends BoomBundle with HasBoomUOP { val mispredict = Bool() val taken = Bool() // which direction did the branch go? val cfi_type = UInt(CFI_SZ.W) // Info for recalculating the pc for this branch val pc_sel = UInt(2.W) val jalr_target = UInt(vaddrBitsExtended.W) val target_offset = SInt(21.W) } class BrUpdateInfo(implicit p: Parameters) extends BoomBundle { // On the first cycle we get masks to kill registers val b1 = new BrUpdateMasks // On the second cycle we get indices to reset pointers val b2 = new BrResolutionInfo } class BrUpdateMasks(implicit p: Parameters) extends BoomBundle { val resolve_mask = UInt(maxBrCount.W) val mispredict_mask = UInt(maxBrCount.W) } /** * Abstract top level functional unit class that wraps a lower level hand made functional unit * * @param isPipelined is the functional unit pipelined? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit * @param hasBranchUnit does this functional unit have a branch unit? */ abstract class FunctionalUnit( val dataWidth: Int, val isAluUnit: Boolean = false, val needsFcsr: Boolean = false) (implicit p: Parameters) extends BoomModule { val io = IO(new Bundle { val kill = Input(Bool()) val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth))) val resp = (new DecoupledIO(new ExeUnitResp(dataWidth))) //val fflags = new ValidIO(new FFlagsResp) val brupdate = Input(new BrUpdateInfo()) // only used by the fpu unit val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null // only used by branch unit val brinfo = if (isAluUnit) Output(Valid(new BrResolutionInfo)) else null }) io.resp.bits.fflags.valid := false.B io.resp.bits.fflags.bits := DontCare io.resp.bits.predicated := false.B } /** * Functional unit that wraps RocketChips ALU * * @param isBranchUnit is this a branch unit? * @param numStages how many pipeline stages does the functional unit have * @param dataWidth width of the data being operated on in the functional unit */ class ALUUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit( isAluUnit = true, dataWidth = dataWidth) with boom.v4.ifu.HasBoomFrontendParameters with freechips.rocketchip.rocket.constants.ScalarOpConstants { io.req.ready := true.B val uop = io.req.bits.uop // immediate generation val imm_xprlen = io.req.bits.imm_data //ImmGen(uop.imm_packed, uop.imm_sel) // operand 1 select // Get the uop PC for jumps val block_pc = AlignPCToBoundary(io.req.bits.ftq_info(0).pc, icBlockBytes) val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U) val op1_shamt = Mux(uop.fcn_op === FN_ADD, io.req.bits.uop.pimm(2,1), 0.U) val op1_shl = Mux(uop.fcn_dw === DW_32, // shaddw io.req.bits.rs1_data(31,0), io.req.bits.rs1_data) << op1_shamt val op1_data = MuxLookup(uop.op1_sel, 0.U)(Seq( OP1_RS1 -> io.req.bits.rs1_data, OP1_PC -> Sext(uop_pc, xLen), OP1_RS1SHL -> op1_shl )) // operand 2 select val op2_oh = UIntToOH(Mux(uop.op2_sel(0), // rs1 io.req.bits.rs2_data, imm_xprlen)(log2Ceil(xLen)-1,0)) val op2_data = MuxLookup(uop.op2_sel, 0.U)(Seq( OP2_IMM -> Sext(imm_xprlen, xLen), OP2_IMMC -> io.req.bits.uop.prs1(4,0), OP2_RS2 -> io.req.bits.rs2_data, OP2_NEXT -> Mux(uop.is_rvc, 2.U, 4.U), OP2_RS2OH -> op2_oh, OP2_IMMOH -> op2_oh )) val alu = Module(new freechips.rocketchip.rocket.ALU()) alu.io.in1 := op1_data.asUInt alu.io.in2 := op2_data.asUInt alu.io.fn := uop.fcn_op alu.io.dw := Mux(uop.op1_sel === OP1_RS1SHL, DW_64, uop.fcn_dw) val rs1 = io.req.bits.rs1_data val rs2 = io.req.bits.rs2_data val br_eq = (rs1 === rs2) val br_ltu = (rs1.asUInt < rs2.asUInt) val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu | rs1(xLen-1) & ~rs2(xLen-1)).asBool val pc_sel = MuxLookup(uop.br_type, PC_PLUS4)( Seq( B_N -> PC_PLUS4, B_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4), B_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4), B_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4), B_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4), B_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4), B_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4), B_J -> PC_BRJMP, B_JR -> PC_JALR )) val is_taken = io.req.valid && (uop.br_type =/= BR_N) && (pc_sel =/= PC_PLUS4) // Branch/Jump Target Calculation // For jumps we read the FTQ, and can calculate the target // For branches we emit the offset for the core to redirect if necessary val target_offset = imm_xprlen(20,0).asSInt def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) { ea } else { // Efficient means to compress 64-bit VA into vaddrBits+1 bits. // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)). val a = a0.asSInt >> vaddrBits val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1)) Cat(msb, ea(vaddrBits-1,0)) } // "mispredict" means that a branch has been resolved and it must be killed val mispredict = WireInit(false.B) val is_br = io.req.valid && uop.is_br && !uop.is_sfb val is_jal = io.req.valid && uop.is_jal val is_jalr = io.req.valid && uop.is_jalr val jalr_target_base = io.req.bits.rs1_data.asSInt val jalr_target_xlen = Wire(UInt(xLen.W)) jalr_target_xlen := (jalr_target_base + target_offset).asUInt val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt val cfi_idx = ((uop.pc_lob ^ Mux(io.req.bits.ftq_info(0).entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1) when (is_br || is_jalr) { when (pc_sel === PC_PLUS4) { mispredict := uop.taken } when (pc_sel === PC_BRJMP) { mispredict := !uop.taken } when (pc_sel === PC_JALR) { mispredict := (!io.req.bits.ftq_info(1).valid || (io.req.bits.ftq_info(1).pc =/= jalr_target) || !io.req.bits.ftq_info(0).entry.cfi_idx.valid || (io.req.bits.ftq_info(0).entry.cfi_idx.bits =/= cfi_idx)) } } val brinfo = Wire(Valid(new BrResolutionInfo)) // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit brinfo.valid := is_br || is_jalr brinfo.bits.mispredict := mispredict brinfo.bits.uop := uop brinfo.bits.cfi_type := Mux(is_jalr, CFI_JALR, Mux(is_br , CFI_BR, CFI_X)) brinfo.bits.taken := is_taken brinfo.bits.pc_sel := pc_sel brinfo.bits.jalr_target := DontCare brinfo.bits.jalr_target := jalr_target brinfo.bits.target_offset := target_offset io.brinfo := brinfo // Response // TODO add clock gate on resp bits from functional units // io.resp.bits.data := RegEnable(alu.io.out, io.req.valid) // val reg_data = Reg(outType = Bits(width = xLen)) // reg_data := alu.io.out // io.resp.bits.data := reg_data val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data, Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data), Mux(io.req.bits.uop.is_mov, io.req.bits.rs2_data, alu.io.out)) io.resp.valid := io.req.valid io.resp.bits.uop := io.req.bits.uop io.resp.bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out) io.resp.bits.predicated := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data assert(io.resp.ready) } /** * Functional unit to wrap lower level FPU * * Currently, bypassing is unsupported! * All FP instructions are padded out to the max latency unit for easy * write-port scheduling. */ class FPUUnit(implicit p: Parameters) extends FunctionalUnit( //numBypassStages = 0, dataWidth = 65, needsFcsr = true) { io.req.ready := true.B val numStages = p(tile.TileKey).core.fpu.get.dfmaLatency val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), numStages)) pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate val fpu = Module(new FPU()) fpu.io.req.valid := io.req.valid fpu.io.req.bits.uop := io.req.bits.uop fpu.io.req.bits.rs1_data := io.req.bits.rs1_data fpu.io.req.bits.rs2_data := io.req.bits.rs2_data fpu.io.req.bits.rs3_data := io.req.bits.rs3_data fpu.io.req.bits.fcsr_rm := io.fcsr_rm io.resp.valid := pipe.io.resp(numStages-1).valid io.resp.bits.uop := pipe.io.resp(numStages-1).bits.uop io.resp.bits.data := fpu.io.resp.bits.data io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits := fpu.io.resp.bits.fflags.bits } /** * Int to FP conversion functional unit * * @param latency the amount of stages to delay by */ class IntToFPUnit(latency: Int)(implicit p: Parameters) extends FunctionalUnit( //numBypassStages = 0, dataWidth = 65, needsFcsr = true) with tile.HasFPUParameters { val io_req = io.req.bits io.req.ready := true.B val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), latency)) pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate val fp_ctrl = io_req.uop.fp_ctrl val fp_rm = Mux(io_req.uop.fp_rm === 7.U, io.fcsr_rm, io_req.uop.fp_rm) val req = Wire(new tile.FPInput) val tag = fp_ctrl.typeTagIn req.viewAsSupertype(new tile.FPUCtrlSigs) <> fp_ctrl req.rm := fp_rm req.in1 := unbox(io_req.rs1_data, tag, None) req.in2 := unbox(io_req.rs2_data, tag, None) req.in3 := DontCare req.typ := io_req.uop.fp_typ req.fmt := DontCare // FIXME: this may not be the right thing to do here req.fmaCmd := DontCare assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool), "[func] IntToFP integer input has 65th high-order bit set!") assert (!(io.req.valid && !fp_ctrl.fromint), "[func] Only support fromInt micro-ops.") val ifpu = Module(new tile.IntToFP(intToFpLatency)) ifpu.io.in.valid := io.req.valid ifpu.io.in.bits := req ifpu.io.in.bits.in1 := io_req.rs1_data val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits io.resp.valid := pipe.io.resp(latency-1).valid io.resp.bits.uop := pipe.io.resp(latency-1).bits.uop io.resp.bits.data := box(ifpu.io.out.bits.data, out_double) io.resp.bits.fflags.valid := io.resp.valid io.resp.bits.fflags.bits := ifpu.io.out.bits.exc } /** * Divide functional unit. * * @param dataWidth data to be passed into the functional unit */ class DivUnit(dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit(dataWidth = dataWidth) { // We don't use the iterative multiply functionality here. // Instead we use the PipelinedMultiplier val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth)) val req = Reg(Valid(new MicroOp())) when (io.req.fire) { req.valid := !IsKilledByBranch(io.brupdate, io.kill, io.req.bits) req.bits := UpdateBrMask(io.brupdate, io.req.bits.uop) } .otherwise { req.valid := !IsKilledByBranch(io.brupdate, io.kill, req.bits) && req.valid req.bits := UpdateBrMask(io.brupdate, req.bits) } when (reset.asBool) { req.valid := false.B } // request div.io.req.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.kill, io.req.bits) div.io.req.bits.dw := io.req.bits.uop.fcn_dw div.io.req.bits.fn := io.req.bits.uop.fcn_op div.io.req.bits.in1 := io.req.bits.rs1_data div.io.req.bits.in2 := io.req.bits.rs2_data div.io.req.bits.tag := DontCare io.req.ready := div.io.req.ready && !req.valid // handle pipeline kills and branch misspeculations div.io.kill := (req.valid && IsKilledByBranch(io.brupdate, io.kill, req.bits)) // response io.resp.valid := div.io.resp.valid && req.valid div.io.resp.ready := io.resp.ready io.resp.valid := div.io.resp.valid && req.valid io.resp.bits.data := div.io.resp.bits.data io.resp.bits.uop := req.bits when (io.resp.fire) { req.valid := false.B } } /** * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier * * @param numStages number of pipeline stages * @param dataWidth size of the data being passed into the functional unit */ class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters) extends FunctionalUnit(dataWidth = dataWidth) { io.req.ready := true.B val imul = Module(new PipelinedMultiplier(xLen, numStages)) val pipe = Module(new BranchKillablePipeline(new FuncUnitReq(dataWidth), numStages)) // request imul.io.req.valid := io.req.valid imul.io.req.bits.fn := io.req.bits.uop.fcn_op imul.io.req.bits.dw := io.req.bits.uop.fcn_dw imul.io.req.bits.in1 := io.req.bits.rs1_data imul.io.req.bits.in2 := io.req.bits.rs2_data imul.io.req.bits.tag := DontCare pipe.io.req := io.req pipe.io.flush := io.kill pipe.io.brupdate := io.brupdate // response io.resp.valid := pipe.io.resp(numStages-1).valid io.resp.bits.uop := pipe.io.resp(numStages-1).bits.uop io.resp.bits.data := imul.io.resp.bits.data io.resp.bits.predicated := false.B }
module PipelinedMulUnit( // @[functional-unit.scala:443:7] input clock, // @[functional-unit.scala:443:7] input reset, // @[functional-unit.scala:443:7] input io_kill, // @[functional-unit.scala:105:14] input io_req_valid, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_type, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_eret, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rocc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:105:14] input io_req_bits_uop_taken, // @[functional-unit.scala:105:14] input io_req_bits_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_op2_sel, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_req_bits_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:105:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:105:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:105:14] input io_req_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_fcn_op, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_typ, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_imm_data, // @[functional-unit.scala:105:14] output io_resp_valid, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:105:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_type, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_eret, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rocc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_mov, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:105:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:105:14] output io_resp_bits_uop_imm_rename, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_imm_sel, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_pimm, // @[functional-unit.scala:105:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_op1_sel, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_op2_sel, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:105:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:105:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_fcn_op, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_fp_rm, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_typ, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_data, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_type, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_eret, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rocc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:105:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:105:14] input io_brupdate_b2_taken, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:105:14] input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:105:14] ); wire io_kill_0 = io_kill; // @[functional-unit.scala:443:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:443:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:443:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:443:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:443:7] wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[functional-unit.scala:443:7] wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:443:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:443:7] wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:443:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:443:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:443:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:443:7] wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[functional-unit.scala:443:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:443:7] wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:443:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:443:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:443:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:443:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:443:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:443:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:443:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:443:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:443:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:443:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:443:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:443:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:443:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:443:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:443:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:443:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[functional-unit.scala:443:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:443:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:443:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:443:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:443:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:443:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[functional-unit.scala:443:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[functional-unit.scala:443:7] wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[functional-unit.scala:443:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:443:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:443:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:443:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:443:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:443:7] wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:443:7] wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:443:7] wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:443:7] wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[functional-unit.scala:443:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:443:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:443:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:443:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:443:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[functional-unit.scala:443:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:443:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:443:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[functional-unit.scala:443:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:443:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[functional-unit.scala:443:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[functional-unit.scala:443:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[functional-unit.scala:443:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:443:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:443:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:443:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:443:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:443:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:443:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:443:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:443:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:443:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:443:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:443:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:443:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:443:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:443:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[functional-unit.scala:443:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:443:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:443:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:443:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:443:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:443:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:443:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:443:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[functional-unit.scala:443:7] wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[functional-unit.scala:443:7] wire [4:0] io_resp_bits_fflags_bits = 5'h0; // @[functional-unit.scala:443:7] wire [39:0] io_req_bits_ftq_info_0_entry_ras_top = 40'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [39:0] io_req_bits_ftq_info_0_pc = 40'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [39:0] io_req_bits_ftq_info_1_entry_ras_top = 40'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [39:0] io_req_bits_ftq_info_1_pc = 40'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [7:0] io_req_bits_ftq_info_0_entry_br_mask = 8'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [7:0] io_req_bits_ftq_info_1_entry_br_mask = 8'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits = 3'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits = 3'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire io_req_bits_ftq_info_0_valid = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_entry_start_bank = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_valid = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_entry_start_bank = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:443:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:443:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:443:7] wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:443:7] wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[functional-unit.scala:105:14, :443:7, :448:20] wire io_req_ready = 1'h1; // @[functional-unit.scala:443:7] wire io_resp_ready = 1'h1; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:443:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:443:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:443:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:443:7] wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:443:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:443:7] wire [3:0] io_resp_bits_uop_br_type_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:443:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:443:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:443:7] wire [4:0] io_resp_bits_uop_pimm_0; // @[functional-unit.scala:443:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:443:7] wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:443:7] wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:443:7] wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:443:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:443:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:443:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:443:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:443:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:443:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:443:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:443:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:443:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:443:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:443:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:443:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:443:7] wire [4:0] io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:443:7] wire [1:0] io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:443:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:443:7] wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:443:7] wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:443:7] wire io_resp_valid_0; // @[functional-unit.scala:443:7] PipelinedMultiplier imul ( // @[functional-unit.scala:447:20] .clock (clock), .reset (reset), .io_req_valid (io_req_valid_0), // @[functional-unit.scala:443:7] .io_req_bits_fn (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:443:7] .io_req_bits_dw (io_req_bits_uop_fcn_dw_0), // @[functional-unit.scala:443:7] .io_req_bits_in1 (io_req_bits_rs1_data_0), // @[functional-unit.scala:443:7] .io_req_bits_in2 (io_req_bits_rs2_data_0), // @[functional-unit.scala:443:7] .io_resp_bits_data (io_resp_bits_data_0) ); // @[functional-unit.scala:447:20] BranchKillablePipeline pipe ( // @[functional-unit.scala:448:20] .clock (clock), .reset (reset), .io_req_valid (io_req_valid_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_inst (io_req_bits_uop_inst_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iq_type_0 (io_req_bits_uop_iq_type_0_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iq_type_1 (io_req_bits_uop_iq_type_1_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iq_type_2 (io_req_bits_uop_iq_type_2_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iq_type_3 (io_req_bits_uop_iq_type_3_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_0 (io_req_bits_uop_fu_code_0_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_1 (io_req_bits_uop_fu_code_1_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_2 (io_req_bits_uop_fu_code_2_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_3 (io_req_bits_uop_fu_code_3_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_4 (io_req_bits_uop_fu_code_4_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_5 (io_req_bits_uop_fu_code_5_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_6 (io_req_bits_uop_fu_code_6_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_7 (io_req_bits_uop_fu_code_7_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_8 (io_req_bits_uop_fu_code_8_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fu_code_9 (io_req_bits_uop_fu_code_9_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iw_issued (io_req_bits_uop_iw_issued_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iw_issued_partial_agen (io_req_bits_uop_iw_issued_partial_agen_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iw_issued_partial_dgen (io_req_bits_uop_iw_issued_partial_dgen_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iw_p1_speculative_child (io_req_bits_uop_iw_p1_speculative_child_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iw_p2_speculative_child (io_req_bits_uop_iw_p2_speculative_child_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iw_p1_bypass_hint (io_req_bits_uop_iw_p1_bypass_hint_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iw_p2_bypass_hint (io_req_bits_uop_iw_p2_bypass_hint_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_iw_p3_bypass_hint (io_req_bits_uop_iw_p3_bypass_hint_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_dis_col_sel (io_req_bits_uop_dis_col_sel_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_br_tag (io_req_bits_uop_br_tag_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_br_type (io_req_bits_uop_br_type_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_fence (io_req_bits_uop_is_fence_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_sfence (io_req_bits_uop_is_sfence_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_eret (io_req_bits_uop_is_eret_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_rocc (io_req_bits_uop_is_rocc_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_mov (io_req_bits_uop_is_mov_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_taken (io_req_bits_uop_taken_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_imm_rename (io_req_bits_uop_imm_rename_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_imm_sel (io_req_bits_uop_imm_sel_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_pimm (io_req_bits_uop_pimm_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_op1_sel (io_req_bits_uop_op1_sel_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_op2_sel (io_req_bits_uop_op2_sel_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_ldst (io_req_bits_uop_fp_ctrl_ldst_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_wen (io_req_bits_uop_fp_ctrl_wen_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_ren1 (io_req_bits_uop_fp_ctrl_ren1_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_ren2 (io_req_bits_uop_fp_ctrl_ren2_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_ren3 (io_req_bits_uop_fp_ctrl_ren3_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_swap12 (io_req_bits_uop_fp_ctrl_swap12_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_swap23 (io_req_bits_uop_fp_ctrl_swap23_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_typeTagIn (io_req_bits_uop_fp_ctrl_typeTagIn_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_typeTagOut (io_req_bits_uop_fp_ctrl_typeTagOut_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_fromint (io_req_bits_uop_fp_ctrl_fromint_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_toint (io_req_bits_uop_fp_ctrl_toint_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_fastpipe (io_req_bits_uop_fp_ctrl_fastpipe_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_fma (io_req_bits_uop_fp_ctrl_fma_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_div (io_req_bits_uop_fp_ctrl_div_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_sqrt (io_req_bits_uop_fp_ctrl_sqrt_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_wflags (io_req_bits_uop_fp_ctrl_wflags_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_ctrl_vec (io_req_bits_uop_fp_ctrl_vec_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_pdst (io_req_bits_uop_pdst_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_prs1 (io_req_bits_uop_prs1_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_prs2 (io_req_bits_uop_prs2_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_prs3 (io_req_bits_uop_prs3_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_ppred (io_req_bits_uop_ppred_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_exception (io_req_bits_uop_exception_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_mem_size (io_req_bits_uop_mem_size_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_is_unique (io_req_bits_uop_is_unique_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_csr_cmd (io_req_bits_uop_csr_cmd_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_ldst (io_req_bits_uop_ldst_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fcn_dw (io_req_bits_uop_fcn_dw_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fcn_op (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_val (io_req_bits_uop_fp_val_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_rm (io_req_bits_uop_fp_rm_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_fp_typ (io_req_bits_uop_fp_typ_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc_0), // @[functional-unit.scala:443:7] .io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc_0), // @[functional-unit.scala:443:7] .io_req_bits_rs1_data (io_req_bits_rs1_data_0), // @[functional-unit.scala:443:7] .io_req_bits_rs2_data (io_req_bits_rs2_data_0), // @[functional-unit.scala:443:7] .io_req_bits_imm_data (io_req_bits_imm_data_0), // @[functional-unit.scala:443:7] .io_flush (io_kill_0), // @[functional-unit.scala:443:7] .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask_0), // @[functional-unit.scala:443:7] .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_inst (io_brupdate_b2_uop_inst_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_debug_inst (io_brupdate_b2_uop_debug_inst_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_rvc (io_brupdate_b2_uop_is_rvc_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_debug_pc (io_brupdate_b2_uop_debug_pc_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iq_type_0 (io_brupdate_b2_uop_iq_type_0_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iq_type_1 (io_brupdate_b2_uop_iq_type_1_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iq_type_2 (io_brupdate_b2_uop_iq_type_2_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iq_type_3 (io_brupdate_b2_uop_iq_type_3_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_0 (io_brupdate_b2_uop_fu_code_0_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_1 (io_brupdate_b2_uop_fu_code_1_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_2 (io_brupdate_b2_uop_fu_code_2_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_3 (io_brupdate_b2_uop_fu_code_3_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_4 (io_brupdate_b2_uop_fu_code_4_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_5 (io_brupdate_b2_uop_fu_code_5_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_6 (io_brupdate_b2_uop_fu_code_6_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_7 (io_brupdate_b2_uop_fu_code_7_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_8 (io_brupdate_b2_uop_fu_code_8_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fu_code_9 (io_brupdate_b2_uop_fu_code_9_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iw_issued (io_brupdate_b2_uop_iw_issued_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iw_issued_partial_agen (io_brupdate_b2_uop_iw_issued_partial_agen_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iw_issued_partial_dgen (io_brupdate_b2_uop_iw_issued_partial_dgen_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iw_p1_speculative_child (io_brupdate_b2_uop_iw_p1_speculative_child_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iw_p2_speculative_child (io_brupdate_b2_uop_iw_p2_speculative_child_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iw_p1_bypass_hint (io_brupdate_b2_uop_iw_p1_bypass_hint_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iw_p2_bypass_hint (io_brupdate_b2_uop_iw_p2_bypass_hint_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_iw_p3_bypass_hint (io_brupdate_b2_uop_iw_p3_bypass_hint_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_dis_col_sel (io_brupdate_b2_uop_dis_col_sel_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_br_mask (io_brupdate_b2_uop_br_mask_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_br_type (io_brupdate_b2_uop_br_type_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_sfb (io_brupdate_b2_uop_is_sfb_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_fence (io_brupdate_b2_uop_is_fence_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_fencei (io_brupdate_b2_uop_is_fencei_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_sfence (io_brupdate_b2_uop_is_sfence_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_amo (io_brupdate_b2_uop_is_amo_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_eret (io_brupdate_b2_uop_is_eret_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_sys_pc2epc (io_brupdate_b2_uop_is_sys_pc2epc_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_rocc (io_brupdate_b2_uop_is_rocc_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_mov (io_brupdate_b2_uop_is_mov_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_ftq_idx (io_brupdate_b2_uop_ftq_idx_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_edge_inst (io_brupdate_b2_uop_edge_inst_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_pc_lob (io_brupdate_b2_uop_pc_lob_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_taken (io_brupdate_b2_uop_taken_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_imm_rename (io_brupdate_b2_uop_imm_rename_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_imm_sel (io_brupdate_b2_uop_imm_sel_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_pimm (io_brupdate_b2_uop_pimm_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_imm_packed (io_brupdate_b2_uop_imm_packed_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_op1_sel (io_brupdate_b2_uop_op1_sel_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_op2_sel (io_brupdate_b2_uop_op2_sel_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_ldst (io_brupdate_b2_uop_fp_ctrl_ldst_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_wen (io_brupdate_b2_uop_fp_ctrl_wen_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_ren1 (io_brupdate_b2_uop_fp_ctrl_ren1_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_ren2 (io_brupdate_b2_uop_fp_ctrl_ren2_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_ren3 (io_brupdate_b2_uop_fp_ctrl_ren3_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_swap12 (io_brupdate_b2_uop_fp_ctrl_swap12_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_swap23 (io_brupdate_b2_uop_fp_ctrl_swap23_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_typeTagIn (io_brupdate_b2_uop_fp_ctrl_typeTagIn_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_typeTagOut (io_brupdate_b2_uop_fp_ctrl_typeTagOut_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_fromint (io_brupdate_b2_uop_fp_ctrl_fromint_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_toint (io_brupdate_b2_uop_fp_ctrl_toint_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_fastpipe (io_brupdate_b2_uop_fp_ctrl_fastpipe_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_fma (io_brupdate_b2_uop_fp_ctrl_fma_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_div (io_brupdate_b2_uop_fp_ctrl_div_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_sqrt (io_brupdate_b2_uop_fp_ctrl_sqrt_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_wflags (io_brupdate_b2_uop_fp_ctrl_wflags_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_ctrl_vec (io_brupdate_b2_uop_fp_ctrl_vec_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_rob_idx (io_brupdate_b2_uop_rob_idx_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_ldq_idx (io_brupdate_b2_uop_ldq_idx_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_stq_idx (io_brupdate_b2_uop_stq_idx_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_rxq_idx (io_brupdate_b2_uop_rxq_idx_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_pdst (io_brupdate_b2_uop_pdst_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_prs1 (io_brupdate_b2_uop_prs1_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_prs2 (io_brupdate_b2_uop_prs2_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_prs3 (io_brupdate_b2_uop_prs3_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_ppred (io_brupdate_b2_uop_ppred_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_prs1_busy (io_brupdate_b2_uop_prs1_busy_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_prs2_busy (io_brupdate_b2_uop_prs2_busy_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_prs3_busy (io_brupdate_b2_uop_prs3_busy_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_ppred_busy (io_brupdate_b2_uop_ppred_busy_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_stale_pdst (io_brupdate_b2_uop_stale_pdst_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_exception (io_brupdate_b2_uop_exception_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_exc_cause (io_brupdate_b2_uop_exc_cause_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_mem_cmd (io_brupdate_b2_uop_mem_cmd_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_mem_size (io_brupdate_b2_uop_mem_size_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_mem_signed (io_brupdate_b2_uop_mem_signed_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_uses_ldq (io_brupdate_b2_uop_uses_ldq_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_uses_stq (io_brupdate_b2_uop_uses_stq_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_is_unique (io_brupdate_b2_uop_is_unique_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_flush_on_commit (io_brupdate_b2_uop_flush_on_commit_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_csr_cmd (io_brupdate_b2_uop_csr_cmd_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_ldst_is_rs1 (io_brupdate_b2_uop_ldst_is_rs1_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_ldst (io_brupdate_b2_uop_ldst_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_lrs1 (io_brupdate_b2_uop_lrs1_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_lrs2 (io_brupdate_b2_uop_lrs2_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_lrs3 (io_brupdate_b2_uop_lrs3_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_dst_rtype (io_brupdate_b2_uop_dst_rtype_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_lrs1_rtype (io_brupdate_b2_uop_lrs1_rtype_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_lrs2_rtype (io_brupdate_b2_uop_lrs2_rtype_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_frs3_en (io_brupdate_b2_uop_frs3_en_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fcn_dw (io_brupdate_b2_uop_fcn_dw_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fcn_op (io_brupdate_b2_uop_fcn_op_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_val (io_brupdate_b2_uop_fp_val_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_rm (io_brupdate_b2_uop_fp_rm_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_fp_typ (io_brupdate_b2_uop_fp_typ_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_xcpt_pf_if (io_brupdate_b2_uop_xcpt_pf_if_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_xcpt_ae_if (io_brupdate_b2_uop_xcpt_ae_if_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_xcpt_ma_if (io_brupdate_b2_uop_xcpt_ma_if_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_bp_debug_if (io_brupdate_b2_uop_bp_debug_if_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_bp_xcpt_if (io_brupdate_b2_uop_bp_xcpt_if_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_debug_fsrc (io_brupdate_b2_uop_debug_fsrc_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_uop_debug_tsrc (io_brupdate_b2_uop_debug_tsrc_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_mispredict (io_brupdate_b2_mispredict_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_taken (io_brupdate_b2_taken_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_cfi_type (io_brupdate_b2_cfi_type_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_pc_sel (io_brupdate_b2_pc_sel_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_jalr_target (io_brupdate_b2_jalr_target_0), // @[functional-unit.scala:443:7] .io_brupdate_b2_target_offset (io_brupdate_b2_target_offset_0), // @[functional-unit.scala:443:7] .io_resp_2_valid (io_resp_valid_0), .io_resp_2_bits_uop_inst (io_resp_bits_uop_inst_0), .io_resp_2_bits_uop_debug_inst (io_resp_bits_uop_debug_inst_0), .io_resp_2_bits_uop_is_rvc (io_resp_bits_uop_is_rvc_0), .io_resp_2_bits_uop_debug_pc (io_resp_bits_uop_debug_pc_0), .io_resp_2_bits_uop_iq_type_0 (io_resp_bits_uop_iq_type_0_0), .io_resp_2_bits_uop_iq_type_1 (io_resp_bits_uop_iq_type_1_0), .io_resp_2_bits_uop_iq_type_2 (io_resp_bits_uop_iq_type_2_0), .io_resp_2_bits_uop_iq_type_3 (io_resp_bits_uop_iq_type_3_0), .io_resp_2_bits_uop_fu_code_0 (io_resp_bits_uop_fu_code_0_0), .io_resp_2_bits_uop_fu_code_1 (io_resp_bits_uop_fu_code_1_0), .io_resp_2_bits_uop_fu_code_2 (io_resp_bits_uop_fu_code_2_0), .io_resp_2_bits_uop_fu_code_3 (io_resp_bits_uop_fu_code_3_0), .io_resp_2_bits_uop_fu_code_4 (io_resp_bits_uop_fu_code_4_0), .io_resp_2_bits_uop_fu_code_5 (io_resp_bits_uop_fu_code_5_0), .io_resp_2_bits_uop_fu_code_6 (io_resp_bits_uop_fu_code_6_0), .io_resp_2_bits_uop_fu_code_7 (io_resp_bits_uop_fu_code_7_0), .io_resp_2_bits_uop_fu_code_8 (io_resp_bits_uop_fu_code_8_0), .io_resp_2_bits_uop_fu_code_9 (io_resp_bits_uop_fu_code_9_0), .io_resp_2_bits_uop_iw_issued (io_resp_bits_uop_iw_issued_0), .io_resp_2_bits_uop_iw_issued_partial_agen (io_resp_bits_uop_iw_issued_partial_agen_0), .io_resp_2_bits_uop_iw_issued_partial_dgen (io_resp_bits_uop_iw_issued_partial_dgen_0), .io_resp_2_bits_uop_iw_p1_speculative_child (io_resp_bits_uop_iw_p1_speculative_child_0), .io_resp_2_bits_uop_iw_p2_speculative_child (io_resp_bits_uop_iw_p2_speculative_child_0), .io_resp_2_bits_uop_iw_p1_bypass_hint (io_resp_bits_uop_iw_p1_bypass_hint_0), .io_resp_2_bits_uop_iw_p2_bypass_hint (io_resp_bits_uop_iw_p2_bypass_hint_0), .io_resp_2_bits_uop_iw_p3_bypass_hint (io_resp_bits_uop_iw_p3_bypass_hint_0), .io_resp_2_bits_uop_dis_col_sel (io_resp_bits_uop_dis_col_sel_0), .io_resp_2_bits_uop_br_mask (io_resp_bits_uop_br_mask_0), .io_resp_2_bits_uop_br_tag (io_resp_bits_uop_br_tag_0), .io_resp_2_bits_uop_br_type (io_resp_bits_uop_br_type_0), .io_resp_2_bits_uop_is_sfb (io_resp_bits_uop_is_sfb_0), .io_resp_2_bits_uop_is_fence (io_resp_bits_uop_is_fence_0), .io_resp_2_bits_uop_is_fencei (io_resp_bits_uop_is_fencei_0), .io_resp_2_bits_uop_is_sfence (io_resp_bits_uop_is_sfence_0), .io_resp_2_bits_uop_is_amo (io_resp_bits_uop_is_amo_0), .io_resp_2_bits_uop_is_eret (io_resp_bits_uop_is_eret_0), .io_resp_2_bits_uop_is_sys_pc2epc (io_resp_bits_uop_is_sys_pc2epc_0), .io_resp_2_bits_uop_is_rocc (io_resp_bits_uop_is_rocc_0), .io_resp_2_bits_uop_is_mov (io_resp_bits_uop_is_mov_0), .io_resp_2_bits_uop_ftq_idx (io_resp_bits_uop_ftq_idx_0), .io_resp_2_bits_uop_edge_inst (io_resp_bits_uop_edge_inst_0), .io_resp_2_bits_uop_pc_lob (io_resp_bits_uop_pc_lob_0), .io_resp_2_bits_uop_taken (io_resp_bits_uop_taken_0), .io_resp_2_bits_uop_imm_rename (io_resp_bits_uop_imm_rename_0), .io_resp_2_bits_uop_imm_sel (io_resp_bits_uop_imm_sel_0), .io_resp_2_bits_uop_pimm (io_resp_bits_uop_pimm_0), .io_resp_2_bits_uop_imm_packed (io_resp_bits_uop_imm_packed_0), .io_resp_2_bits_uop_op1_sel (io_resp_bits_uop_op1_sel_0), .io_resp_2_bits_uop_op2_sel (io_resp_bits_uop_op2_sel_0), .io_resp_2_bits_uop_fp_ctrl_ldst (io_resp_bits_uop_fp_ctrl_ldst_0), .io_resp_2_bits_uop_fp_ctrl_wen (io_resp_bits_uop_fp_ctrl_wen_0), .io_resp_2_bits_uop_fp_ctrl_ren1 (io_resp_bits_uop_fp_ctrl_ren1_0), .io_resp_2_bits_uop_fp_ctrl_ren2 (io_resp_bits_uop_fp_ctrl_ren2_0), .io_resp_2_bits_uop_fp_ctrl_ren3 (io_resp_bits_uop_fp_ctrl_ren3_0), .io_resp_2_bits_uop_fp_ctrl_swap12 (io_resp_bits_uop_fp_ctrl_swap12_0), .io_resp_2_bits_uop_fp_ctrl_swap23 (io_resp_bits_uop_fp_ctrl_swap23_0), .io_resp_2_bits_uop_fp_ctrl_typeTagIn (io_resp_bits_uop_fp_ctrl_typeTagIn_0), .io_resp_2_bits_uop_fp_ctrl_typeTagOut (io_resp_bits_uop_fp_ctrl_typeTagOut_0), .io_resp_2_bits_uop_fp_ctrl_fromint (io_resp_bits_uop_fp_ctrl_fromint_0), .io_resp_2_bits_uop_fp_ctrl_toint (io_resp_bits_uop_fp_ctrl_toint_0), .io_resp_2_bits_uop_fp_ctrl_fastpipe (io_resp_bits_uop_fp_ctrl_fastpipe_0), .io_resp_2_bits_uop_fp_ctrl_fma (io_resp_bits_uop_fp_ctrl_fma_0), .io_resp_2_bits_uop_fp_ctrl_div (io_resp_bits_uop_fp_ctrl_div_0), .io_resp_2_bits_uop_fp_ctrl_sqrt (io_resp_bits_uop_fp_ctrl_sqrt_0), .io_resp_2_bits_uop_fp_ctrl_wflags (io_resp_bits_uop_fp_ctrl_wflags_0), .io_resp_2_bits_uop_fp_ctrl_vec (io_resp_bits_uop_fp_ctrl_vec_0), .io_resp_2_bits_uop_rob_idx (io_resp_bits_uop_rob_idx_0), .io_resp_2_bits_uop_ldq_idx (io_resp_bits_uop_ldq_idx_0), .io_resp_2_bits_uop_stq_idx (io_resp_bits_uop_stq_idx_0), .io_resp_2_bits_uop_rxq_idx (io_resp_bits_uop_rxq_idx_0), .io_resp_2_bits_uop_pdst (io_resp_bits_uop_pdst_0), .io_resp_2_bits_uop_prs1 (io_resp_bits_uop_prs1_0), .io_resp_2_bits_uop_prs2 (io_resp_bits_uop_prs2_0), .io_resp_2_bits_uop_prs3 (io_resp_bits_uop_prs3_0), .io_resp_2_bits_uop_ppred (io_resp_bits_uop_ppred_0), .io_resp_2_bits_uop_prs1_busy (io_resp_bits_uop_prs1_busy_0), .io_resp_2_bits_uop_prs2_busy (io_resp_bits_uop_prs2_busy_0), .io_resp_2_bits_uop_prs3_busy (io_resp_bits_uop_prs3_busy_0), .io_resp_2_bits_uop_ppred_busy (io_resp_bits_uop_ppred_busy_0), .io_resp_2_bits_uop_stale_pdst (io_resp_bits_uop_stale_pdst_0), .io_resp_2_bits_uop_exception (io_resp_bits_uop_exception_0), .io_resp_2_bits_uop_exc_cause (io_resp_bits_uop_exc_cause_0), .io_resp_2_bits_uop_mem_cmd (io_resp_bits_uop_mem_cmd_0), .io_resp_2_bits_uop_mem_size (io_resp_bits_uop_mem_size_0), .io_resp_2_bits_uop_mem_signed (io_resp_bits_uop_mem_signed_0), .io_resp_2_bits_uop_uses_ldq (io_resp_bits_uop_uses_ldq_0), .io_resp_2_bits_uop_uses_stq (io_resp_bits_uop_uses_stq_0), .io_resp_2_bits_uop_is_unique (io_resp_bits_uop_is_unique_0), .io_resp_2_bits_uop_flush_on_commit (io_resp_bits_uop_flush_on_commit_0), .io_resp_2_bits_uop_csr_cmd (io_resp_bits_uop_csr_cmd_0), .io_resp_2_bits_uop_ldst_is_rs1 (io_resp_bits_uop_ldst_is_rs1_0), .io_resp_2_bits_uop_ldst (io_resp_bits_uop_ldst_0), .io_resp_2_bits_uop_lrs1 (io_resp_bits_uop_lrs1_0), .io_resp_2_bits_uop_lrs2 (io_resp_bits_uop_lrs2_0), .io_resp_2_bits_uop_lrs3 (io_resp_bits_uop_lrs3_0), .io_resp_2_bits_uop_dst_rtype (io_resp_bits_uop_dst_rtype_0), .io_resp_2_bits_uop_lrs1_rtype (io_resp_bits_uop_lrs1_rtype_0), .io_resp_2_bits_uop_lrs2_rtype (io_resp_bits_uop_lrs2_rtype_0), .io_resp_2_bits_uop_frs3_en (io_resp_bits_uop_frs3_en_0), .io_resp_2_bits_uop_fcn_dw (io_resp_bits_uop_fcn_dw_0), .io_resp_2_bits_uop_fcn_op (io_resp_bits_uop_fcn_op_0), .io_resp_2_bits_uop_fp_val (io_resp_bits_uop_fp_val_0), .io_resp_2_bits_uop_fp_rm (io_resp_bits_uop_fp_rm_0), .io_resp_2_bits_uop_fp_typ (io_resp_bits_uop_fp_typ_0), .io_resp_2_bits_uop_xcpt_pf_if (io_resp_bits_uop_xcpt_pf_if_0), .io_resp_2_bits_uop_xcpt_ae_if (io_resp_bits_uop_xcpt_ae_if_0), .io_resp_2_bits_uop_xcpt_ma_if (io_resp_bits_uop_xcpt_ma_if_0), .io_resp_2_bits_uop_bp_debug_if (io_resp_bits_uop_bp_debug_if_0), .io_resp_2_bits_uop_bp_xcpt_if (io_resp_bits_uop_bp_xcpt_if_0), .io_resp_2_bits_uop_debug_fsrc (io_resp_bits_uop_debug_fsrc_0), .io_resp_2_bits_uop_debug_tsrc (io_resp_bits_uop_debug_tsrc_0) ); // @[functional-unit.scala:448:20] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iq_type_1 = io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iq_type_2 = io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iq_type_3 = io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_1 = io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_2 = io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_3 = io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_4 = io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_5 = io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_6 = io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_7 = io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_8 = io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fu_code_9 = io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iw_issued = io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iw_issued_partial_agen = io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iw_issued_partial_dgen = io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iw_p1_speculative_child = io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iw_p2_speculative_child = io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iw_p1_bypass_hint = io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iw_p2_bypass_hint = io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_iw_p3_bypass_hint = io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_dis_col_sel = io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_br_type = io_resp_bits_uop_br_type_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_sfence = io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_eret = io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_rocc = io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_mov = io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_imm_rename = io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_imm_sel = io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_pimm = io_resp_bits_uop_pimm_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_op1_sel = io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_op2_sel = io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_ldst = io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_wen = io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_ren1 = io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_ren2 = io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_ren3 = io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_swap12 = io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_swap23 = io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_typeTagIn = io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_typeTagOut = io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_fromint = io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_toint = io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_fastpipe = io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_fma = io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_div = io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_sqrt = io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_wflags = io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_ctrl_vec = io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_csr_cmd = io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fcn_dw = io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fcn_op = io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_rm = io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_fp_typ = io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:443:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:443:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:443:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }
module IntSyncSyncCrossingSink_n1x1_24( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File DMA.scala: package icenet import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.tilelink._ class StreamReadRequest extends Bundle { val address = UInt(48.W) val length = UInt(15.W) val partial = Bool() } class StreamReader(nXacts: Int, outFlits: Int, maxBytes: Int) (implicit p: Parameters) extends LazyModule { val core = LazyModule(new StreamReaderCore(nXacts, outFlits, maxBytes)) val node = core.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val dataBits = core.module.dataBits val io = IO(new Bundle { val req = Flipped(Decoupled(new StreamReadRequest)) val resp = Decoupled(Bool()) val out = Decoupled(new StreamChannel(dataBits)) }) core.module.io.req <> io.req io.resp <> core.module.io.resp val buffer = Module(new ReservationBuffer(nXacts, outFlits, dataBits)) buffer.io.alloc <> core.module.io.alloc buffer.io.in <> core.module.io.out val aligner = Module(new Aligner(dataBits)) aligner.io.in <> buffer.io.out io.out <> aligner.io.out } } class StreamReaderCore(nXacts: Int, outFlits: Int, maxBytes: Int) (implicit p: Parameters) extends LazyModule { val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = "stream-reader", sourceId = IdRange(0, nXacts)))))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (tl, edge) = node.out(0) val dataBits = tl.params.dataBits val beatBytes = dataBits / 8 val byteAddrBits = log2Ceil(beatBytes) val addrBits = tl.params.addressBits val lenBits = 15 require (edge.manager.minLatency > 0) val io = IO(new Bundle { val req = Flipped(Decoupled(new StreamReadRequest)) val resp = Decoupled(Bool()) val alloc = Decoupled(new ReservationBufferAlloc(nXacts, outFlits)) val out = Decoupled(new ReservationBufferData(nXacts, dataBits)) }) val s_idle :: s_read :: s_resp :: Nil = Enum(3) val state = RegInit(s_idle) // Physical (word) address in memory val sendaddr = Reg(UInt(addrBits.W)) // Number of words to send val sendlen = Reg(UInt(lenBits.W)) // 0 if last packet in sequence, 1 otherwise val sendpart = Reg(Bool()) val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) val xactId = OHToUInt(xactOnehot) val xactLast = Reg(UInt(nXacts.W)) val xactLeftKeep = Reg(Vec(nXacts, UInt(beatBytes.W))) val xactRightKeep = Reg(Vec(nXacts, UInt(beatBytes.W))) val reqSize = MuxCase(byteAddrBits.U, (log2Ceil(maxBytes) until byteAddrBits by -1).map(lgSize => // Use the largest size (beatBytes <= size <= maxBytes) // s.t. sendaddr % size == 0 and sendlen > size (sendaddr(lgSize-1,0) === 0.U && (sendlen >> lgSize.U) =/= 0.U) -> lgSize.U)) val isLast = (xactLast >> tl.d.bits.source)(0) && edge.last(tl.d) val canSend = state === s_read && !xactBusy.andR val fullKeep = ~0.U(beatBytes.W) val loffset = Reg(UInt(byteAddrBits.W)) val roffset = Reg(UInt(byteAddrBits.W)) val lkeep = fullKeep << loffset val rkeep = fullKeep >> roffset val first = Reg(Bool()) xactBusy := (xactBusy | Mux(tl.a.fire, xactOnehot, 0.U)) & ~Mux(tl.d.fire && edge.last(tl.d), UIntToOH(tl.d.bits.source), 0.U) val helper = DecoupledHelper(tl.a.ready, io.alloc.ready) io.req.ready := state === s_idle io.alloc.valid := helper.fire(io.alloc.ready, canSend) io.alloc.bits.id := xactId io.alloc.bits.count := (1.U << (reqSize - byteAddrBits.U)) tl.a.valid := helper.fire(tl.a.ready, canSend) tl.a.bits := edge.Get( fromSource = xactId, toAddress = sendaddr, lgSize = reqSize)._2 val outLeftKeep = xactLeftKeep(tl.d.bits.source) val outRightKeep = xactRightKeep(tl.d.bits.source) io.out.valid := tl.d.valid io.out.bits.id := tl.d.bits.source io.out.bits.data.data := tl.d.bits.data io.out.bits.data.keep := MuxCase(fullKeep, Seq( (edge.first(tl.d) && edge.last(tl.d)) -> (outLeftKeep & outRightKeep), edge.first(tl.d) -> outLeftKeep, edge.last(tl.d) -> outRightKeep)) io.out.bits.data.last := isLast tl.d.ready := io.out.ready io.resp.valid := state === s_resp io.resp.bits := true.B when (io.req.fire) { val req = io.req.bits val lastaddr = req.address + req.length val startword = req.address(addrBits-1, byteAddrBits) val endword = lastaddr(addrBits-1, byteAddrBits) + Mux(lastaddr(byteAddrBits-1, 0) === 0.U, 0.U, 1.U) loffset := req.address(byteAddrBits-1, 0) roffset := Cat(endword, 0.U(byteAddrBits.W)) - lastaddr first := true.B sendaddr := Cat(startword, 0.U(byteAddrBits.W)) sendlen := Cat(endword - startword, 0.U(byteAddrBits.W)) sendpart := req.partial state := s_read assert(req.length > 0.U, "request length must be >0") } when (tl.a.fire) { val reqBytes = 1.U << reqSize sendaddr := sendaddr + reqBytes sendlen := sendlen - reqBytes when (sendlen === reqBytes) { xactLast := (xactLast & ~xactOnehot) | Mux(sendpart, 0.U, xactOnehot) xactRightKeep(xactId) := rkeep state := s_resp } .otherwise { xactLast := xactLast & ~xactOnehot xactRightKeep(xactId) := fullKeep } when (first) { first := false.B xactLeftKeep(xactId) := lkeep } .otherwise { xactLeftKeep(xactId) := fullKeep } } when (io.resp.fire) { state := s_idle } } } class StreamWriteRequest extends Bundle { val address = UInt(48.W) val length = UInt(16.W) } class StreamWriter(nXacts: Int, maxBytes: Int) (implicit p: Parameters) extends LazyModule { val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( name = "stream-writer", sourceId = IdRange(0, nXacts)))))) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (tl, edge) = node.out(0) val dataBits = tl.params.dataBits val beatBytes = dataBits / 8 val byteAddrBits = log2Ceil(beatBytes) val addrBits = tl.params.addressBits val lenBits = 16 require (edge.manager.minLatency > 0) val io = IO(new Bundle { val req = Flipped(Decoupled(new StreamWriteRequest)) val resp = Decoupled(UInt(lenBits.W)) val in = Flipped(Decoupled(new StreamChannel(dataBits))) }) val s_idle :: s_data :: s_resp :: Nil = Enum(3) val state = RegInit(s_idle) val length = Reg(UInt(lenBits.W)) val baseAddr = Reg(UInt(addrBits.W)) val offset = Reg(UInt(addrBits.W)) val addrMerged = baseAddr + offset val bytesToSend = length - offset val baseByteOff = baseAddr(byteAddrBits-1, 0) val byteOff = addrMerged(byteAddrBits-1, 0) val extraBytes = Mux(baseByteOff === 0.U, 0.U, beatBytes.U - baseByteOff) val xactBusy = RegInit(0.U(nXacts.W)) val xactOnehot = PriorityEncoderOH(~xactBusy) val xactId = OHToUInt(xactOnehot) val maxBeats = maxBytes / beatBytes val beatIdBits = log2Ceil(maxBeats) val beatsLeft = Reg(UInt(beatIdBits.W)) val headAddr = Reg(UInt(addrBits.W)) val headXact = Reg(UInt(log2Ceil(nXacts).W)) val headSize = Reg(UInt(log2Ceil(maxBytes + 1).W)) val newBlock = beatsLeft === 0.U val canSend = !xactBusy.andR || !newBlock val reqSize = MuxCase(0.U, (log2Ceil(maxBytes) until 0 by -1).map(lgSize => (addrMerged(lgSize-1,0) === 0.U && (bytesToSend >> lgSize.U) =/= 0.U) -> lgSize.U)) xactBusy := (xactBusy | Mux(tl.a.fire && newBlock, xactOnehot, 0.U)) & ~Mux(tl.d.fire, UIntToOH(tl.d.bits.source), 0.U) val overhang = RegInit(0.U(dataBits.W)) val sendTrail = bytesToSend <= extraBytes val fulldata = (overhang | (io.in.bits.data << Cat(baseByteOff, 0.U(3.W)))) val fromSource = Mux(newBlock, xactId, headXact) val toAddress = Mux(newBlock, addrMerged, headAddr) val lgSize = Mux(newBlock, reqSize, headSize) val wdata = fulldata(dataBits-1, 0) val wmask = Cat((0 until beatBytes).map( i => (i.U >= byteOff) && (i.U < bytesToSend)).reverse) val wpartial = !wmask.andR val putPartial = edge.Put( fromSource = xactId, toAddress = addrMerged & ~(beatBytes-1).U(addrBits.W), lgSize = log2Ceil(beatBytes).U, data = Mux(sendTrail, overhang, wdata), mask = wmask)._2 val putFull = edge.Put( fromSource = fromSource, toAddress = toAddress, lgSize = lgSize, data = wdata)._2 io.req.ready := state === s_idle tl.a.valid := (state === s_data) && (io.in.valid || sendTrail) && canSend tl.a.bits := Mux(wpartial, putPartial, putFull) tl.d.ready := xactBusy.orR io.in.ready := state === s_data && canSend && !sendTrail && tl.a.ready io.resp.valid := state === s_resp && !xactBusy.orR io.resp.bits := length when (io.req.fire) { offset := 0.U baseAddr := io.req.bits.address length := io.req.bits.length beatsLeft := 0.U state := s_data } when (tl.a.fire) { when (!newBlock) { beatsLeft := beatsLeft - 1.U } .elsewhen (reqSize > byteAddrBits.U) { val nBeats = 1.U << (reqSize - byteAddrBits.U) beatsLeft := nBeats - 1.U headAddr := addrMerged headXact := xactId headSize := reqSize } val bytesSent = PopCount(wmask) offset := offset + bytesSent overhang := fulldata >> dataBits.U when (bytesSent === bytesToSend) { state := s_resp } } when (io.resp.fire) { state := s_idle } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. */ sealed trait LazyModuleImpLike extends RawModule { /** [[LazyModule]] that contains this instance. */ val wrapper: LazyModule /** IOs that will be automatically "punched" for this instance. */ val auto: AutoBundle /** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */ protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /** Set module name. Defaults to the containing LazyModule's desiredName. */ override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /** [[Parameters]] for chisel [[Module]]s. */ implicit val p: Parameters = wrapper.p /** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. */ protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /** Instantiate hardware of this `Module`. */ val (auto, dangles) = instantiate() } /** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. */ class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /** drive clock explicitly. */ val childClock: Clock = Wire(Clock()) /** drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} |acquireB = ${acquireB} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} |arithmetic = ${arithmetic} |logical = ${logical} |get = ${get} |putFull = ${putFull} |putPartial = ${putPartial} |hint = ${hint} | |""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB || supportsGet, w = supportsAcquireT || supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} |Slave Address = ${address} |supports = ${supports.infoString} | |""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ || _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B || s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_||_) }.foldLeft(false.B)(_||_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} |visibility = ${visibility} |emits = ${emits.infoString} |sourceId = ${sourceId} | |""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_||_) }.foldLeft(false.B)(_||_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE || x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps */ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /** One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. */ case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module */ case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. */ case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */ case object MonitorsEnabled extends Field[Boolean](true) /** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. */ case object RenderFlipped extends Field[Boolean](false) /** The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} */ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /** Debug info of nodes binding. */ def bindingInfo: String = s"""$iBindingInfo |$oBindingInfo |""".stripMargin /** Debug info of ports connecting. */ def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] |${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] |""".stripMargin /** Debug info of parameters propagations. */ def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] |${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] |${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] |${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] |""".stripMargin /** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. */ protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /** Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. */ protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. */ protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /** @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. */ protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /** @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. */ protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /** @return list of nodes involved in flex bindings with this node. */ protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. */ protected[diplomacy] lazy val flexOffset: Int = { /** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. */ def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) || !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a :*=* b :*=* c * d :*=* b * e :*=* f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` */ val flexSet = DFS(this, Map()).values /** The total number of :*= operators where we're on the left. */ val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. */ val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 || allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */ protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /** For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. */ protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */ private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*= * bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N` */ protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo :=* N // + Number of bar :=* foo :*=* N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N :*= foo // + Number of N :*=* foo :*= bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar :*= foo :*=* N // + foo.iStar for foo :*= N // + 0 for foo :=* N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N :*=* foo :=* bar // + foo.oStar for N :=* foo // + 0 for N :*= foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /** Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. */ protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /** Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. */ protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. */ lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of outward ports should equal the number of produced outward parameters. |$context |$connectedPortsInfo |Downstreamed inward parameters: [${diParams.mkString(",")}] |Produced outward parameters: [${o.mkString(",")}] |""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: |At the following node, the number of inward ports should equal the number of produced inward parameters. |$context |$connectedPortsInfo |Upstreamed outward parameters: [${uoParams.mkString(",")}] |Produced inward parameters: [${i.mkString(",")}] |""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /** Outward edge parameters. */ protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /** Inward edge parameters. */ protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /** A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). */ lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */ protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */ protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */ protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */ protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /** Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /** Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. */ def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. */ protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /** Connects the outward part of a node with the inward part of this node. */ protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } /* Metadata for printing the node graph. */ def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /** Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module StreamWriter( // @[DMA.scala:188:9] input clock, // @[DMA.scala:188:9] input reset, // @[DMA.scala:188:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_req_ready, // @[DMA.scala:198:16] input io_req_valid, // @[DMA.scala:198:16] input [47:0] io_req_bits_address, // @[DMA.scala:198:16] input [15:0] io_req_bits_length, // @[DMA.scala:198:16] input io_resp_ready, // @[DMA.scala:198:16] output io_resp_valid, // @[DMA.scala:198:16] output [15:0] io_resp_bits, // @[DMA.scala:198:16] output io_in_ready, // @[DMA.scala:198:16] input io_in_valid, // @[DMA.scala:198:16] input [63:0] io_in_bits_data, // @[DMA.scala:198:16] input [7:0] io_in_bits_keep, // @[DMA.scala:198:16] input io_in_bits_last // @[DMA.scala:198:16] ); wire auto_out_a_ready_0 = auto_out_a_ready; // @[DMA.scala:188:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DMA.scala:188:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DMA.scala:188:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DMA.scala:188:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DMA.scala:188:9] wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DMA.scala:188:9] wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DMA.scala:188:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DMA.scala:188:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DMA.scala:188:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DMA.scala:188:9] wire io_req_valid_0 = io_req_valid; // @[DMA.scala:188:9] wire [47:0] io_req_bits_address_0 = io_req_bits_address; // @[DMA.scala:188:9] wire [15:0] io_req_bits_length_0 = io_req_bits_length; // @[DMA.scala:188:9] wire io_resp_ready_0 = io_resp_ready; // @[DMA.scala:188:9] wire io_in_valid_0 = io_in_valid; // @[DMA.scala:188:9] wire [63:0] io_in_bits_data_0 = io_in_bits_data; // @[DMA.scala:188:9] wire [7:0] io_in_bits_keep_0 = io_in_bits_keep; // @[DMA.scala:188:9] wire io_in_bits_last_0 = io_in_bits_last; // @[DMA.scala:188:9] wire [31:0] _putPartial_T = 32'hFFFFFFF8; // @[DMA.scala:253:32] wire [2:0] putPartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [3:0] putPartial_size = 4'h3; // @[Edges.scala:500:17] wire _wmask_T_21 = 1'h1; // @[DMA.scala:248:17] wire _putPartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putPartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putPartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putPartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putPartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putPartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _putPartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _putPartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _putFull_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putFull_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire auto_out_a_bits_corrupt = 1'h0; // @[DMA.scala:188:9] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _putPartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:29] wire _putPartial_legal_T_74 = 1'h0; // @[Parameters.scala:684:54] wire putPartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire _putFull_legal_T_68 = 1'h0; // @[Parameters.scala:684:29] wire _putFull_legal_T_74 = 1'h0; // @[Parameters.scala:684:54] wire putFull_corrupt = 1'h0; // @[Edges.scala:480:17] wire _nodeOut_a_bits_T_corrupt = 1'h0; // @[DMA.scala:266:21] wire [2:0] auto_out_a_bits_param = 3'h0; // @[DMA.scala:188:9] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] putPartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] putFull_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] putFull_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _nodeOut_a_bits_T_param = 3'h0; // @[DMA.scala:266:21] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DMA.scala:188:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DMA.scala:188:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DMA.scala:188:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DMA.scala:188:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DMA.scala:188:9] wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DMA.scala:188:9] wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DMA.scala:188:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DMA.scala:188:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DMA.scala:188:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DMA.scala:188:9] wire _io_req_ready_T; // @[DMA.scala:264:27] wire _io_resp_valid_T_3; // @[DMA.scala:269:39] wire _io_in_ready_T_4; // @[DMA.scala:268:62] wire [2:0] auto_out_a_bits_opcode_0; // @[DMA.scala:188:9] wire [3:0] auto_out_a_bits_size_0; // @[DMA.scala:188:9] wire [2:0] auto_out_a_bits_source_0; // @[DMA.scala:188:9] wire [31:0] auto_out_a_bits_address_0; // @[DMA.scala:188:9] wire [7:0] auto_out_a_bits_mask_0; // @[DMA.scala:188:9] wire [63:0] auto_out_a_bits_data_0; // @[DMA.scala:188:9] wire auto_out_a_valid_0; // @[DMA.scala:188:9] wire auto_out_d_ready_0; // @[DMA.scala:188:9] wire io_req_ready_0; // @[DMA.scala:188:9] wire io_resp_valid_0; // @[DMA.scala:188:9] wire [15:0] io_resp_bits_0; // @[DMA.scala:188:9] wire io_in_ready_0; // @[DMA.scala:188:9] wire _nodeOut_a_valid_T_3; // @[DMA.scala:265:68] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DMA.scala:188:9] wire [2:0] _nodeOut_a_bits_T_opcode; // @[DMA.scala:266:21] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DMA.scala:188:9] wire [3:0] _nodeOut_a_bits_T_size; // @[DMA.scala:266:21] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DMA.scala:188:9] wire [2:0] _nodeOut_a_bits_T_source; // @[DMA.scala:266:21] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DMA.scala:188:9] wire [31:0] _nodeOut_a_bits_T_address; // @[DMA.scala:266:21] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DMA.scala:188:9] wire [7:0] _nodeOut_a_bits_T_mask; // @[DMA.scala:266:21] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DMA.scala:188:9] wire [63:0] _nodeOut_a_bits_T_data; // @[DMA.scala:266:21] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DMA.scala:188:9] wire _nodeOut_d_ready_T; // @[DMA.scala:267:28] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DMA.scala:188:9] reg [1:0] state; // @[DMA.scala:205:24] reg [15:0] length; // @[DMA.scala:207:21] assign io_resp_bits_0 = length; // @[DMA.scala:188:9, :207:21] reg [31:0] baseAddr; // @[DMA.scala:208:23] reg [31:0] offset; // @[DMA.scala:209:21] wire [32:0] _GEN = {1'h0, offset}; // @[DMA.scala:209:21, :210:31] wire [32:0] _addrMerged_T = {1'h0, baseAddr} + _GEN; // @[DMA.scala:208:23, :210:31] wire [31:0] addrMerged = _addrMerged_T[31:0]; // @[DMA.scala:210:31] wire [32:0] _bytesToSend_T = {17'h0, length} - _GEN; // @[DMA.scala:207:21, :210:31, :211:30] wire [31:0] bytesToSend = _bytesToSend_T[31:0]; // @[DMA.scala:211:30] wire [2:0] baseByteOff = baseAddr[2:0]; // @[DMA.scala:208:23, :212:31] wire [2:0] byteOff = addrMerged[2:0]; // @[DMA.scala:210:31, :213:29] wire [2:0] _reqSize_T_15 = addrMerged[2:0]; // @[DMA.scala:210:31, :213:29, :233:22] wire _extraBytes_T = baseByteOff == 3'h0; // @[DMA.scala:212:31, :214:38] wire [4:0] _extraBytes_T_1 = 5'h8 - {2'h0, baseByteOff}; // @[DMA.scala:212:31, :214:64] wire [3:0] _extraBytes_T_2 = _extraBytes_T_1[3:0]; // @[DMA.scala:214:64] wire [3:0] extraBytes = _extraBytes_T ? 4'h0 : _extraBytes_T_2; // @[DMA.scala:214:{25,38,64}] reg [7:0] xactBusy; // @[DMA.scala:216:27] wire [7:0] _xactOnehot_T = ~xactBusy; // @[DMA.scala:216:27, :217:40] wire _xactOnehot_T_1 = _xactOnehot_T[0]; // @[OneHot.scala:85:71] wire _xactOnehot_T_2 = _xactOnehot_T[1]; // @[OneHot.scala:85:71] wire _xactOnehot_T_3 = _xactOnehot_T[2]; // @[OneHot.scala:85:71] wire _xactOnehot_T_4 = _xactOnehot_T[3]; // @[OneHot.scala:85:71] wire _xactOnehot_T_5 = _xactOnehot_T[4]; // @[OneHot.scala:85:71] wire _xactOnehot_T_6 = _xactOnehot_T[5]; // @[OneHot.scala:85:71] wire _xactOnehot_T_7 = _xactOnehot_T[6]; // @[OneHot.scala:85:71] wire _xactOnehot_T_8 = _xactOnehot_T[7]; // @[OneHot.scala:85:71] wire [7:0] _xactOnehot_T_9 = {_xactOnehot_T_8, 7'h0}; // @[OneHot.scala:85:71] wire [7:0] _xactOnehot_T_10 = _xactOnehot_T_7 ? 8'h40 : _xactOnehot_T_9; // @[OneHot.scala:85:71] wire [7:0] _xactOnehot_T_11 = _xactOnehot_T_6 ? 8'h20 : _xactOnehot_T_10; // @[OneHot.scala:85:71] wire [7:0] _xactOnehot_T_12 = _xactOnehot_T_5 ? 8'h10 : _xactOnehot_T_11; // @[OneHot.scala:85:71] wire [7:0] _xactOnehot_T_13 = _xactOnehot_T_4 ? 8'h8 : _xactOnehot_T_12; // @[OneHot.scala:85:71] wire [7:0] _xactOnehot_T_14 = _xactOnehot_T_3 ? 8'h4 : _xactOnehot_T_13; // @[OneHot.scala:85:71] wire [7:0] _xactOnehot_T_15 = _xactOnehot_T_2 ? 8'h2 : _xactOnehot_T_14; // @[OneHot.scala:85:71] wire [7:0] xactOnehot = _xactOnehot_T_1 ? 8'h1 : _xactOnehot_T_15; // @[OneHot.scala:58:35, :85:71] wire [3:0] xactId_hi = xactOnehot[7:4]; // @[OneHot.scala:30:18] wire [3:0] xactId_lo = xactOnehot[3:0]; // @[OneHot.scala:31:18] wire _xactId_T = |xactId_hi; // @[OneHot.scala:30:18, :32:14] wire [3:0] _xactId_T_1 = xactId_hi | xactId_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] xactId_hi_1 = _xactId_T_1[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] xactId_lo_1 = _xactId_T_1[1:0]; // @[OneHot.scala:31:18, :32:28] wire _xactId_T_2 = |xactId_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _xactId_T_3 = xactId_hi_1 | xactId_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _xactId_T_4 = _xactId_T_3[1]; // @[OneHot.scala:32:28] wire [1:0] _xactId_T_5 = {_xactId_T_2, _xactId_T_4}; // @[OneHot.scala:32:{10,14}] wire [2:0] xactId = {_xactId_T, _xactId_T_5}; // @[OneHot.scala:32:{10,14}] wire [2:0] putPartial_source = xactId; // @[OneHot.scala:32:10] reg [2:0] beatsLeft; // @[DMA.scala:223:24] reg [31:0] headAddr; // @[DMA.scala:224:23] reg [2:0] headXact; // @[DMA.scala:225:23] reg [6:0] headSize; // @[DMA.scala:226:23] wire newBlock = beatsLeft == 3'h0; // @[DMA.scala:223:24, :228:30] wire _canSend_T = &xactBusy; // @[DMA.scala:216:27, :229:29] wire _canSend_T_1 = ~_canSend_T; // @[DMA.scala:229:{19,29}] wire _canSend_T_2 = ~newBlock; // @[DMA.scala:228:30, :229:37] wire canSend = _canSend_T_1 | _canSend_T_2; // @[DMA.scala:229:{19,34,37}] wire [5:0] _reqSize_T = addrMerged[5:0]; // @[DMA.scala:210:31, :233:22] wire _reqSize_T_1 = _reqSize_T == 6'h0; // @[DMA.scala:233:{22,35}] wire [31:0] _reqSize_T_2 = {6'h0, bytesToSend[31:6]}; // @[DMA.scala:211:30, :233:35, :234:26] wire _reqSize_T_3 = |_reqSize_T_2; // @[DMA.scala:234:{26,39}] wire _reqSize_T_4 = _reqSize_T_1 & _reqSize_T_3; // @[DMA.scala:233:{35,43}, :234:39] wire [4:0] _reqSize_T_5 = addrMerged[4:0]; // @[DMA.scala:210:31, :233:22] wire _reqSize_T_6 = _reqSize_T_5 == 5'h0; // @[DMA.scala:233:{22,35}] wire [31:0] _reqSize_T_7 = {5'h0, bytesToSend[31:5]}; // @[DMA.scala:211:30, :233:35, :234:26] wire _reqSize_T_8 = |_reqSize_T_7; // @[DMA.scala:234:{26,39}] wire _reqSize_T_9 = _reqSize_T_6 & _reqSize_T_8; // @[DMA.scala:233:{35,43}, :234:39] wire [3:0] _reqSize_T_10 = addrMerged[3:0]; // @[DMA.scala:210:31, :233:22] wire _reqSize_T_11 = _reqSize_T_10 == 4'h0; // @[DMA.scala:233:{22,35}] wire [31:0] _reqSize_T_12 = {4'h0, bytesToSend[31:4]}; // @[DMA.scala:211:30, :234:26] wire _reqSize_T_13 = |_reqSize_T_12; // @[DMA.scala:234:{26,39}] wire _reqSize_T_14 = _reqSize_T_11 & _reqSize_T_13; // @[DMA.scala:233:{35,43}, :234:39] wire _reqSize_T_16 = _reqSize_T_15 == 3'h0; // @[DMA.scala:233:{22,35}] wire [31:0] _reqSize_T_17 = {3'h0, bytesToSend[31:3]}; // @[DMA.scala:211:30, :234:26] wire _reqSize_T_18 = |_reqSize_T_17; // @[DMA.scala:234:{26,39}] wire _reqSize_T_19 = _reqSize_T_16 & _reqSize_T_18; // @[DMA.scala:233:{35,43}, :234:39] wire [1:0] _reqSize_T_20 = addrMerged[1:0]; // @[DMA.scala:210:31, :233:22] wire _reqSize_T_21 = _reqSize_T_20 == 2'h0; // @[DMA.scala:233:{22,35}] wire [31:0] _reqSize_T_22 = {2'h0, bytesToSend[31:2]}; // @[DMA.scala:211:30, :234:26] wire _reqSize_T_23 = |_reqSize_T_22; // @[DMA.scala:234:{26,39}] wire _reqSize_T_24 = _reqSize_T_21 & _reqSize_T_23; // @[DMA.scala:233:{35,43}, :234:39] wire _reqSize_T_25 = addrMerged[0]; // @[DMA.scala:210:31, :233:22] wire _reqSize_T_26 = ~_reqSize_T_25; // @[DMA.scala:233:{22,35}] wire [31:0] _reqSize_T_27 = {1'h0, bytesToSend[31:1]}; // @[DMA.scala:211:30, :234:26] wire _reqSize_T_28 = |_reqSize_T_27; // @[DMA.scala:234:{26,39}] wire _reqSize_T_29 = _reqSize_T_26 & _reqSize_T_28; // @[DMA.scala:233:{35,43}, :234:39] wire _reqSize_T_30 = _reqSize_T_29; // @[Mux.scala:126:16] wire [1:0] _reqSize_T_31 = _reqSize_T_24 ? 2'h2 : {1'h0, _reqSize_T_30}; // @[Mux.scala:126:16] wire [1:0] _reqSize_T_32 = _reqSize_T_19 ? 2'h3 : _reqSize_T_31; // @[Mux.scala:126:16] wire [2:0] _reqSize_T_33 = _reqSize_T_14 ? 3'h4 : {1'h0, _reqSize_T_32}; // @[Mux.scala:126:16] wire [2:0] _reqSize_T_34 = _reqSize_T_9 ? 3'h5 : _reqSize_T_33; // @[Mux.scala:126:16] wire [2:0] reqSize = _reqSize_T_4 ? 3'h6 : _reqSize_T_34; // @[Mux.scala:126:16] wire _xactBusy_T = nodeOut_a_ready & nodeOut_a_valid; // @[Decoupled.scala:51:35] wire _xactBusy_T_1 = _xactBusy_T & newBlock; // @[Decoupled.scala:51:35] wire [7:0] _xactBusy_T_2 = _xactBusy_T_1 ? xactOnehot : 8'h0; // @[Mux.scala:50:70] wire [7:0] _xactBusy_T_3 = xactBusy | _xactBusy_T_2; // @[DMA.scala:216:27, :236:{27,32}] wire _xactBusy_T_4 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire [7:0] _xactBusy_T_5 = 8'h1 << nodeOut_d_bits_source; // @[OneHot.scala:58:35] wire [7:0] _xactBusy_T_6 = _xactBusy_T_4 ? _xactBusy_T_5 : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _xactBusy_T_7 = ~_xactBusy_T_6; // @[DMA.scala:237:{21,25}] wire [7:0] _xactBusy_T_8 = _xactBusy_T_3 & _xactBusy_T_7; // @[DMA.scala:236:{27,74}, :237:21] reg [63:0] overhang; // @[DMA.scala:239:27] wire sendTrail = bytesToSend <= {28'h0, extraBytes}; // @[DMA.scala:211:30, :214:25, :240:33] wire [5:0] _fulldata_T = {baseByteOff, 3'h0}; // @[DMA.scala:212:31, :241:55] wire [126:0] _fulldata_T_1 = {63'h0, io_in_bits_data_0} << _fulldata_T; // @[DMA.scala:188:9, :241:{49,55}] wire [126:0] fulldata = {63'h0, overhang} | _fulldata_T_1; // @[DMA.scala:239:27, :241:{30,49}] wire [2:0] fromSource = newBlock ? xactId : headXact; // @[OneHot.scala:32:10] wire [2:0] putFull_source = fromSource; // @[Edges.scala:480:17] wire [31:0] toAddress = newBlock ? addrMerged : headAddr; // @[DMA.scala:210:31, :224:23, :228:30, :244:24] wire [31:0] _putFull_legal_T_14 = toAddress; // @[Parameters.scala:137:31] wire [31:0] putFull_address = toAddress; // @[Edges.scala:480:17] wire [6:0] _GEN_0 = {4'h0, reqSize}; // @[Mux.scala:126:16] wire [6:0] lgSize = newBlock ? _GEN_0 : headSize; // @[DMA.scala:226:23, :228:30, :245:21] wire [6:0] _putFull_a_mask_sizeOH_T = lgSize; // @[Misc.scala:202:34] wire [63:0] wdata = fulldata[63:0]; // @[DMA.scala:241:30, :246:25] wire [63:0] putFull_data = wdata; // @[Edges.scala:480:17] wire _wmask_T = byteOff == 3'h0; // @[DMA.scala:213:29, :248:17] wire _wmask_T_1 = |bytesToSend; // @[DMA.scala:211:30, :248:37] wire _wmask_T_2 = _wmask_T & _wmask_T_1; // @[DMA.scala:248:{17,29,37}] wire _wmask_T_3 = byteOff < 3'h2; // @[DMA.scala:213:29, :248:17] wire _wmask_T_4 = |(bytesToSend[31:1]); // @[DMA.scala:211:30, :234:26, :248:37] wire _wmask_T_5 = _wmask_T_3 & _wmask_T_4; // @[DMA.scala:248:{17,29,37}] wire _wmask_T_6 = byteOff < 3'h3; // @[DMA.scala:213:29, :248:17] wire _wmask_T_7 = bytesToSend > 32'h2; // @[DMA.scala:211:30, :248:37] wire _wmask_T_8 = _wmask_T_6 & _wmask_T_7; // @[DMA.scala:248:{17,29,37}] wire _wmask_T_9 = ~(byteOff[2]); // @[DMA.scala:213:29, :248:17] wire _wmask_T_10 = |(bytesToSend[31:2]); // @[DMA.scala:211:30, :234:26, :248:37] wire _wmask_T_11 = _wmask_T_9 & _wmask_T_10; // @[DMA.scala:248:{17,29,37}] wire _wmask_T_12 = byteOff < 3'h5; // @[DMA.scala:213:29, :248:17] wire _wmask_T_13 = bytesToSend > 32'h4; // @[DMA.scala:211:30, :248:37] wire _wmask_T_14 = _wmask_T_12 & _wmask_T_13; // @[DMA.scala:248:{17,29,37}] wire _wmask_T_15 = byteOff[2:1] != 2'h3; // @[DMA.scala:213:29, :248:17] wire _wmask_T_16 = bytesToSend > 32'h5; // @[DMA.scala:211:30, :248:37] wire _wmask_T_17 = _wmask_T_15 & _wmask_T_16; // @[DMA.scala:248:{17,29,37}] wire _wmask_T_18 = byteOff != 3'h7; // @[DMA.scala:213:29, :248:17] wire _wmask_T_19 = bytesToSend > 32'h6; // @[DMA.scala:211:30, :248:37] wire _wmask_T_20 = _wmask_T_18 & _wmask_T_19; // @[DMA.scala:248:{17,29,37}] wire _wmask_T_22 = |(bytesToSend[31:3]); // @[DMA.scala:211:30, :234:26, :248:37] wire _wmask_T_23 = _wmask_T_22; // @[DMA.scala:248:{29,37}] wire [1:0] wmask_lo_lo = {_wmask_T_5, _wmask_T_2}; // @[DMA.scala:247:20, :248:29] wire [1:0] wmask_lo_hi = {_wmask_T_11, _wmask_T_8}; // @[DMA.scala:247:20, :248:29] wire [3:0] wmask_lo = {wmask_lo_hi, wmask_lo_lo}; // @[DMA.scala:247:20] wire [1:0] wmask_hi_lo = {_wmask_T_17, _wmask_T_14}; // @[DMA.scala:247:20, :248:29] wire [1:0] wmask_hi_hi = {_wmask_T_23, _wmask_T_20}; // @[DMA.scala:247:20, :248:29] wire [3:0] wmask_hi = {wmask_hi_hi, wmask_hi_lo}; // @[DMA.scala:247:20] wire [7:0] wmask = {wmask_hi, wmask_lo}; // @[DMA.scala:247:20] wire [7:0] putPartial_mask = wmask; // @[Edges.scala:500:17] wire _wpartial_T = &wmask; // @[DMA.scala:247:20, :249:27] wire wpartial = ~_wpartial_T; // @[DMA.scala:249:{20,27}] wire [31:0] _putPartial_T_1 = addrMerged & 32'hFFFFFFF8; // @[DMA.scala:210:31, :253:30] wire [31:0] _putPartial_legal_T_14 = _putPartial_T_1; // @[Parameters.scala:137:31] wire [31:0] putPartial_address = _putPartial_T_1; // @[Edges.scala:500:17] wire [63:0] _putPartial_T_2 = sendTrail ? overhang : wdata; // @[DMA.scala:239:27, :240:33, :246:25, :255:17] wire [63:0] putPartial_data = _putPartial_T_2; // @[Edges.scala:500:17] wire [31:0] _putPartial_legal_T_4 = {_putPartial_T_1[31:14], _putPartial_T_1[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_5 = {1'h0, _putPartial_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_6 = _putPartial_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_7 = _putPartial_legal_T_6; // @[Parameters.scala:137:46] wire _putPartial_legal_T_8 = _putPartial_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _putPartial_legal_T_9 = _putPartial_legal_T_8; // @[Parameters.scala:684:54] wire _putPartial_legal_T_75 = _putPartial_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [32:0] _putPartial_legal_T_15 = {1'h0, _putPartial_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_16 = _putPartial_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_17 = _putPartial_legal_T_16; // @[Parameters.scala:137:46] wire _putPartial_legal_T_18 = _putPartial_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putPartial_legal_T_19 = {_putPartial_T_1[31:21], _putPartial_T_1[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_20 = {1'h0, _putPartial_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_21 = _putPartial_legal_T_20 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_22 = _putPartial_legal_T_21; // @[Parameters.scala:137:46] wire _putPartial_legal_T_23 = _putPartial_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putPartial_legal_T_24 = {_putPartial_T_1[31:26], _putPartial_T_1[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_25 = {1'h0, _putPartial_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_26 = _putPartial_legal_T_25 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_27 = _putPartial_legal_T_26; // @[Parameters.scala:137:46] wire _putPartial_legal_T_28 = _putPartial_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putPartial_legal_T_29 = {_putPartial_T_1[31:26], _putPartial_T_1[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_30 = {1'h0, _putPartial_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_31 = _putPartial_legal_T_30 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_32 = _putPartial_legal_T_31; // @[Parameters.scala:137:46] wire _putPartial_legal_T_33 = _putPartial_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_1 = {_putPartial_T_1[31:28], _putPartial_T_1[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _putPartial_legal_T_34; // @[Parameters.scala:137:31] assign _putPartial_legal_T_34 = _GEN_1; // @[Parameters.scala:137:31] wire [31:0] _putPartial_legal_T_39; // @[Parameters.scala:137:31] assign _putPartial_legal_T_39 = _GEN_1; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_35 = {1'h0, _putPartial_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_36 = _putPartial_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_37 = _putPartial_legal_T_36; // @[Parameters.scala:137:46] wire _putPartial_legal_T_38 = _putPartial_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _putPartial_legal_T_40 = {1'h0, _putPartial_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_41 = _putPartial_legal_T_40 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_42 = _putPartial_legal_T_41; // @[Parameters.scala:137:46] wire _putPartial_legal_T_43 = _putPartial_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putPartial_legal_T_44 = {_putPartial_T_1[31:29], _putPartial_T_1[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_45 = {1'h0, _putPartial_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_46 = _putPartial_legal_T_45 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_47 = _putPartial_legal_T_46; // @[Parameters.scala:137:46] wire _putPartial_legal_T_48 = _putPartial_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putPartial_legal_T_49 = {_putPartial_T_1[31:29], _putPartial_T_1[28:0] ^ 29'h10012000}; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_50 = {1'h0, _putPartial_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_51 = _putPartial_legal_T_50 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_52 = _putPartial_legal_T_51; // @[Parameters.scala:137:46] wire _putPartial_legal_T_53 = _putPartial_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putPartial_legal_T_54 = _putPartial_T_1 ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_55 = {1'h0, _putPartial_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_56 = _putPartial_legal_T_55 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_57 = _putPartial_legal_T_56; // @[Parameters.scala:137:46] wire _putPartial_legal_T_58 = _putPartial_legal_T_57 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _putPartial_legal_T_59 = _putPartial_legal_T_18 | _putPartial_legal_T_23; // @[Parameters.scala:685:42] wire _putPartial_legal_T_60 = _putPartial_legal_T_59 | _putPartial_legal_T_28; // @[Parameters.scala:685:42] wire _putPartial_legal_T_61 = _putPartial_legal_T_60 | _putPartial_legal_T_33; // @[Parameters.scala:685:42] wire _putPartial_legal_T_62 = _putPartial_legal_T_61 | _putPartial_legal_T_38; // @[Parameters.scala:685:42] wire _putPartial_legal_T_63 = _putPartial_legal_T_62 | _putPartial_legal_T_43; // @[Parameters.scala:685:42] wire _putPartial_legal_T_64 = _putPartial_legal_T_63 | _putPartial_legal_T_48; // @[Parameters.scala:685:42] wire _putPartial_legal_T_65 = _putPartial_legal_T_64 | _putPartial_legal_T_53; // @[Parameters.scala:685:42] wire _putPartial_legal_T_66 = _putPartial_legal_T_65 | _putPartial_legal_T_58; // @[Parameters.scala:685:42] wire _putPartial_legal_T_67 = _putPartial_legal_T_66; // @[Parameters.scala:684:54, :685:42] wire [31:0] _putPartial_legal_T_69 = {_putPartial_T_1[31:17], _putPartial_T_1[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _putPartial_legal_T_70 = {1'h0, _putPartial_legal_T_69}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putPartial_legal_T_71 = _putPartial_legal_T_70 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putPartial_legal_T_72 = _putPartial_legal_T_71; // @[Parameters.scala:137:46] wire _putPartial_legal_T_73 = _putPartial_legal_T_72 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _putPartial_legal_T_76 = _putPartial_legal_T_75 | _putPartial_legal_T_67; // @[Parameters.scala:684:54, :686:26] wire putPartial_legal = _putPartial_legal_T_76; // @[Parameters.scala:686:26] wire _putFull_legal_T_1 = lgSize < 7'hD; // @[Parameters.scala:92:38] wire _putFull_legal_T_2 = _putFull_legal_T_1; // @[Parameters.scala:92:{33,38}] wire _putFull_legal_T_3 = _putFull_legal_T_2; // @[Parameters.scala:684:29] wire [31:0] _putFull_legal_T_4 = {toAddress[31:14], toAddress[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_5 = {1'h0, _putFull_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_6 = _putFull_legal_T_5 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_7 = _putFull_legal_T_6; // @[Parameters.scala:137:46] wire _putFull_legal_T_8 = _putFull_legal_T_7 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _putFull_legal_T_9 = _putFull_legal_T_3 & _putFull_legal_T_8; // @[Parameters.scala:684:{29,54}] wire _putFull_legal_T_75 = _putFull_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _putFull_legal_T_11 = lgSize < 7'h7; // @[Parameters.scala:92:38] wire _putFull_legal_T_12 = _putFull_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _putFull_legal_T_13 = _putFull_legal_T_12; // @[Parameters.scala:684:29] wire [32:0] _putFull_legal_T_15 = {1'h0, _putFull_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_16 = _putFull_legal_T_15 & 33'h9A112000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_17 = _putFull_legal_T_16; // @[Parameters.scala:137:46] wire _putFull_legal_T_18 = _putFull_legal_T_17 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putFull_legal_T_19 = {toAddress[31:21], toAddress[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_20 = {1'h0, _putFull_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_21 = _putFull_legal_T_20 & 33'h9A103000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_22 = _putFull_legal_T_21; // @[Parameters.scala:137:46] wire _putFull_legal_T_23 = _putFull_legal_T_22 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putFull_legal_T_24 = {toAddress[31:26], toAddress[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_25 = {1'h0, _putFull_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_26 = _putFull_legal_T_25 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_27 = _putFull_legal_T_26; // @[Parameters.scala:137:46] wire _putFull_legal_T_28 = _putFull_legal_T_27 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putFull_legal_T_29 = {toAddress[31:26], toAddress[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_30 = {1'h0, _putFull_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_31 = _putFull_legal_T_30 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_32 = _putFull_legal_T_31; // @[Parameters.scala:137:46] wire _putFull_legal_T_33 = _putFull_legal_T_32 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _GEN_2 = {toAddress[31:28], toAddress[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [31:0] _putFull_legal_T_34; // @[Parameters.scala:137:31] assign _putFull_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [31:0] _putFull_legal_T_39; // @[Parameters.scala:137:31] assign _putFull_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_35 = {1'h0, _putFull_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_36 = _putFull_legal_T_35 & 33'h98000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_37 = _putFull_legal_T_36; // @[Parameters.scala:137:46] wire _putFull_legal_T_38 = _putFull_legal_T_37 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [32:0] _putFull_legal_T_40 = {1'h0, _putFull_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_41 = _putFull_legal_T_40 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_42 = _putFull_legal_T_41; // @[Parameters.scala:137:46] wire _putFull_legal_T_43 = _putFull_legal_T_42 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putFull_legal_T_44 = {toAddress[31:29], toAddress[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_45 = {1'h0, _putFull_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_46 = _putFull_legal_T_45 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_47 = _putFull_legal_T_46; // @[Parameters.scala:137:46] wire _putFull_legal_T_48 = _putFull_legal_T_47 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putFull_legal_T_49 = {toAddress[31:29], toAddress[28:0] ^ 29'h10012000}; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_50 = {1'h0, _putFull_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_51 = _putFull_legal_T_50 & 33'h9A113000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_52 = _putFull_legal_T_51; // @[Parameters.scala:137:46] wire _putFull_legal_T_53 = _putFull_legal_T_52 == 33'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] _putFull_legal_T_54 = toAddress ^ 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_55 = {1'h0, _putFull_legal_T_54}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_56 = _putFull_legal_T_55 & 33'h90000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_57 = _putFull_legal_T_56; // @[Parameters.scala:137:46] wire _putFull_legal_T_58 = _putFull_legal_T_57 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _putFull_legal_T_59 = _putFull_legal_T_18 | _putFull_legal_T_23; // @[Parameters.scala:685:42] wire _putFull_legal_T_60 = _putFull_legal_T_59 | _putFull_legal_T_28; // @[Parameters.scala:685:42] wire _putFull_legal_T_61 = _putFull_legal_T_60 | _putFull_legal_T_33; // @[Parameters.scala:685:42] wire _putFull_legal_T_62 = _putFull_legal_T_61 | _putFull_legal_T_38; // @[Parameters.scala:685:42] wire _putFull_legal_T_63 = _putFull_legal_T_62 | _putFull_legal_T_43; // @[Parameters.scala:685:42] wire _putFull_legal_T_64 = _putFull_legal_T_63 | _putFull_legal_T_48; // @[Parameters.scala:685:42] wire _putFull_legal_T_65 = _putFull_legal_T_64 | _putFull_legal_T_53; // @[Parameters.scala:685:42] wire _putFull_legal_T_66 = _putFull_legal_T_65 | _putFull_legal_T_58; // @[Parameters.scala:685:42] wire _putFull_legal_T_67 = _putFull_legal_T_13 & _putFull_legal_T_66; // @[Parameters.scala:684:{29,54}, :685:42] wire [31:0] _putFull_legal_T_69 = {toAddress[31:17], toAddress[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [32:0] _putFull_legal_T_70 = {1'h0, _putFull_legal_T_69}; // @[Parameters.scala:137:{31,41}] wire [32:0] _putFull_legal_T_71 = _putFull_legal_T_70 & 33'h9A110000; // @[Parameters.scala:137:{41,46}] wire [32:0] _putFull_legal_T_72 = _putFull_legal_T_71; // @[Parameters.scala:137:46] wire _putFull_legal_T_73 = _putFull_legal_T_72 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _putFull_legal_T_76 = _putFull_legal_T_75 | _putFull_legal_T_67; // @[Parameters.scala:684:54, :686:26] wire putFull_legal = _putFull_legal_T_76; // @[Parameters.scala:686:26] wire [7:0] _putFull_a_mask_T; // @[Misc.scala:222:10] wire [3:0] putFull_size; // @[Edges.scala:480:17] wire [7:0] putFull_mask; // @[Edges.scala:480:17] assign putFull_size = lgSize[3:0]; // @[Edges.scala:480:17, :483:15] wire [1:0] putFull_a_mask_sizeOH_shiftAmount = _putFull_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _putFull_a_mask_sizeOH_T_1 = 4'h1 << putFull_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _putFull_a_mask_sizeOH_T_2 = _putFull_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] putFull_a_mask_sizeOH = {_putFull_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire putFull_a_mask_sub_sub_sub_0_1 = lgSize > 7'h2; // @[Misc.scala:206:21] wire putFull_a_mask_sub_sub_size = putFull_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire putFull_a_mask_sub_sub_bit = toAddress[2]; // @[Misc.scala:210:26] wire putFull_a_mask_sub_sub_1_2 = putFull_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire putFull_a_mask_sub_sub_nbit = ~putFull_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire putFull_a_mask_sub_sub_0_2 = putFull_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _putFull_a_mask_sub_sub_acc_T = putFull_a_mask_sub_sub_size & putFull_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_sub_sub_0_1 = putFull_a_mask_sub_sub_sub_0_1 | _putFull_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _putFull_a_mask_sub_sub_acc_T_1 = putFull_a_mask_sub_sub_size & putFull_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_sub_sub_1_1 = putFull_a_mask_sub_sub_sub_0_1 | _putFull_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire putFull_a_mask_sub_size = putFull_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire putFull_a_mask_sub_bit = toAddress[1]; // @[Misc.scala:210:26] wire putFull_a_mask_sub_nbit = ~putFull_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire putFull_a_mask_sub_0_2 = putFull_a_mask_sub_sub_0_2 & putFull_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _putFull_a_mask_sub_acc_T = putFull_a_mask_sub_size & putFull_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_sub_0_1 = putFull_a_mask_sub_sub_0_1 | _putFull_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_sub_1_2 = putFull_a_mask_sub_sub_0_2 & putFull_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _putFull_a_mask_sub_acc_T_1 = putFull_a_mask_sub_size & putFull_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_sub_1_1 = putFull_a_mask_sub_sub_0_1 | _putFull_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_sub_2_2 = putFull_a_mask_sub_sub_1_2 & putFull_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _putFull_a_mask_sub_acc_T_2 = putFull_a_mask_sub_size & putFull_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_sub_2_1 = putFull_a_mask_sub_sub_1_1 | _putFull_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_sub_3_2 = putFull_a_mask_sub_sub_1_2 & putFull_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _putFull_a_mask_sub_acc_T_3 = putFull_a_mask_sub_size & putFull_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_sub_3_1 = putFull_a_mask_sub_sub_1_1 | _putFull_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_size = putFull_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire putFull_a_mask_bit = toAddress[0]; // @[Misc.scala:210:26] wire putFull_a_mask_nbit = ~putFull_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire putFull_a_mask_eq = putFull_a_mask_sub_0_2 & putFull_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _putFull_a_mask_acc_T = putFull_a_mask_size & putFull_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_acc = putFull_a_mask_sub_0_1 | _putFull_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_eq_1 = putFull_a_mask_sub_0_2 & putFull_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _putFull_a_mask_acc_T_1 = putFull_a_mask_size & putFull_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_acc_1 = putFull_a_mask_sub_0_1 | _putFull_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_eq_2 = putFull_a_mask_sub_1_2 & putFull_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _putFull_a_mask_acc_T_2 = putFull_a_mask_size & putFull_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_acc_2 = putFull_a_mask_sub_1_1 | _putFull_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_eq_3 = putFull_a_mask_sub_1_2 & putFull_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _putFull_a_mask_acc_T_3 = putFull_a_mask_size & putFull_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_acc_3 = putFull_a_mask_sub_1_1 | _putFull_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_eq_4 = putFull_a_mask_sub_2_2 & putFull_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _putFull_a_mask_acc_T_4 = putFull_a_mask_size & putFull_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_acc_4 = putFull_a_mask_sub_2_1 | _putFull_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_eq_5 = putFull_a_mask_sub_2_2 & putFull_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _putFull_a_mask_acc_T_5 = putFull_a_mask_size & putFull_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_acc_5 = putFull_a_mask_sub_2_1 | _putFull_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_eq_6 = putFull_a_mask_sub_3_2 & putFull_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _putFull_a_mask_acc_T_6 = putFull_a_mask_size & putFull_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_acc_6 = putFull_a_mask_sub_3_1 | _putFull_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire putFull_a_mask_eq_7 = putFull_a_mask_sub_3_2 & putFull_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _putFull_a_mask_acc_T_7 = putFull_a_mask_size & putFull_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire putFull_a_mask_acc_7 = putFull_a_mask_sub_3_1 | _putFull_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] putFull_a_mask_lo_lo = {putFull_a_mask_acc_1, putFull_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_lo_hi = {putFull_a_mask_acc_3, putFull_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_lo = {putFull_a_mask_lo_hi, putFull_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] putFull_a_mask_hi_lo = {putFull_a_mask_acc_5, putFull_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] putFull_a_mask_hi_hi = {putFull_a_mask_acc_7, putFull_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] putFull_a_mask_hi = {putFull_a_mask_hi_hi, putFull_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _putFull_a_mask_T = {putFull_a_mask_hi, putFull_a_mask_lo}; // @[Misc.scala:222:10] assign putFull_mask = _putFull_a_mask_T; // @[Misc.scala:222:10] assign _io_req_ready_T = state == 2'h0; // @[DMA.scala:205:24, :264:27] assign io_req_ready_0 = _io_req_ready_T; // @[DMA.scala:188:9, :264:27] wire _GEN_3 = state == 2'h1; // @[DMA.scala:205:24, :265:26] wire _nodeOut_a_valid_T; // @[DMA.scala:265:26] assign _nodeOut_a_valid_T = _GEN_3; // @[DMA.scala:265:26] wire _io_in_ready_T; // @[DMA.scala:268:26] assign _io_in_ready_T = _GEN_3; // @[DMA.scala:265:26, :268:26] wire _nodeOut_a_valid_T_1 = io_in_valid_0 | sendTrail; // @[DMA.scala:188:9, :240:33, :265:54] wire _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T & _nodeOut_a_valid_T_1; // @[DMA.scala:265:{26,38,54}] assign _nodeOut_a_valid_T_3 = _nodeOut_a_valid_T_2 & canSend; // @[DMA.scala:229:34, :265:{38,68}] assign nodeOut_a_valid = _nodeOut_a_valid_T_3; // @[DMA.scala:265:68] assign _nodeOut_a_bits_T_opcode = {2'h0, wpartial}; // @[DMA.scala:249:20, :266:21] assign _nodeOut_a_bits_T_size = wpartial ? 4'h3 : putFull_size; // @[Edges.scala:480:17] assign _nodeOut_a_bits_T_source = wpartial ? putPartial_source : putFull_source; // @[Edges.scala:480:17, :500:17] assign _nodeOut_a_bits_T_address = wpartial ? putPartial_address : putFull_address; // @[Edges.scala:480:17, :500:17] assign _nodeOut_a_bits_T_mask = wpartial ? putPartial_mask : putFull_mask; // @[Edges.scala:480:17, :500:17] assign _nodeOut_a_bits_T_data = wpartial ? putPartial_data : putFull_data; // @[Edges.scala:480:17, :500:17] assign nodeOut_a_bits_opcode = _nodeOut_a_bits_T_opcode; // @[DMA.scala:266:21] assign nodeOut_a_bits_size = _nodeOut_a_bits_T_size; // @[DMA.scala:266:21] assign nodeOut_a_bits_source = _nodeOut_a_bits_T_source; // @[DMA.scala:266:21] assign nodeOut_a_bits_address = _nodeOut_a_bits_T_address; // @[DMA.scala:266:21] assign nodeOut_a_bits_mask = _nodeOut_a_bits_T_mask; // @[DMA.scala:266:21] assign nodeOut_a_bits_data = _nodeOut_a_bits_T_data; // @[DMA.scala:266:21] assign _nodeOut_d_ready_T = |xactBusy; // @[DMA.scala:216:27, :267:28] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[DMA.scala:267:28] wire _io_in_ready_T_1 = _io_in_ready_T & canSend; // @[DMA.scala:229:34, :268:{26,37}] wire _io_in_ready_T_2 = ~sendTrail; // @[DMA.scala:240:33, :268:51] wire _io_in_ready_T_3 = _io_in_ready_T_1 & _io_in_ready_T_2; // @[DMA.scala:268:{37,48,51}] assign _io_in_ready_T_4 = _io_in_ready_T_3 & nodeOut_a_ready; // @[DMA.scala:268:{48,62}] assign io_in_ready_0 = _io_in_ready_T_4; // @[DMA.scala:188:9, :268:62] wire _io_resp_valid_T = state == 2'h2; // @[DMA.scala:205:24, :269:28] wire _io_resp_valid_T_1 = |xactBusy; // @[DMA.scala:216:27, :267:28, :269:52] wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[DMA.scala:269:{42,52}] assign _io_resp_valid_T_3 = _io_resp_valid_T & _io_resp_valid_T_2; // @[DMA.scala:269:{28,39,42}] assign io_resp_valid_0 = _io_resp_valid_T_3; // @[DMA.scala:188:9, :269:39] wire [3:0] _beatsLeft_T = {1'h0, beatsLeft} - 4'h1; // @[DMA.scala:223:24, :282:32] wire [2:0] _beatsLeft_T_1 = _beatsLeft_T[2:0]; // @[DMA.scala:282:32] wire [3:0] _nBeats_T = {1'h0, reqSize} - 4'h3; // @[Mux.scala:126:16] wire [2:0] _nBeats_T_1 = _nBeats_T[2:0]; // @[DMA.scala:284:38] wire [7:0] nBeats = 8'h1 << _nBeats_T_1; // @[OneHot.scala:58:35] wire [8:0] _beatsLeft_T_2 = {1'h0, nBeats} - 9'h1; // @[DMA.scala:284:26, :285:29] wire [7:0] _beatsLeft_T_3 = _beatsLeft_T_2[7:0]; // @[DMA.scala:285:29] wire _bytesSent_T = wmask[0]; // @[DMA.scala:247:20, :291:31] wire _bytesSent_T_1 = wmask[1]; // @[DMA.scala:247:20, :291:31] wire _bytesSent_T_2 = wmask[2]; // @[DMA.scala:247:20, :291:31] wire _bytesSent_T_3 = wmask[3]; // @[DMA.scala:247:20, :291:31] wire _bytesSent_T_4 = wmask[4]; // @[DMA.scala:247:20, :291:31] wire _bytesSent_T_5 = wmask[5]; // @[DMA.scala:247:20, :291:31] wire _bytesSent_T_6 = wmask[6]; // @[DMA.scala:247:20, :291:31] wire _bytesSent_T_7 = wmask[7]; // @[DMA.scala:247:20, :291:31] wire [1:0] _bytesSent_T_8 = {1'h0, _bytesSent_T} + {1'h0, _bytesSent_T_1}; // @[DMA.scala:291:31] wire [1:0] _bytesSent_T_9 = _bytesSent_T_8; // @[DMA.scala:291:31] wire [1:0] _bytesSent_T_10 = {1'h0, _bytesSent_T_2} + {1'h0, _bytesSent_T_3}; // @[DMA.scala:291:31] wire [1:0] _bytesSent_T_11 = _bytesSent_T_10; // @[DMA.scala:291:31] wire [2:0] _bytesSent_T_12 = {1'h0, _bytesSent_T_9} + {1'h0, _bytesSent_T_11}; // @[DMA.scala:291:31] wire [2:0] _bytesSent_T_13 = _bytesSent_T_12; // @[DMA.scala:291:31] wire [1:0] _bytesSent_T_14 = {1'h0, _bytesSent_T_4} + {1'h0, _bytesSent_T_5}; // @[DMA.scala:291:31] wire [1:0] _bytesSent_T_15 = _bytesSent_T_14; // @[DMA.scala:291:31] wire [1:0] _bytesSent_T_16 = {1'h0, _bytesSent_T_6} + {1'h0, _bytesSent_T_7}; // @[DMA.scala:291:31] wire [1:0] _bytesSent_T_17 = _bytesSent_T_16; // @[DMA.scala:291:31] wire [2:0] _bytesSent_T_18 = {1'h0, _bytesSent_T_15} + {1'h0, _bytesSent_T_17}; // @[DMA.scala:291:31] wire [2:0] _bytesSent_T_19 = _bytesSent_T_18; // @[DMA.scala:291:31] wire [3:0] _bytesSent_T_20 = {1'h0, _bytesSent_T_13} + {1'h0, _bytesSent_T_19}; // @[DMA.scala:291:31] wire [3:0] bytesSent = _bytesSent_T_20; // @[DMA.scala:291:31] wire [32:0] _offset_T = _GEN + {29'h0, bytesSent}; // @[DMA.scala:210:31, :291:31, :292:24] wire [31:0] _offset_T_1 = _offset_T[31:0]; // @[DMA.scala:292:24] wire [126:0] _overhang_T = {64'h0, fulldata[126:64]}; // @[DMA.scala:241:30, :293:28] wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[DMA.scala:188:9] if (reset) begin // @[DMA.scala:188:9] state <= 2'h0; // @[DMA.scala:205:24] xactBusy <= 8'h0; // @[DMA.scala:216:27] overhang <= 64'h0; // @[DMA.scala:239:27] end else begin // @[DMA.scala:188:9] if (io_resp_ready_0 & io_resp_valid_0) // @[Decoupled.scala:51:35] state <= 2'h0; // @[DMA.scala:205:24] else if (_xactBusy_T & {28'h0, bytesSent} == bytesToSend) // @[Decoupled.scala:51:35] state <= 2'h2; // @[DMA.scala:205:24] else if (_T) // @[Decoupled.scala:51:35] state <= 2'h1; // @[DMA.scala:205:24] xactBusy <= _xactBusy_T_8; // @[DMA.scala:216:27, :236:74] if (_xactBusy_T) // @[Decoupled.scala:51:35] overhang <= _overhang_T[63:0]; // @[DMA.scala:239:27, :293:{16,28}] end if (_T) begin // @[Decoupled.scala:51:35] length <= io_req_bits_length_0; // @[DMA.scala:188:9, :207:21] baseAddr <= io_req_bits_address_0[31:0]; // @[DMA.scala:188:9, :208:23, :274:16] end if (_xactBusy_T) begin // @[Decoupled.scala:51:35] offset <= _offset_T_1; // @[DMA.scala:209:21, :292:24] if (newBlock) begin // @[DMA.scala:228:30] if (reqSize[2]) // @[Mux.scala:126:16] beatsLeft <= _beatsLeft_T_3[2:0]; // @[DMA.scala:223:24, :285:{19,29}] else if (_T) // @[Decoupled.scala:51:35] beatsLeft <= 3'h0; // @[DMA.scala:223:24] end else // @[DMA.scala:228:30] beatsLeft <= _beatsLeft_T_1; // @[DMA.scala:223:24, :282:32] end else if (_T) begin // @[Decoupled.scala:51:35] offset <= 32'h0; // @[DMA.scala:209:21, :248:37] beatsLeft <= 3'h0; // @[DMA.scala:223:24] end if (_xactBusy_T & newBlock & reqSize[2]) begin // @[Mux.scala:126:16] headAddr <= addrMerged; // @[DMA.scala:210:31, :224:23] headXact <= xactId; // @[OneHot.scala:32:10] headSize <= _GEN_0; // @[DMA.scala:226:23, :245:21] end always @(posedge) assign auto_out_a_valid = auto_out_a_valid_0; // @[DMA.scala:188:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[DMA.scala:188:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[DMA.scala:188:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[DMA.scala:188:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[DMA.scala:188:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[DMA.scala:188:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[DMA.scala:188:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[DMA.scala:188:9] assign io_req_ready = io_req_ready_0; // @[DMA.scala:188:9] assign io_resp_valid = io_resp_valid_0; // @[DMA.scala:188:9] assign io_resp_bits = io_resp_bits_0; // @[DMA.scala:188:9] assign io_in_ready = io_in_ready_0; // @[DMA.scala:188:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined || nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined || nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBits*rowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /** Bundle definitions for HellaCache interfaces */ trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /** Base classes for Diplomatic TL2 HellaCaches */ abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated */ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /** Metadata array used for all HellaCaches */ class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst }
module tag_array( // @[HellaCache.scala:339:30] input [3:0] RW0_addr, input RW0_en, input RW0_clk, input RW0_wmode, input [47:0] RW0_wdata, output [47:0] RW0_rdata, input [1:0] RW0_wmask ); tag_array_ext tag_array_ext ( // @[HellaCache.scala:339:30] .RW0_addr (RW0_addr), .RW0_en (RW0_en), .RW0_clk (RW0_clk), .RW0_wmode (RW0_wmode), .RW0_wdata (RW0_wdata), .RW0_rdata (RW0_rdata), .RW0_wmask (RW0_wmask) ); // @[HellaCache.scala:339:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File loop.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomLoopPredictorParams( nWays: Int = 4, threshold: Int = 7 ) class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val tagSz = 10 override val nSets = 16 class LoopMeta extends Bundle { val s_cnt = UInt(10.W) } class LoopEntry extends Bundle { val tag = UInt(tagSz.W) val conf = UInt(3.W) val age = UInt(3.W) val p_cnt = UInt(10.W) val s_cnt = UInt(10.W) } class LoopBranchPredictorColumn extends Module { val io = IO(new Bundle { val f2_req_valid = Input(Bool()) val f2_req_idx = Input(UInt()) val f3_req_fire = Input(Bool()) val f3_pred_in = Input(Bool()) val f3_pred = Output(Bool()) val f3_meta = Output(new LoopMeta) val update_mispredict = Input(Bool()) val update_repair = Input(Bool()) val update_idx = Input(UInt()) val update_resolve_dir = Input(Bool()) val update_meta = Input(new LoopMeta) }) val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val entries = Reg(Vec(nSets, new LoopEntry)) val f2_entry = WireInit(entries(io.f2_req_idx)) when (io.update_repair && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := io.update_meta.s_cnt } .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := 0.U } val f3_entry = RegNext(f2_entry) val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx), io.update_meta.s_cnt, f3_entry.s_cnt) val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))) io.f3_pred := io.f3_pred_in io.f3_meta.s_cnt := f3_scnt when (f3_entry.tag === f3_tag) { when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) { io.f3_pred := !io.f3_pred_in } } val f4_fire = RegNext(io.f3_req_fire) val f4_entry = RegNext(f3_entry) val f4_tag = RegNext(f3_tag) val f4_scnt = RegNext(f3_scnt) val f4_idx = RegNext(RegNext(io.f2_req_idx)) when (f4_fire) { when (f4_entry.tag === f4_tag) { when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) { entries(f4_idx).age := 7.U entries(f4_idx).s_cnt := 0.U } .otherwise { entries(f4_idx).s_cnt := f4_scnt + 1.U entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U) } } } val entry = entries(io.update_idx) val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)) val tag_match = entry.tag === tag val ctr_match = entry.p_cnt === io.update_meta.s_cnt val wentry = WireInit(entry) when (io.update_mispredict && !doing_reset) { // Learned, tag match -> decrement confidence when (entry.conf === 7.U && tag_match) { wentry.s_cnt := 0.U wentry.conf := 0.U // Learned, no tag match -> do nothing? Don't evict super-confident entries? } .elsewhen (entry.conf === 7.U && !tag_match) { // Confident, tag match, ctr_match -> increment confidence, reset counter } .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) { wentry.conf := entry.conf + 1.U wentry.s_cnt := 0.U // Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter } .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) { wentry.conf := 0.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) { wentry.tag := tag wentry.conf := 1.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age > 0 -> decrement age } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) { wentry.age := entry.age - 1.U // Unconfident, tag match, ctr match -> increment confidence } .elsewhen (entry.conf === 0.U && tag_match && ctr_match) { wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, tag match, no ctr match -> set previous counter } .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) { wentry.p_cnt := io.update_meta.s_cnt wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, no tag match -> set previous counter and tag } .elsewhen (entry.conf === 0.U && !tag_match) { wentry.tag := tag wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt } entries(io.update_idx) := wentry } .elsewhen (io.update_repair && !doing_reset) { when (tag_match && !(f4_fire && io.update_idx === f4_idx)) { wentry.s_cnt := io.update_meta.s_cnt entries(io.update_idx) := wentry } } when (doing_reset) { entries(reset_idx) := (0.U).asTypeOf(new LoopEntry) } } val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) } val mems = Nil // TODO fix val f3_meta = Wire(Vec(bankWidth, new LoopMeta)) override val metaSz = f3_meta.asUInt.getWidth val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta)) for (w <- 0 until bankWidth) { columns(w).io.f2_req_valid := s2_valid columns(w).io.f2_req_idx := s2_idx columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire && RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br)) columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken io.resp.f3(w).taken := columns(w).io.f3_pred columns(w).io.update_mispredict := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_mispredict_update && s1_update.bits.cfi_mispredicted) columns(w).io.update_repair := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_repair_update) columns(w).io.update_idx := s1_update_idx columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken columns(w).io.update_meta := update_meta(w) f3_meta(w) := columns(w).io.f3_meta } io.f3_meta := f3_meta.asUInt }
module LoopBranchPredictorColumn_7( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [35:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [35:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [35:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [35:0] f4_idx_REG; // @[loop.scala:92:35] reg [35:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36] wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) || c.visibility.map(_.contains(address)).reduce(_ || _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) || (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) || (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) || (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) || bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight | a_set) & ~d_clr inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) || bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight | c_set) & ~d_clr inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight | d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool*) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool*) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. */ object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ || _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) | c i.U((s.length*8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ || _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc || (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) */ private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /** Typeclass for converting a type to a doctype string * @tparam A some type */ trait Doctypeable[A] { /** Return the doctype string for some option */ def toDoctype(a: Option[A]): String } /** Object containing implementations of the Doctypeable typeclass */ object Doctypes { /** Converts an Int => "INT" */ implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /** Converts a BigInt => "INT" */ implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /** Converts a String => "STRING" */ implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } /* This wrapper class has no outputs, making it clear it is a simulation-only construct */ class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /** PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. */ def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. */ def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty /* Add a new PlusArg */ @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /** Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help */ def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) /* From plus args, generate help text */ private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""|$tab+$arg=${info.doctype}\\n\\ |$tab${" "*20}${info.docstring}\\n\\ |""".stripMargin ++ info.default.map{ case default => s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" /* From plus args, generate a char array of their names */ private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " * 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs */ def serialize_cHeader(): String = s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ |${serializeHelp_cHeader(" "*7)} |${serializeArray_cHeader()} |""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width */ def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /** Any Data subtype that has a Bool member named valid. */ type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /** converts from camel case to to underscores, also removing all spaces */ def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /** converts spaces or underscores to hyphens, also lowering case */ def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y | (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y || y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x | (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /** Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /** * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. */ object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff *Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to *Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions */ object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min || max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U | (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base | x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) | remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask | bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) || !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData || // opcode === TLMessages.PutPartialData || // opcode === TLMessages.ArithmeticData || // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.ProbeAckData || // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData || // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode | small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U || beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }
module TLMonitor_89( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 | _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 | _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1759 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1759; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1759; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1827 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1827; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1827; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1827; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1692 = _T_1759 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1692 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1692 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1692 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1692 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1692 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1738 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1738 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1707 = _T_1827 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1707 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1707 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1707 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1803 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1803 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1785 = _T_1827 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1785 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1785 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1785 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]